Single-diffusion blocking structure and its manufacturing method

Abstract

This invention discloses a single-diffusion blocking structure and its manufacturing method. The semiconductor structure with single-diffusion blocking includes a substrate defining a first unit region and a second unit region thereon. The first unit region and the second unit region are adjacent to each other and have their respective fins. A shallow trench isolation structure is located on the substrate and surrounds the fins. A plurality of gates cross the fins. A dummy gate is located on the shallow trench isolation structure between the first region and the second region and is spaced apart from the gates. At least one conductive pattern is located on the dummy gate and connected thereto. At least one dummy via is located on the at least one conductive pattern and connected thereto.

Description

Technical Field

[0001] This invention relates to a single-diffusion break (SDB) structure, and more specifically, to a single-diffusion break structure located on a shallow trench isolation (STI) structure and connected with a dummy via, and a method for manufacturing the same. Background Technology

[0002] Single-diffusion break (SDB), or single-dummy gate, is a semiconductor technology that eliminates the need for two dummy gates at the boundary between two adjacent semiconductor cells to isolate them. Compared to the traditional double-diffusion break (DDB) technology, which requires two dummy gates at the boundary, SDB only requires one dummy gate or blocking structure. This allows for further miniaturization of semiconductor cells without affecting cell height or underlying components, while simultaneously providing better stress control and reducing fabrication process variability.

[0003] Typical single-diffusion blocking or double-diffusion blocking techniques utilize dummy patterns in the layout, such as dummy gates, to achieve diffusion blocking. Dummy patterns can also improve fabrication quality and yield, for example, by helping to balance exposure and development in photolithography, ensuring the clarity and accuracy of other important patterns, and reducing defect rates by increasing the uniformity of the layout pattern, thereby improving overall yield. These dummy patterns typically do not participate in actual circuit function, but play a crucial role in the fabrication process. However, in some practical applications, dummy vias (V0) located on the zeroth metal layer (M0) may form unnecessary conductive paths, causing bridging and leakage between adjacent active blocks.

[0004] by Figure 1 For example, it is a schematic diagram of the layout of a semiconductor circuit with a single diffusion blocking structure in the prior art. In Figure 1In this design, each active block (AAblock) has multiple fins F extending in a first direction D1 and spaced apart in a second direction D2. Furthermore, each active block also has multiple gates G and multiple first conductive patterns MD (also known as metal zero over oxide, MOOD, abbreviated as MD in this text), both extending in the second direction D2 past the fins F and spaced apart in the first direction D1. To separate different cell regions within the block, a single-diffusion blocking structure SDB is also formed. In practice, the gate G located at the boundary between two cell regions is usually replaced by a dummy gate as part of the single-diffusion blocking structure SDB, which has the same shape as a regular gate G and is located between the two first conductive patterns MD at the boundary.

[0005] Please refer to now. Figure 2 , its purpose is Figure 1 A cross-sectional view along line A-A'. Besides the gate G and the first conductive pattern MD mentioned above, the zeroth metal layer M0 also includes a zeroth metal layer via V0 and a second conductive pattern MP (also known as a metal zero over polysilicon (MOOP), abbreviated as MP in this text). In the prior art, the zeroth metal layer via V0 is generally disposed on and connected to the first conductive pattern MD. The first conductive pattern MD and the fin F connected below it are connected to the upper first metal layer M1 through the zeroth metal layer via V0, and then connected to the subsequent circuitry. The second conductive pattern MP is disposed on and connected to the gate G. In some designs, the second conductive pattern MP can also be connected to the adjacent first conductive pattern MD, such as... Figure 1 As shown. The aforementioned fin F, first conductive pattern MD, zeroth metal layer via V0, and first metal layer M1 can form a conductive path. However, in the case of a dummy pattern, the presence of the zeroth metal layer via V0 allows the circuit of that block to be connected to the circuit of an adjacent block via the first metal layer M1, such as... Figure 1 As shown in path B, this causes circuit bridging and leakage between the two blocks. Therefore, those skilled in the art need to improve the existing single-diffusion blocking structure to solve the above problem. Summary of the Invention

[0006] In view of the problems encountered in the prior art, the present invention proposes a novel single-diffusion blocking structure, characterized in that a dummy guide hole is set on the single-diffusion blocking structure on the shallow trench isolation structure, so that the leakage path can be blocked by the single-diffusion blocking structure, thus solving the leakage problem caused by setting dummy patterns in the prior art.

[0007] One aspect of the present invention is to provide a single-diffusion blocking structure, comprising: a substrate having a plurality of fins protruding from the substrate and extending in a first direction, and defining a first unit region and a second unit region on the substrate, the first unit region and the second unit region being adjacent in the first direction and having their respective fins; a shallow trench isolation structure located on the substrate and surrounding the fins; a plurality of gates extending in a second direction across the fins; a dummy gate located on the shallow trench isolation structure between the first region and the second region and extending in the second direction, the dummy gate and the gates being spaced apart in the first direction; a plurality of first conductive patterns extending in the second direction across the fins and connected thereto, the first conductive patterns and the dummy gate and the gates being alternately spaced apart in the first direction; at least one second conductive pattern located on and connected to the dummy gate; and at least one via located on and connected to the at least one second conductive pattern.

[0008] Another aspect of the present invention is to provide a method for manufacturing a single-diffusion blocking structure, comprising: providing a substrate, wherein a first region and a second region are defined on the substrate, the first region and the second region being adjacent in a first direction; forming a plurality of fins on the substrate, the fins protruding from the substrate and extending in the first direction; forming a shallow trench on the fins between the first region and the second region; filling the shallow trench with a first dielectric layer to form a first shallow trench isolation structure; forming a dummy gate on the first shallow trench isolation structure between the first region and the second region, the dummy gate extending in a second direction; forming at least one second conductive pattern on the dummy gate; and forming at least one dummy via on the at least one second conductive pattern.

[0009] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the layout of a semiconductor circuit with a single diffusion blocking structure in the prior art;

[0011] Figure 2 For Figure 1 A schematic diagram of the cross section drawn along the midsection line A-A';

[0012] Figure 3 This is a schematic diagram of the layout of a semiconductor structure with single diffusion blocking according to Embodiment 1 of the present invention;

[0013] Figure 4 For Figure 3 A schematic diagram of the cross section drawn along the midsection line Y-Y';

[0014] Figure 5 This is a schematic diagram of the layout of a semiconductor structure with single diffusion blocking according to another embodiment of the present invention;

[0015] Figure 6 For Figure 5 A schematic diagram of the cross section drawn along the midsection line Y-Y';

[0016] Figure 7 For Figure 3 as well as Figure 5 A schematic diagram of the cross section drawn along the midsection line X-X';

[0017] Figures 8 to 10 This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure with single diffusion blocking according to Embodiment 1 of the present invention; and

[0018] Figures 11 to 13 This is a cross-sectional schematic diagram of the fabrication process of a semiconductor structure with single diffusion blocking according to another embodiment of the present invention.

[0019] It should be noted that all illustrations in this specification are for illustrative purposes. For clarity and ease of illustration, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments.

[0020] Symbol Explanation

[0021] 100 base

[0022] 102 Pad Oxide Layer

[0023] 104 Gate oxide layer

[0024] 106 Nitrided Layer

[0025] 108 Plasma-enhanced oxide layer

[0026] Path B

[0027] D1 First Direction

[0028] D2 Second Direction

[0029] DG Dummy Gate

[0030] F fin

[0031] G gate

[0032] M0 Zero Metal Layer

[0033] M1 First Metal Layer

[0034] MD First Conductive Pattern

[0035] MP Second Conductive Pattern

[0036] P1 Photolithography process

[0037] P2 photolithography process

[0038] R1 First Area

[0039] R2 Second Region

[0040] SDB Single-Diffusion Blocking (Structure)

[0041] SP spacer

[0042] ST shallow trench

[0043] STI Shallow Trench Isolation Structure

[0044] V0 Virtual via, zero-layer metal via, virtual vertical interconnect Detailed Implementation

[0045] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various features in the embodiments that do not conflict with each other can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0046] Readers should readily understand that the meanings of "on," "above," and "above" in this context should be interpreted broadly. "On" not only means "directly on" something, but also includes being "on" something with an intervening feature or layering structure. Similarly, "above" or "above" not only means "above" or "above" something, but also includes being "above" or "above" something without an intervening feature or layering structure (i.e., directly on something). Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0047] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any opposing horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layered structure, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0048] Readers can generally understand the terminology used in this invention, at least in part, from its usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," "the," or "described" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0049] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0050] First, please refer to the following: Figure 3 , Figure 4 as well as Figure 7 ,in Figure 3 This is a schematic diagram of the layout of a semiconductor structure with a single-diffusion break (SDB) according to Embodiment 1 of the present invention. Figure 4 For Figure 3 A schematic diagram of the cross section drawn along the midsection line Y-Y'. Figure 7 For Figure 3A cross-sectional diagram along line X-X' is shown. These diagrams allow the reader to fully understand the overlapping relationships of the planar layout pattern of the semiconductor structure of the present invention, as well as the relative positions and connections of the components in the vertical direction. As shown, the single diffusion blocking structure SDB of the present invention includes multiple fins F. These fins F can be extensions of a substrate 100, protruding upward from the surface of the substrate 100 and extending along a first direction D1. These fins F are spaced apart along a second direction D2, which is preferably orthogonal to the second direction D2. The materials of the fins F and the substrate 100 can be monocrystalline silicon. In embodiments of the present invention, these fins F can be located in an active block defined on the substrate 100. Each active block has its own group of fins, and can be further divided into multiple cell regions, such as the first region R1 and the second region R2 shown in the figure. Each unit region may have different operating voltages, physical characteristics, or specific functions, and electrical isolation can be achieved between them using a single diffusion blocking structure (SDB).

[0051] In the embodiments, the semiconductor structure of the present invention also has the following characteristics: Figure 1 The gate G and the first conductive pattern MD (also known as the metal zero over oxide, MOOD, abbreviated as MD in this document) are arranged alternately at intervals in the first direction D1, and their long axis extends across the fin F in the second direction D2. However, for the sake of simplicity and to avoid obscuring the focus of the invention, only the components and features near the single diffusion blocking structure SDB are shown in the figure. Figure 3 As shown, a single-diffusion blocking structure (SDB) includes a dummy gate (DG), whose pattern is generally the same as the gate (G), and is positioned between the two first conductive patterns (MD) closest to the boundary. The dummy gate (DG) can be made of doped polysilicon. Furthermore, from... Figure 7 As can be seen, unlike a typical gate G, the dummy gate DG is generally disposed on a shallow trench isolation (STI) structure. More specifically, it is disposed on the STI between two unit regions (first region R1 and second region R2), with its long axis extending in the second direction D2, and its sides passing over the ends of the fins F in the two regions respectively. A gate oxide layer 101 is formed between the dummy gate DG and the fins F to isolate them. Figure 4As can be seen, on the Y-Y' cross-section (i.e., the boundary between the two regions), the dummy gate DG is completely located on and directly connected to the shallow trench isolation structure STI. The shallow trench isolation structure STI can be made of silicon oxide or silicon nitride, and it is disposed on the substrate 100 and surrounds the fins F to isolate different component areas in the circuit, preventing electrical interference between different components. In embodiments, the areas exposed or protruding from the shallow trench isolation structure STI (i.e., the fins F) can also be referred to as oxide definition (OD) patterns or active areas.

[0052] Rereference Figure 3 , Figure 4 as well as Figure 7 In this invention, the dummy gate DG of the single diffusion blocking structure SDB also has a second conductive pattern MP (also known as a metal zero over polysilicon, MOOP, hereinafter referred to as MP) and dummy vias (V0). In this embodiment, the second conductive pattern MP can be disposed at both ends of the dummy gate DG in the second direction D2 and directly connected to the dummy gate DG. The second conductive pattern MP is preferably the same height as the adjacent first conductive pattern MD, and can be made of the same metal material, such as tungsten, aluminum, copper, titanium, etc. In some embodiments, the second conductive pattern MP can be connected to the first conductive pattern MD or be integrated with it, without limitation. In this embodiment, two dummy vias V0 are respectively disposed on the second conductive pattern MP located at both ends and directly connected to it. The dummy gate DG is then connected to the first metal layer M1 of the upper semiconductor back-end (BEOL) interconnect circuit through the second conductive pattern MP and the dummy vias V0. The material of the dummy guide hole V0 can be the same as that of the first conductive pattern MD and the second conductive pattern MP, such as tungsten, aluminum, copper, titanium, etc. Figure 7 As shown, from a vertical structure perspective, the first conductive pattern MD, the second conductive pattern MP, and the dummy via V0 can be considered as the zero metal layer M0 between the active region of the semiconductor front section (FEOL) and the first metal layer M1 of the semiconductor back section, while the shallow trench isolation structure STI, the dummy gate DG, the second conductive pattern MP, and the dummy via V0 in the figure can be considered as the single diffusion blocking structure SDB of the present invention.

[0053] It should be noted that, in this invention, compared to Figure 1In the prior art shown, the dummy via V0, which was originally disposed on the first conductive pattern MD, is instead disposed on the second conductive pattern MP in the single-diffusion blocking structure SDB. With this design, the dummy via V0, which would have formed a conductive path on the first conductive pattern MD, is instead disposed on the single-diffusion blocking structure SDB. Thus, although there is a connection to the first metal layer M1, because the fins F of the two lower unit regions are separated by the shallow trench isolation structure STI and the gate oxide layer 104, no channel is formed, preventing leakage between different regions.

[0054] Now please refer to the following: Figure 5 and Figure 6 , among them Figure 5 This is a schematic diagram of the layout of a semiconductor structure with single diffusion blocking according to another embodiment of the present invention. Figure 6 For Figure 5 A schematic diagram of the cross-section along the midline Y-Y'. The structure of this embodiment is largely the same as the previous embodiment, except that the dummy guide hole V0, originally set on the second conductive pattern MP, is changed to a long strip (hereinafter referred to as the dummy vertical interconnect strip V0). Figure 5 As shown, in this embodiment, the long axis of the dummy vertical interconnect V0 extends in the second direction D2, and it can approximately coincide with the dummy gate DG below in the vertical direction. The dummy vertical interconnect V0 is connected to the second conductive pattern MP located at both ends of the dummy gate DG below. The dummy gate DG is connected upward to the first metal layer M1 of the upper semiconductor back-end interconnect circuit through the two second conductive patterns MP and the dummy vertical interconnect V0.

[0055] After describing the semiconductor structure of the present invention, the following embodiments will be referred to in sequence. Figures 8 to 10 The fabrication process of a semiconductor structure with single diffusion blocking according to an embodiment of the present invention will be described. Figures 8 to 10 The cross section is similar Figure 3 The line X-X' in the middle cuts through the single fin F and the single diffusion blocking structure in the middle along the first direction D1.

[0056] First, please refer to... Figure 8A substrate 100 is provided as the basis for the semiconductor structure of the present invention. Fins F are pre-formed on the substrate 100. In an embodiment, the fabrication steps of the fins F are as follows: first, a pad oxide layer 102 is formed on the substrate 100, which can be formed by directly oxidizing the silicon substrate 100 by thermal oxidation. Next, a photolithography process is performed to pattern the substrate 100, thereby forming the fins F protruding from the surface of the substrate 100. Then, a deposition process, such as a flowable chemical vapor deposition (FCVD) process, is performed to form a shallow trench isolation structure (not shown), such as a silicon oxide layer, around the fins F. The fins F are the active regions defined by the shallow trench isolation structure. The steps for forming these fins F and the shallow trench isolation structure are existing fabrication processes, and are not specifically shown in the figures to avoid obscuring the focus of the present invention. After the fin F is formed, another photolithography process P1 is used to pattern the fin F, thus forming a shallow groove ST on the fin F, as shown. Figure 8 As shown. In an embodiment, the shallow trench ST may be located between two unit regions, such as... Figure 3 The first region R1 and the second region R2 shown divide the originally single fin F (such as a fin located in an active block) into two fins F located in two different unit regions. The depth of the shallow trench ST can be higher than, equal to or lower than the bottom of the original fin F, without limitation. The pad oxide layer 102 can protect the fin F and the substrate 100 in the above photolithography process, avoiding unnecessary etching damage to certain areas and ensuring the accuracy and uniformity of the photolithography process.

[0057] Please refer to Figure 9After the shallow trench ST is formed, another shallow trench isolation structure STI is then formed within the shallow trench ST. In this embodiment of the invention, the fabrication process for forming the shallow trench isolation structure STI may include a deposition process, such as an FCVD process, to fill the shallow trench ST with a dielectric material. This dielectric material is preferably different from the aforementioned shallow trench isolation structure around the fin F, such as silicon nitride. Subsequently, an etch-back process is performed to remove the dielectric material located outside the shallow trench ST, thus forming the shallow trench isolation structure STI located only within the shallow trench ST. In this etch-back step, since the material (silicon oxide) of the shallow trench isolation structure around the fin F has a significant etch selectivity ratio compared to the material (silicon nitride) of the shallow trench isolation structure STI in the shallow trench ST, this etch-back process will not damage the shallow trench isolation structure around the fin F. It should be noted that in this embodiment, the shallow trench isolation structure STI in the shallow trench ST and the general shallow trench isolation structure defining the active region around the fin F are formed in different steps and preferably have different materials. The shallow trench isolation structure around the fin F is used to define the fin F, and the shallow trench isolation structure STI in the shallow trench ST is part of the single diffusion blocking structure SDB of the present invention, used to isolate the fin F located in different unit regions on both sides.

[0058] Please refer to Figure 10 After the shallow trench isolation structure (STI) is formed, a doping process is performed to form the well region required for the device in the fin F. Then, an etching process is performed to reduce the height of the aforementioned shallow trench isolation structure, including the general shallow trench isolation structure around the fin F and the shallow trench isolation structure (STI) in the shallow trench ST, thus making the fin F protrude to fabricate a fin field-effect transistor (FinFET). The aforementioned pad oxide layer 102 can also be removed in this step. Figure 10 As shown, after the fin F protrudes, a gate oxide layer 104 can be formed on the exposed surface of the fin F. This layer can be formed by directly oxidizing the exposed silicon fin F through thermal oxidation, or by a CVD fabrication process. Subsequently, dummy gates DG and gates G are formed on the fin F. The planar layout patterns of the dummy gates DG and G are as follows... Figure 1 As shown, they are spaced apart in the first direction D1 and their long axis extends across multiple fins F in the second direction D2. The dummy gate DG is generally disposed on the aforementioned shallow trench isolation structure STI, and more specifically, it is disposed in two unit regions (e.g., Figure 3On the shallow trench isolation structure STI between the first region R1 and the second region R2, the fins F extend beyond the ends of these two regions on both sides. The dummy gate DG and gate G are formed by depositing a polysilicon layer on the fin F using a CVD process followed by photolithography patterning. Furthermore, spacers SP can be formed on the sidewalls of the dummy gate DG and gate G to provide protection and define the source / drain regions on both sides of the device. The spacer SP can be made of silicon oxide, silicon nitride, or a multilayer structure thereof. After the dummy gate DG, gate G, and spacers are formed, the first conductive pattern MD, the second conductive pattern MP, and the dummy via V0, etc., in the semiconductor structure of this invention can be formed subsequently. Since the fabrication processes for these components are existing technologies, they will not be described in detail here to avoid obscuring the focus of this invention.

[0059] Please refer to the following in order. Figures 11 to 13 This describes the fabrication process of a semiconductor structure with single diffusion blocking according to another embodiment of the present invention. The difference between this embodiment and the previous embodiment is that the shallow trench ST is formed in different stages. Generally, the patterning process for fins may involve multiple dicing processes to cut out the desired fin pattern. For example, a first dicing process may be performed to cut off the head and tail portions of the spacers surrounding the mandrel to form multiple fins, followed by a second dicing process to remove other unnecessary fin portions to define the fins located in each active block, such as... Figure 1 The fin-like features within. Based on this, such as... Figure 11 As shown, in this embodiment, a photolithography process P2 is performed to pattern the fin F, thereby forming a shallow trench ST on the fin F. In this embodiment, the photolithography process P2 can be performed after the aforementioned first dicing process and before the second dicing process. The shallow trench ST can be located between two unit regions, such as... Figure 3 The first region R1 and the second region R2 shown divide the original single fin F (such as a fin located in an active block) into two fins F located in two different unit regions. The depth of the shallow trench ST can be higher than, equal to or lower than the bottom of the original fin F, without limitation. In this embodiment, a pad oxide layer 102, a pad nitride layer 106 and a plasma-enhanced oxide layer 108 are sequentially formed on the top surface of the fin F. The pad oxide layer 102 can serve as a buffer layer between the pad nitride layer 106 and the fin F, and the pad nitride layer 106 can serve as a stop layer in the planarization step (such as chemical mechanical planarization, CMP) in the shallow trench isolation structure fabrication process. The plasma-enhanced oxide layer 108 can serve as an isolation layer to prevent the silicon nitride layer from reacting with other layer structures.

[0060] Please refer to Figure 12 After the fin F and shallow trench ST are formed, a deposition process, such as an FCVD process, can be performed to fill the shallow trench ST with a dielectric material. In this embodiment, the dielectric material can simultaneously surround the fin F and fill the shallow trench ST. Subsequently, an etching process is performed to remove the dielectric material located above the top surface of the fin F and outside the shallow trench ST, thus forming a shallow trench isolation structure (STI) surrounding the fin F and located within the shallow trench ST. In this embodiment, unlike the previous embodiments, the shallow trench isolation structure (STI) in the shallow trench ST is integral with the shallow trench isolation structure defining the active region around the fin F. They have the same material, such as silicon oxide, and are formed in the same fabrication process. The portion of the shallow trench isolation structure (STI) located in the shallow trench ST serves as part of the single diffusion blocking structure of this invention, used to isolate the fin F located in different unit regions on both sides.

[0061] Please refer to Figure 13 After the shallow trench isolation structure (STI) is formed, a doping process is then performed to form the well region required for the device in the fin F. A subsequent etching process removes a portion of the aforementioned shallow trench isolation structure (STI), including the general shallow trench isolation structure around the fin F and the shallow trench isolation structure within the shallow trench ST. This reduces the height of the STI, causing the fin F to protrude for subsequent fin field-effect transistor (FinFET) fabrication. The aforementioned pad oxide layer 102 can also be removed in this step. Figure 13 As shown, after the fin F protrudes, a gate oxide layer 104 can be formed on the exposed surface of the fin F. This layer can be formed by directly oxidizing the exposed silicon fin F through thermal oxidation or by a CVD fabrication process. Subsequently, dummy gates DG and gates G are formed on the fin F. The planar layout patterns of the dummy gates DG and G are as follows... Figure 1 As shown, they are spaced apart in the first direction D1 and their long axis extends across multiple fins F in the second direction D2. The dummy gate DG is generally disposed on the aforementioned shallow trench isolation structure STI, and more specifically, it is disposed in two unit regions (e.g., Figure 3 On the shallow trench isolation structure STI between the first region R1 and the second region R2, the fins F extend beyond the ends of the two regions on both sides. Furthermore, spacers SP can be formed on the sidewalls of the dummy gate DG and the gate G to provide protection and define the source / drain regions on both sides of the element. After the dummy gate DG, the gate G, and the spacers SP are formed, the first conductive pattern MD, the second conductive pattern MP, and the dummy via V0, etc., in the semiconductor structure of this invention can be formed subsequently. Since the fabrication processes for these components are existing technologies, they will not be described in detail here to avoid obscuring the focus of this invention.

[0062] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure with single diffusion blocking, comprising: A base having multiple fins protruding from the base and extending in a first direction, and defining a first unit region and a second unit region on the base, the first unit region and the second unit region being adjacent in the first direction and having their respective fins; A shallow groove isolation structure is located on the base and surrounds the fins; Multiple gates extend in a second direction across the fins; A dummy gate is located on the shallow trench isolation structure between the first region and the second region and extends in the second direction; the dummy gate and the gates are spaced apart in the first direction. Multiple first conductive patterns extend across and connect to the fins in the second direction, and the first conductive patterns and the dummy gates are alternately spaced in the first direction; At least one second conductive pattern is located on and connected to the dummy gate; as well as At least one dummy guide hole is located on and connected to the at least one second conductive pattern.

2. The semiconductor structure with single diffusion blocking as claimed in claim 1, wherein the first conductive patterns are at the same height as the at least one second conductive pattern.

3. The semiconductor structure with single diffusion blocking as claimed in claim 1, wherein the at least one second conductive pattern is two second conductive patterns, respectively located at both ends of the polysilicon pattern.

4. The semiconductor structure with single diffusion blocking as described in claim 3, wherein the at least one dummy via is two dummy vias, respectively located on the two second conductive patterns.

5. The semiconductor structure with single diffusion blocking as claimed in claim 3, wherein the at least one dummy via is a dummy vertical interconnect strip that extends in the second direction and is located on the two second conductive patterns.

6. The semiconductor structure with single diffusion blocking as claimed in claim 1, wherein the at least one dummy via is not present on the two first conductive patterns closest to the dummy gate in the first direction.

7. The semiconductor structure with single diffusion blocking as claimed in claim 1, wherein the first conductive patterns are zero metal layer patterns on an oxide-bound layer, the dummy gate is made of polysilicon, the at least one second conductive pattern is a zero metal layer pattern (MP) on polysilicon, the at least one dummy via is a zero metal layer via, and the zero metal layer via is upwardly connected to the first metal layer.

8. The semiconductor structure with single diffusion blocking as claimed in claim 1, wherein the dummy gate spans the fins in the first region and the second region on both sides.

9. A method for manufacturing a single-diffusion blocking structure, comprising: A substrate is provided on which a first region and a second region are defined, the first region and the second region being adjacent in a first direction; Multiple fins are formed on the base, and these fins protrude from the base and extend in the first direction; Shallow grooves are formed on the fins between the first region and the second region; A first dielectric layer is filled into the shallow trench to form a first shallow trench isolation structure; A dummy gate is formed on the first shallow trench isolation structure between the first region and the second region, and the dummy gate extends in the second direction; At least one second conductive pattern is formed on the dummy gate; as well as At least one dummy via is formed on the at least one second conductive pattern.

10. The method for manufacturing a single diffusion blocking structure as claimed in claim 9, wherein the step of forming the fins on the substrate includes a first cutting process and a second cutting process, and the step of forming the shallow trench is performed after the second cutting process.

11. The method of manufacturing a single diffusion blocking structure as claimed in claim 10, further comprising depositing a second dielectric layer around the fins after the second cutting fabrication process and before the shallow trench is formed, thereby forming a second shallow trench isolation structure.

12. The method for manufacturing a single diffusion blocking structure as described in claim 11 further includes removing portions of the first shallow trench isolation structure and the second shallow trench isolation structure by performing a back etching process after the first shallow trench isolation structure and the second shallow trench isolation structure are formed, thereby reducing the height of the first shallow trench isolation structure and the second shallow trench isolation structure so that the fins protrude.

13. The method for manufacturing a single diffusion blocking structure as claimed in claim 9, wherein the step of forming the fins on the substrate includes a first cutting process and a second cutting process, and the step of forming the shallow trench is performed between the first cutting process and the second cutting process.

14. The method of manufacturing a single diffusion blocking structure as claimed in claim 13, further comprising forming the first dielectric layer around the fins and in the shallow trench after the second cutting fabrication process.

15. The method for manufacturing a single diffusion blocking structure as described in claim 14 further includes removing a portion of the first shallow trench isolation structure by a back etching process after the first shallow trench isolation structure is formed, thereby reducing the height of the first shallow trench isolation structure and causing the fins to protrude.

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