Silicon-on-insulator substrate and its formation method

Abstract

This disclosure relates to a silicon-on-insulator (SOI) substrate and a method for forming the same. In the method for forming an SOI substrate, a stop layer may be formed on a first wafer having a first surface and a second surface facing each other, the stop layer having an etch selectivity different from that of the first wafer. A semiconductor layer with an etch selectivity different from that of the stop layer may be formed on the stop layer. A buried insulating layer may be formed on the semiconductor layer. The buried insulating layer may be formed by applying compressive stress conditions such that the height of the central portion of the buried insulating layer is formed to be higher than the height of the edge portion of the buried insulating layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2024-0163986, filed on November 18, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure generally relate to silicon-on-insulator (SOI) substrates and methods of forming the same, and more specifically to SOI substrates configured to improve stress imbalances and methods of forming the SOI substrates. Background Technology

[0004] Semiconductor memory devices, such as DRAM (Dynamic Random Access Memory) devices, may require high memory operation speeds and high integration density. However, the capacitors configured to perform memory operations in DRAM devices may face limitations in increasing their capacity within the limited area of ​​the chip.

[0005] To address this issue, a semiconductor memory device utilizing vertical-channel transistors as switching elements has been proposed. For example, vertical-channel transistors can be fabricated in an SOI substrate to achieve complete isolation between the channels of adjacent vertical-channel transistors formed in the SOI substrate.

[0006] Currently, SOI substrates can be formed by bonding donor wafers and processing wafers together. The characteristics of semiconductor memory devices can depend on the bonding characteristics of the donor and processing wafers. Summary of the Invention

[0007] Various embodiments of this disclosure provide a method for forming an SOI substrate that can alleviate stress on a semiconductor layer by improving the bonding characteristics between a donor wafer and a processing wafer.

[0008] Embodiments of this disclosure also provide an SOI substrate manufactured by the method described above for forming an SOI substrate.

[0009] According to one embodiment of this disclosure, a method for forming an SOI substrate is provided. In the method for forming an SOI substrate, a stop layer may be formed on a first wafer having a first surface and a second surface facing each other. The stop layer may have an etch selectivity different from that of the first wafer. A semiconductor layer with an etch selectivity different from that of the stop layer may be formed on the stop layer. A buried insulating layer may be formed on the semiconductor layer. The buried insulating layer may be formed by applying compressive stress to it, such that the height of the central portion of the buried insulating layer is higher than the height of the edge portion of the buried insulating layer.

[0010] According to one embodiment of this disclosure, a method for forming an SOI substrate is provided. In the method for forming an SOI substrate, a stop layer, a semiconductor layer, a buried insulating layer, and a first bonding insulating layer can be sequentially formed on a first wafer to form a first structure. A second bonding insulating layer can be formed on a second wafer to form a second structure. The first structure can be bonded to the second structure so that the first bonding insulating layer is in contact with the second bonding insulating layer. The first wafer and the stop layer can be sequentially removed to transfer the semiconductor layer onto the second structure. The buried insulating layer can be formed under certain process conditions such that the height of the central portion of the buried insulating layer can be higher than the height of the edge portion of the buried insulating layer.

[0011] According to one embodiment of this disclosure, an SOI substrate is provided. The SOI substrate may include a wafer, a bonding insulating layer, a buried insulating layer, and a semiconductor layer. The bonding insulating layer may be formed on the wafer. The buried insulating layer may be formed on the bonding insulating layer. The semiconductor layer may be formed on the buried insulating layer.

[0012] In one embodiment of this disclosure, the embedded insulating layer may include a first TEOS insulating layer and a second TEOS insulating layer. The first TEOS insulating layer may contact the semiconductor layer. The first TEOS insulating layer may have a first thickness. The second TEOS insulating layer may be formed on the surface of the first TEOS insulating layer. The second TEOS insulating layer may have a second thickness different from the first thickness. The density of the second TEOS insulating layer may be greater than the density of the first TEOS insulating layer.

[0013] According to one embodiment of this disclosure, a buried insulating layer can be formed on a first wafer under conditions where high compressive stress can be provided. Therefore, even if a buried insulating layer with a uniform thickness can be formed, it can deform due to the high compressive stress, allowing the height of the central portion of the buried insulating layer to be higher than the height of its edge portions. This deformation of the buried insulating layer improves the bonding efficiency of the central portion during bonding of the first and second wafers. Furthermore, one embodiment of the buried insulating layer may include a TEOS insulating layer using a TEOS precursor with a high hydrogen content to ensure sufficient compressive stress. By performing the deposition process at a temperature of approximately 300°C to approximately 550°C, a relatively high compressive stress can be formed, which is higher than the process temperature of conventional PEALD (plasma-enhanced atomic layer deposition) methods. Moreover, during the deposition of the TEOS insulating layer, the flow rate of the reaction source can be increased compared to the TEOS precursor to further increase the compressive stress.

[0014] Furthermore, in one embodiment of this disclosure, the buried insulating layer can be formed in a dual plasma deposition chamber, wherein LF power and HF power can be alternately supplied at least once, thereby increasing the compressive stress. As described above, since the LF power and HF power can be alternated at least once, the buried insulating layer can be formed as a structure in which the LF insulating layer and the HF insulating layer can be stacked at least once. In this case, the HF insulating layer can provide a relatively high density, which can enhance the compressive stress. The LF insulating layer can increase the deposition rate and prevent residual oxygen atoms generated during the formation of the HF insulating layer from diffusing into the semiconductor layer. By using the dual plasma deposition method to form the buried insulating layer, sufficient compressive stress and deposition rate can be ensured, and the diffusion of oxygen components into the semiconductor layer can be prevented. Attached Figure Description

[0015] The above and other aspects, features and advantages of the subject matter of this disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0016] Figures 1A to 1E This is a cross-sectional view showing a method for forming a first structure according to an embodiment of the present disclosure;

[0017] Figure 2 This is a flowchart illustrating a method for forming a first structure according to an embodiment of the present disclosure;

[0018] Figure 3 This is a cross-sectional view showing a plasma deposition apparatus configured to deposit a buried insulating layer according to an embodiment of the present disclosure;

[0019] Figure 4A and Figure 4B This is a cross-sectional view showing an embedded insulating layer according to an embodiment of the present disclosure;

[0020] Figure 5 This is a cross-sectional view showing a second structure according to an embodiment of the present disclosure;

[0021] Figure 6 This is a flowchart illustrating a method for forming a second structure according to an embodiment of the present disclosure;

[0022] Figures 7A to 7C This is a cross-sectional view illustrating a method for fabricating an SOI substrate using a first structure and a second structure according to an embodiment of the present disclosure; and

[0023] Figure 8 This is a flowchart illustrating a method for manufacturing an SOI substrate according to an embodiment of the present disclosure. Detailed Implementation

[0024] The advantages and features of the embodiments of this disclosure, as well as the methods of implementing them, will become apparent when the embodiments are described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments disclosed herein, but may be implemented in many other different embodiments, forms, or variations of the described embodiments. These described embodiments are provided to complete the disclosure of the invention and to enable those skilled in the art to fully understand the technical concept and scope of the embodiments as defined by the claims. For clarity, the dimensions and relative sizes of layers and regions in the figures may be exaggerated. Throughout the specification, the same reference numerals refer to the same components.

[0025] An SOI substrate, comprising a semiconductor layer and a buried insulating layer, can be formed by bonding a first wafer and a second wafer. To improve the bonding characteristics between the first and second wafers, the buried insulating layer can be formed with compressive stress, such that the central portion has a more convex shape than the edges. Therefore, when bonding the first and second wafers, bonding can be performed from the central portion, thereby improving the bonding characteristics between the first and second wafers.

[0026] Figures 1A to 1E This is a cross-sectional view illustrating a method for forming a first structure according to an embodiment of the present disclosure. Figure 2 This is a flowchart illustrating a method for forming a first structure according to an embodiment of the present disclosure.

[0027] refer to Figure 1A and Figure 2 A first wafer 100 (S1) may be provided having a first surface 100a and a second surface 100b opposite to each other. For example, the first wafer 100 may be a donor wafer that can be sacrificed and subsequently removed. The first wafer 100 may include at least one of the following materials: Si, Ge, SiC, group IV-IV, group III-V or group II-VI semiconductor compounds and piezoelectric materials (such as, for example, LiNbO3 and LiTaO3).

[0028] refer to Figure 1B and Figure 2 A stop layer 110 can be formed on the first surface 100a of the first wafer 100 (S2). The stop layer 110 can be a layer that prevents the loss of a subsequently formed semiconductor layer when the first wafer 100 can be removed. Therefore, the stop layer 110 can include a material having etch selectivity with the first wafer 100. Furthermore, the stop layer 110 can be formed of a semiconductor material having properties that are as small as possible compared to the semiconductor layer to be formed. In one embodiment of this disclosure, the stop layer 110 can be formed of a single-crystal SiGe layer. In addition, the stop layer 110 can be formed with a thickness of 1 nm to 100 nm to protect the semiconductor layer to be formed during subsequent operations when the first wafer 100 is removed.

[0029] refer to Figure 1C and Figure 2 A semiconductor layer 120 can be formed on the stop layer 110 (S3). In one embodiment, the semiconductor layer 120 can be a region in a semiconductor memory device where a transistor channel can be formed. For example, the semiconductor layer 120 can include a single-crystal Si material.

[0030] In one embodiment of this disclosure, the stop layer 110 and the semiconductor layer 120 can be formed by epitaxial growth in situ. For example, the semiconductor layer 120 can be formed to have a thickness of 5 nm to 500 nm, but the embodiments are not limited thereto.

[0031] For example, the lattice constant of the SiGe material used as the stop layer 110 can be greater than the lattice constant of the Si material used as the semiconductor layer 120. Therefore, when the stop layer 110 including the SiGe material and the semiconductor layer 120 including the Si material are epitaxially grown sequentially, the semiconductor layer 120 including the Si material can be grown under a first condition with a first compressive stress.

[0032] Next, refer to Figure 1D and Figure 2 A buried insulating layer 130 can be formed on the semiconductor layer 120 (S4). The buried insulating layer 130 can be formed under a second condition where a second compressive stress greater than the first compressive stress is applied. Since the second compressive stress of the buried insulating layer 130 is greater than the first compressive stress of the semiconductor layer 120, the buried insulating layer 130 can be formed such that the height of the central portion of the buried insulating layer 130 can be relatively higher than the height of the edge portion of the buried insulating layer 130.

[0033] The embedded insulation layer 130 can be formed by changing at least one process condition (such as process gas, process method and process temperature) to increase the compressive stress of the embedded insulation layer 130.

[0034] In one embodiment of this disclosure, the embedded insulating layer 130 can be formed using a plasma-enhanced tetraethyl orthosilicate (PETEOS) precursor with a relatively high hydrogen content to form the TEOS insulating layer. Furthermore, the TEOS insulating layer can be formed by plasma deposition to provide higher compressive stress. Additionally, the TEOS precursor can include a greater amount of hydrogen than SixHy series gases (such as silane gases). Therefore, the compressive stress increases when using a TEOS precursor with a higher hydrogen content as the source gas compared to using SixHy gas as the source gas. However, the supply ratio of silane gas can be increased, or SixHy series gases, such as monosilane, disilane, or trisilane, can be used with their hydrogen content adjusted to the level of the TEOS precursor.

[0035] Figure 3This is a cross-sectional view showing a plasma deposition apparatus configured to deposit a buried insulating layer according to an embodiment of the present disclosure.

[0036] See Figure 3 The plasma deposition apparatus 30 may include a plasma deposition chamber 300, a nozzle 310, a substrate support block 320, and a plasma power supply 350. Furthermore, the plasma deposition apparatus 30 may also include a gas supply device 340, a matching network 360, and a controller 380. In one embodiment, the plasma deposition apparatus 30 may include a plasma-enhanced atomic layer deposition (PEALD) chamber or a plasma-enhanced chemical vapor deposition (PECVD) chamber.

[0037] The plasma deposition chamber 300 may include a body 301 and a top cover 305. The body 301 may define a space for depositing a thin layer on a wafer. The body 301 may have an open top. The top cover 305 may be mounted on the top periphery of the body 301. The top cover 305 may have a cover shape with a window (not shown) into which a nozzle 310 can be inserted. The body 301 may have a door G on a side of the body 301, the door being configured to allow a wafer to be loaded or unloaded through the door G.

[0038] The plasma deposition apparatus 30 may also include an exhaust port 302 connected to the plasma deposition chamber 300 and a pump 303 connected to the exhaust port 302. The pump 303 can evacuate the interior of the plasma deposition chamber 300 and remove process residues from the plasma deposition chamber 300.

[0039] The nozzle 310 can be connected to a gas supply device 340 to inject source gas and reactive gas onto the first wafer 100 on the substrate support block 320. In one embodiment of the invention, the nozzle 310 can be electrically connected to a power supply 350 to serve as a first electrode for generating plasma.

[0040] The substrate support block 320 may include a base 322 and a support shaft 324. The base 322 may have an integral flat plate shape to support at least one first wafer 100. The support shaft 324 may be vertically coupled to the rear of the base 322. The support shaft 324 may be provided with a driving force to raise, lower, and / or rotate the base 322. In one embodiment of this disclosure, the base 322 may include a heater 325. The heater 325 may be adapted to regulate the temperature of the first wafer 100 to be processed. Furthermore, the substrate support block 320 may receive a ground voltage to serve as a second electrode for generating plasma.

[0041] For example, the gas supply device 340 may include at least one source gas supply device 340a and at least one reaction gas supply device 340b.

[0042] For example, the source gas supply device 340a may include a TEOS precursor. Alternatively, in another embodiment, the source gas may include the SixHy series, such as monosilane, disilane, and trisilane, whose hydrogen content is adjusted to the level of the TEOS precursor.

[0043] The reaction gas supply device 340b may include a gas containing oxygen, such as O2 gas or N2O source.

[0044] The gas supply device 340 can be connected to the nozzle 310 via the gas supply line L. At least one valve V1 and V2 can be installed in the gas supply line L, which is connected to at least one source gas supply device 340a and at least one reaction gas supply device 340b, respectively. Valves V1 and V2 can regulate the gas supply in the gas supply line 340.

[0045] The plasma power supply 350 may include a first power supply 351 and a second power supply 353.

[0046] For example, the first power source 351 can provide the plasma deposition chamber 300 (such as nozzle 310) with high-frequency (hereinafter referred to as HF) power with a center frequency band of about 10 MHz to about 40 MHz (such as about 13.56 MHz).

[0047] The second power source 353 can supply low-frequency (hereinafter referred to as LF) power with a center frequency band of about 300 kHz to about 500 kHz (such as 370 kHz) to the plasma deposition chamber 300 (such as nozzle 310).

[0048] For example, the plasma deposition apparatus 30 in the embodiment may be a dual plasma deposition apparatus with different applied powers.

[0049] Matching network 360 may include a first matching unit 361 and a second matching unit 363. The first matching unit 361 can be connected between the first power supply 351 and the nozzle 310. The first matching unit 361 matches the output impedance of the first power supply 351 with the load impedance of the plasma deposition chamber 300. The second matching unit 362 can be connected between the second power supply 353 and the nozzle 310, and it matches the output impedance of the second power supply 353 with the load impedance of the plasma deposition chamber 300. Therefore, the reflection losses of the HF and LF power supplies can be reduced.

[0050] The controller 380 can be configured to control the overall operation of the plasma deposition apparatus 30. For example, the controller 380 can control the operation of components 310 to 360 of the plasma deposition apparatus 30 and each of valves V1 and V2.

[0051] More specifically, the controller 380 can control the type of source gas used to form a thin layer on the first wafer 100, the flow rate of the source gas in the gas supply device 340, and the process conditions in the plasma deposition chamber 300 used to form the thin layer.

[0052] In one embodiment of this disclosure, if the plasma deposition apparatus 30 includes a PEALD chamber, the embedded insulating layer 130 can be formed by injecting a TEOS precursor as a source gas at a constant flow rate to adsorb onto the surface of the resulting product, purging unadsorbed TEOS components, supplying a reactive gas to react with the adsorbed TEOS components, and purging unreacted reactive gas components.

[0053] To further increase the compressive stress of the embedded insulating layer 130, the reaction gas used to decompose the TEOS source can be at least one of O2 and N2O.

[0054] For example, the reactant gas can be supplied at a relatively high flow rate relative to the source gas (e.g., TEOS precursor), for example, about 1 to about 10 times, such as 6,000 to 11,000 sccm (standard cubic centimeters per minute). In this way, by increasing the flow rate of the reactant gas relative to the source gas, the compressive stress can be further enhanced.

[0055] In one embodiment of this disclosure, when the embedded insulating layer 130 is formed from a PETEOS insulating layer, the embedded insulating layer 130 is deposited at a temperature of about 300°C to about 550°C, which can be higher than the typical deposition temperature range of about 100°C to about 250°C for PEALD. The increased deposition temperature can improve the decomposition efficiency of the source gas and reactant gas, thereby increasing the density of the embedded insulating layer 130, which can further increase the compressive stress. For example, the deposition temperature can be regulated by a heater 325 in the base 322.

[0056] In addition, in order to generate plasma in the space of plasma deposition chamber 300, an inert gas, such as helium, can be supplied to plasma deposition chamber 300 to increase the compressive stress of the embedded insulating layer 130.

[0057] Figure 4A and Figure 4B This is a cross-sectional view of the embedded insulating layer according to an embodiment of the present disclosure.

[0058] refer to Figure 3 , Figure 4A and Figure 4B The embedded insulation layer 130 may include LF insulation layer 130a and HF insulation layer 130b that are stacked alternately at least once.

[0059] For example, LF power and HF power can be alternately supplied to nozzle 310 by controlling plasma power supply 350 to alternately deposit LF insulating layer 130a and HF insulating layer 130b at least once.

[0060] For example, the LF power can range from about 500 watts to about 5,000 watts. The LF insulating layer 130a formed by applying LF power to the nozzle 310 can be more porous than the HF insulating layer 130b. The porous LF insulating layer 130a can prevent the embedded insulating layer 130 from cracking. The LF insulating layer 130a can prevent reactive gas components (e.g., oxygen components) from diffusing into the semiconductor layer 120.

[0061] For example, the HF power can range from about 1,000 watts to about 5,000 watts. Since the plasma potential in the plasma deposition chamber 300 increases due to the HF power, the ion bombardment phenomenon may also increase. Therefore, the HF insulating layer 130b can have a higher density compared to the LF insulating layer 130a, and thus has a relatively higher compressive stress compared to the LF insulating layer 130a.

[0062] In one embodiment of this disclosure, such as Figure 4A As shown, the buried insulating layer 130 may include alternating and repeatedly stacked LF insulating layers 130a (LF TEOS insulating layer) and HF insulating layers 130b (HF TEOS insulating layer). For example, the thickness of the HF insulating layer 130b may be formed to be thicker than the thickness of the LF insulating layer 130a, so that the buried insulating layer 130 as a whole can have compressive stress. In addition, the LF insulating layers 130a located between the HF insulating layers 130b or between the HF insulating layers 130b and the semiconductor layer (not shown) can supplement the overall deposition rate of the buried insulating layer 130 and can prevent the diffusion of reactive gas components remaining during the deposition of the HF insulating layer 130b into the semiconductor layer 120.

[0063] In one embodiment of this disclosure, such as Figure 4B As shown, the buried insulating layer 130 may include an LF insulating layer 130a formed on the semiconductor layer 120 with a first thickness and an HF insulating layer 130b formed on the LF insulating layer 130a with a second thickness greater than the first thickness. Since the HF insulating layer 130b can be formed thicker than the LF insulating layer 130a, the compressive stress of the buried insulating layer 130 can be increased. Furthermore, the LF insulating layer 130a may be located between the HF insulating layer 130b and the semiconductor layer 120, and can block the diffusion of reactive gas components during the formation of the HF insulating layer 130b.

[0064] The buried insulating layer 130 is formed in the manner described above, allowing the height of the central portion of the buried insulating layer 130 to be higher than the height of the edge portions. Therefore, the bonding gap can be reduced in subsequent wafer bonding processes for bonding wafers.

[0065] Subsequently, reference Figure 1E and Figure 2 A first bonded insulating layer 140 may be formed on the embedded insulating layer 130 having a relatively large second compressive stress, as described above (S5), to form the first structure 10. The first bonded insulating layer 140 may include at least one of SiCN, SiO2, and Si3N4. However, various insulating layers having bonding properties may be included herein.

[0066] In one embodiment of this disclosure, the first bonding insulating layer 140 may be formed along the shape of the embedded insulating layer 130. Since the height of the central portion of the embedded insulating layer 130 is higher than the height of the edge portions of the embedded insulating layer 130, the first bonding insulating layer 140 may also have a central portion with a height higher than the edge portions of the first bonding insulating layer 140.

[0067] Figure 5 This is a cross-sectional view showing a second structure according to an embodiment of the present disclosure. Figure 6 This is a flowchart illustrating a method for forming a second structure according to an embodiment of the present disclosure.

[0068] refer to Figure 5 and Figure 6 A second wafer 200 can be prepared (S11). The second wafer 200 may include a first surface 200a and a second surface 200b facing each other. For example, the second wafer 200 may include a carrier substrate. The second wafer 200 may include at least one of Si, SiC, glass, sapphire, AlN or other available materials in the substrate.

[0069] A second bonding insulating layer 210 may be formed on the first surface 200a of the second wafer 200 to form the second structure 20 (S12). The second bonding insulating layer 210 may include a material suitable for bonding with the first bonding insulating layer 140, such as an insulating layer having the same or substantially the same coefficient of thermal expansion as the first bonding insulating layer 140. In one embodiment of this disclosure, the second bonding insulating layer 210 may include at least one of SiCN, SiO2, and Si3N4, which is the same or substantially the same as the first bonding insulating layer 140.

[0070] Figures 7A to 7C This is a cross-sectional view illustrating a method for fabricating an SOI substrate using a first structure and a second structure according to an embodiment of the present disclosure. Figure 8This is a flowchart illustrating a method for manufacturing an SOI substrate according to an embodiment of the present disclosure.

[0071] refer to Figure 7A and Figure 8 The first structure 10 can be stacked on the second structure 20 such that the first bonding insulating layer 140 of the first structure 10 and the second bonding insulating layer 210 of the second structure 20 can face each other. Then, pressure can be applied to the upper surface of the first structure 10 (such as the second surface 100b of the first wafer 100) to bond the first bonding insulating layer 140 to the second bonding insulating layer 210, thereby bonding the first structure 10 to the second structure 20 (S21). Reference numeral 220 indicates a bonding layer formed by bonding the first bonding insulating layer 140 and the second bonding insulating layer 210 together.

[0072] In one embodiment of this disclosure, the bonding process between the first structure 10 and the second structure 20 can be performed by direct bonding, hot pressing, or electrostatic bonding, including molecular adhesion, but the embodiments are not limited thereto.

[0073] As described above, since the buried insulating layer 130 can be subjected to high pressure stress, the height of the central portion of the first bonding insulating layer 140 formed along the surface of the buried insulating layer 130 can be increased relative to the height of the edge portion of the first bonding insulating layer 140. In other words, through the compressive stress of the buried insulating layer 130, the shape of the first structure 10 can be deformed and adjusted to facilitate bonding with the second structure 20. Since bonding begins from the center of the wafer, the bonding gap at the wafer edge can be improved.

[0074] In one embodiment of this disclosure, the surface of the first bonding insulating layer 140 of the first structure 10 and the surface of the second bonding insulating layer 210 of the second structure 20 can be cleaned before the bonding process of the first structure 10 and the second structure 20.

[0075] refer to Figure 7B and Figure 8 The first wafer 100 of the first structure 10 can be removed to expose the stop layer 110. The first wafer 100 can be selectively removed using a smart dicing method. Smart dicing methods may include, for example, laser dicing, plasma etching, or mechanical scribing. Smart dicing ensures clean and accurate separation without damaging the remaining structure. Alternatively, the first wafer 100 can be selectively removed using annealing and grinding methods. Furthermore, the first wafer 100 can be selectively removed using annealing, grinding, and chemical mechanical polishing (CMP) processes.

[0076] When the first wafer 100 can be selectively removed, the semiconductor layer 120 located on the first wafer 100 can be transferred to the second structure 20 (S22).

[0077] refer to Figure 7C and Figure 8 Optionally, the stop layer 110 can be removed to form an SOI substrate (S23).

[0078] In one embodiment of this disclosure, the stop layer 110 may comprise a SiGe material having a different etch selectivity than the semiconductor layer 120 comprising a Si material, as described above, such that it can be selectively removed using a plasma etching process. However, various etching processes may be included herein without affecting the properties of the semiconductor layer 120.

[0079] Subsequently, although not shown in the figure, various semiconductor devices, such as three-dimensional semiconductor devices with vertical channels, can be fabricated within the semiconductor layer 120 of the SOI substrate.

[0080] According to one embodiment of this disclosure, the buried insulating layer formed on the first wafer can be formed under conditions that provide strong compressive stress. Therefore, even though a buried insulating layer with a uniform thickness can be formed, due to the strong compressive stress, the buried insulating layer can deform such that the height of the central portion of the buried insulating layer can be in the form of the height of the edge portion. Due to the shape deformation of the buried insulating layer, when bonding the first wafer and the second wafer, bonding begins from the center of the first wafer and the second wafer, which can effectively reduce or completely prevent the formation of any bonding voids, including at the edges of the first wafer and the second wafer.

[0081] Furthermore, one embodiment of the embedded insulating layer may include a TEOS insulating layer using a TEOS precursor with a high hydrogen content to ensure sufficient compressive stress. By performing the deposition process at a temperature of 300°C to 550°C, a relatively high compressive stress can be deposited, which is higher than the process temperature of a typical PEALD process. Additionally, during the deposition of the TEOS insulating layer, the flow rate of the reactive gas can be increased compared to that of the TEOS precursor to further increase the compressive stress.

[0082] Furthermore, in one embodiment, the buried insulating layer can be formed in a dual plasma deposition chamber, where LF power and HF power can be alternately supplied at least once, thereby increasing the compressive stress. Therefore, as described above, since the LF power and HF power can be alternated at least once, the buried insulating layer can be formed with a structure in which LF insulating layers and HF insulating layers are stacked at least once. Thus, the HF insulating layer can provide a relatively high density, which can enhance the compressive stress. The LF insulating layer can increase the deposition rate and prevent residual oxygen atoms generated during the formation of the HF insulating layer from diffusing into the semiconductor layer. Forming the buried insulating layer using this dual plasma deposition process ensures sufficient compressive stress and deposition rate, and prevents oxygen diffusion into the semiconductor layer.

[0083] Although this disclosure has been described in detail with reference to various embodiments, the invention is not limited to the embodiments described above. Many modifications can be conceived by those skilled in the art, all of which fall within the scope of this disclosure. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A method for forming an SOI substrate, SOI referring to silicon-on-insulator, the method comprising: A first wafer is provided, the first wafer including a first surface and a second surface opposite to each other; A stop layer is formed on the first wafer, the stop layer having an etching selectivity different from that of the first wafer; A semiconductor layer is formed on the stop layer, the semiconductor layer having an etching selectivity different from that of the stop layer; as well as An embedded insulating layer is formed on the semiconductor layer. The embedded insulating layer is deposited under compressive stress, and the height of the central portion of the embedded insulating layer is formed to be higher than the height of the edge portion of the embedded insulating layer.

2. The method according to claim 1, wherein, The stop layer includes a SiGe layer, and The semiconductor layer includes a single-crystal Si layer.

3. The method according to claim 1, wherein, Forming the stop layer includes: forming a SiGe layer based on the first wafer using an epitaxial growth process, and The formation of the semiconductor layer includes forming a Si layer based on the stop layer through the epitaxial growth process.

4. The method according to claim 1, wherein, Forming the embedded insulation layer includes: forming the TEOS insulation layer using a TEOS precursor and a reactive gas including oxygen.

5. The method according to claim 4, wherein, The flow rate of the reactant gas, including the oxygen, is supplied at a rate of 1 to 10 times that of the TEOS precursor.

6. The method according to claim 1, wherein, The embedded insulating layer is formed in a plasma deposition chamber.

7. The method according to claim 6, wherein, Forming the embedded insulating layer includes: alternately applying LF power and HF power to the plasma deposition chamber at least once, where LF refers to low frequency and HF refers to high frequency.

8. The method according to claim 6, wherein, Forming the embedded insulation layer includes: Applying LF power to the plasma deposition chamber to deposit an LF insulating layer having a first thickness on the semiconductor layer; and HF power is applied to the plasma deposition chamber to deposit an HF insulating layer with a second thickness, which is different from the first thickness, on the LF insulating layer.

9. The method according to claim 8, wherein, The second thickness is greater than the first thickness.

10. The method according to claim 1, wherein, The embedded insulating layer is formed at a temperature of 300°C to 550°C by PEALD, which stands for Plasma Enhanced Atomic Layer Deposition.

11. The method according to claim 1, further comprising: A first bonding insulating layer is formed on the embedded insulating layer to form a first structure; A second bonding insulating layer is formed on the second wafer to form a second structure; The first structure is stacked on the second structure so that the first bonding insulating layer faces the second bonding insulating layer; The second structure is bonded to the first structure; Remove the first wafer of the first structure; as well as The stop layer is selectively etched.

12. A method for forming an SOI substrate, the method comprising: The first structure is formed by sequentially depositing a stop layer, a semiconductor layer, a buried insulating layer and a first bonding insulating layer on a first wafer; The second structure is formed by forming a second bonding insulating layer on the second wafer; The first structure is bonded to the second structure so that the first bonding insulating layer contacts the second bonding insulating layer; as well as The semiconductor layer is transferred onto the second structure by sequentially removing the first wafer and the stop layer. The embedded insulating layer is formed under at least one process condition such that the height of the central portion of the embedded insulating layer is higher than the height of the edge portion of the embedded insulating layer.

13. The method according to claim 12, wherein, Depositing the buried insulating layer includes: The first wafer, on which the semiconductor layer is formed, is loaded into the plasma deposition chamber; LF power is applied to the plasma deposition chamber to deposit an LF TEOS insulating layer on the semiconductor layer, where LF refers to low frequency; and HF power is applied to the plasma deposition chamber to deposit an HF TEOS insulating layer on the LF TEOS insulating layer. HF refers to high frequency. The LF TEOS insulating layer and the HF TEOS insulating layer are deposited alternately at least once.

14. The method according to claim 13, wherein, The LF TEOS insulating layer and the HF TEOS insulating layer are deposited to have different thicknesses.

15. The method according to claim 12, wherein, The embedded insulating layer is formed of TEOS insulating layer. The TEOS insulating layer is formed by supplying a TEOS precursor as a source gas and a reactant gas including oxygen. The flow rate of the reactant gas, including the oxygen, is supplied at a rate of 1 to 10 times that of the TEOS precursor.

16. The method according to claim 15, wherein, The TEOS insulating layer is formed at a temperature of approximately 300°C to approximately 550°C using a PEALD process, where PEALD stands for Plasma Enhanced Atomic Layer Deposition.

17. An SOI substrate, comprising: Chips; A bonding insulating layer is formed on the wafer; An insulating layer is embedded thereon, which is formed on the bonded insulating layer; as well as A semiconductor layer is formed on the buried insulating layer. The embedded insulating layer includes: A first TEOS insulating layer, which is in contact with the semiconductor layer and has a first thickness; and A second TEOS insulating layer is formed on the surface of the first TEOS insulating layer, and the second TEOS insulating layer has a second thickness different from the first thickness. The density of the second TEOS insulating layer is greater than that of the first TEOS insulating layer.

18. The SOI substrate according to claim 17, wherein, The first TEOS insulating layer and the second TEOS insulating layer are stacked alternately at least once.

19. An SOI substrate, comprising: Chips; A bonding insulating layer is formed on the wafer; An insulating layer is embedded thereon, which is formed on the bonded insulating layer; as well as A semiconductor layer is formed on the buried insulating layer. The embedded insulating layer includes: A first insulating layer, which is in contact with the semiconductor layer; and A second insulating layer is formed on the surface of the first insulating layer. The thickness of the second insulating layer is greater than the thickness of the first insulating layer.

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