Memory control method and storage device

Abstract

The application belongs to the field of memory control, and provides a memory control method and a memory device. The method comprises the following steps: in response to a voltage abnormal event, obtaining an operation state of a memory module and determining an abnormal level; if the operation state is busy, sending a transmission suspension command to a host system, and judging whether the memory module supports an operation suspension function; if the memory module supports the operation suspension function, sending a suspension execution command, otherwise marking that the operation needs to be re-executed; recording an operation context containing a progress parameter, and writing the operation context into a non-volatile backup area when a supply voltage is higher than a backup voltage threshold; setting a timing duration according to the abnormal level; if the supply voltage returns to normal before the timing duration expires, reading the operation context and continuing to execute the suspended operation from a suspension point. The application executes differentiated interruption protection according to hardware capability when the voltage is abnormal, and realizes breakpoint continuation after the voltage returns to normal, thereby effectively improving the data reliability of the memory device in a severe power supply environment.

Description

Technical Field

[0001] This application relates to the field of memory control, and more particularly to a memory control method and a memory device. Background Technology

[0002] With the widespread application of mobile terminals and embedded systems, storage devices using non-volatile memory as the storage medium, such as secure digital cards, embedded multimedia memory cards, and solid-state drives (SSDs), have become core components for data storage. In practical applications, the power supply voltage of storage devices is not always stable. When the storage device is operating in a portable device, a decrease in battery power may cause the power supply voltage to gradually drop; when connected to an interface with insufficient power supply, hot-swapping operations may cause voltage interruptions; in scenarios where multiple devices share a power source, the startup of high-power devices may also cause voltage drops. All of these fluctuations in power supply voltage can trigger abnormal operating states of the storage device.

[0003] In response to abnormal voltage conditions, existing technologies typically employ simple countermeasures. One approach is to immediately halt ongoing read / write operations and report an error status to the host system when the supply voltage is detected to be below the operating threshold. Another approach is to directly perform a hardware reset on the storage device during a voltage anomaly, causing it to restart. However, both of these methods have significant drawbacks. Directly halting operations may result in data corruption because the data being written may not be fully stored on the storage medium. Directly resetting the device will cause the loss of the address mapping table and operating state maintained internally by the memory module. Once the voltage recovers, the storage device cannot return to the pre-interruption operating state, affecting data integrity and system stability. Summary of the Invention

[0004] In view of this, this application provides a memory control method and a storage device to solve the technical problem of unstable operation of storage devices due to power failure in the prior art.

[0005] This application provides a memory control method applied to a storage device including a memory module and a memory controller. The method includes: in response to a voltage anomaly event occurring in the storage device, obtaining the current operating state of the memory module and determining the voltage anomaly level; if the operating state is busy, executing a safety interruption procedure: sending a stop transmission command to the host system and determining whether the memory module supports an operation pause function; if it supports it, sending a pause execution command to the memory module to pause the currently executed operation; if it does not support it, marking that the current operation needs to be re-executed after recovery; recording the operation context of the paused operation and writing the operation context into the non-volatile backup area of ​​the memory module, wherein the operation context includes the progress parameters of the paused operation, and the progress parameters include at least the amount of data already transmitted. The data length or completed operation stage; before writing the operation context, it is determined whether the current power supply voltage is higher than the preset backup voltage threshold. If so, the write operation is performed; otherwise, the write operation is skipped and the process jumps directly to the abnormal recovery process. A timeout duration is set according to the voltage abnormality level. If the power supply voltage recovers to the preset normal voltage threshold range before the timeout duration expires, the operation context in the non-volatile backup area is read, and the recovery process of the suspended operation is executed based on the read operation context to continue the programming or erasure operation from the pause point. If a voltage abnormality is detected again during the recovery process, the recovery is abandoned and the abnormal recovery process is entered. If the power supply voltage still fails to recover to the normal voltage threshold range after the timeout duration expires, the abnormal recovery process is executed, which includes an ordered restart process.

[0006] An embodiment of this application further provides a storage device, which includes a connection interface for electrically connecting to a host system; a memory module including multiple planes, each plane including multiple blocks, each block including multiple pages; and a memory controller including error checking and correction circuitry, a buffer memory, and memory control circuitry, electrically connected to the connection interface and the memory module; wherein the memory controller is configured to perform the memory control method described above.

[0007] The beneficial effects of this application are: By associating power supply voltage anomaly detection with the memory module's operational status, and executing a safety interrupt procedure that includes halting transmission to the host system and suspending execution of the memory module during busy states, the system avoids the problems of incomplete data writing and address mapping loss caused by direct operation stoppage or reset in existing technologies. By writing the operation context of the suspended operation to a non-volatile backup area, the system ensures that the interrupted operation's context information is reliably preserved even after a complete power supply loss, providing a precise basis for autonomous resumption of operation after voltage recovery. Furthermore, by dynamically setting the timer's waiting duration based on the voltage anomaly level, a reasonable balance is achieved between effectively filtering instantaneous voltage fluctuations and rapidly responding to severe anomalies, avoiding unnecessary recovery process triggering and improving the robustness of the storage device in complex power supply environments. When the voltage recovers within the timed period, the recovery procedure is executed by reading the operation context, achieving automatic continuation of the interrupted operation without requiring the host system to reissue the complete instruction sequence, significantly improving the operational continuity and data reliability of the storage device.

[0008] To make the above-mentioned objectives, technical solutions and beneficial effects of this application more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, and these are all within the protection scope of this application.

[0010] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application; Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application; Figure 3 This is a flowchart illustrating a memory control method according to an embodiment of this application; Figure 4 This is a schematic flowchart of the voltage anomaly event determination method provided in the embodiments of this application; Figure 5 This is a schematic diagram of the process for obtaining the operating status of a memory module according to an embodiment of this application; Figure 6 This is a schematic diagram of the timer duration setting process provided in the embodiments of this application; Figure 7 This is a schematic diagram of the operation context writing process provided in the embodiments of this application; Figure 8This is another schematic flowchart illustrating a memory control method according to an embodiment of this application. Detailed Implementation

[0011] Reference will now be made in detail to exemplary embodiments of this application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0012] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, automotive infotainment system, advanced driver assistance system (ADAS), game console, server, or computer system installed in a specific carrier (e.g., vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. Furthermore, the storage device 12 can include solid-state drives (SSDs), universal flash storage (UFS), embedded multi-media cards (eMMC), USB flash drives, memory cards, or other types of non-volatile storage devices. It is particularly suitable for fields with stringent requirements for reliability, data integrity, environmental tolerance, and long-term stability, such as industrial control, edge computing, and automotive electronics.

[0013] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multimedia cards, general-purpose flash memory, Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0014] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics. For multi-level memory cells, such as MLC (Multi Level Cell), TLC (Triple Level Cell), QLC (Quad Level Cell), and PLC (Penta Level Cell), flash memory modules that have undergone special screening and testing can be used to meet the requirements of wide operating temperature range (e.g., -40°C to 105°C or higher), high durability, and data retention.

[0015] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller. In particular, for automotive functional safety requirements, the architecture of memory controller 123 may include safety islands, dual-core lockstep, or other redundancy and monitoring mechanisms to ensure the reliability of control logic.

[0016] The memory controller 123 can send instruction sequences to the memory module 122 to access data in the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in this application. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0017] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0018] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0019] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and controlled by the memory controller 123 to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. Specifically, the logical-to-physical mapping table and its higher-level address management unit are typically resident or cached in the buffer memory 24 to support high-speed access and updates. To ensure the reliability and consistency of the mapping table data (described in detail below) in the event of sudden events such as abnormal power failures, the buffer memory 24 may employ a storage medium with power loss protection (PLP) characteristics or incorporate a backup capacitor design to ensure that critical metadata has sufficient time to be written into the memory module 122.

[0020] In one embodiment, the memory controller 123 may further include an error checking and correction circuit 25. The error checking and correction circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the error checking and correction circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code.

[0021] In one embodiment, the memory controller 123 may also include other types of various circuit modules (e.g., power management circuits, etc.), which are not limited in this application.

[0022] In one embodiment, the memory controller 123 may further include a power management circuit 26. The power management circuit 26 is connected to the memory control circuit 23 and is used to control the power supply of the storage device 12. The power management circuit 26 not only manages conventional power consumption, but also meets the complex power sequences and low static power consumption requirements of automotive electronics, and can handle voltage fluctuations during vehicle start-stop processes, ensuring that the storage device 12 operates stably in harsh power environments.

[0023] In one embodiment, the memory controller 123 may further include an analog-to-digital converter 27 for converting the acquired analog signal into a digital signal, such as converting an analog voltage signal into a digital voltage signal.

[0024] Figure 3This is a general flowchart of a memory control method shown in an embodiment of this application. The method is applied to a storage device 12 including a memory module 122. A memory control circuit 23 or a memory controller 123 is configured to perform this method. The method begins at step S1.

[0025] S1. In response to a voltage anomaly event in the storage device, obtain the current operating status of the storage module and determine the voltage anomaly level.

[0026] In this embodiment, a voltage anomaly event refers to a state triggered by the supply voltage exceeding a preset normal voltage threshold range for multiple (M) consecutive monitoring cycles, requiring the activation of a protection response. The operating state indicates the status of the memory module, i.e., whether it is currently performing a programming or erasing operation, and its busy / idle status. The voltage anomaly level is determined by the magnitude of the voltage deviation between the supply voltage and the normal voltage threshold range.

[0027] Further, see Figure 4 As shown, Figure 4 This is a schematic flowchart of the voltage anomaly event determination method provided in the embodiments of this application, which specifically includes the following steps: A1. Based on the preset sampling frequency, the voltage data of the power supply interface of the storage device is acquired through an analog-to-digital converter.

[0028] Specifically, the memory controller integrates an analog-to-digital converter (ADC), whose input is electrically connected to the power supply interface of the storage device. During initialization, the ADC's operating parameters are configured to put it into a ready state that can be triggered periodically. A hardware timer is maintained, which periodically generates a trigger signal according to a preset sampling frequency. The specific value of the sampling frequency can be preset according to the power supply noise characteristics of the environment in which the storage device is used. Each time a trigger signal is generated, the ADC performs a sample-and-hold operation and analog-to-digital conversion on the current analog voltage value of the power supply interface, outputting a digital quantity proportional to the analog voltage value; this digital quantity is the voltage data acquired in this sampling. This voltage data is read and stored in the internal buffer memory. The above sampling actions are repeated at fixed time intervals, thus forming a continuous digital sampling sequence of the power supply interface voltage state in the time dimension. For example, the ADC configuration parameters include: a resolution of 10 bits or 12 bits, a reference voltage of an internal bandgap reference voltage, and a sample-and-hold time set to 2 microseconds. During initialization, the factory calibration value is obtained by reading the internal calibration register, and offset and gain corrections are performed on the ADC output.

[0029] A2. Filter the voltage data.

[0030] Specifically, because the supply voltage in a real working environment may be affected by factors such as power supply ripple, transient load changes, and electromagnetic interference, the raw voltage data collected by the analog-to-digital converter often contains random noise components. To obtain a stable value that truly reflects the trend of supply voltage changes, the collected voltage data needs to be digitally filtered. N consecutively collected voltage data points form a filtered data set, where N is a preset filtering window length and is an integer greater than 1. The value of N is determined based on the ratio between the sampling frequency and the supply voltage ripple frequency, ensuring that the filtering window duration covers at least one complete ripple cycle, thereby effectively suppressing ripple interference. Typical values ​​for N are 4 to 16, for example, N can be 4, 8, or 16. The arithmetic mean of these N voltage data points is calculated and used as the filtered voltage data at the current moment. After each mean calculation, the result is written to the internal buffer memory. As new voltage data is acquired, the filtered data set is updated. The oldest voltage data point in the set is removed, and the newly acquired voltage data is added to the set to maintain a constant filtering window length and continue calculating the arithmetic mean for the next time step. This filtering method is an implementation of sliding window mean filtering, which can effectively suppress high-frequency random noise and smooth voltage change curves.

[0031] It should be noted that during the first N-1 monitoring periods after system initialization, no filtering is performed or the average is calculated using the already collected data because not enough data has been collected. Once N data points have been collected, the sliding window average will be output normally.

[0032] A3. Use the filtered voltage data as the power supply voltage for the storage device.

[0033] Specifically, the calculated filtered voltage data is used as the effective representation of the power supply voltage of the storage device at the current moment. This value is then used in subsequent steps, including voltage anomaly event detection, voltage anomaly level determination, and voltage recovery detection, for all calculations and comparisons involving the power supply voltage. Replacing the original single-sample instantaneous value with this filtered voltage data avoids false triggering caused by noise spikes.

[0034] A4. Determine if a voltage anomaly event has occurred in the storage device based on the power supply voltage.

[0035] Specifically, the memory controller determines whether a voltage anomaly event has occurred in the memory device based on a preset normal voltage threshold range. In this embodiment, the anomaly triggering condition is that the supply voltage continuously exceeds the normal voltage threshold range a preset number of times. If the triggering condition is met, a voltage anomaly event is determined to have occurred; otherwise, no voltage anomaly event is determined to have occurred. In other words, if the monitored supply voltage of the memory device is not within the normal voltage threshold range, a voltage anomaly event is determined to have occurred; otherwise, no voltage anomaly event has occurred.

[0036] Furthermore, A4, determining a voltage anomaly event in a storage device based on the power supply voltage specifically includes the following steps: A41. If the power supply voltage exceeds the preset normal voltage threshold range for at least M consecutive monitoring cycles, a voltage abnormality event is determined to have occurred; where M≥2 and is an integer.

[0037] In this process, the memory controller continuously monitors the supply voltage, obtaining a filtered supply voltage value in each monitoring cycle. A monitoring cycle refers to the time interval between the controller completing one full voltage sampling and filtering process and outputting a valid supply voltage value. A counter variable is maintained to accumulate the number of monitoring cycles in which the supply voltage continuously exceeds the normal voltage threshold range. At the end of each monitoring cycle, the controller compares the current supply voltage value with the normal voltage threshold range pre-stored in the firmware. The normal voltage threshold range is defined by a lower limit and an upper limit; a supply voltage value less than the lower limit or greater than the upper limit is considered to be outside the normal voltage threshold range. If the current supply voltage value exceeds the normal voltage threshold range, the counter variable is incremented by 1. If the current supply voltage value does not exceed the normal voltage threshold range, i.e., falls within the interval defined by the lower and upper limits, the counter variable is reset to zero. The current value of the counter variable is checked in each monitoring cycle. When the value of the counter variable reaches a preset integer M, a voltage anomaly event is determined. The value of M determines the degree to which the judgment mechanism suppresses transient voltage fluctuations; a larger M value results in a stronger filtering effect on transient spikes, but the anomaly response time is correspondingly prolonged. For example, the value of M ranges from 2 to 8, and is determined based on the power stability of the storage device's application environment. The higher the power stability, the smaller the value of M.

[0038] The normal voltage threshold range is a pre-set set of voltage boundary values ​​used to define the normal fluctuation range of the supply voltage. The specific values ​​of this range are determined according to the interface protocol specifications followed by the storage device or the hardware datasheet of the memory module. For example, for a storage device conforming to the standard SD card protocol specification, its nominal operating voltage range is 2.7 volts to 3.6 volts, so the lower limit of the normal voltage threshold range can be set to 2.7 volts, and the upper limit can be set to 3.6 volts. For storage devices supporting low-voltage operating modes, the lower and upper limits of the normal voltage threshold range are adjusted to 1.7 volts to 1.95 volts respectively.

[0039] M is a preset integer threshold used for continuous judgment of voltage anomalies. Its value determines the degree to which the judgment mechanism suppresses transient voltage fluctuations. M is determined by balancing the requirements for false trigger suppression with the speed of anomaly response based on the actual application scenario. When the storage device is used in a stable power environment with low ripple, M can be a smaller value, such as 2 or 3, to speed up the response to real voltage drop events. When the storage device is used in complex power environments such as industrial control or automotive systems, with frequent load switching or electromagnetic interference, M can be a larger value, such as 5 or 8 or even higher, to effectively filter out occasional voltage spikes and prevent false triggers from causing the storage device to frequently enter protection mode, thus affecting availability.

[0040] Further, see Figure 5 , Figure 5 This is a schematic diagram of the process for obtaining the operating status of a memory module according to an embodiment of this application, which specifically includes the following steps: S11A. Query the first status register and read the busy / idle flag in the first status register.

[0041] Specifically, the first status register reflects the current operating status of the memory module in real time. The first status register defines a busy / idle flag, the value of which is automatically updated based on whether a programming or erasing operation is currently in progress. When the memory module is performing a programming or erasing operation, the busy / idle flag is set to a value indicating a busy state, such as logic 1. When the memory module is not performing any programming or erasing operation, the busy / idle flag is set to a value indicating an idle state, such as logic 0. A status read command is sent to the memory module via the internal bus interface. The memory module responds to this command by returning the current value of the first status register to the controller. The controller parses the returned status byte, extracts the busy / idle flag, and temporarily stores it in an internal working register.

[0042] S12A. If the busy / idle flag indicates a busy state, identify the type of operation currently being performed and determine the identification result as the current operation state. The operation type includes at least programming operations and erasing operations.

[0043] Specifically, when the read busy / idle flag indicates that the memory module is busy, it is necessary to further determine the specific operation type currently being executed so that a matching pause command can be selected during the subsequent execution of the safety interrupt procedure. The current operation type is identified by querying a pre-maintained command history. In one implementation, when an operation command is issued to the memory module, the corresponding operation type is simultaneously recorded in an internal cache. When the current operation type needs to be identified, the recorded value in the internal cache can be read directly. In another implementation, a query command can be sent to the memory module to obtain the currently executing command word, and then the corresponding operation type can be parsed out. The identified operation types include at least programming and erasing operations. The controller combines the identified operation type information with the busy status information as a complete description of the current operation state.

[0044] S13A. If the busy / idle flag indicates an idle state, then the idle state is determined as the current operating state. Specifically, when the read busy / idle flag indicates that the memory module is in an idle state, it means that no programming or erasing operations are currently being performed. In this case, there is no need to further identify the operation type; the idle state is directly determined as the current operating state.

[0045] As an optional method, the voltage anomaly level corresponding to the voltage anomaly event is determined, including: The deviation between the supply voltage and a preset normal voltage threshold range is calculated. Specifically, after a voltage anomaly is detected, the degree of deviation of the current supply voltage is quantified to determine the stringency of subsequent processing strategies. First, the filtered supply voltage value for the current monitoring period is obtained. Then, this supply voltage value is compared with the pre-stored normal voltage threshold range to determine the direction and amount of deviation. If the supply voltage value is less than the lower limit of the normal voltage threshold range, the deviation value equals the lower limit minus the supply voltage value. If the supply voltage value is greater than the upper limit of the normal voltage threshold range, the deviation value equals the supply voltage value minus the upper limit value. The deviation value reflects the absolute extent to which the supply voltage exceeds the allowable normal operating range; a larger deviation value indicates a more severe power supply environment.

[0046] Determine the corresponding voltage anomaly level according to the deviation value. Among them, there is a pre-set correspondence table or segmented threshold between the deviation value and the voltage anomaly level. This correspondence defines the mapping rules between different deviation value intervals and different voltage anomaly levels. Compare the calculated deviation value with the pre-set level division threshold in sequence. The level division threshold can be set according to the percentage of the normal voltage threshold range. For example, the situation where the deviation value is less than 5% of the lower limit of the normal voltage is classified as the first-level anomaly, the situation where the deviation value is greater than or equal to 10% of the lower limit of the normal voltage is classified as the second-level anomaly, and the deviation values between 5% and 10% can be classified into one of the levels according to the pre-set rules. Generally speaking, the smaller the deviation value, the lower the corresponding voltage anomaly level, and the larger the deviation value, the higher the corresponding voltage anomaly level. Determine the voltage anomaly level to which the current voltage anomaly event belongs according to the comparison result, and use this level information as the basis for setting the subsequent timing duration and selecting the processing branch.

[0047] The pre-set level division rule is: use a certain proportion of the lower limit value of the normal voltage threshold range as the division threshold. Specifically, the deviation value corresponding to the first-level anomaly is less than a% of the lower limit value, and the deviation value corresponding to the second-level anomaly is greater than or equal to b% of the lower limit value, where a < b. The values of a and b are determined according to the sensitivity of the memory module to voltage deviation. The typical values are a = 5 and b = 10.

[0048] For example, the lower limit value of the normal voltage is 2.7 volts. The pre-set level division rule is that when the deviation value is less than 0.135 volts, that is, 5% of the lower limit value, it is determined as the first-level anomaly; when the deviation value is greater than or equal to 0.27 volts, that is, 10% of the lower limit value, it is determined as the second-level anomaly; when the deviation value is between 0.135 volts and 0.27 volts, it is also determined as the second-level anomaly. When the supply voltage is 2.4 volts, the deviation value is calculated as 0.3 volts, and 0.3 volts is greater than 0.27 volts. Therefore, it is determined that the voltage anomaly level of this voltage anomaly event is the second-level anomaly. If the supply voltage is 2.6 volts and the deviation value is 0.1 volts, which is less than 0.135 volts, then the voltage anomaly level is determined as the first-level anomaly.

[0049] In another embodiment, the voltage anomaly level can be divided into three levels or more levels, and the corresponding timing durations of each level decrease in sequence. When it is detected that the supply voltage is lower than the pre-set emergency power-off threshold (such as 70% of the normal lower limit value), it is determined as the third-level anomaly (emergency anomaly). At this time, the timer is not started to wait, and the orderly restart process is directly executed to protect the memory module from low-voltage damage to the greatest extent.

[0050] S2. If the operation status is the busy state, then execute the safe interruption process: send an abort transmission command to the host system, and determine whether the memory module supports the operation pause function.

[0051] Specifically, when the operation status obtained in step S1 is busy, it indicates that programming or erasing operations are in progress inside the memory module, and safety measures must be taken to interrupt the operation. First, a stop transmission command conforming to the corresponding protocol specification is sent to the host system through the interface protocol layer between the storage device and the host system to notify the host to stop sending the remaining part of the current data transmission transaction. Then, it is necessary to determine whether the currently connected memory module supports the operation pause function. This determination can be achieved by querying the device feature register of the memory module. A certain feature bit in the device feature register is used to identify whether the module supports programming pause commands or erase pause commands. Reading this feature bit, if the feature bit indicates support for the pause function, proceed to step S3; otherwise, proceed to step S4.

[0052] In one embodiment, for the SD (Secure Digital) protocol, the abort transmission command is CMD12 (STOP_TRANSMISSION); for the eMMC (Embedded Multi-Media Card) protocol, the abort transmission command is CMD12; for the UFS (Universal Flash Storage) protocol, the abort transmission command is fAbortTask (abort task flag) in the QUERY REQUEST; and for the NVMe (Non-Volatile Memory Express) protocol, the abort transmission command is Abort Command.

[0053] S3. If supported, send a pause command to the memory module to pause the currently executing operation.

[0054] In step S2, when it is determined that the memory module supports the operation pause function, a pause command matching the current operation type is sent to the memory module. If a programming operation is currently being performed, a programming pause command is sent. If an erasure operation is currently being performed, an erasure pause command is sent. Upon receiving the pause command, the memory module's internal state machine suspends the current operation, stops the operation of the internal high-voltage generation circuit, and places the memory cell array in a stable intermediate state. This operation ensures that the memory cells will not suffer physical damage due to forced interruption under abnormal voltage conditions, and also preserves the basis for subsequent recovery operations.

[0055] In one embodiment, the pause command is either Program Suspend (command word 85h) or Erase Suspend (command word B0h) from the NAND Flash standard command set. After sending the pause command, the memory controller polls the status register to confirm that the operation has been successfully paused. This approach is applicable to NAND Flash memory modules that support suspend functionality.

[0056] S4. If not supported, mark the current operation as needing to be re-executed after recovery.

[0057] In step S2, if it is determined that the memory module does not support the operation pause function, the current operation cannot be safely frozen by sending a pause command. In this case, the attempt to terminate the internal operation of the memory module is abandoned, and instead a flag is recorded. This flag indicates that the currently interrupted operation cannot be continued from the breakpoint and must be re-executed from the starting position after the voltage is restored. This flag can exist as a flag field in the operation context data structure. In the subsequent recovery process, after parsing this flag, a full redo strategy will be adopted instead of resuming from the pause point.

[0058] S5. Record the operation context of the suspended operation and write the operation context into the non-volatile backup area of ​​the memory module. The operation context includes the progress parameters of the suspended operation. The progress parameters include at least the length of data transmitted or the completed operation stage. Before writing the operation context, determine whether the current power supply voltage is higher than the preset backup voltage threshold. If so, execute the write. Otherwise, skip the write and jump directly to the abnormal recovery process.

[0059] Specifically, after completing the pause operation or re-execution of the flag setting on the memory module, an operation context data structure describing the details of the paused operation is constructed. This operation context data structure includes fixed fields such as operation type and target physical address, and specifically includes a progress parameter field. The progress parameter field records the execution breakpoint position of the paused operation at the time of interruption. For paused programming operations, the progress parameter can record the length of data successfully written to the memory module, such as the number of sectors or bytes written. For paused erase operations, the progress parameter can record the range of physical blocks or physical page numbers that have been erased. Before writing the operation context to the non-volatile backup area of ​​the memory module, a power supply voltage pre-check is performed. The current power supply voltage value is obtained and compared with a preset backup voltage threshold in the firmware.

[0060] The backup voltage threshold is a lower voltage limit specifically designed to ensure the reliability of non-volatile write operations. Its value is slightly higher than the minimum programming voltage specified in the memory module datasheet. For example, in a system with a minimum programming voltage of 2.7 volts, the backup voltage threshold can be set to 2.9 volts. If the current supply voltage is higher than the backup voltage threshold, it indicates that the power supply environment can still meet the energy requirements for a complete non-volatile write operation, and the operation context is written to the allocated free physical pages of the non-volatile backup area. If the current supply voltage is lower than or equal to the backup voltage threshold, it indicates that the supply voltage has dropped to a level where the write operation cannot be guaranteed to execute correctly, and the writing of the operation context to the non-volatile backup area is abandoned. The process then jumps directly to the anomaly recovery procedure, which includes an ordered restart procedure. In the case of abandoning the write operation, because the operation context is not non-volatilely saved, the controller will not be able to know the exact breakpoint of the suspended operation during subsequent voltage recovery, and will only treat the suspended operation as a complete operation that needs to be re-executed from the beginning.

[0061] For example: Suppose the paused operation is a programming operation that writes 4096 bytes of data across 8 sectors. When a voltage anomaly occurs, the programming operation has successfully written the first 5 sectors to the specified physical page of the memory module, with the remaining 3 sectors yet to be transferred. When constructing the operation context, the operation type field is set to programming operation, the target physical address field is set to chip 0, block 100, page 50, and the progress parameter field is set to the length of data transferred: 2560 bytes, or 5 sectors. Before writing the operation context, the current supply voltage is read as 3.0 volts, which is higher than the preset backup voltage threshold of 2.9 volts. Based on this, it is determined that the current supply voltage supports safe writing, and the operation context, including the progress parameter, is then written to page 5 of block 2042 in the non-volatile backup area. If the current supply voltage is 2.8 volts, lower than 2.9 volts, the write operation is abandoned, and the process jumps directly to the anomaly recovery procedure. During subsequent voltage recovery, the paused operation is treated as a completely new operation request, and programming is re-executed starting from the first sector.

[0062] S6. Set the timing duration according to the voltage abnormality level.

[0063] The higher the voltage anomaly level, the more severe the voltage deviation from the normal range, the shorter the corresponding timing duration, in order to trigger a protective reset as soon as possible to prevent the hardware from being exposed to a harsh electrical environment for a long time; conversely, for minor voltage anomalies, the timing duration is set to a longer recovery waiting time to filter out brief power fluctuations.

[0064] Further, see Figure 6 As shown, Figure 6 This is a schematic diagram of the timer duration setting process provided in the embodiments of this application, which specifically includes the following steps: S61. If the voltage abnormality level is Level 1, set the timer duration value to the first value.

[0065] Specifically, when the voltage anomaly event is identified as Level 1, it indicates a minor deviation in the supply voltage, classifying it as a slight anomaly. In this case, the supply voltage has a high probability of recovering to normal within a short period, such as due to a brief voltage drop caused by instantaneous load fluctuations in the power supply. To ensure data security and equipment availability, a relatively lenient tolerance waiting time is granted for such minor anomalies. A pre-configured first value is read, representing a longer waiting time, such as 6 seconds; a second value represents a shorter waiting time, such as 3 seconds. The ratio of the first value to the second value is not less than 2 to reflect the differentiated tolerance strategy between different voltage anomaly levels. The target count value of the timer is set to this first value, and then the timer is started.

[0066] S62. If the voltage abnormality level is the second level, set the timing duration to the second value. The voltage deviation of the first level abnormality is less than that of the second level abnormality, and the first value is greater than the second value.

[0067] Specifically, when the voltage anomaly event corresponds to a Level 2 anomaly, it indicates a significant deviation in the supply voltage, constituting a severe anomaly. Such situations may be caused by serious hardware problems such as power supply failure, poor power line contact, or load short circuits. The probability of the supply voltage recovering on its own within a short time is low, and prolonged exposure to severely deviated voltage environments increases the risk of irreversible damage to the memory module. Therefore, a relatively strict tolerance waiting time is assigned to such severe anomalies. A pre-configured second value is read, representing a shorter waiting time, such as 3 seconds. The timeout threshold of the internal timer is set to the second value, and the timing is started. The voltage deviation corresponding to a Level 1 anomaly is smaller than that corresponding to a Level 2 anomaly, while the timing duration corresponding to the first value (Level 1 anomaly) is greater than that corresponding to the second value (Level 2 anomaly). This inverse relationship reflects the core strategy of graded response: the more severe the anomaly, the shorter the tolerance time and the faster the protection action. For example, the first value ranges from 5 to 10 seconds, the second value ranges from 2 to 5 seconds, and the ratio of the first value to the second value is not less than 1.5.

[0068] This embodiment employs a time-sharing tolerance strategy for voltage anomalies. For Level 1 anomalies with small deviations, the controller allocates a longer initial value as a recovery waiting time to effectively filter out brief power fluctuations, maximize the availability of the storage device, and avoid unnecessary reset operations. For Level 2 anomalies with larger deviations, the controller allocates a shorter second value as a recovery waiting time to quickly trigger a protective response, reducing the risk of damage to the memory module in harsh electrical environments.

[0069] S7. Before the timeout period expires, if the power supply voltage recovers to the preset normal voltage threshold range, read the operation context in the non-volatile backup area, and execute the recovery process of the suspended operation based on the read operation context to continue the programming operation or erasure operation from the pause point; if the voltage abnormality is detected again during the recovery process, the recovery is abandoned and the abnormal recovery process is entered.

[0070] During the set timeout period, the power supply voltage is continuously monitored. If the power supply voltage has recovered and stabilized within the preset normal voltage threshold range before the timeout expires, the voltage anomaly event is considered resolved, and the power supply environment has returned to a state that supports the normal operation of the memory module. At this point, the recovery process for the suspended operation is initiated. First, the non-volatile backup area of ​​the memory module is accessed. Based on the address mapping information, the physical page address of the previously saved operation context is found, and a read command is sent to the memory module to read the operation context data into the controller's internal buffer memory. The read operation context is then subjected to integrity verification, which can be performed using cyclic redundancy check or checksum comparison. If the verification passes, the fields in the operation context are parsed to obtain the operation type, target physical address, and progress parameters of the suspended operation. If the verification fails, the anomaly recovery process is executed, and the operation context is cleared.

[0071] If the aforementioned paused operation is marked as needing to be re-executed (i.e., the memory module does not support the operation pause function), the progress parameter is ignored, and the complete programming or erasing operation is restarted from the starting position. If the paused operation supports pausing and the pause command has been successfully sent, the recovery operation is calculated from where to continue execution based on the breakpoint position indicated by the progress parameter. If the paused operation is a programming operation, starting from the length of data already transmitted recorded in the progress parameter, a sequence of programming commands for the remaining data is sent to the memory module until all data is written. If the paused operation is an erasing operation, starting from the completed operation stage recorded in the progress parameter, erasing commands continue to be sent to complete the erasure of the remaining physical area. During the execution of the recovery process, the power supply voltage is still monitored. If, during the recovery process, the power supply voltage is detected to drop below the normal voltage threshold range again, i.e., a secondary voltage anomaly event occurs, the current recovery operation is immediately terminated, the recovery attempt is abandoned, and the process jumps to the abnormal recovery process. The abnormal recovery process may include triggering a hardware reset process (i.e., an ordered restart process) according to a preset strategy.

[0072] When the timer count set in step S6 returns to zero, i.e., the timer duration expires, if the power supply voltage still has not recovered to the preset normal voltage threshold range, then the process will no longer wait for the power supply voltage to recover, but will instead force the abnormal recovery process to begin.

[0073] In one embodiment, regardless of whether the power supply voltage has recovered to the normal voltage threshold range at the timeout point, the abnormal recovery process is directly initiated, and an orderly restart is performed.

[0074] Specifically, if the power supply voltage has not recovered by the timeout point, it indicates that the duration of the power supply anomaly has exceeded the preset tolerance limit. Continuing to wait may expose the memory module to the abnormal voltage environment for an extended period, increasing the risk of hardware damage. If the power supply voltage recovers just in time, but the recovery time is too close to the timeout boundary, it is also advisable to perform a complete reset of the hardware state through an ordered restart process to eliminate any internal state disorder or register residual errors that may have occurred during the voltage anomaly.

[0075] In detail, the core component of the anomaly recovery process is the ordered restart process. The ordered restart process first writes the current anomaly recovery status flag to the non-volatile backup area of ​​the memory module. This flag is used to notify the initialization program of any uncompleted transactions after restarting. Subsequently, a reset command is sent to the hardware reset circuit inside the storage device, triggering a hardware reset operation of the memory controller and memory module. After the reset is complete, the initialization program is re-executed, checking for the presence of the anomaly recovery status flag in the non-volatile backup area during the initialization phase. If the flag exists and the current supply voltage has stabilized within the normal voltage threshold range, the operation context in the non-volatile backup area is read, and the recovery process for the suspended operations is executed based on the operation context. If the supply voltage still does not recover after the reset, the anomaly recovery status flag is cleared, and the operation context is marked as invalid.

[0076] Further, see Figure 7 , Figure 7 This is a schematic diagram of the operation context writing process provided in the embodiments of this application, which specifically includes the following steps: S51. Allocate one or more free physical pages in the non-volatile backup region for the operating context.

[0077] S52. Write the operation context to the allocated free physical page.

[0078] S53. After writing is completed, update the address mapping information of the non-volatile backup area. The address mapping information is used to record the correspondence between the storage location of the operation context and the suspended operation.

[0079] Allocate one or more free physical pages in the non-volatile backup region for the operating context.

[0080] After physical page allocation is complete, the operation context is written from the internal buffer memory to the corresponding physical page address in the non-volatile backup area of ​​the memory module. A programming command sequence is sent to the memory module via the internal Flash interface bus, specifying the target physical address as the allocated physical page address, and the operation context is transmitted to the memory module as the write data payload. Upon receiving the data, the memory module performs the programming operation within its internal physical block, non-volatilely saving the operation context. To improve data reliability, the controller can employ redundant writing methods, such as writing the same operation context to two different physical pages simultaneously, or attaching error correction codes when writing data. After writing is complete, the success of the programming operation can be confirmed by reading the status register.

[0081] To accurately locate and retrieve the saved operation context after voltage recovery, the address mapping information of the non-volatile backup region needs to be updated after the write operation is completed. This address mapping information is a pre-maintained set of management data used to establish the association between the identifier of the suspended operation and the actual physical address of the operation context. The unique identifier of the suspended operation, such as an operation sequence number or timestamp, is recorded in the address mapping information along with the allocated physical page address. The address mapping information itself is also stored in a designated location in the non-volatile backup region, such as the first physical page of the non-volatile backup region or a fixed offset address, to ensure that it can still be correctly read after the storage device is reset or power is lost. The updated address mapping information allows the controller to quickly retrieve the storage location of the operation context using the identifier of the suspended operation during the recovery phase.

[0082] Furthermore, the process of allocating free physical pages includes: After constructing the operation context structure, the first step is to determine the storage space occupied by the data block in the non-volatile backup area. The actual byte length of the operation context structure is read; this length is determined by the fixed width and variable length of each field in the operation context. The non-volatile backup area is divided into several fixed-size physical pages. The storage capacity of each physical page is a known constant in the controller firmware, such as 2 kilobytes or 4 kilobytes. The operation context size is divided by the capacity of a single physical page. If the division result has a remainder, the quotient is incremented by 1 to determine the required number of physical pages; otherwise, the quotient is used directly as the required number of physical pages. This determines the minimum number of physical pages to allocate, avoiding wasted storage space.

[0083] The management of the non-volatile backup area relies on a pre-maintained list of free physical pages. This list records the unique identifiers of all currently unallocated physical pages within the backup area. Each physical page identifier can be a combination of a physical block number and a physical page number, or a global physical page sequence number. Once the number of physical pages to be allocated is determined, the required number of physical page identifiers are retrieved sequentially from the head of the list. The retrieval operation follows a first-in-first-out (FIFO) or last-in-first-out (LIFO) order, depending on the specific implementation of the list. Each time a physical page identifier is retrieved, the list head pointer or index moves accordingly, and the retrieved physical page identifier is temporarily stored in the controller's internal working buffer for use in subsequent address allocation steps.

[0084] In another embodiment, free physical page management can employ a bitmap structure, where each bit represents the occupied / free status of a physical page; or it can be managed using a free page count array combined with a starting address.

[0085] Physical page identifiers retrieved from the free physical page management list are allocated to the operation context in a predefined allocation order. This predefined allocation order can be ascending order of identifier values ​​(smallest to largest) or the original order in which they were retrieved. The physical page identifiers are then converted into physical page addresses recognizable by the memory module. These physical page addresses include the chip select signal number, physical block address, and physical page address. After conversion, these physical page addresses are marked as occupied by the current operation context. Simultaneously, the physical page identifiers retrieved and allocated from the free physical page management list need to be permanently removed. This is done either by updating the list structure synchronously during identifier retrieval or by rewriting the remaining portion of the list to the non-volatile management area for persistence after allocation. The updated free physical page management list will no longer contain allocated physical page identifiers, and subsequent allocation requests will not re-allocate the same physical pages.

[0086] As an optional method, see Figure 8 As shown, Figure 8 This is another schematic flowchart illustrating a memory control method provided in an embodiment of this application. In addition to S1-S7, this embodiment also includes: S8. If the operation status indicates that the memory module is in an idle state, set the storage device to a busy state visible to the protocol layer to refuse to accept new access commands from the host system.

[0087] The operational state is one of the standard states defined by the storage protocol specification. Upon detecting this state, the host system will suspend sending any new data read / write or erase commands to the storage device, allowing only status-related commands to pass. The protocol-layer visible busy state refers to the busy state announced by the storage device to the host system through the status register of the standard storage protocol. This state only affects the host system's command issuance behavior and is unrelated to the physical busy / idle state of the memory module.

[0088] Furthermore, when the current operating state is determined to be idle, meaning it is confirmed that no programming or erasing operations are being performed within the memory module, the system enters the voltage anomaly protection branch in the idle state. The goal of this branch is to prevent the host system from sending new access commands to the memory device and initiating new memory module operations during periods of abnormal power supply voltage, rather than to interrupt the currently executing operation.

[0089] The storage device is equipped with a second status register, which is used to notify the host system of the current protocol layer status of the storage device. A busy flag is defined in the second status register, and the value of this flag directly affects the host system's judgment of the storage device's availability. When the busy flag is set to the first bit value, the storage device is marked as busy from a protocol layer perspective. Upon detecting this status, the host system will suspend issuing new data read / write commands or erase commands to the storage device. The first bit value can be either logic 1 or logic 0, depending on the specific definition of the protocol specification. For example, in the SD protocol, a logic 1 first bit value indicates a busy state; in the eMMC protocol, a logic 0 first bit value indicates a busy state. Those skilled in the art can determine this based on the specific protocol.

[0090] After completing the second status register setting operation, there is no need to actively send a notification signal to the host system. Before sending any subsequent commands to the storage device, the host system typically queries the storage device's status register to confirm its availability. After sending a status query command, the host system returns the status register content, including the busy flag bit set to the first value, as response data. The host system parses this response data, detects that the busy flag bit is the first value, determines that the storage device is busy, and accordingly suspends the sending of new access commands. Access commands refer to operation commands issued by the host system for reading, writing, or erasing data, such as the CMD24 write single-block command, CMD25 write multiple-block command, and CMD38 erase command in the SD (Secure Digital Memory) protocol. The host system may continue to send status query commands to poll for changes in the busy flag bit, but will not send new data operation commands, thereby achieving the protection purpose of blocking new operations during voltage anomalies.

[0091] When the host system detects that the storage device is in a busy state, it continuously polls the status register according to the storage protocol specification, with polling intervals typically in the millisecond range. If the busy state lasts longer than the host system's preset command timeout (usually tens of seconds), the host system may mark the command as failed and report the error to the application layer. Therefore, the timing duration set by the memory controller should not exceed the host system's typical command timeout to avoid causing unnecessary upper-layer error handling.

[0092] S9. Set the timer duration according to the voltage anomaly level. The timer is a hardware timer module inside the memory controller, which continues timing even when entering a low-power or abnormal state. The timer's timing accuracy is no less than 1 millisecond, and the maximum settable duration is no less than 10 seconds.

[0093] The method and principle for setting the timer duration in S9 are the same as those in step S6 above. Figure 6The embodiments shown are the same, and will not be described again here.

[0094] S10. Before the timeout period expires, monitor whether the power supply voltage has returned to the preset normal voltage threshold range.

[0095] In each monitoring cycle, the filtered power supply voltage value is acquired and compared with a preset normal voltage threshold range. If the power supply voltage has returned to and stabilized within the normal voltage threshold range, the voltage anomaly event is determined to be resolved, and step S11 is executed; otherwise, step S12 is executed.

[0096] S11. If yes, the storage device will be taken out of the busy state to resume normal response to access commands from the host system.

[0097] In step S8, the busy flag is cleared, allowing the storage device to switch from a busy state visible at the protocol layer back to a ready state.

[0098] Furthermore, when it is determined that the power supply voltage has recovered to the normal voltage threshold range before the timeout period expires, the busy state exit procedure is initiated. A write operation is performed on the second status register inside the storage device, modifying the busy flag bit in the register from the previously set first bit value to the second bit value. The second bit value is the logical complement of the first bit value; if the first bit value is 1, the second bit value is 0, and if the first bit value is 0, the second bit value is 1. Its specific value depends on the storage protocol specification followed. After the busy flag bit is set to the second bit value, from the protocol layer perspective, it indicates that the storage device has exited the busy state and returned to the ready state. This register modification operation only involves register write operations within the controller and does not require interaction with the memory module.

[0099] After clearing or setting the second status register, no active notification signal needs to be sent to the host system. When the host system continues to poll the storage device status, it returns the contents of the second status register, including the busy flag which has been modified to the second bit value, as response data. The host system parses this response data, detects that the busy flag has changed to the second bit value, and determines that the storage device has exited the busy state and is ready. The host system then lifts the restriction on sending new access commands and resumes sending normal data read / write and erase commands to the storage device. At this point, the storage device returns to normal operation and can continue to respond to various access requests from the host system.

[0100] S12. If not, perform an ordered restart procedure on the storage device. The ordered restart procedure does not include the restoration of the operating context.

[0101] If it is determined that the power supply voltage has not recovered to the normal voltage threshold range after the timeout period, it is determined that the current power supply environment is still in a bad state and it is meaningless to continue waiting, and then the orderly restart process is initiated.

[0102] An ordered restart process refers to a controlled reset process that is executed when the power supply voltage cannot be restored for a long time. That is, the ordered restart process does not include saving and restoring the operating context, but only includes: performing a hardware reset and re-initializing the storage device 12 after the reset.

[0103] In one embodiment, a further scheme regarding the abnormal recovery process is proposed. Specifically, for the abnormal recovery process triggered under busy conditions, the internal ordered restart process includes more complex recovery operations.

[0104] Specifically, if the current supply voltage is higher than a preset backup voltage threshold, an abnormal recovery status flag is saved to the aforementioned non-volatile backup area. This abnormal recovery status flag is used to indicate the existence of an incomplete operation context; control the storage device to perform a hardware reset; during the initialization phase after the reset, check whether there is an abnormal recovery status flag in the non-volatile backup area; if it exists, and the supply voltage monitored after the reset recovers to the normal voltage threshold range, then read the operation context in the non-volatile backup area, and execute the recovery process of the suspended operation based on the read operation context; if the supply voltage still does not recover after the reset, then clear the abnormal recovery status flag and mark the operation context as invalid.

[0105] Specifically, when it is determined that the power supply voltage has not recovered to the normal voltage threshold range after the timeout period, the first step of the orderly restart process is initiated. An abnormal recovery status flag is generated. This flag is a data marker with a specific preset value, such as a specific byte value of 0x01. The meaning of this flag is to convey to the restart initialization program that there was a suspended operation that failed to complete normally due to abnormal voltage timeout before this reset, and the corresponding operation context has been saved in the non-volatile backup area. This abnormal recovery status flag is written to a designated management location in the non-volatile backup area of ​​the memory module. This location can be one or more reserved physical pages in the backup area. After writing, the flag data can still be correctly read after the storage device is powered off or reset. For example, the non-volatile backup area is organized as follows: Page 0 is the area management information page, storing the total capacity, used capacity, and address mapping information of the backup area; Pages 1 to N are the operation context storage area; Page N+1 is the abnormal recovery status flag page.

[0106] After saving the abnormal recovery status flag, the memory controller initiates a hardware reset process. It writes a reset instruction to its own hardware reset control register or generates a reset pulse signal via internal reset control circuitry. This reset signal simultaneously acts on all functional modules within the memory controller and their connected memory modules, restoring all hardware registers to their default initial values ​​and returning the state machine to its power-on initial state. After the reset operation is complete, the firmware initialization program will restart, just like a normal power-on process.

[0107] After the hardware reset is complete, the firmware initialization procedure begins. At appropriate points during the initialization phase, the non-volatile backup area of ​​the memory module is accessed, and data is read from a pre-defined management physical address to check for the presence of a saved abnormal recovery status flag. Specifically, the read data is compared with a preset flag value, such as 0x01. If the read data equals the preset flag value, an unprocessed abnormal recovery status is identified, requiring subsequent recovery operations. If the read data does not equal the preset flag value, no unprocessed abnormal recovery status is identified, and the controller continues with the normal initialization process.

[0108] When an abnormal recovery status flag is detected, the recovery operation is not performed immediately. Instead, a power supply voltage check is performed first. The current power supply voltage value is obtained and compared with a preset normal voltage threshold range. If the power supply voltage has recovered to the normal voltage threshold range, the current power supply environment is determined to be suitable for memory module operations. Subsequently, the previously saved operation context is read from the non-volatile backup area, and the same recovery process as described above is executed. This recovery process includes verifying the integrity of the operation context, resolving the operation type and target address, re-initiating the programming or erasure operation, and verifying the data after the operation. If the power supply voltage still has not recovered to the normal range, the system can re-enter a busy state waiting loop or maintain the safe state after reset until the power supply voltage returns to normal before attempting recovery again.

[0109] This embodiment can reduce the probability of the storage device being falsely triggered to reset or shut down due to short-term fluctuations in power supply voltage. While ensuring hardware safety, it maximizes the availability of the storage device to the host system and further enhances the robustness of the storage device in harsh power supply environments.

[0110] In one embodiment, a non-volatile backup region is allocated by the memory controller from the total physical capacity of the memory module during the initial initialization of the storage device, accounting for 0.1% to 1% of the total capacity. This region is isolated from the regular data storage region through a separate logical address space. The starting physical block address and size of the backup region are recorded in the system information area of ​​the memory module and read by the controller each time power-on initialization occurs.

[0111] In one embodiment, the buffer memory uses a storage medium with power-loss protection to ensure that data is not lost during power supply voltage drops. In another embodiment, if data in the buffer memory is lost, a request is made to the host system to retransmit the corresponding data after the voltage is restored. The data is then retrieved from the host system based on the logical address before a recovery programming operation is performed.

[0112] In one embodiment, during the operation of the storage device, statistical information such as the frequency of voltage anomaly events, deviation amplitude, and recovery time is continuously recorded. Based on historical data, the deviation threshold and timing duration parameters corresponding to the voltage anomaly level are dynamically adjusted. For example, if slight voltage fluctuations occur frequently in a specific application environment but can recover on their own, the controller can appropriately relax the deviation threshold for the first-level anomaly and appropriately extend the first value to reduce unnecessary protection triggering. If the voltage anomalies in the environment are mostly continuous drops that cannot recover on their own, the voltage anomaly level trigger threshold can be reduced and the timing duration shortened to improve the protection response speed.

[0113] In one embodiment, the normal voltage threshold range can be divided into multiple sub-ranges, including a normal range, a warning range, and a danger range. When the supply voltage enters the warning range but has not yet triggered an abnormal event determination, the memory controller performs preventative measures, including: reducing the operating frequency of the memory module, suspending non-critical background tasks (such as garbage collection), and pre-flushing the data in the buffer memory to a non-volatile medium. When the supply voltage enters the danger range and is determined to be a voltage abnormal event, the safety interruption procedure of this application is executed. This multi-level warning mechanism can gain more protection time before the voltage drops completely, further improving data security margin.

[0114] Figures 3 to 8 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figures 3 to 8 Each step can be implemented as multiple program codes or circuits, and this application does not impose any limitations. Furthermore, Figures 3 to 8 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this application does not impose any restrictions.

[0115] In summary, the memory control method and storage device proposed in the embodiments of this application effectively prevent data corruption or firmware loss caused by power fluctuations by immediately suspending memory module operation and saving the operation context to a non-volatile area when a voltage anomaly occurs. Furthermore, it can accurately recover interrupted tasks after voltage recovery, ensuring the continuity of storage operations and the integrity of data. By dynamically adjusting the timing duration according to the degree of voltage deviation, this application achieves both flexibility and reliability in its protection mechanism. It can filter out minor voltage disturbances to avoid unnecessary recovery processes, and can respond quickly in the event of severe voltage anomalies, thereby achieving an effective balance between system stability and data security.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory control method, characterized in that, Applied to a storage device including a memory module and a memory controller, the method includes: In response to a voltage anomaly event in the storage device, the current operating status of the memory module is obtained, and the voltage anomaly level is determined; If the operation status is busy, then execute the safety interruption procedure: Send a stop transmission command to the host system and determine whether the memory module supports the operation pause function; If supported, a pause command is sent to the memory module to pause the currently executing operation; If not supported, mark the current operation as needing to be re-executed after recovery; Record the operation context of the suspended operation and write the operation context into the non-volatile backup area of ​​the memory module. The operation context includes the progress parameters of the suspended operation, and the progress parameters include at least the length of data transmitted or the completed operation stage. Before writing to the operation context, it is determined whether the current power supply voltage is higher than the preset backup voltage threshold. If so, the writing is performed; otherwise, the writing is skipped and the process is directly jumped to the abnormal recovery process. The timing duration is set according to the voltage anomaly level. If the power supply voltage recovers to the preset normal voltage threshold range before the timing duration expires, the operation context in the non-volatile backup area is read, and the recovery process of the suspended operation is executed based on the read operation context to continue the programming operation or erasure operation from the pause point. If the voltage anomaly is detected again during the recovery process, the recovery is abandoned and the anomaly recovery process is entered.

2. The memory control method according to claim 1, characterized in that, Also includes: If the operating state indicates that the memory module is in an idle state, the storage device is set to a busy state visible at the protocol layer to refuse to accept new access commands from the host system; Set the timer duration according to the voltage anomaly level; Before the timeout period expires, monitor whether the power supply voltage has recovered to the preset normal voltage threshold range; If so, the storage device will be taken out of the busy state to resume normal response to access commands from the host system; If not, an ordered restart procedure is performed on the storage device, which does not include the restoration of the operating context.

3. The memory control method according to claim 1, characterized in that, Before responding to a voltage anomaly event in the storage device, obtaining the current operating state of the memory module, and determining the voltage anomaly level, the method further includes: Based on a preset sampling frequency, voltage data of the host interface of the storage device is acquired through an analog-to-digital converter; The voltage data is then filtered. The filtered voltage data is used as the power supply voltage for the storage device; The storage device is determined to have experienced a voltage anomaly based on the power supply voltage.

4. The memory control method according to claim 3, characterized in that, The filtering process for the voltage data includes: Acquire N consecutively collected voltage data points, where N is a preset filter window length and is an integer greater than 1; Calculate the arithmetic mean of the N voltage data points, and use the arithmetic mean as the filtered voltage data at the current moment; The filtered voltage data is written into a buffer memory.

5. The memory control method according to claim 3, characterized in that, The determination of a voltage anomaly event in the storage device based on the power supply voltage includes: If the power supply voltage exceeds the preset normal voltage threshold range for at least M consecutive monitoring cycles, then the storage device is determined to have experienced a voltage abnormality event; where M ≥ 2 and is an integer.

6. The memory control method according to claim 1, characterized in that, The determination of the voltage anomaly level includes: Calculate the deviation between the power supply voltage of the storage device and the preset normal voltage threshold range; The corresponding voltage anomaly level is determined based on the deviation value.

7. The memory control method according to claim 1, characterized in that, The setting of the timing duration based on the voltage anomaly level includes: If the voltage anomaly level is Level 1, the value of the timing duration is set to the first value; If the voltage anomaly level is the second level, the value of the timing duration is set to the second value; wherein the voltage deviation of the first level anomaly is less than the voltage deviation of the second level anomaly, and the first value is greater than the second value.

8. The memory control method according to claim 1, characterized in that, The step of reading the operation context in the non-volatile backup area and executing the recovery process of the suspended operation based on the read operation context includes: Read the operation context in the non-volatile backup area; Perform integrity verification on the operation context; If the verification passes, the recovery process of the suspended operation is executed based on the operation context. If the verification fails, the exception recovery process is executed, and the operation context is cleared.

9. The memory control method according to claim 1, characterized in that, The process of obtaining the current operating status of the memory module includes: Query the first status register and read the busy / idle flag bit in the first status register; If the busy / idle flag indicates a busy state, the type of operation currently being executed is identified by querying the pre-maintained command history or sending a query command to the memory module, and the identification result is determined as the current operation state. The operation type includes at least programming operations and erasing operations. If the busy / idle flag indicates an idle state, then the idle state is determined as the current operating state.

10. The memory control method according to claim 2, characterized in that, If the operating state indicates that the memory module is in an idle state, setting the storage device to a protocol-layer visible busy state to reject new access commands from the host system includes: If the operation status indicates that the memory module is in an idle state. Set the busy flag in the second status register inside the storage device to the first bit value, whereby the first bit value indicates that the storage device is in a busy state visible to the protocol layer. According to the storage protocol followed by the storage device, the host system is notified of the busy flag set to the first bit value through the corresponding protocol mechanism to refuse to accept new access commands from the host system.

11. The memory control method according to claim 2, characterized in that, If so, the storage device will be taken out of the busy state to resume normal response to access commands from the host system, including: If so, the busy flag in the second status register inside the storage device is set to the second bit value, which indicates that the storage device has exited the busy state. According to the storage protocol followed by the storage device, the busy flag set to the second bit value is notified to the host system through the corresponding protocol mechanism to resume normal response to the host system's access commands.

12. The memory control method according to claim 2, characterized in that, If not, then an ordered restart process is performed on the storage device, including: If not, perform a hardware reset operation and reinitialize the storage device after the reset; The ordered restart process does not include the restoration of the operation context.

13. The memory control method according to claim 1, characterized in that, The ordered restart process in the anomaly recovery process includes: If the current power supply voltage is higher than the preset backup voltage threshold, the abnormal recovery status flag is saved to the non-volatile backup area. The abnormal recovery status flag is used to indicate that there is an incomplete operation context. Control the storage device to perform a hardware reset; During the initialization phase after reset, check whether the abnormal recovery status flag exists in the non-volatile backup area; If it exists, and the power supply voltage monitored after the reset recovers to the normal voltage threshold range, then the operation context in the non-volatile backup area is read, and the recovery process of the suspended operation is executed based on the read operation context; If the power supply voltage does not recover after the reset, the abnormal recovery status flag is cleared, and the operation context is marked as invalid.

14. The memory control method according to claim 1, characterized in that, The recording of the operation context of the paused operation, and the writing of the operation context into the non-volatile backup area of ​​the memory module, includes: Allocate one or more free physical pages in the non-volatile backup region to the operating context; Write the operation context to the allocated free physical page; After the write operation is completed, the address mapping information of the non-volatile backup area is updated. The address mapping information is used to record the correspondence between the storage location of the operation context and the suspended operation.

15. The memory control method according to claim 14, characterized in that, The step of allocating one or more free physical pages in the non-volatile backup region to the operating context includes: Obtain the data size of the operation context, and determine the number of physical pages required based on the data size; Query the free physical page management list corresponding to the non-volatile backup area, and sequentially retrieve a number of free physical page identifiers equal to the number of physical pages from the free physical page management list; According to a preset allocation order, the physical page address corresponding to the retrieved free physical page identifier is allocated to the operation context. The preset allocation order is either ascending order of identifier values ​​from smallest to largest or the original order in which the identifiers are retrieved from the free physical page management list. Update the free physical page management list to remove the allocated free physical page identifier.

16. A storage device, characterized in that, include: A connection interface for electrically connecting to a host system; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple pages; as well as The memory controller includes an error checking and correction circuit, a buffer memory, and a memory control circuit, and is electrically connected to the connection interface and the memory module; The memory controller is configured to perform the memory control method as described in any one of claims 1 to 15.

Images