Reorganization method of system on chip and reorganization device of system on chip
By adjusting the functional module affiliation of the intellectual property core in the on-chip system and performing logical verification, the problem of uneven resource allocation was solved, the performance of the on-chip system was improved, and the operational stability was ensured.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-13
- Publication Date
- 2026-05-29
AI Technical Summary
The system-on-a-chip suffers from an uneven distribution of intellectual property core resources during the design phase, leading to performance degradation.
By logically reorganizing the functional modules of the intellectual property core, and determining the reorganized register transfer level based on the topological connection relationship and reorganization scheme, logical verification is performed to improve performance and ensure stability.
It effectively improved the problem of uneven resource allocation, enhanced the performance of the on-chip system, and ensured the stability of the reorganized system.
Smart Images
Figure CN122111947A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a method and apparatus for reassembling a system-on-a-chip. Background Technology
[0002] System-on-a-Chip (SoC) is widely used in mobile terminals, smart homes, IoT devices, aerospace, and many other fields, directly determining the performance of electronic devices. However, during the design phase of SoC, there may be design flaws, such as uneven resource allocation of intellectual property cores. These problems can reduce the performance of the SoC, and consequently, the performance of the electronic device. Summary of the Invention
[0003] In view of this, embodiments of the present invention provide a system-on-a-chip (SoC) reconfiguration method and an SoC reconfiguration apparatus, so as to improve the performance of the SoC through logical reconfiguration while ensuring the operational stability of the SoC after logical reconfiguration through logical verification.
[0004] In a first aspect, embodiments of the present invention provide a method for reassembling an on-chip system, the method comprising: The first reorganization scheme based on the initial on-chip system determines the intellectual property core combination in the initial on-chip system. The intellectual property core combination includes a source intellectual property core and a target intellectual property core. The first reorganization scheme is used to modify the logical attribution of the target functional module from the source intellectual property core to the target intellectual property core. Determine the topological connection relationship of each functional module in the intellectual property core assembly; The reconfiguration register transfer level of the first on-chip system is determined based on the topological connection relationship and the first reconfiguration scheme. Logical verification is performed on the reconfiguration register transfer stage.
[0005] Optionally, the method further includes: A second reconfiguration scheme for the first on-chip system is determined based on the reconfiguration register transfer level, and the second reconfiguration scheme is used to modify the layout information of the first on-chip system; The intellectual property cores to be reassembled are determined based on the initial register transfer level description information of the first on-chip system and the second reassembly scheme. The initial register transfer level description information includes first description information and second description information. The first description information includes port information of each intellectual property core in the first on-chip system, and the second description information includes the logical connection relationship of each intellectual property core in the register transfer level top-level module. Based on the target logical connection relationship of the intellectual property core to be reorganized and the second reorganization scheme, the first on-chip system is physically reorganized to obtain the second on-chip system; The second on-chip system is evaluated based on the reconfiguration register transfer level description information.
[0006] Optionally, determining the second reassembly scheme of the first on-chip system based on the reassembly register transfer level includes: The layout and routing results of the first on-chip system are determined based on the reconfiguration register transfer stage; Based on the layout and routing results, the performance parameters of each intellectual property core in the first on-chip system are determined. The performance parameters include at least one of the timing information, power consumption information and resource information of each intellectual property core. The second recombination scheme is determined based on the aforementioned performance parameters.
[0007] Optionally, determining the second recombination scheme based on each of the performance parameters includes: Obtain the reconfiguration target of the first on-chip system, the reconfiguration target including reducing the area of the first on-chip system; The second recombination scheme is determined based on the recombination objective and each of the performance parameters.
[0008] Optionally, the logical verification includes an equivalence check; The logical verification of the reassembled register transfer stage includes: Obtain the initial register transfer stage of the initial on-chip system; The equivalence check is performed on the reassembled register transfer stage based on the initial register transfer stage.
[0009] Optionally, determining the placement and routing results of the first on-chip system based on the reconfiguration register transfer stage includes: In response to the successful logic verification, the placement and routing result is determined based on the reconfiguration register transfer stage.
[0010] Secondly, embodiments of the present invention provide a system-on-chip reconfiguration apparatus, the apparatus comprising: The combination determination unit is used to determine the combination of intellectual property cores in the initial on-chip system based on a first reorganization scheme of the initial on-chip system. The combination of intellectual property cores includes a source intellectual property core and a target intellectual property core. The first reorganization scheme is used to modify the logical affiliation of the target functional module from the source intellectual property core to the target intellectual property core. A relationship determination unit is used to determine the topological connection relationship of each functional module in the intellectual property core assembly; The design determination unit is used to determine the reconfiguration register transfer stage of the first on-chip system based on the topology connection relationship and the first reconfiguration scheme. The verification unit is used to perform logical verification on the reconfiguration register transfer stage.
[0011] Thirdly, embodiments of the present invention provide an electronic device, including a memory and a processor, wherein the memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method as described in any one of the first aspects.
[0012] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method as described in any one of the first aspects.
[0013] Fifthly, embodiments of the present invention provide a computer program product, the computer program product including a computer program / instruction, which, when executed by a processor, implements the method as described in any one of the first aspects.
[0014] This invention discloses a system-on-a-chip (SoC) reconfiguration method and apparatus. Based on an SoC reconfiguration scheme, this invention determines the intellectual property core combination to be logically reconfigured and the topological linking relationships of each functional module within that intellectual property core combination. Based on the topological linking relationships and the reconfiguration scheme, it determines the reconfigured register transfer stage, and then performs logical verification on the reconfigured register transfer stage. In this invention, the SoC reconfiguration scheme is used to modify the logical attribution of a specified functional module from the source intellectual property core in the intellectual property core combination to the target intellectual property core. Therefore, this invention can improve the performance of the SoC through logical reconfiguration while ensuring the operational stability of the reconfigured SoC through logical verification. Attached Figure Description
[0015] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a flowchart of the reorganization method of the upper system according to an embodiment of the present invention; Figure 2 This is a system block diagram of the initial on-chip system according to an embodiment of the present invention; Figure 3 This is a system block diagram of the first system-on-a-chip according to an embodiment of the present invention; Figure 4 This is a flowchart of the on-chip system reassembly method according to an embodiment of the present invention; Figure 5 This is a flowchart of the on-chip system reassembly method according to an embodiment of the present invention; Figure 6This is a system block diagram of the second system-on-a-chip according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a system-on-chip reassembly device according to an embodiment of the present invention; Figure 8 This is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation
[0016] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0017] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.
[0018] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".
[0019] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0020] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.
[0021] A system-on-a-chip (SoC), also known as a system-on-a-chip (SoC), consists of an embedded processor, memory, dedicated intellectual property (IP) cores, input / output (I / O) interface IP cores, on-chip buses, and other IP cores. Compared to traditional chips, SoCs offer higher performance, smaller size, and lower power consumption, making them widely used in various fields. During the SoC design phase, designers encapsulate different IP cores into distinct IP cores. These IP cores have different characteristics; for example, shaders integrate a large number of computational units, resulting in a high standard cell density; while interconnect-type IP cores such as network-on-a-chip (NOC) primarily focus on data links and routing logic, with fewer computational units, resulting in a low standard cell density. This difference can easily lead to design flaws in SoCs, such as uneven resource allocation among IP cores. These problems degrade the performance of the SoC and, consequently, the performance of the electronic device.
[0022] To address the aforementioned issues, this invention provides a system-on-a-chip (SoC) reconfiguration method and apparatus, which improve the performance of the SoC through logical reconfiguration while ensuring the operational stability of the reconfigured SoC.
[0023] The following describes the method through examples. Figure 1 This is a flowchart of the reorganization method of the upper system according to an embodiment of the present invention. For example... Figure 1 As shown, the method of this embodiment of the invention may include the following steps: Step S100: Determine the intellectual property core combination in the initial on-chip system based on the first reconfiguration scheme of the initial on-chip system.
[0024] During the design phase of a system-on-a-chip (SoC), in order to reduce the possibility of unreasonable SoC design, designers usually reorganize and optimize the intellectual property core at the Register Transfer Level (RTL) to improve the performance of the SoC and optimize the rationality of resource allocation, timing convergence and power consumption.
[0025] In this embodiment, the reorganization of intellectual property cores includes logical reorganization. Logical reorganization is a reorganization method that optimizes the logical structure of the on-chip system by modifying the partitioning, signal connections, or function allocation of intellectual property cores. The on-chip system can implement logical reorganization based on a pre-determined first reorganization scheme, which can be obtained from the performance parameters of the on-chip system. The performance parameters of the on-chip system can include at least one of the following: the occupancy status of the on-chip system's physical resources (such as the number, density, and utilization rate of standard cells, lookup tables, wiring channels, etc.), timing, power consumption, etc. During the logical reorganization stage, the performance parameters of the on-chip system can be obtained from the register-transfer level report of the on-chip system. Furthermore, the register-transfer level report of the on-chip system can be obtained by converting the register-transfer level code of the on-chip system into a gate-level netlist using electronic design automation software, such as DC (Design Compiler).
[0026] After obtaining the performance parameters of the on-chip system, the first reorganization scheme for the on-chip system can be determined in various ways. For example, the prompt words for the large language model can be determined based on the performance parameters of the on-chip system, and the obtained prompt words can be used as the input of the large language model to obtain the first reorganization scheme for the on-chip system. In this embodiment, the large language model can be a series of models such as GPT (Generative Pre-trained Transformer), Meta Llama, BLOOM (BigScience Large Open-science Open-access Multilingual Language Model), or Tongyi Qianwen, etc. Alternatively, the reorganization scheme can be designed by the designer according to actual needs.
[0027] In this embodiment, the first reconfiguration scheme of the initial on-chip system is used to modify the logical attribution of functional modules from one intellectual property core to another. Therefore, in this step, the on-chip system that needs to be logically reconfigured can be identified as the initial on-chip system, and the functional modules whose logical attribution needs to be modified can be identified as target functional modules according to the first reconfiguration scheme of the initial on-chip system. Then, the source intellectual property core and the target intellectual property core of the target functional module can be identified as an intellectual property core combination.
[0028] Step S200: Determine the topological connection relationship of each functional module in the intellectual property core assembly.
[0029] In this embodiment, the purpose of logical reorganization is only to modify the logical affiliation of the target functional module, and not to modify the topological connection relationship between functional modules. Therefore, in order to ensure that the source intellectual property core of the target functional module and the topological connection relationship of each functional module in the target intellectual property core do not change after the logical affiliation of the target functional module is modified, the topological connection relationship of each functional module can be determined and recorded.
[0030] Step S300: Determine the reconfiguration register transfer level of the first on-chip system based on the topology connection relationship and the first reconfiguration scheme.
[0031] In this step, the register transfer level (i.e., the initial register transfer level) of the initial on-chip system can be edited according to the topological connection relationship of each functional module and the first reconfiguration scheme of the initial on-chip system, so as to obtain the register transfer level (i.e., the reconfigured register transfer level) of the first on-chip system.
[0032] In this step, the above process can be implemented using code manipulation tools. For example, it can be implemented using a Verilog AST (Abstract Syntax Tree) processing script. Specifically, the reassembly scheme can be transformed into a structured specification that can be processed by the Verilog AST processing script, such as an Excel file, an IP-XACT file, or a JSON (JavaScript Object Notation) join table. Then, the structured specification and the initial register transfer level of the initial on-chip system are used as input to the Verilog AST processing script to obtain the reassembled register transfer level corresponding to the reassembly scheme.
[0033] Figure 2 This is a system block diagram of the initial on-chip system according to an embodiment of the present invention. Figure 3 This is a system block diagram of the first system-on-a-chip according to an embodiment of the present invention. Figure 2As shown, the initial on-chip system includes four intellectual property cores: LLC cache (Last Level Cache), on-chip interconnect architecture 22, on-chip interconnect architecture 23, and L2 cache. Specifically, the LLC cache includes LLC caches 21A to 21H, with LLC cache 21A including cache core 211, LLC cache 21B including cache core 212, LLC cache 21C including cache core 213, LLC cache 21D including cache core 214, LLC cache 21E including cache core 215, LLC cache 21F including cache core 216, LLC cache 21G including cache core 217, and LLC cache 21H including cache core 218; the on-chip interconnect architecture 22 includes switching units 221 to 228; the on-chip interconnect architecture 23 includes switching units 231 to 238; and the L2 cache includes 24A to 24H.
[0034] The first reconfiguration scheme is used to change the logical ownership of switching units 221 to 228 from the on-chip interconnect architecture 22 to LLC cache. Specifically, the logical ownership of switching unit 221 is changed to LLC cache 21A, the logical ownership of switching unit 222 is changed to LLC cache 21B, the logical ownership of switching unit 223 is changed to LLC cache 21C, the logical ownership of switching unit 224 is changed to LLC cache 21D, the logical ownership of switching unit 225 is changed to LLC cache 21E, the logical ownership of switching unit 226 is changed to LLC cache 21F, the logical ownership of switching unit 227 is changed to LLC cache 21G, and the logical ownership of switching unit 228 is changed to LLC cache 21H. This determines that the intellectual property core combination is an on-chip interconnect architecture and LLC cache, and determines the topological connection relationship between switching units 231 to 238 and between cache cores 211 and 218. Furthermore, as... Figure 3 As shown, the system block diagram of the first on-chip system can be obtained based on the topological connection relationship between switching units 231 to 238 and cache cores 211 to 218 and the first reconfiguration scheme. Meanwhile, since the on-chip interconnect architecture 22 does not contain other functional modules, the first on-chip system no longer retains the on-chip interconnect architecture 22.
[0035] Step S400: Perform logical verification on the reconfiguration register transfer stage.
[0036] After determining the reconfiguration register transfer level, logical verification can be performed on the reconfiguration register transfer level to ensure that the logical function of the system on the first chip remains correct after the logical attribution of the functional modules is modified.
[0037] Optionally, formal verification can be performed on the reassembled register transfer level. Formal verification may include equivalence checking (EC) and property checking (PC). Taking equivalence checking as an example, equivalence checking includes system-level equivalence checking, which can obtain the initial register transfer level of the initial on-chip system and perform equivalence checking on the reassembled register transfer level based on the initial register transfer level.
[0038] Specifically, the initial register transfer stage and the reassembled register transfer stage can be used as inputs to formal verification tools, such as Synopsys Formality and Cadence Conformal. The formal verification tool will bind the ports, clock, and reset signals of the two register transfer stages and transform them into a unified mathematical logic model. Then, the reassembled register transfer stage is used as the test object. Through mathematical algorithms, such as Binary Decision Diagram (BDD) and Boolean Satisfiability Problem (SAT), all logical states and input combinations are exhausted. The consistency of combinational logic, sequential logic, and output behavior is compared, and finally, the equivalence check result of the reassembled register transfer stage is obtained.
[0039] In this embodiment of the invention, the first reconfiguration scheme of the on-chip system is determined based on the performance parameters of each intellectual property core in the on-chip system. Therefore, by modifying the logical affiliation of functional modules, the problem of uneven resource allocation can be effectively improved, the problem of unreasonable on-chip system design can be reduced, and the performance of the on-chip system can be improved. Furthermore, before logical reconfiguration, only the topological connection relationships of the functional modules to be reconfigured are recorded, effectively reducing the amount of data. During logical reconfiguration, only the topological connection relationships of the functional modules to be reconfigured are rebuilt, which can effectively improve the efficiency of logical reconfiguration. Simultaneously, after logical reconfiguration of the on-chip system, the reconfigured register transfer level is verified, which can simultaneously ensure the operational stability of the on-chip system.
[0040] In practical applications, when the logical affiliation of a functional module is modified from the source intellectual property core to the target intellectual property core, the layout of the functional module usually also needs to be moved from the source intellectual property core to the target intellectual property core. Therefore, the change in the logical affiliation of a functional module often involves not only the logical reorganization of the intellectual property core but also its physical reorganization. Therefore, optionally, in one possible implementation of this embodiment, the on-chip system reorganization method may also include physical reorganization.
[0041] Figure 4 This is a flowchart of a system-on-chip reconfiguration method according to an embodiment of the present invention. Figure 4As shown, in one optional implementation, this embodiment may include the following steps: Step S500: Determine the second reassembly scheme of the first on-chip system based on the reassembly register transfer stage.
[0042] To improve the optimization effect of the system-on-chip (SoC), this embodiment can physically reassemble the first SoC using a second reassembly scheme, i.e., modify the layout information of the first SoC. In this step, the second reassembly scheme of the first SoC can be determined based on the reassembly register transfer level of the first SoC. In some optional implementations, the second reassembly scheme can be determined by the designer according to actual needs.
[0043] In some optional implementations, this embodiment may perform physical reconfiguration after logical reconfiguration of the on-chip system; that is, step S500 may be executed after step S400. In some optional implementations, this embodiment may perform physical reconfiguration only on the on-chip system.
[0044] Figure 5 This is a flowchart of a system-on-chip reconfiguration method according to an embodiment of the present invention. Figure 4 As shown, in an optional implementation of this embodiment, step S500 may include the following steps: Step S510: Determine the layout and routing results of the first on-chip system based on the reconfiguration register transfer stage.
[0045] In this step, a hierarchical gate-level netlist for the first on-chip system can be generated based on the reconfiguration register transfer stage, and the place and route (PR) results for the first on-chip system in Customer Owned Tooling (COT) can be determined based on this hierarchical gate-level netlist. Optionally, the hierarchical gate-level netlist can be generated using electronic design automation software; the place and route results can be generated using IC physical implementation tools such as Candence Innovus, Synopsys IC Complier II (ICC2), etc.
[0046] Optionally, in order to reduce the design time cost of the system-on-chip, the layout and routing results of the first system-on-chip can be determined based on the reconfiguration register transfer stage after the logic verification is confirmed.
[0047] Step S520: Determine the performance parameters of each intellectual property core in the first on-chip system based on the layout and routing results.
[0048] The placement and routing results of the customer-owned model include timing reports, power consumption reports, and area and density reports of the first system-on-a-chip. Therefore, in this step, the performance parameters of each intellectual property core in the first system-on-a-chip can be determined based on the placement and routing results of the first system-on-a-chip.
[0049] Step S530: Determine the second recombination scheme based on each performance parameter.
[0050] In this step, a second reconfiguration scheme for the first on-chip system can be determined based on the performance parameters of each intellectual property core. Optionally, to further improve the design rationality of the on-chip system, the second reconfiguration scheme can also be determined based on a pre-set reconfiguration objective, that is, the second reconfiguration scheme can be determined based on the reconfiguration objective and the performance parameters of each intellectual property core. The reconfiguration objective can be set according to actual needs, such as reducing the area of the first on-chip system, achieving timing convergence of the first on-chip system (e.g., fixing timing violations, reducing clock skew, etc.), and reducing the power consumption of the first on-chip system (e.g., optimizing the clock tree, reducing dynamic power consumption, etc.).
[0051] Step S600: Determine the intellectual property core to be reorganized based on the initial register transfer level description information of the first on-chip system and the second reorganization scheme.
[0052] In existing technologies, after determining the second reassembly scheme, the reassembly register transfer stage of the first on-chip system is typically flattened, and then physically reassembled according to the second reassembly scheme to obtain the second on-chip system. For example, the reassembly register transfer stage and the second reassembly scheme can be used as inputs to an IC physical implementation tool, which flattens the reassembly register transfer stage. Then, after physically reassembling the first on-chip system according to the flattened reassembly register transfer stage, the physically reassembled reassembly register transfer stage is output.
[0053] However, in practical applications, the architecture of on-chip systems is often quite complex, resulting in a very large and complex data volume after the register transfer stage is flattened. This makes physical reassembly efficiency low and difficult for designers to understand when physically reassembling the on-chip system at the flattened register transfer stage. Therefore, in some optional implementations, this embodiment can write the register transfer stage based on a DSL (Domain-Specific Language).
[0054] To improve the processability of the reconfigured register transfer stage (RTL), the top-level module of the RTL consists only of signal interconnections between intellectual property cores, without complex logic such as if / else branches, for loops, or arithmetic logic. This means that the top-level RTL description (also known as the second description) in the first on-chip system's RTL description only includes the logical connections between the intellectual property cores in the top-level module. Simultaneously, the on-chip system's layout and routing results can provide the physical location information of each intellectual property core. In other words, the second reconfiguration scheme can define the physical location changes of each intellectual property core before and after physical reconfiguration. Therefore, in this embodiment, it is not necessary to flatten the reconfigured RTL to determine the intellectual property cores to be reconfigured.
[0055] Therefore, in this step, the Register Transfer Level (RTL) parser can perform syntax analysis on the reconfigured Register Transfer Level (RTL) of the first on-chip system based on the RTL description information of the first on-chip system and the second reconfiguration scheme to determine the intellectual property cores (i.e., the intellectual property cores to be reconfigured) that need to be physically reconfigured. Specifically, the RTL parser can search for the initial RTL description information of the first on-chip system based on the file list of the first on-chip system, and then determine the intellectual property cores to be reconfigured based on the first description information (including the port information of each intellectual property core in the first on-chip system) and the second description information in the initial RTL description information.
[0056] Optionally, the processing method for reassembling the register transfer level can be determined based on the register transfer level parser, i.e., whether to flatten the reassembly register transfer level. If the processing method indicates that flattening the reassembly register transfer level is not required, the intellectual property core to be reassembled can be directly determined based on the first and second description information in the initial register transfer level description information.
[0057] Step S700: Based on the target logical connection relationship of the intellectual property core to be reorganized and the second reorganization scheme, the first on-chip system is physically reorganized to obtain the second on-chip system.
[0058] In this step, the logical connection relationship of the intellectual property core to be reorganized can be obtained from the register transfer level description information of the first on-chip system based on the register transfer level parser as the target logical connection relationship. Then, the first on-chip system is physically reorganized according to the target logical connection relationship and the second reorganization scheme, thereby determining the physically reorganized first on-chip system as the second on-chip system.
[0059] In this way, the register transfer level of some on-chip systems does not need to be flattened, and physical reassembly can be performed directly at the register transfer level. Therefore, it can effectively improve the physical reassembly efficiency of on-chip systems and is easier for designers to understand.
[0060] Figure 6 This is a system block diagram of the second system-on-a-chip according to an embodiment of the present invention. (In conjunction with...) Figure 3 The first system-on-a-chip includes four intellectual property cores: LLC cache, on-chip interconnect architecture 23, and L2 cache. The LLC cache includes LLC caches 21A to 21H; the L2 cache includes 24A to 24H. The physical spacing between LLC cache 21A and on-chip interconnect architecture 23 is d31, LLC cache 21B and on-chip interconnect architecture 23 is d32, LLC cache 21C and on-chip interconnect architecture 23 is d33, LLC cache 21D and on-chip interconnect architecture 23 is d34, LLC cache 21E and on-chip interconnect architecture 23 is d35, LLC cache 21F and on-chip interconnect architecture 23 is d36, LLC cache 21G and on-chip interconnect architecture 23 is d37, and LLC cache 21H and on-chip interconnect architecture 23 is d38. When determining the second reorganization scheme as shortening the physical distance between LLC cache 21A and LLC cache 21H based on the reorganization register transfer level of the first on-chip system, such as Figure 7 As shown, it can be determined that the physical layout of the second on-chip system has changed as follows: the physical spacing between LLC cache 21A and on-chip interconnect architecture 23 has changed to d61, the physical spacing between LLC cache 21B and on-chip interconnect architecture 23 has changed to d62, the physical spacing between LLC cache 21C and on-chip interconnect architecture 23 has changed to d63, the physical spacing between LLC cache 21D and on-chip interconnect architecture 23 has changed to d64, and the physical spacing between LLC cache 21E and on-chip interconnect architecture 23 has changed to d64. The physical spacing between LLC cache 21F and on-chip interconnect architecture 23 is changed to d65, d63, d67, and d68, respectively, with d61 < d31, d62 < d32, d63 < d33, d64 < d34, d65 < d35, d66 < d36, d67 < d37, and d68 < d38.
[0061] Step S800: Verify the performance of the second on-chip system based on the reconfiguration register transfer level description information of the second on-chip system.
[0062] After physically reassembling the on-chip system, the register-transfer level parser also outputs a list of physically reassembled files. Therefore, in this step, the register-transfer level description information of the second on-chip system (i.e., the reassembled register-transfer level description information) can be obtained from the physically reassembled file list, and the performance of the second on-chip system can be verified based on the reassembled register-transfer level description information.
[0063] In this embodiment, performance verification may include at least one of the following: power consumption verification, area verification, timing verification, and performance verification of the second system-on-a-chip (SoC), to verify whether at least one of the power consumption, area, timing, and performance of the second SoC is improved compared to the first register. For example, if power consumption verification is performed on the second SoC, a power consumption report of the second SoC can be obtained through an IC physical implementation tool. The IC physical implementation tool can be combined with power consumption tools, such as PrimePower, to complete the power consumption analysis of the second SoC based on the process library and SDF (Standard Delay Format) / RC (resistance-capacitance) parasitic parameters.
[0064] This invention, based on a system-on-a-chip (SoC) reconfiguration scheme, determines the intellectual property core combination to be logically reconfigured and the topological linking relationships of each functional module within that combination. Based on the topological linking relationships and the reconfiguration scheme, it determines the reconfigured register transfer level and then performs logical verification on the reconfigured register transfer level. In this invention, the SoC reconfiguration scheme is used to modify the logical affiliation of a specified functional module from the source intellectual property core in the intellectual property core combination to the target intellectual property core. Therefore, this invention can improve the performance of the SoC through logical reconfiguration while ensuring the operational stability of the reconfigured SoC through logical verification.
[0065] Figure 7 This is a schematic diagram of a reconfiguration device for an on-chip system according to an embodiment of the present invention. Figure 7 As shown, the on-chip system reconfiguration device of this embodiment includes a combination determination unit 701, a relationship determination unit 702, a design determination unit 703, and a verification unit 704.
[0066] The combination determination unit 701 is used to determine the intellectual property core combination in the initial on-chip system based on the first reconfiguration scheme of the initial on-chip system. The intellectual property core combination includes a source intellectual property core and a target intellectual property core. The first reconfiguration scheme is used to modify the logical affiliation of the target functional module from the source intellectual property core to the target intellectual property core. The relationship determination unit 702 is used to determine the topological connection relationship of each functional module in the intellectual property core combination. The design determination unit 703 is used to determine the reconfiguration register transfer stage of the first on-chip system according to the topological connection relationship and the first reconfiguration scheme. The verification unit 704 is used to perform logical verification on the reconfiguration register transfer stage.
[0067] This invention, based on a system-on-a-chip (SoC) reconfiguration scheme, determines the intellectual property core combination to be logically reconfigured and the topological linking relationships of each functional module within that combination. Based on the topological linking relationships and the reconfiguration scheme, it determines the reconfigured register transfer level and then performs logical verification on the reconfigured register transfer level. In this invention, the SoC reconfiguration scheme is used to modify the logical affiliation of a specified functional module from the source intellectual property core in the intellectual property core combination to the target intellectual property core. Therefore, this invention can improve the performance of the SoC through logical reconfiguration while ensuring the operational stability of the reconfigured SoC through logical verification.
[0068] Figure 8 This is a schematic diagram of an electronic device according to an embodiment of the present invention. In this embodiment, the electronic device 8 includes a server, a terminal, etc. Figure 8 As shown, the electronic device 8 includes at least one processor 801; a memory 802 communicatively connected to at least one processor 801; and a communication component 803 communicatively connected to a scanning device, wherein the communication component 803 receives and transmits data under the control of the processor 801; wherein the memory 802 stores instructions executable by at least one processor 801, the instructions being executed by at least one processor 801 to implement the above-described on-chip system reconfiguration method.
[0069] Specifically, the electronic device includes: one or more processors 801 and a memory 802. Figure 8 Taking a processor 801 as an example, the processor 801 and the memory 802 can be connected via a bus or other means. Figure 8 Taking a bus connection as an example, memory 802, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Processor 801 executes various functional applications and data processing of the device by running the non-volatile software programs, instructions, and modules stored in memory 802, thus realizing the aforementioned on-chip system reconfiguration method.
[0070] Memory 802 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store an option list, etc. Furthermore, memory 802 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 802 may optionally include memory remotely located relative to processor 801, and these remote memories can be connected to external devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
[0071] One or more modules are stored in memory 802, and when executed by one or more processors 801, they perform the on-chip system reconfiguration method in any of the above method embodiments.
[0072] The above-mentioned products can perform the methods provided in the embodiments of this application, and have the corresponding functional modules and beneficial effects of performing the methods. For technical details not described in detail in this embodiment, please refer to the methods provided in the embodiments of this application.
[0073] This invention, based on a system-on-a-chip (SoC) reconfiguration scheme, determines the intellectual property core combination to be logically reconfigured and the topological linking relationships of each functional module within that combination. Based on the topological linking relationships and the reconfiguration scheme, it determines the reconfigured register transfer level and then performs logical verification on the reconfigured register transfer level. In this invention, the SoC reconfiguration scheme is used to modify the logical affiliation of a specified functional module from the source intellectual property core in the intellectual property core combination to the target intellectual property core. Therefore, this invention can improve the performance of the SoC through logical reconfiguration while ensuring the operational stability of the reconfigured SoC through logical verification.
[0074] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program for use by a computer to execute some or all of the above-described method embodiments.
[0075] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
[0076] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for reassembling an on-chip system, characterized in that, The method includes: The first reorganization scheme based on the initial on-chip system determines the intellectual property core combination in the initial on-chip system. The intellectual property core combination includes a source intellectual property core and a target intellectual property core. The first reorganization scheme is used to modify the logical affiliation of the target functional module from the source intellectual property core to the target intellectual property core. Determine the topological connection relationship of each functional module in the intellectual property core assembly; The reconfiguration register transfer level of the first on-chip system is determined based on the topological connection relationship and the first reconfiguration scheme. Logical verification is performed on the reconfiguration register transfer stage.
2. The method according to claim 1, characterized in that, The method further includes: A second reconfiguration scheme for the first on-chip system is determined based on the reconfiguration register transfer level, and the second reconfiguration scheme is used to modify the layout information of the first on-chip system; The intellectual property cores to be reassembled are determined based on the initial register transfer level description information of the first on-chip system and the second reassembly scheme. The initial register transfer level description information includes first description information and second description information. The first description information includes port information of each intellectual property core in the first on-chip system, and the second description information includes the logical connection relationship of each intellectual property core in the register transfer level top-level module. Based on the target logical connection relationship of the intellectual property core to be reorganized and the second reorganization scheme, the first on-chip system is physically reorganized to obtain the second on-chip system; The second on-chip system is evaluated based on the reconfiguration register transfer level description information.
3. The method according to claim 2, characterized in that, The step of determining the second reassembly scheme of the first on-chip system based on the reassembly register transfer level includes: The layout and routing results of the first on-chip system are determined based on the reconfiguration register transfer stage; Based on the layout and routing results, the performance parameters of each intellectual property core in the first on-chip system are determined. The performance parameters include at least one of the timing information, power consumption information and resource information of each intellectual property core. The second recombination scheme is determined based on the aforementioned performance parameters.
4. The method according to claim 3, characterized in that, Determining the second recombination scheme based on each of the performance parameters includes: Obtain the reorganization objective of the first on-chip system, the reorganization objective including reducing the area of the first on-chip system; The second recombination scheme is determined based on the recombination objective and each of the performance parameters.
5. The method according to claim 1, characterized in that, The logical verification includes equivalence checks; The logical verification of the reassembled register transfer stage includes: Obtain the initial register transfer stage of the initial on-chip system; The equivalence check is performed on the reassembled register transfer stage based on the initial register transfer stage.
6. The method according to claim 3, characterized in that, The step of determining the placement and routing result of the first on-chip system based on the reconfiguration register transfer stage includes: In response to the successful logic verification, the placement and routing result is determined based on the reconfiguration register transfer stage.
7. A system-on-chip reconfiguration device, characterized in that, The device includes: The combination determination unit is used to determine the combination of intellectual property cores in the initial on-chip system based on a first reorganization scheme of the initial on-chip system. The combination of intellectual property cores includes a source intellectual property core and a target intellectual property core. The first reorganization scheme is used to modify the logical affiliation of the target functional module from the source intellectual property core to the target intellectual property core. A relationship determination unit is used to determine the topological connection relationship of each functional module in the intellectual property core assembly; The design determination unit is used to determine the reconfiguration register transfer stage of the first on-chip system based on the topology connection relationship and the first reconfiguration scheme. The verification unit is used to perform logical verification on the reconfiguration register transfer stage.
8. An electronic device comprising a memory and a processor, characterized in that, The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method as described in any one of claims 1-6.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1-6.
10. A computer program product, characterized in that, The computer program product includes a computer program / instruction that, when executed by a processor, implements the method as described in any one of claims 1-6.