Method and system for thermal management and electrical co-optimization of high power gallium nitride devices

Abstract

The application provides a high-power gallium nitride device thermal management and electrical synergistic optimization method and system, relates to the technical field of semiconductors, and comprises establishing a correlation mapping of a thermal conduction time coefficient and a pulse width modulation period; determining a matching relationship of a heat dissipation fin spacing and a switch tube conduction time according to a hot spot temperature gradient; synchronously adjusting a cooling medium flow rate and a dead time, and maintaining a ratio of a heat dissipation capacity change rate to an output power change rate in a preset interval. The application realizes timing synergistic optimization of a heat dissipation system and a power control circuit, improves system heat dissipation efficiency, prolongs device service life, and reduces power consumption.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and system for thermal management and electrical synergistic optimization of high-power gallium nitride devices. Background Technology

[0002] Gallium nitride (GaN) power devices have broad application prospects in high-frequency, high-power electronic systems due to their high breakdown electric field, high electron saturation velocity, and low on-resistance. However, with the continuous increase in power density, GaN devices generate a large amount of heat during operation, leading to a rise in device temperature and affecting device performance and reliability. Traditional heat dissipation system design and circuit control optimization are usually carried out independently, lacking a systematic and coordinated consideration.

[0003] Traditional heat dissipation system designs are mainly designed for the maximum heat dissipation requirements under steady-state conditions, and cannot effectively cope with the transient thermal response characteristics of GaN devices in high-frequency pulse operation mode. This leads to a mismatch between the time response of the heat dissipation system and the power circuit, resulting in wasted heat dissipation resources or insufficient heat dissipation.

[0004] The existing power control circuit parameter design and heat dissipation system parameter configuration lack a quantitative correlation mechanism, making it difficult to achieve dynamic coordinated adjustment of heat dissipation intensity and power output. When the power changes stepwise, it is easy to cause local overheating of devices or excessive heat dissipation, reducing the overall system efficiency. Summary of the Invention

[0005] The present invention provides a method and system for thermal management and electrical synergistic optimization of high-power gallium nitride devices, which can solve the problems in the prior art.

[0006] A first aspect of the present invention provides a method for co-optimizing thermal management and electrical performance of high-power gallium nitride devices, comprising: The heat conduction time coefficients of each level of the heat dissipation system of gallium nitride devices from the heat source to the environment are determined, and the pulse width modulation period of the power control circuit is extracted to establish the correlation mapping relationship between the heat conduction time coefficients of each level and the pulse width modulation period; Based on the aforementioned correlation mapping relationship, the hot spot temperature gradient under different operating modes is calculated. According to the hot spot temperature gradient, the matching relationship between the heat dissipation fin spacing in the heat dissipation system and the switching time in the power control circuit is determined. By adjusting the heat dissipation fin spacing and the switching time, the time difference between the response time when the heat dissipation system reaches its peak heat dissipation capacity and the time when the power control circuit outputs maximum power is less than a preset synchronization threshold. Based on the matching relationship, the cooling medium flow rate of the heat dissipation system and the dead time of the power control circuit are adjusted synchronously. When the output power of the power control circuit changes abruptly, the ratio of the rate of change of the heat dissipation capacity of the heat dissipation system to the rate of change of the output power is maintained within a preset coordinated range through the coordinated control between the adjustment amount of the cooling medium flow rate and the adjustment amount of the dead time. Based on the adjusted heat sink fin spacing, switching transistor conduction time, cooling medium flow rate, and dead time, the heat dissipation system design parameters and power control circuit control parameters are generated to control the heat dissipation intensity of the heat dissipation system and the switching action of the power control circuit.

[0007] Determine the heat conduction time coefficients of each level of the gallium nitride device's heat dissipation system from the heat source to the environment, extract the pulse width modulation period of the power control circuit, and establish the correlation mapping relationship between the heat conduction time coefficients of each level and the pulse width modulation period, including: The gallium nitride device includes a chip packaging layer, a thermally conductive interface material layer, a metal substrate layer, a heat dissipation fin layer, and a convection heat transfer layer. The thermal resistance is calculated based on the ratio of the thickness to the thermal conductivity of each layer in the gallium nitride device. The heat capacity is calculated based on the product of the contact area, thickness, density, and specific heat capacity of each layer. The thermal resistance and heat capacity are multiplied to obtain the heat conduction time coefficient. The ratio of the heat conduction time coefficient to the pulse width modulation period is then determined. When the ratio is less than a preset fast response threshold, the level is classified as a fast response level, and a one-to-one mapping relationship is established between its heat conduction time coefficient and the on-time of the switching transistor within a single pulse width modulation cycle; when the ratio is between the preset fast response threshold and the preset slow response threshold, the level is classified as a medium-speed response level, and a mapping relationship is established between the heat conduction time coefficient of this level and the cumulative time of multiple consecutive pulse width modulation cycles. When the ratio is greater than the preset slow response threshold, the level is divided into a slow response level, and a mapping relationship is established between the heat conduction time constant and the duty cycle change envelope corresponding to multiple continuous pulse width modulation periods.

[0008] Based on the aforementioned correlation mapping relationship, the hotspot temperature gradient under different operating modes is calculated. The matching relationship between the heat dissipation fin spacing in the heat dissipation system and the conduction time of the switching transistor in the power control circuit is determined according to the hotspot temperature gradient, including: Extract the heat transfer paths corresponding to the heat conduction time coefficients of each level of the heat dissipation system in the associated mapping relationship, and identify the bottleneck areas with the highest thermal resistance density in the heat transfer paths; calculate the instantaneous loss distribution of the switching transistors of the power control circuit under different operating modes, and determine the hot spot location coordinates corresponding to each operating mode based on the positional relationship between the instantaneous loss distribution and the bottleneck areas; For each hot spot location, calculate the temperature gradient value from that location to the surface of the heat sink fins. Then, correlate the temperature gradient value with the reciprocal of the heat sink fin spacing to establish an inverse proportional constraint relationship between the temperature gradient value and the heat sink fin spacing. Extract the switching loss curves of the switching transistor in the power control circuit at different conduction times, and identify the time period with the largest loss rise rate in the switching loss curve; The spacing of the heat dissipation fins corresponding to the maximum temperature gradient value in the inverse proportional constraint relationship is paired with the conduction time of the switch in the time period. By iteratively adjusting the spacing of the heat dissipation fins and the conduction time of the switch, the time difference between the moment when the heat dissipation system absorbs the peak heat flow and the moment when the power control circuit generates the peak loss is converged to within the preset synchronization threshold.

[0009] Pairing the heat sink fin spacing corresponding to the maximum temperature gradient value in the inverse proportional constraint relationship with the switching transistor conduction time within the time period, and iteratively adjusting the heat sink fin spacing and the switching transistor conduction time to bring the time difference between the moment when the heat dissipation system absorbs peak heat flux and the moment when the power control circuit generates peak loss to within the preset synchronization threshold includes: Identify the initial value of the heat sink fin spacing corresponding to the maximum value of the temperature gradient from the inverse proportional constraint relationship; extract the initial value of the switch turn-on time corresponding to the maximum loss rise rate from the time period; and form an initial pairing parameter group by combining the initial value of the heat sink fin spacing and the initial value of the switch turn-on time. Calculate the thermal response delay time required for the heat dissipation system to reach peak heat dissipation capacity from receiving heat flow based on the initial value of the heat dissipation fin spacing; calculate the electrical response delay time required for the power control circuit to generate peak loss from the start of switching action based on the initial value of the switching transistor conduction time. Calculate the time difference between the time corresponding to the thermal response delay time and the time corresponding to the electrical response delay time, and determine whether the time difference is less than the preset synchronization threshold. When the time difference is greater than or equal to the preset synchronization threshold, the adjustment direction is determined according to the sign of the time difference. When the time difference is positive, the heat sink fin spacing is reduced and the switching transistor conduction time is increased. When the time difference is negative, the heat sink fin spacing is increased and the switching transistor conduction time is reduced. The spacing between the heat sink fins and the turn-on time of the switching transistor are synchronously adjusted according to the adjustment direction. After adjustment, the thermal response delay time and electrical response delay time are recalculated, and the time difference is updated. The above judgment and adjustment operation is repeated until the time difference converges to less than the preset synchronization threshold. The spacing between the heat sink fins and the turn-on time of the switching transistor at the time of convergence are used as the final pairing parameter group.

[0010] Based on the matching relationship, the cooling medium flow rate of the heat dissipation system and the dead time of the power control circuit are adjusted synchronously. When the output power of the power control circuit changes abruptly, the ratio of the rate of change of the heat dissipation capacity of the heat dissipation system to the rate of change of the output power is maintained within a preset coordinated range through coordinated control between the adjustment amount of the cooling medium flow rate and the adjustment amount of the dead time. A candidate adjustment sequence for the cooling medium flow rate is set based on the flow rate adjustment range of the cooling medium conveying device, and a candidate adjustment sequence for the dead time is set based on the dead time adjustment range of the drive circuit. The two sequences are then combined to form a candidate adjustment combination set. The cooling medium flow rate adjustment is added to the current cooling medium flow rate, and the predicted heat dissipation capacity is calculated based on the adjusted flow rate. The dead time adjustment is added to the current dead time, and the switching loss and conduction loss are recalculated based on the adjusted dead time to determine the predicted output power. The ratio of the difference between the predicted heat dissipation capacity and the current heat dissipation capacity to the step duration is calculated as the predicted rate of change of heat dissipation capacity. A second ratio is then calculated between the predicted rate of change of heat dissipation capacity and the rate of change of output power. Candidate adjustment combinations that make the second ratio fall within the preset coordination interval are selected, and the combination that minimizes the absolute value of the deviation between the second ratio and the center value of the preset coordination interval is selected as the final adjustment scheme from the selection results.

[0011] The method also includes determining the output power change rate and determining the current heat dissipation capacity: Determine the steady-state values ​​of output power before and after the step change, and calculate the difference between the two steady-state values ​​as the power step amplitude; measure the time elapsed from the moment of the step change until the output power reaches the steady-state value after the step change as the step duration; determine the output power change rate based on a first ratio of the power step amplitude to the step duration. Extract the benchmark value of heat dissipation capacity per unit area corresponding to the current heat dissipation fin spacing from the matching relationship, obtain the current cooling medium flow rate, and take the product of the current cooling medium flow rate, the benchmark value of heat dissipation capacity per unit area, and the effective heat dissipation area of ​​the heat dissipation fins as the current heat dissipation capacity.

[0012] The cooling medium flow rate adjustment is added to the current cooling medium flow rate, and the predicted heat dissipation capacity is calculated based on the adjusted flow rate. The dead time adjustment is added to the current dead time, and the switching loss and conduction loss are recalculated based on the adjusted dead time to determine the predicted output power, including: Extract the cooling medium flow rate adjustment from the candidate adjustment combination, add the adjusted cooling medium flow rate to the current cooling medium flow rate to obtain the adjusted cooling medium flow rate; and calculate the adjusted convective heat transfer coefficient by substituting the adjusted cooling medium flow rate into the power function relationship between the cooling medium flow rate and the convective heat transfer coefficient. The adjusted convective heat transfer coefficient is multiplied by the effective heat dissipation area of ​​the heat dissipation fins and the temperature difference between the surface temperature of the heat dissipation fins and the ambient temperature to calculate the adjusted heat dissipation power, which is then used as the predicted value of the heat dissipation capacity. Extract the dead time adjustment from the candidate adjustment combination, add the dead time adjustment to the current dead time to obtain the adjusted dead time; calculate the actual on-time and actual off-time of the switch in one pulse width modulation cycle based on the adjusted dead time, and calculate the adjusted conduction loss by multiplying the actual on-time by the on-resistance and the square of the on-state current of the switch. Based on the adjusted dead time, calculate the time period during which voltage and current coexist during the switching process and turn-off of the switching transistor, and calculate the adjusted switching loss by integrating the instantaneous voltage and current values ​​over time during the time period; The adjusted conduction loss is added to the adjusted switching loss to obtain the adjusted total loss. The predicted output power value is determined based on the difference between the input power of the power control circuit and the adjusted total loss.

[0013] A second aspect of the present invention provides a high-power gallium nitride device thermal management and electrical co-optimization system, comprising: The first unit is used to determine the heat conduction time coefficients of each level of the heat dissipation system of gallium nitride devices from the heat source to the environment, extract the pulse width modulation period of the power control circuit, and establish the correlation mapping relationship between the heat conduction time coefficients of each level and the pulse width modulation period; The second unit is used to calculate the hot spot temperature gradient under different operating modes based on the correlation mapping relationship, determine the matching relationship between the heat dissipation fin spacing in the heat dissipation system and the switching time in the power control circuit based on the hot spot temperature gradient, and adjust the heat dissipation fin spacing and the switching time to make the time difference between the response time when the heat dissipation system reaches its peak heat dissipation capacity and the time when the power control circuit outputs the maximum power less than a preset synchronization threshold. The third unit is used to synchronously adjust the cooling medium flow rate of the heat dissipation system and the dead time of the power control circuit according to the matching relationship. When the output power of the power control circuit changes abruptly, the ratio of the rate of change of the heat dissipation capacity of the heat dissipation system to the rate of change of the output power is maintained within a preset coordinated range through the coordinated control between the adjustment amount of the cooling medium flow rate and the adjustment amount of the dead time. The fourth unit is used to generate the design parameters of the heat dissipation system and the control parameters of the power control circuit based on the adjusted heat dissipation fin spacing, switching transistor conduction time, cooling medium flow rate and dead time, and to control the heat dissipation intensity of the heat dissipation system and the switching action of the power control circuit.

[0014] A third aspect of the present invention, An electronic device is provided, comprising: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the aforementioned method.

[0015] Fourth aspect of the present invention, A computer-readable storage medium is provided, having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0016] The beneficial effects of this application are as follows: By establishing a correlation mapping relationship between the heat conduction time coefficient and the pulse width modulation period, time-domain coordination between the heat dissipation system and the power control circuit is realized, enabling the system to accurately predict and respond to hot spot temperature changes and improve heat dissipation efficiency.

[0017] By optimizing the matching relationship between the spacing of the heat sink fins and the conduction time of the switching transistor, the response time of the heat dissipation system to reach its peak heat dissipation capacity is synchronized with the time when the power control circuit outputs the maximum power. This avoids the problem of device overheating caused by heat dissipation lag and significantly improves the thermal stability of the system.

[0018] By employing a coordinated control strategy of cooling medium flow rate and dead time, the rate of change of heat dissipation capacity and the rate of change of output power are kept in dynamic balance. Especially under the condition of step power change, it can achieve real-time matching of heat dissipation and power consumption, reduce temperature fluctuations, and extend device life. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the thermal management and electrical synergistic optimization method for high-power gallium nitride devices according to an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0022] Figure 1 This is a flowchart illustrating the thermal management and electrical co-optimization method for high-power gallium nitride devices according to an embodiment of the present invention. Figure 1 As shown, the method includes: The heat conduction time coefficients of each level of the heat dissipation system of gallium nitride devices from the heat source to the environment are determined, and the pulse width modulation period of the power control circuit is extracted to establish the correlation mapping relationship between the heat conduction time coefficients of each level and the pulse width modulation period; Based on the aforementioned correlation mapping relationship, the hot spot temperature gradient under different operating modes is calculated. According to the hot spot temperature gradient, the matching relationship between the heat dissipation fin spacing in the heat dissipation system and the switching time in the power control circuit is determined. By adjusting the heat dissipation fin spacing and the switching time, the time difference between the response time when the heat dissipation system reaches its peak heat dissipation capacity and the time when the power control circuit outputs maximum power is less than a preset synchronization threshold. Based on the matching relationship, the cooling medium flow rate of the heat dissipation system and the dead time of the power control circuit are adjusted synchronously. When the output power of the power control circuit changes abruptly, the ratio of the rate of change of the heat dissipation capacity of the heat dissipation system to the rate of change of the output power is maintained within a preset coordinated range through the coordinated control between the adjustment amount of the cooling medium flow rate and the adjustment amount of the dead time. Based on the adjusted heat sink fin spacing, switching transistor conduction time, cooling medium flow rate, and dead time, the heat dissipation system design parameters and power control circuit control parameters are generated to control the heat dissipation intensity of the heat dissipation system and the switching action of the power control circuit.

[0023] In one optional implementation, determining the heat conduction time coefficients of each level of the gallium nitride device's heat dissipation system from the heat source to the environment, extracting the pulse width modulation period of the power control circuit, and establishing the correlation mapping relationship between the heat conduction time coefficients of each level and the pulse width modulation period includes: The gallium nitride device includes a chip packaging layer, a thermally conductive interface material layer, a metal substrate layer, a heat dissipation fin layer, and a convection heat transfer layer. The thermal resistance is calculated based on the ratio of the thickness to the thermal conductivity of each layer in the gallium nitride device. The heat capacity is calculated based on the product of the contact area, thickness, density, and specific heat capacity of each layer. The thermal resistance and heat capacity are multiplied to obtain the heat conduction time coefficient. The ratio of the heat conduction time coefficient to the pulse width modulation period is then determined. When the ratio is less than a preset fast response threshold, the level is classified as a fast response level, and a one-to-one mapping relationship is established between its heat conduction time coefficient and the on-time of the switching transistor within a single pulse width modulation cycle; when the ratio is between the preset fast response threshold and the preset slow response threshold, the level is classified as a medium-speed response level, and a mapping relationship is established between the heat conduction time coefficient of this level and the cumulative time of multiple consecutive pulse width modulation cycles. When the ratio is greater than the preset slow response threshold, the level is divided into a slow response level, and a mapping relationship is established between the heat conduction time constant and the duty cycle change envelope corresponding to multiple continuous pulse width modulation periods.

[0024] Determine the heat transfer time coefficients of each layer in the heat dissipation system of a gallium nitride (GaN) device, from the heat source to the environment. In practical applications, the heat dissipation system of a GaN device typically includes a chip packaging layer, a thermally conductive interface material layer, a metal substrate layer, a heat sink fin layer, and a convection heat transfer layer. Each layer has different thermophysical properties, which determine the rate of heat conduction between layers.

[0025] For the chip packaging layer, a typical packaging material is selected, with a thickness of 0.5 mm, a thermal conductivity of 25 W / m·K, a contact area of ​​100 square millimeters, a density of 2200 kg / m³, and a specific heat capacity of 700 J / kg·K. According to the thermal resistance calculation formula: Thermal Resistance = Thickness / (Thermal Conductivity × Area), the thermal resistance of the chip packaging layer is 0.2 K / W. The heat capacity calculation formula is: Heat Capacity = Area × Thickness × Density × Specific Heat Capacity, yielding a heat capacity of 77 J / K for the chip packaging layer. Multiplying the thermal resistance and heat capacity values ​​gives a heat conduction time coefficient of 15.4 milliseconds.

[0026] For the thermally conductive interface material layer, its thickness is 0.1 mm, its thermal conductivity is 5 W / m·K, its contact area is 100 mm², its density is 3000 kg / m³, and its specific heat capacity is 1000 J / kg·K. The calculated thermal resistance is 0.2 K / W, the heat capacity is 30 J / K, and the thermal conduction time coefficient is 6 ms.

[0027] The metal substrate layer is typically made of aluminum or copper, with a thickness of 3 mm, a thermal conductivity of 200 W / m·K, a contact area of ​​400 mm², a density of 8900 kg / m³, and a specific heat capacity of 380 J / kg·K. The calculated thermal resistance is 0.0375 K / W, the heat capacity is 4060.8 J / K, and the thermal conductivity time coefficient is 152 ms.

[0028] The heat dissipation fin layer consists of multiple fins with an equivalent thickness of 20 mm, an equivalent thermal conductivity of 150 W / m·K, a contact area of ​​1600 mm², a density of 2700 kg / m³, and a specific heat capacity of 900 J / kg·K. The calculated thermal resistance is 0.0833 K / W, the heat capacity is 77760 J / K, and the heat transfer time coefficient is 6477 ms.

[0029] The convection heat transfer layer is the interface between the heat dissipation system and the ambient air. Its heat transfer characteristics are mainly determined by the heat transfer coefficient and the heat transfer area. Under natural convection conditions, the heat transfer coefficient is 10 W / m²·K, the heat transfer area is 0.02 m², the calculated thermal resistance is 5 K / W, the heat capacity is mainly determined by the surrounding air, assumed to be 10,000 J / K, and the heat conduction time coefficient is approximately 50,000 milliseconds.

[0030] The pulse width modulation period of the power control circuit is extracted. In this embodiment, the gallium nitride power device operates in a power conversion circuit with a switching frequency of 100 kHz, and the corresponding pulse width modulation period is 10 microseconds.

[0031] Based on the above calculation results, a correlation mapping relationship between the heat conduction time coefficient of each level and the pulse width modulation period is established. First, the preset fast response threshold is determined to be 100, and the preset slow response threshold is determined to be 10000.

[0032] For the chip packaging layer, the ratio of its thermal conduction time coefficient to the pulse width modulation period is 15.4 ms / 0.01 ms = 1540. This ratio is greater than the preset fast response threshold of 100, but less than the preset slow response threshold of 10000. Therefore, the chip packaging layer is classified as a medium-speed response level. In actual control, a mapping relationship is established between the thermal conduction time coefficient of the chip packaging layer and the cumulative time of 100 consecutive pulse width modulation periods (corresponding to 1 ms).

[0033] For the thermally conductive interface material layer, the ratio of its thermal conduction time coefficient to the pulse width modulation period is 6 milliseconds / 0.01 milliseconds = 600, which is also between the preset fast response threshold and the preset slow response threshold. It is divided into the medium-speed response level and a mapping relationship is established with the cumulative time of 50 consecutive pulse width modulation periods.

[0034] For the metal substrate layer, the ratio of its heat conduction time coefficient to the pulse width modulation period is 152 ms / 0.01 ms = 15200, which is greater than the preset slow response threshold of 10000. Therefore, the metal substrate layer is classified as a slow response layer. A mapping relationship is established between the heat conduction time coefficient of the metal substrate layer and the envelope of the duty cycle change corresponding to the pulse width modulation period. Specifically, this is manifested by predicting the temperature change of the metal substrate layer by monitoring the change trend of the duty cycle within 1500 consecutive cycles (15 ms).

[0035] For the heat dissipation fin layer, the ratio of its heat conduction time coefficient to the pulse width modulation period is 6477 ms / 0.01 ms = 647700, which is much larger than the preset slow response threshold. It is classified as a slow response level and a mapping relationship is established with the duty cycle change envelope within 6500 consecutive cycles (65 ms).

[0036] For the convective heat transfer layer, the ratio of its heat conduction time coefficient to the pulse width modulation period is 50000 ms / 0.01 ms = 5000000, which is also much larger than the preset slow response threshold. It is divided into a slow response level and a mapping relationship is established with the duty cycle change envelope within 50000 consecutive cycles (500 ms).

[0037] By establishing the aforementioned hierarchical mapping relationship, the thermal management strategy for gallium nitride (GaN) devices can be optimized at different time scales. For the fast response level, the power can be directly adjusted based on the on-time of the switching transistor within a single pulse width modulation cycle. For the medium response level, the power control parameters are adjusted by monitoring the cumulative effect over multiple consecutive cycles. For the slow response level, thermal management strategies need to be implemented based on the duty cycle variation trend over a longer period, such as adjusting the cooling fan speed or actively reducing system power.

[0038] By mapping the hierarchical thermal conduction time coefficient to the pulse width modulation period, fine-grained management of different thermal conduction paths in gallium nitride devices can be achieved, improving system reliability and power density.

[0039] In one optional implementation, calculating the hotspot temperature gradient under different operating modes based on the correlation mapping relationship, and determining the matching relationship between the heat dissipation fin spacing in the heat dissipation system and the on-time of the switching transistor in the power control circuit based on the hotspot temperature gradient includes: Extract the heat transfer paths corresponding to the heat conduction time coefficients of each level of the heat dissipation system in the associated mapping relationship, and identify the bottleneck areas with the highest thermal resistance density in the heat transfer paths; calculate the instantaneous loss distribution of the switching transistors of the power control circuit under different operating modes, and determine the hot spot location coordinates corresponding to each operating mode based on the positional relationship between the instantaneous loss distribution and the bottleneck areas; For each hot spot location, calculate the temperature gradient value from that location to the surface of the heat sink fins. Then, correlate the temperature gradient value with the reciprocal of the heat sink fin spacing to establish an inverse proportional constraint relationship between the temperature gradient value and the heat sink fin spacing. Extract the switching loss curves of the switching transistor in the power control circuit at different conduction times, and identify the time period with the largest loss rise rate in the switching loss curve; The spacing of the heat dissipation fins corresponding to the maximum temperature gradient value in the inverse proportional constraint relationship is paired with the conduction time of the switch in the time period. By iteratively adjusting the spacing of the heat dissipation fins and the conduction time of the switch, the time difference between the moment when the heat dissipation system absorbs the peak heat flow and the moment when the power control circuit generates the peak loss is converged to within the preset synchronization threshold.

[0040] The heat transfer paths corresponding to the heat conduction time coefficients of each layer of the heat dissipation system are extracted from the correlation mapping relationship. Specifically, the heat conduction parameters of the multi-layer structure from the junction temperature point of the switching transistor to the surface of the heat sink fins in the power control system are collected, including the heat conduction coefficients of the switching transistor chip, substrate, thermal paste, heat sink base, and heat sink fins. A three-dimensional heat conduction model is established using thermal flow field analysis software, and the thermal network method is used to simplify each layer structure into a parallel thermal resistance network. The heat conduction time coefficient τi=CiRi of each layer structure is calculated, where Ci represents the heat capacity and Ri represents the thermal resistance.

[0041] In the heat transfer path, the bottleneck region with the highest thermal resistance density is identified. By calculating the thermal resistance value per square centimeter, a thermal resistance density cloud map is plotted, and the region where the thermal resistance value exceeds a preset threshold (such as more than twice the average thermal resistance value of the system) is located as the bottleneck region. In practical applications, this bottleneck region is usually located at the contact interface between the solder layer between the switching transistor chip and the substrate, or between the thermal paste and the heat sink base.

[0042] The instantaneous loss distribution of the switching transistor in the power control circuit under different operating modes (such as light load, medium load, and heavy load) is calculated. Taking dual pulse width modulation control as an example, the voltage and current waveforms of the switching transistor in the three operating modes are collected, and the conduction loss Pon=I²Ron and the switching loss Psw=(UI·tr) / 2 are calculated respectively, where I is the conduction current, Ron is the conduction resistance, U is the switching voltage, and tr is the rise time. Based on the loss data and the spatial distribution of the bottleneck area, the coordinates of the hot spot location (xi,yi,zi) corresponding to each operating mode are determined by thermal field simulation.

[0043] For each hotspot location coordinate, the temperature gradient from that location to the heatsink fin surface is calculated. Using the finite element method, a multi-point temperature sampling line is established from the hotspot to the fin surface. The temperature gradient G = ΔT / Δd is calculated under different power densities, where ΔT is the temperature difference and Δd is the spatial distance. For example, under heavy load operation, the temperature gradient from a certain hotspot location to the fin surface is 12℃ / mm.

[0044] The calculated temperature gradient value is correlated with the reciprocal of the heat sink fin spacing to establish an inverse proportional constraint relationship between the two. The relationship G=k / S is determined through data fitting, where G is the temperature gradient value, S is the heat sink fin spacing, and k is the fitting coefficient. In experimental verification, when the temperature gradient is 12℃ / mm, the optimal heat sink fin spacing is approximately 2.5mm.

[0045] Subsequently, the switching loss curves of the switching transistor in the power control circuit at different conduction times were extracted. A sweep test was performed on the conduction time of the switching transistor within the range of 100 ns to 5 μs, and the switching loss value at each time point was recorded, plotting the loss-time curve. By calculating the loss difference between adjacent time points, the time period with the largest loss rise rate was identified. For example, in the tested power MOSFET, the loss rise rate reached its maximum value of 0.8 W / ns in the range where the conduction time increased from 200 ns to 500 ns.

[0046] The spacing of the heat sink fins corresponding to the maximum temperature gradient value in the inverse proportional constraint relationship is paired with the on-time of the switching transistor within a time period. For the case of a maximum temperature gradient of 12℃ / mm, the optimal heat sink fin spacing is 2.5mm, and the corresponding optimal on-time of the switching transistor is 350ns. Through an iterative adjustment process, the heat sink fin spacing (e.g., in 0.1mm increments) and the switching transistor on-time (e.g., in 10ns increments) are gradually changed. The time difference between the moment when the heat dissipation system absorbs the peak heat flux and the moment when the power control circuit generates the peak loss is calculated after each adjustment. When this difference is less than a preset synchronization threshold (e.g., 50ns), the optimal matching state is considered to have been achieved.

[0047] The above methods achieve a coordinated design between the heat dissipation system and the power control circuit, effectively improving the heat dissipation efficiency and stability of the power control system. In practical application tests, the power control system designed using this matching method, compared with the traditional design method, showed a maximum temperature reduction of approximately 15% and a system efficiency improvement of approximately 8% at the same power output.

[0048] In one optional implementation, the spacing of the heat dissipation fins corresponding to the maximum temperature gradient value in the inverse proportional constraint relationship is paired with the on-time of the switching transistor within the time period. By iteratively adjusting the spacing of the heat dissipation fins and the on-time of the switching transistor, the time difference between the moment when the heat dissipation system absorbs the peak heat flow and the moment when the power control circuit generates the peak loss converges to within the preset synchronization threshold, including: Identify the initial value of the heat sink fin spacing corresponding to the maximum value of the temperature gradient from the inverse proportional constraint relationship; extract the initial value of the switch turn-on time corresponding to the maximum loss rise rate from the time period; and form an initial pairing parameter group by combining the initial value of the heat sink fin spacing and the initial value of the switch turn-on time. Calculate the thermal response delay time required for the heat dissipation system to reach peak heat dissipation capacity from receiving heat flow based on the initial value of the heat dissipation fin spacing; calculate the electrical response delay time required for the power control circuit to generate peak loss from the start of switching action based on the initial value of the switching transistor conduction time. Calculate the time difference between the time corresponding to the thermal response delay time and the time corresponding to the electrical response delay time, and determine whether the time difference is less than the preset synchronization threshold. When the time difference is greater than or equal to the preset synchronization threshold, the adjustment direction is determined according to the sign of the time difference. When the time difference is positive, the heat sink fin spacing is reduced and the switching transistor conduction time is increased. When the time difference is negative, the heat sink fin spacing is increased and the switching transistor conduction time is reduced. The spacing between the heat sink fins and the turn-on time of the switching transistor are synchronously adjusted according to the adjustment direction. After adjustment, the thermal response delay time and electrical response delay time are recalculated, and the time difference is updated. The above judgment and adjustment operation is repeated until the time difference converges to less than the preset synchronization threshold. The spacing between the heat sink fins and the turn-on time of the switching transistor at the time of convergence are used as the final pairing parameter group.

[0049] In this embodiment, it will be explained in detail how to improve heat dissipation efficiency by iteratively adjusting the spacing of the heat sink fins and the conduction time of the switching transistor so that the moment when the heat dissipation system absorbs the peak heat flow is synchronized with the moment when the power control circuit generates the peak loss.

[0050] The initial fin spacing is identified from the inverse proportional constraint relationship to determine when the temperature gradient reaches its maximum value. Specifically, a mathematical model of the fin spacing and temperature gradient is established to analyze the temperature distribution under different fin spacings. When the temperature gradient reaches its maximum value, the fin spacing at that point is recorded as the initial value. For example, by simulating the heat dissipation effect under different fin spacings using finite element analysis software, when the temperature gradient reaches its maximum value of 2.5℃ / mm, the corresponding initial fin spacing might be 2.8mm.

[0051] Extract the initial value of the switching transistor's on-time corresponding to the point of maximum loss rise rate within a time period. By analyzing the loss curves of the switching transistor at different on-times, calculate the rate of change of loss over time, identify the point with the largest rate of change, and use the switching transistor's on-time at that point as the initial value. For example, when the loss rise rate of the power control circuit reaches its maximum value, record the initial value of the switching transistor's on-time as 15 microseconds.

[0052] The initial pairing parameter set is composed of the initial value of the heat sink fin spacing and the initial value of the switching transistor conduction time, in the form of (2.8mm, 15 microseconds). This set of parameters will serve as the starting point for subsequent iterative adjustments.

[0053] The thermal response delay time required for the cooling system to reach its peak heat dissipation capacity from receiving heat flux is calculated based on the initial fin spacing. After the cooling system receives heat flux, heat transfer requires a certain amount of time to fully unfold due to the heat capacity and thermal resistance of the materials. This time depends on factors such as the fin spacing and the thermal conductivity of the materials. The thermal response delay time can be obtained through calculation using a heat conduction model, such as thermal network analysis. Assuming an initial fin spacing of 2.8 mm corresponds to a thermal response delay time of 250 microseconds.

[0054] The electrical response delay time required for the power control circuit to generate peak losses from the start of switching action is calculated based on the initial value of the switch's on-time. This process involves the switch's turn-on process, current rise time, and the moment when peak losses occur. The electrical response delay time can be obtained through circuit model analysis, such as using SPICE simulation tools. Assuming an initial switch on-time of 15 microseconds corresponds to an electrical response delay time of 220 microseconds.

[0055] Calculate the time difference between the time corresponding to the thermal response delay and the time corresponding to the electrical response delay, i.e., 250 microseconds - 220 microseconds = 30 microseconds. Determine if the time difference is less than the preset synchronization threshold. Assuming the preset synchronization threshold is 10 microseconds, then 30 microseconds is greater than 10 microseconds, and adjustment is required.

[0056] Since the time difference is positive (30 microseconds > 0), it indicates that the cooling system reaches its peak cooling capacity later than the power control circuit generates peak losses. Therefore, it's necessary to reduce the spacing between the heat sink fins and increase the switching transistor's on-time. According to the inverse proportionality constraint, reducing the heat sink fin spacing can advance the time when the cooling system reaches its peak cooling capacity; increasing the switching transistor's on-time can delay the time when the power control circuit generates peak losses.

[0057] Following the aforementioned adjustment direction, the heatsink fin spacing and switching transistor turn-on time are adjusted synchronously. For example, the heatsink fin spacing is adjusted to 2.6mm, and the switching transistor turn-on time is adjusted to 16 microseconds, forming a new pairing parameter set (2.6mm, 16 microseconds).

[0058] Recalculate the adjusted thermal response delay and electrical response delay. Assume the new heatsink fin spacing of 2.6mm corresponds to a thermal response delay of 235 microseconds, and the new switching transistor turn-on time of 16 microseconds corresponds to an electrical response delay of 230 microseconds. The update time difference is 235 microseconds - 230 microseconds = 5 microseconds.

[0059] Determine if the updated time difference of 5 microseconds is less than the preset synchronization threshold of 10 microseconds. Since 5 microseconds < 10 microseconds, the time difference has converged to within the preset synchronization threshold, and the iterative adjustment is complete. Use the heat sink fin spacing of 2.6mm and the switching transistor conduction time of 16 microseconds at the time of convergence as the final pairing parameter set (2.6mm, 16 microseconds).

[0060] In practical applications, temperature sensors can be used to monitor the temperature distribution of the heat dissipation system in real time, and current and voltage sensors can be used to monitor the losses of the power control circuit. Based on the monitoring data, the spacing of the heat dissipation fins (e.g., through an adjustable fin structure) and the conduction time of the switching transistors (e.g., by adjusting the PWM control signal) can be dynamically adjusted to achieve the best match between the heat dissipation system and the power control circuit.

[0061] This method is particularly suitable for high power density electronic devices, such as motor controllers in electric vehicles and cooling systems for high-performance computing equipment. By synchronizing the timing of peak heat flux absorption by the cooling system with the timing of peak power loss generated by the power control circuit, the cooling capacity of the cooling system can be maximized, improving overall system efficiency, extending equipment life, and reducing failure rates.

[0062] In one optional implementation, the cooling medium flow rate of the heat dissipation system and the dead time of the power control circuit are synchronously adjusted according to the matching relationship. When the output power of the power control circuit undergoes a step change, the ratio of the rate of change of the heat dissipation capacity of the heat dissipation system to the rate of change of the output power is maintained within a preset coordinated range through coordinated control between the adjustment amount of the cooling medium flow rate and the adjustment amount of the dead time. A candidate adjustment sequence for the cooling medium flow rate is set based on the flow rate adjustment range of the cooling medium conveying device, and a candidate adjustment sequence for the dead time is set based on the dead time adjustment range of the drive circuit. The two sequences are then combined to form a candidate adjustment combination set. The cooling medium flow rate adjustment is added to the current cooling medium flow rate, and the predicted heat dissipation capacity is calculated based on the adjusted flow rate. The dead time adjustment is added to the current dead time, and the switching loss and conduction loss are recalculated based on the adjusted dead time to determine the predicted output power. The ratio of the difference between the predicted heat dissipation capacity and the current heat dissipation capacity to the step duration is calculated as the predicted rate of change of heat dissipation capacity. A second ratio is then calculated between the predicted rate of change of heat dissipation capacity and the rate of change of output power. Candidate adjustment combinations that make the second ratio fall within the preset coordination interval are selected, and the combination that minimizes the absolute value of the deviation between the second ratio and the center value of the preset coordination interval is selected as the final adjustment scheme from the selection results.

[0063] The cooling medium flow rate of the heat dissipation system and the dead time of the power control circuit are adjusted synchronously according to the matching relationship. This is mainly used to maintain the ratio of the rate of change of the heat dissipation capacity of the heat dissipation system to the rate of change of the output power within a preset range when the output power of the power control circuit changes abruptly, thereby achieving stable and efficient operation of the circuit.

[0064] The system obtains the operating parameters of the power control circuit and the cooling system. The operating parameters of the power control circuit include the current switching frequency, dead time, on-time ratio, current and voltage values, etc. The parameters of the cooling system include the current cooling medium flow rate, the thermal resistance characteristics of the heat exchanger, and the heat dissipation efficiency, etc. Based on these parameters, the current output power value and the current heat dissipation capacity value can be calculated, and a matching relationship between the two can be established.

[0065] When a step change in the output power of the power control circuit is detected, the rate of change of output power is first calculated. Assuming the output power changes from P1 to P2, and the step duration is T, the rate of change of output power can be expressed as (P2-P1) / T. This rate of change is a key reference value for coordinated control, and the rate of change of heat dissipation capacity will be kept in a certain proportional relationship with it by adjusting the parameters of the heat dissipation system.

[0066] The candidate adjustment sequence of the cooling medium flow rate is set according to the flow rate adjustment range of the cooling medium delivery device. For example, if the current cooling medium flow rate is v and the flow rate adjustment range is [v_min, v_max], the candidate adjustment sequence can be set as {-Δv3, -Δv2, -Δv1, 0, +Δv1, +Δv2, +Δv3}, where Δv1<Δv2<Δv3 and satisfies the conditions v-Δv3≥v_min and v+Δv3≤v_max.

[0067] Simultaneously, a candidate adjustment sequence for the dead time is set based on the adjustable range of the dead time of the drive circuit. If the current dead time is t_d and the adjustable range of the dead time is [t_d_min, t_d_max], then the candidate adjustment sequence is set as {-Δt3, -Δt2, -Δt1, 0, +Δt1, +Δt2, +Δt3}, where Δt1<Δt2<Δt3 and satisfies the conditions t_d-Δt3≥t_d_min and t_d+Δt3≤t_d_max.

[0068] The two sequences are combined to form a set of candidate adjustment combinations. For the two candidate adjustment sequences, a total of 7×7=49 adjustment combinations are formed. Each combination contains a cooling medium flow rate adjustment and a dead time adjustment, such as (0,0), (-Δv1,+Δt2), (+Δv3,-Δt1), etc.

[0069] For each candidate combination of adjustment values, the predicted values ​​of the adjusted heat dissipation capacity and output power are calculated. First, the adjusted cooling medium flow rate is added to the current cooling medium flow rate to obtain the adjusted cooling medium flow rate. According to the heat transfer model, there is usually a non-linear relationship between the cooling medium flow rate and the heat dissipation capacity. The predicted heat dissipation capacity corresponding to the adjusted flow rate can be determined by empirical formulas or table lookup methods.

[0070] The adjusted dead time is obtained by adding the dead time adjustment to the current dead time. Dead time affects switching losses and conduction losses, which in turn affect output power. Based on the loss model in power electronics, the switching losses and conduction losses are recalculated to determine the predicted value of the adjusted output power.

[0071] The ratio of the predicted rate of change of heat dissipation capacity to the rate of change of output power is calculated. The predicted rate of change of heat dissipation capacity equals the difference between the predicted heat dissipation capacity and the current heat dissipation capacity, divided by the step duration. The rate of change of output power has already been calculated. The ratio of the two is the second ratio, which is the core indicator of coordinated control.

[0072] The preset coordination range is typically determined by the system designer based on device characteristics, reliability requirements, and efficiency targets. For example, it can be set to [0.95, 1.05], indicating that the rate of change in heat dissipation capacity should basically match the rate of change in output power, with a slight redundancy. For all candidate adjustment combinations, the combination that makes the second ratio fall within the preset coordination range is selected. If multiple combinations meet the condition, the combination that minimizes the absolute value of the deviation between the second ratio and the center value of the preset coordination range is chosen as the final adjustment scheme.

[0073] In this embodiment, it is assumed that the output power of the power control circuit increases from 800W to 1000W, with a step duration of 2 seconds and an output power change rate of 100W / s. The current cooling medium flow rate is 2L / min, and the current dead time is 200ns. Calculations show that among all adjustment schemes that meet the coordination interval [0.95, 1.05] requirement, the combination of a cooling medium flow rate adjustment of +0.4L / min and a dead time adjustment of -20ns results in a ratio of 1.02, which is closest to the center value of the coordination interval (1.0). Therefore, this combination is selected as the final adjustment scheme.

[0074] The finalized adjustment scheme was applied to the heat dissipation system and power control circuit. Specifically, a control signal was sent to the cooling medium delivery device to adjust the cooling medium flow rate from 2 L / min to 2.4 L / min; simultaneously, a control signal was sent to the drive circuit to adjust the dead time from 200 ns to 180 ns. This coordinated adjustment ensures that the response of the heat dissipation system matches the power change during power step variations, avoiding overcooling or overheating and improving system efficiency and reliability.

[0075] In one alternative implementation, the method further includes determining the output power change rate and determining the current heat dissipation capacity: Determine the steady-state values ​​of output power before and after the step change, and calculate the difference between the two steady-state values ​​as the power step amplitude; measure the time elapsed from the moment of the step change until the output power reaches the steady-state value after the step change as the step duration; determine the output power change rate based on a first ratio of the power step amplitude to the step duration. Extract the benchmark value of heat dissipation capacity per unit area corresponding to the current heat dissipation fin spacing from the matching relationship, obtain the current cooling medium flow rate, and take the product of the current cooling medium flow rate, the benchmark value of heat dissipation capacity per unit area, and the effective heat dissipation area of ​​the heat dissipation fins as the current heat dissipation capacity.

[0076] To determine the rate of change of output power, key data is obtained by measuring the power parameters of the electronic device during the step change process. Specifically, during system operation, the measuring device continuously monitors the output power of the electronic device, recording the steady-state output power value P1 before the step change and the steady-state output power value P2 after the step change. The criterion for determining the steady-state value is: when the fluctuation range of the output power within a specific time window (e.g., 30 consecutive seconds) is less than a preset threshold (e.g., 2% of full scale), the system is considered to have reached a steady state. The difference between the two steady-state values, ΔP = P2 - P1, is calculated to obtain the power step amplitude.

[0077] Simultaneously, the system records the moment of the step change, t1, which is the point at which the output power begins to deviate significantly from the initial steady-state value P1, and the moment t2, when the output power first reaches and stabilizes at P2. The difference between the two time points, ΔT = t2 - t1, is the step duration. The system calculates the rate of change of output power based on the ratio of the power step amplitude to the step duration, ΔP / ΔT.

[0078] To determine the current heat dissipation capacity, the baseline value h0 of the heat dissipation capacity per unit area corresponding to the current fin spacing is first extracted from a pre-established matching relationship database. This matching relationship is obtained through fitting a large amount of experimental data and reflects the benchmark of heat dissipation performance under different fin spacings. For example, when the fin spacing is 2 mm, the corresponding baseline value of heat dissipation capacity per unit area may be 0.08 W / cm² / °C; while when the spacing increases to 3 mm, this value may drop to 0.06 W / cm² / °C.

[0079] Obtain the current cooling medium flow rate v. The cooling medium flow rate is usually obtained by real-time measurement using a flow rate sensor, or it can be indirectly estimated from a calibration curve of fan speed versus flow rate. The cooling medium flow rate has a significant impact on heat dissipation capacity; the flow rate and heat dissipation capacity are approximately linearly positively correlated.

[0080] Calculate the effective heat dissipation area A of the heat sink fins. The effective heat dissipation area includes all surface areas that are in direct contact with the cooling medium and participate in heat exchange, and can be calculated from the fin geometry. For regularly shaped fins, such as rectangular fins, the effective heat dissipation area can be expressed as a function of fin height, width, number, and surface roughness correction factor.

[0081] The current heat dissipation capacity Q = v × h0 × A is calculated by multiplying the current cooling medium flow rate v, the baseline value of heat dissipation capacity per unit area h0, and the effective heat dissipation area A of the heat sink fins. This heat dissipation capacity represents the maximum amount of heat that the cooling system can transfer from the electronic device to the environment under the current operating conditions.

[0082] The output power change rate and current heat dissipation capacity determined by the above methods provide a scientific basis for the dynamic adjustment of the heat dissipation system parameters. When the output power change rate is high, the system can predict rapid changes in heat load and adjust the fin spacing in advance to meet the upcoming heat dissipation demand. When it is determined that the current heat dissipation capacity is insufficient to meet the heat dissipation needs of electronic devices, the system can appropriately reduce the heat dissipation fin spacing to improve the heat dissipation efficiency per unit area; conversely, it can increase the spacing to reduce energy consumption. This intelligent control strategy based on real-time data ensures that the heat dissipation system always operates in the optimal state, guaranteeing the safe and reliable operation of electronic devices while maximizing energy savings.

[0083] In one optional implementation, the cooling medium flow rate adjustment is added to the current cooling medium flow rate, and the predicted heat dissipation capacity is calculated based on the adjusted flow rate; the dead time adjustment is added to the current dead time, and the switching loss and conduction loss are recalculated based on the adjusted dead time to determine the predicted output power, including: Extract the cooling medium flow rate adjustment from the candidate adjustment combination, add the adjusted cooling medium flow rate to the current cooling medium flow rate to obtain the adjusted cooling medium flow rate; and calculate the adjusted convective heat transfer coefficient by substituting the adjusted cooling medium flow rate into the power function relationship between the cooling medium flow rate and the convective heat transfer coefficient. The adjusted convective heat transfer coefficient is multiplied by the effective heat dissipation area of ​​the heat dissipation fins and the temperature difference between the surface temperature of the heat dissipation fins and the ambient temperature to calculate the adjusted heat dissipation power, which is then used as the predicted value of the heat dissipation capacity. Extract the dead time adjustment from the candidate adjustment combination, add the dead time adjustment to the current dead time to obtain the adjusted dead time; calculate the actual on-time and actual off-time of the switch in one pulse width modulation cycle based on the adjusted dead time, and calculate the adjusted conduction loss by multiplying the actual on-time by the on-resistance and the square of the on-state current of the switch. Based on the adjusted dead time, calculate the time period during which voltage and current coexist during the switching process and turn-off of the switching transistor, and calculate the adjusted switching loss by integrating the instantaneous voltage and current values ​​over time during the time period; The adjusted conduction loss is added to the adjusted switching loss to obtain the adjusted total loss. The predicted output power value is determined based on the difference between the input power of the power control circuit and the adjusted total loss.

[0084] The cooling medium flow rate adjustment is extracted from the candidate adjustment combination. This combination includes multiple pre-calculated adjustment parameters generated based on system operating status, environmental conditions, and historical data. The extracted cooling medium flow rate adjustment is added to the current cooling medium flow rate to obtain the adjusted flow rate. For example, if the current cooling medium flow rate is 2 m / s and the adjustment is 0.5 m / s, the adjusted flow rate will be 2.5 m / s.

[0085] The adjusted convective heat transfer coefficient is calculated based on the power function relationship between the cooling medium velocity and the convective heat transfer coefficient. This power function relationship can be expressed as: h = k·v^n, where h is the convective heat transfer coefficient, k is the proportionality coefficient, v is the cooling medium velocity, and n is the power exponent. The proportionality coefficient k and the power exponent n are determined based on the type of cooling medium, flow state, and heat transfer surface shape. In air cooling systems, n is typically taken between 0.5 and 0.8. Substituting the adjusted cooling medium velocity into this function yields the adjusted convective heat transfer coefficient.

[0086] The heat dissipation power is equal to the product of the convective heat transfer coefficient, the effective heat dissipation area of ​​the heat sink fins, and the temperature difference. The temperature difference refers to the difference between the surface temperature of the heat sink fins and the ambient temperature. For example, if the adjusted convective heat transfer coefficient is 50 watts / (square meter·Kelvin), the effective heat dissipation area of ​​the heat sink fins is 0.2 square meters, the surface temperature of the heat sink fins is 75 degrees Celsius, and the ambient temperature is 25 degrees Celsius, then the temperature difference is 50 Kelvin. Multiplying these values ​​together yields an adjusted heat dissipation power of 500 watts, which is the predicted heat dissipation capacity.

[0087] Dead time refers to the delay time set during the switching process of the power switch to prevent a short circuit caused by the simultaneous conduction of the upper and lower bridge arm switches. The adjusted dead time is obtained by adding the dead time adjustment amount to the current dead time. For example, if the current dead time is 200 nanoseconds and the dead time adjustment amount is -20 nanoseconds, then the adjusted dead time is 180 nanoseconds.

[0088] Based on the adjusted dead time, calculate the actual on-time and actual off-time of the switching transistor within one pulse width modulation (PWM) cycle. The actual on-time equals the theoretical on-time minus half the dead time, and the actual off-time equals the theoretical off-time plus half the dead time. For example, with a PWM cycle of 10 microseconds and a duty cycle of 0.7, the theoretical on-time is 7 microseconds and the theoretical off-time is 3 microseconds. With an adjusted dead time of 180 nanoseconds, the actual on-time is approximately 6.91 microseconds, and the actual off-time is approximately 3.09 microseconds.

[0089] Conduction loss is equal to the product of the switching resistance, the square of the on-state current, and the actual conduction time. Assuming the switching resistance is 0.1 ohms, the on-state current is 10 amperes, the actual conduction time is 6.91 microseconds, and the pulse width modulation frequency is 100 kHz, then the adjusted conduction loss is 691 watts.

[0090] Switching losses are calculated based on the adjusted dead time. Switching losses occur during the transient processes of switching on and off the transistor, when both voltage and current exist simultaneously across the transistor. The duration of this transient process is related to the dead time and can be determined through experimental measurement or theoretical analysis. During the transient process, the voltage gradually decreases from a high level to a low level (the on-process) or gradually increases from a low level to a high level (the off-process), while the current does the opposite. By integrating the product of the instantaneous voltage and current values ​​over time during the transient process, the energy loss of one switching process can be obtained. Multiplying this value by the switching frequency yields the adjusted switching loss.

[0091] Add the adjusted conduction loss to the adjusted switching loss to obtain the adjusted total loss. For example, if the adjusted conduction loss is 691 watts and the adjusted switching loss is 104 watts, then the adjusted total loss is 795 watts.

[0092] Finally, the predicted output power is determined based on the difference between the input power of the power control circuit and the adjusted total loss. Assuming the input power of the power control circuit is 5000 watts and the adjusted total loss is 795 watts, the predicted output power is 4205 watts.

[0093] Through the above steps, the heat dissipation capacity and output power prediction based on the adjustment of cooling medium flow rate and dead time have been completed, providing a basis for subsequent selection of the optimal combination of adjustment values. In practical applications, the calculation methods of relevant parameters can be adjusted according to the specific characteristics of the heat dissipation system and power control circuit to obtain more accurate prediction results.

[0094] The present invention provides a high-power gallium nitride device thermal management and electrical co-optimization system, comprising: The first unit is used to determine the heat conduction time coefficients of each level of the heat dissipation system of gallium nitride devices from the heat source to the environment, extract the pulse width modulation period of the power control circuit, and establish the correlation mapping relationship between the heat conduction time coefficients of each level and the pulse width modulation period; The second unit is used to calculate the hot spot temperature gradient under different operating modes based on the correlation mapping relationship, determine the matching relationship between the heat dissipation fin spacing in the heat dissipation system and the switching time in the power control circuit based on the hot spot temperature gradient, and adjust the heat dissipation fin spacing and the switching time to make the time difference between the response time when the heat dissipation system reaches its peak heat dissipation capacity and the time when the power control circuit outputs the maximum power less than a preset synchronization threshold. The third unit is used to synchronously adjust the cooling medium flow rate of the heat dissipation system and the dead time of the power control circuit according to the matching relationship. When the output power of the power control circuit changes abruptly, the ratio of the rate of change of the heat dissipation capacity of the heat dissipation system to the rate of change of the output power is maintained within a preset coordinated range through the coordinated control between the adjustment amount of the cooling medium flow rate and the adjustment amount of the dead time. The fourth unit is used to generate the design parameters of the heat dissipation system and the control parameters of the power control circuit based on the adjusted heat dissipation fin spacing, switching transistor conduction time, cooling medium flow rate and dead time, and to control the heat dissipation intensity of the heat dissipation system and the switching action of the power control circuit.

[0095] A third aspect of the present invention provides an electronic device, comprising: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the aforementioned method.

[0096] A fourth aspect of the present invention provides a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0097] This invention can be a method, apparatus, system, and / or computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of the invention.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for co-optimizing thermal management and electrical performance of high-power gallium nitride devices, characterized in that, include: The heat conduction time coefficients of each level of the heat dissipation system of gallium nitride devices from the heat source to the environment are determined, and the pulse width modulation period of the power control circuit is extracted to establish the correlation mapping relationship between the heat conduction time coefficients of each level and the pulse width modulation period; Based on the aforementioned correlation mapping relationship, the hot spot temperature gradient under different operating modes is calculated. According to the hot spot temperature gradient, the matching relationship between the heat dissipation fin spacing in the heat dissipation system and the switching time in the power control circuit is determined. By adjusting the heat dissipation fin spacing and the switching time, the time difference between the response time when the heat dissipation system reaches its peak heat dissipation capacity and the time when the power control circuit outputs maximum power is less than a preset synchronization threshold. Based on the matching relationship, the cooling medium flow rate of the heat dissipation system and the dead time of the power control circuit are adjusted synchronously. When the output power of the power control circuit changes abruptly, the ratio of the rate of change of the heat dissipation capacity of the heat dissipation system to the rate of change of the output power is maintained within a preset coordinated range through the coordinated control between the adjustment amount of the cooling medium flow rate and the adjustment amount of the dead time. Based on the adjusted heat sink fin spacing, switching transistor conduction time, cooling medium flow rate, and dead time, the heat dissipation system design parameters and power control circuit control parameters are generated to control the heat dissipation intensity of the heat dissipation system and the switching action of the power control circuit.

2. The method according to claim 1, characterized in that, Determine the heat conduction time coefficients of each level of the gallium nitride device's heat dissipation system from the heat source to the environment, extract the pulse width modulation period of the power control circuit, and establish the correlation mapping relationship between the heat conduction time coefficients of each level and the pulse width modulation period, including: The gallium nitride device includes a chip packaging layer, a thermally conductive interface material layer, a metal substrate layer, a heat dissipation fin layer, and a convection heat transfer layer. The thermal resistance is calculated based on the ratio of the thickness to the thermal conductivity of each layer in the gallium nitride device. The heat capacity is calculated based on the product of the contact area, thickness, density, and specific heat capacity of each layer. The thermal resistance and heat capacity are multiplied to obtain the heat conduction time coefficient. The ratio of the heat conduction time coefficient to the pulse width modulation period is then determined. When the ratio is less than a preset fast response threshold, the level is classified as a fast response level, and a one-to-one mapping relationship is established between its heat conduction time coefficient and the on-time of the switching transistor within a single pulse width modulation cycle; when the ratio is between the preset fast response threshold and the preset slow response threshold, the level is classified as a medium-speed response level, and a mapping relationship is established between the heat conduction time coefficient of this level and the cumulative time of multiple consecutive pulse width modulation cycles. When the ratio is greater than the preset slow response threshold, the level is divided into a slow response level, and a mapping relationship is established between the heat conduction time constant and the duty cycle change envelope corresponding to multiple continuous pulse width modulation periods.

3. The method according to claim 1, characterized in that, Based on the aforementioned correlation mapping relationship, the hotspot temperature gradient under different operating modes is calculated. The matching relationship between the heat dissipation fin spacing in the heat dissipation system and the conduction time of the switching transistor in the power control circuit is determined according to the hotspot temperature gradient, including: Extract the heat transfer paths corresponding to the heat conduction time coefficients of each level of the heat dissipation system in the associated mapping relationship, and identify the bottleneck areas with the highest thermal resistance density in the heat transfer paths; calculate the instantaneous loss distribution of the switching transistors of the power control circuit under different operating modes, and determine the hot spot location coordinates corresponding to each operating mode based on the positional relationship between the instantaneous loss distribution and the bottleneck areas; For each hot spot location, calculate the temperature gradient value from that location to the surface of the heat sink fins. Then, correlate the temperature gradient value with the reciprocal of the heat sink fin spacing to establish an inverse proportional constraint relationship between the temperature gradient value and the heat sink fin spacing. Extract the switching loss curves of the switching transistor in the power control circuit at different conduction times, and identify the time period with the largest loss rise rate in the switching loss curve; The spacing of the heat dissipation fins corresponding to the maximum temperature gradient value in the inverse proportional constraint relationship is paired with the conduction time of the switch in the time period. By iteratively adjusting the spacing of the heat dissipation fins and the conduction time of the switch, the time difference between the moment when the heat dissipation system absorbs the peak heat flow and the moment when the power control circuit generates the peak loss is converged to within the preset synchronization threshold.

4. The method according to claim 3, characterized in that, Pairing the heat sink fin spacing corresponding to the maximum temperature gradient value in the inverse proportional constraint relationship with the switching transistor conduction time within the time period, and iteratively adjusting the heat sink fin spacing and the switching transistor conduction time to bring the time difference between the moment when the heat dissipation system absorbs peak heat flux and the moment when the power control circuit generates peak loss to within the preset synchronization threshold includes: Identify the initial value of the heat sink fin spacing corresponding to the maximum value of the temperature gradient from the inverse proportional constraint relationship; extract the initial value of the switch turn-on time corresponding to the maximum loss rise rate from the time period; and form an initial pairing parameter group by combining the initial value of the heat sink fin spacing and the initial value of the switch turn-on time. Calculate the thermal response delay time required for the heat dissipation system to reach peak heat dissipation capacity from receiving heat flow based on the initial value of the heat dissipation fin spacing; calculate the electrical response delay time required for the power control circuit to generate peak loss from the start of switching action based on the initial value of the switching transistor conduction time. Calculate the time difference between the time corresponding to the thermal response delay time and the time corresponding to the electrical response delay time, and determine whether the time difference is less than the preset synchronization threshold. When the time difference is greater than or equal to the preset synchronization threshold, the adjustment direction is determined according to the sign of the time difference. When the time difference is positive, the heat sink fin spacing is reduced and the switching transistor conduction time is increased. When the time difference is negative, the heat sink fin spacing is increased and the switching transistor conduction time is reduced. The spacing between the heat sink fins and the turn-on time of the switching transistor are synchronously adjusted according to the adjustment direction. After adjustment, the thermal response delay time and electrical response delay time are recalculated, and the time difference is updated. The above judgment and adjustment operation is repeated until the time difference converges to less than the preset synchronization threshold. The spacing between the heat sink fins and the turn-on time of the switching transistor at the time of convergence are used as the final pairing parameter group.

5. The method according to claim 1, characterized in that, Based on the matching relationship, the cooling medium flow rate of the heat dissipation system and the dead time of the power control circuit are adjusted synchronously. When the output power of the power control circuit changes abruptly, the ratio of the rate of change of the heat dissipation capacity of the heat dissipation system to the rate of change of the output power is maintained within a preset coordinated range through coordinated control between the adjustment amount of the cooling medium flow rate and the adjustment amount of the dead time. A candidate adjustment sequence for the cooling medium flow rate is set based on the flow rate adjustment range of the cooling medium conveying device, and a candidate adjustment sequence for the dead time is set based on the dead time adjustment range of the drive circuit. The two sequences are then combined to form a candidate adjustment combination set. The cooling medium flow rate adjustment is added to the current cooling medium flow rate, and the predicted heat dissipation capacity is calculated based on the adjusted flow rate. The dead time adjustment is added to the current dead time, and the switching loss and conduction loss are recalculated based on the adjusted dead time to determine the predicted output power. The ratio of the difference between the predicted heat dissipation capacity and the current heat dissipation capacity to the step duration is calculated as the predicted rate of change of heat dissipation capacity. A second ratio is then calculated between the predicted rate of change of heat dissipation capacity and the rate of change of output power. Candidate adjustment combinations that make the second ratio fall within the preset coordination interval are selected, and the combination that minimizes the absolute value of the deviation between the second ratio and the center value of the preset coordination interval is selected as the final adjustment scheme from the selection results.

6. The method according to claim 5, characterized in that, The method also includes determining the output power change rate and determining the current heat dissipation capacity: Determine the steady-state values ​​of output power before and after the step change, and calculate the difference between the two steady-state values ​​as the power step amplitude; measure the time elapsed from the moment of the step change until the output power reaches the steady-state value after the step change as the step duration; determine the output power change rate based on a first ratio of the power step amplitude to the step duration. Extract the benchmark value of heat dissipation capacity per unit area corresponding to the current heat dissipation fin spacing from the matching relationship, obtain the current cooling medium flow rate, and take the product of the current cooling medium flow rate, the benchmark value of heat dissipation capacity per unit area, and the effective heat dissipation area of ​​the heat dissipation fins as the current heat dissipation capacity.

7. The method according to claim 5, characterized in that, The cooling medium flow rate adjustment is added to the current cooling medium flow rate, and the predicted heat dissipation capacity is calculated based on the adjusted flow rate. The dead time adjustment is added to the current dead time, and the switching loss and conduction loss are recalculated based on the adjusted dead time to determine the predicted output power, including: Extract the cooling medium flow rate adjustment from the candidate adjustment combination, add the adjusted cooling medium flow rate to the current cooling medium flow rate to obtain the adjusted cooling medium flow rate; and calculate the adjusted convective heat transfer coefficient by substituting the adjusted cooling medium flow rate into the power function relationship between the cooling medium flow rate and the convective heat transfer coefficient. The adjusted convective heat transfer coefficient is multiplied by the effective heat dissipation area of ​​the heat dissipation fins and the temperature difference between the surface temperature of the heat dissipation fins and the ambient temperature to calculate the adjusted heat dissipation power, which is then used as the predicted value of the heat dissipation capacity. Extract the dead time adjustment from the candidate adjustment combination, add the dead time adjustment to the current dead time to obtain the adjusted dead time; calculate the actual on-time and actual off-time of the switch in one pulse width modulation cycle based on the adjusted dead time, and calculate the adjusted conduction loss by multiplying the actual on-time by the on-resistance and the square of the on-state current of the switch. Based on the adjusted dead time, calculate the time period during which voltage and current coexist during the switching process and turn-off of the switching transistor, and calculate the adjusted switching loss by integrating the instantaneous voltage and current values ​​over time during the time period; The adjusted conduction loss is added to the adjusted switching loss to obtain the adjusted total loss. The predicted output power value is determined based on the difference between the input power of the power control circuit and the adjusted total loss.

8. A high-power gallium nitride device thermal management and electrical co-optimization system, used to implement the method as described in any one of claims 1-7, characterized in that, include: The first unit is used to determine the heat conduction time coefficients of each level of the heat dissipation system of gallium nitride devices from the heat source to the environment, extract the pulse width modulation period of the power control circuit, and establish the correlation mapping relationship between the heat conduction time coefficients of each level and the pulse width modulation period; The second unit is used to calculate the hot spot temperature gradient under different operating modes based on the correlation mapping relationship, determine the matching relationship between the heat dissipation fin spacing in the heat dissipation system and the switching time in the power control circuit based on the hot spot temperature gradient, and adjust the heat dissipation fin spacing and the switching time to make the time difference between the response time when the heat dissipation system reaches its peak heat dissipation capacity and the time when the power control circuit outputs the maximum power less than a preset synchronization threshold. The third unit is used to synchronously adjust the cooling medium flow rate of the heat dissipation system and the dead time of the power control circuit according to the matching relationship. When the output power of the power control circuit changes abruptly, the ratio of the rate of change of the heat dissipation capacity of the heat dissipation system to the rate of change of the output power is maintained within a preset coordinated range through the coordinated control between the adjustment amount of the cooling medium flow rate and the adjustment amount of the dead time. The fourth unit is used to generate the design parameters of the heat dissipation system and the control parameters of the power control circuit based on the adjusted heat dissipation fin spacing, switching transistor conduction time, cooling medium flow rate and dead time, and to control the heat dissipation intensity of the heat dissipation system and the switching action of the power control circuit.

9. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 7.

Images