Semiconductor device and method of manufacturing the same
By forming gate dielectric layers and source/drain regions of non-uniform thickness in semiconductor devices, the problem of hot carrier injection effect is solved, improving device reliability and reducing the risk of circuit failure.
Patent Information
- Application Number
- CN202411739442.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2026-05-29
AI Technical Summary
With the development of integrated circuit process nodes, the device density of semiconductor devices per unit area has increased. The shrinkage of device size has led to an increase in the lateral electric field strength in the channel, and hot carrier injection is more likely to occur near the source and drain, affecting device performance and reliability.
A gate dielectric layer with uneven thickness is formed on a semiconductor substrate. The thickness of the edge region of the gate dielectric layer is greater than that of the center region, and source and drain regions are formed on both sides of the gate dielectric layer. The source and drain regions are formed by source and drain ion implantation process.
This reduces the electric field intensity at the edge of the gate dielectric layer, decreases the hot carrier injection effect, improves device reliability, and reduces the risk of circuit failure.
Smart Images
Figure CN122121247A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] With the continuous development of integrated circuit process nodes, the device density of semiconductor devices per unit area is constantly increasing, and the device size is also shrinking proportionally. However, as the device size continues to shrink, the lateral electric field strength in the channel of the semiconductor device also increases. The regions near the source and drain have high electric field strength. Therefore, under the influence of the lateral and longitudinal electric fields, hot carrier injection (HCI) is more likely to occur near the source and drain, affecting the performance and reliability of the device, and ultimately leading to device and circuit failure. Currently, the main method to solve the hot carrier injection effect is to improve the electric field distribution in the source and drain regions through ion implantation, thereby reducing the hot carrier injection effect. However, the adjustment capability of this method is limited. Summary of the Invention
[0003] The purpose of this invention is to provide a semiconductor device and its fabrication method to improve the hot carrier injection effect of the device.
[0004] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device, comprising:
[0005] Provide semiconductor substrates;
[0006] A gate dielectric layer and a gate are sequentially formed on the semiconductor substrate. The gate covers the gate dielectric layer. The gate dielectric layer includes a first edge region and a first center region. The thickness of the first edge region is greater than the thickness of the first center region. The first edge region is located on both sides of the first center region, and the semiconductor substrate is partially exposed on both sides of the gate dielectric layer.
[0007] A source / drain ion implantation process is performed to form source / drain regions in the semiconductor substrate on both sides of the gate dielectric layer.
[0008] Optionally, in the method for fabricating the semiconductor device, the method for forming the gate dielectric layer and the gate includes:
[0009] A gate dielectric material layer and a gate material layer are formed sequentially, the gate material layer covers the gate dielectric material layer, and the gate dielectric material layer covers the semiconductor substrate. The gate dielectric material layer includes a second edge region and a second center region. The thickness of the second edge region is greater than the thickness of the second center region, wherein the second edge region is located on both sides of the second center region.
[0010] A patterned photoresist layer is formed on the gate material layer, the patterned photoresist layer covering the gate material layer on the second central region and a portion of the gate material layer on the second edge region;
[0011] Using the patterned photoresist layer as a mask, the gate material layer is etched to form the gate, and the gate exposes a portion of the second edge region of the gate dielectric material layer;
[0012] Using the patterned photoresist layer as a mask, the exposed gate dielectric material layer is etched to form the gate dielectric layer;
[0013] Remove the patterned photoresist layer.
[0014] Optionally, in the method for fabricating the semiconductor device, the method for forming the gate dielectric material layer includes:
[0015] A virtual gate is formed on the semiconductor substrate, the virtual gate covering a portion of the semiconductor substrate;
[0016] A lightly doped ion implantation process is performed using the virtual gate as a mask to form lightly doped regions in the semiconductor substrate on both sides of the virtual gate;
[0017] Remove the dummy gate to expose the semiconductor substrate between the lightly doped regions;
[0018] The gate dielectric material layer is formed by a furnace tube process, the gate dielectric material layer covers the lightly doped region and the exposed semiconductor substrate, the thickness of the gate dielectric material layer on the lightly doped region is greater than the thickness of the gate dielectric material layer on the semiconductor substrate, wherein the gate dielectric material layer on the lightly doped region is the second edge region, and the gate dielectric material layer on the semiconductor substrate is the second center region.
[0019] Optionally, in the semiconductor device fabrication method, when forming the gate dielectric material layer using a furnace tube process, the deposition rate of the gate dielectric material layer on the lightly doped region is greater than the deposition rate of the gate dielectric layer on the semiconductor substrate.
[0020] Optionally, in the method for fabricating the semiconductor device, the material of the virtual gate includes photoresist.
[0021] Optionally, in the method for fabricating the semiconductor device, the width of the gate is greater than the width of the dummy gate.
[0022] Optionally, in the method for fabricating the semiconductor device, the method further includes:
[0023] Before forming the virtual gate, a sacrificial layer is formed on the semiconductor substrate, the sacrificial layer covering the semiconductor substrate, and the virtual gate is located on the sacrificial layer;
[0024] After removing the virtual gate, the sacrificial layer is removed.
[0025] Optionally, in the method for fabricating the semiconductor device, a well region is formed in the semiconductor substrate, the gate dielectric layer is located on the well region, and the source / drain regions are located in the well region on both sides of the gate dielectric layer.
[0026] Optionally, in the method for fabricating the semiconductor device, the method for performing the source / drain ion implantation process includes:
[0027] A sidewall layer is formed, which covers the sidewalls of the gate dielectric layer and the sidewalls of the gate.
[0028] Using the sidewall layer as a mask, the source / drain ion implantation process is performed to form the source / drain region.
[0029] Based on the same inventive concept, the present invention also provides a semiconductor device, comprising:
[0030] Semiconductor substrate;
[0031] A gate dielectric layer is formed on the semiconductor substrate. The gate dielectric layer includes a first edge region and a first center region. The thickness of the first edge region is greater than the thickness of the first center region. The first edge region is located on both sides of the first center region, and the semiconductor substrate is partially exposed on both sides of the gate dielectric layer.
[0032] Gate, covering the gate dielectric layer;
[0033] The source and drain regions are located in the semiconductor substrate on both sides of the gate dielectric layer.
[0034] In the semiconductor device and its fabrication method provided by this invention, the gate dielectric layer includes a first edge region and a first central region. The thickness of the first edge region is greater than the thickness of the first central region, and the first edge region is located on both sides of the first central region. Source and drain regions are formed in the semiconductor substrates on both sides of the gate dielectric layer. Because the thickness of the first edge region of the gate dielectric layer is greater than the thickness of the first central region, the electric field strength of the first edge region of the gate dielectric layer can be reduced, thereby reducing the longitudinal electric field strength near the source and drain regions and reducing the electron injection energy. This increases the difficulty for electrons to penetrate the first edge region of the gate dielectric layer and inject into the gate, thereby improving the hot carrier injection effect of the device, improving the reliability of the device, and reducing the risk of circuit failure in the device. Attached Figure Description
[0035] Figure 1 This is a schematic flowchart of the semiconductor device fabrication method provided in the embodiments of the present invention;
[0036] Figures 2 to 11 This is a schematic cross-sectional view of the structure formed in the method for fabricating the semiconductor device provided in the embodiments of the present invention;
[0037] The reference numerals in the attached figures are explained as follows:
[0038] 100 - Semiconductor substrate; 101 - Shallow trench isolation structure; 102 - Well region; 103 - Sacrificial layer; 104 - Virtual gate; 105 - Lightly doped region; 106 - Patterned photoresist layer;
[0039] 110 - Gate dielectric material layer; 110a - Second edge region; 110b - Second center region; 111 - Gate dielectric layer; 111a - First edge region; 111b - First center region;
[0040] 120 - Gate material layer; 121 - Gate;
[0041] 130 - Sidewall layer;
[0042] 140 - Source / Leakage Zone. Detailed Implementation
[0043] The semiconductor device and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0044] Figure 1 This is a schematic flowchart of the semiconductor device fabrication method provided in an embodiment of the present invention. Figure 1 As shown, the method for fabricating the semiconductor device provided in this embodiment includes:
[0045] Step S1: Provide a semiconductor substrate;
[0046] Step S2: A gate dielectric layer and a gate are sequentially formed on the semiconductor substrate. The gate covers the gate dielectric layer. The gate dielectric layer includes a first edge region and a first central region. The thickness of the first edge region is greater than the thickness of the first central region. The first edge region is located on both sides of the first central region, and the semiconductor substrate is partially exposed on both sides of the gate dielectric layer.
[0047] Step S3: Perform source / drain ion implantation to form source / drain regions in the semiconductor substrate on both sides of the gate dielectric layer.
[0048] Figures 2 to 11 This is a schematic cross-sectional view of the structure formed in the fabrication method of the semiconductor device provided in the embodiments of the present invention. The following will refer to the accompanying drawings. Figures 2 to 11 The method for fabricating the semiconductor device provided in this embodiment will be described in more detail.
[0049] refer to Figure 2 As shown, step S1 is performed to provide a semiconductor substrate 100. Specifically, the semiconductor substrate 100 may be made of any one of silicon, germanium, silicon-germanium, gallium arsenide, gallium nitride, and silicon carbide, or a composite substrate composed of two or more of these materials. In this embodiment, the semiconductor substrate 100 is made of silicon, and its conductivity type is P-type.
[0050] like Figure 2 As shown, a well region 102 is formed in the semiconductor substrate 100. The conductivity type of the well region 102 is the same as that of the semiconductor substrate 100. That is, if the conductivity type of the semiconductor substrate 100 is P-type, then the conductivity type of the well region 102 is P-type.
[0051] Furthermore, shallow trench isolation structures (STI) 101 are formed in the semiconductor substrate 100 on both sides of the well region 102.
[0052] Next, refer to Figure 10 In step S2, a gate dielectric layer 111 and a gate 121 are sequentially formed on the semiconductor substrate 100. The gate 121 covers the gate dielectric layer 111. The gate dielectric layer 111 includes a first edge region 111a and a first central region 111b. The thickness of the first edge region 111a is greater than the thickness of the first central region 111b. The first edge region 111a is located on both sides of the first central region 111b, and the semiconductor substrate 100 is partially exposed on both sides of the gate dielectric layer 111.
[0053] In this embodiment, the method for forming the gate dielectric layer 111 and the gate 121 includes the following steps one to four.
[0054] Step 1, refer to Figure 6 and Figure 7 As shown, a gate dielectric material layer 110 and a gate material layer 120 are formed sequentially. The gate material layer 120 covers the gate dielectric material layer 110, and the gate dielectric material layer 110 covers the semiconductor substrate 100. The gate dielectric material layer 110 includes a second edge region 110a and a second central region 110b. The thickness of the second edge region 110a is greater than the thickness of the second central region 110b.
[0055] Specifically, the method for forming the gate dielectric material layer 110 includes: firstly, as... Figure 3 As shown, a sacrificial layer 103 is formed on the semiconductor substrate 100, the sacrificial layer 103 covers the semiconductor substrate 100, the material of the sacrificial layer 103 includes silicon oxide, and it can be formed by thermal oxidation process. The sacrificial layer 103 is used to mitigate the direct impact of subsequent ion implantation on the semiconductor substrate 100.
[0056] Then, a dummy gate 104 is formed on the semiconductor substrate 100, the dummy gate 104 covering a portion of the semiconductor substrate 100. Further, the dummy gate 104 is located on the well region 102, and portions of the sacrificial layer 103 are exposed on both sides of the dummy gate 104. The dummy gate 104 is used to define the positions of the subsequently formed gate dielectric layer and gate, thereby controlling the starting position of the thicker region in the gate dielectric layer (i.e., the first edge region), and to block ions in subsequent lightly doped ion implantation processes. In other words, the dummy gate 104 can also be used as a barrier layer in subsequent lightly doped ion implantation processes.
[0057] Preferably, the width L1 of the virtual gate 104 is smaller than the width of the gate 121 subsequently formed, that is, the width of the virtual gate 104 is smaller than the width of the gate 121 subsequently formed at the same position.
[0058] Furthermore, the material of the virtual gate 104 includes photoresist. The formation process of the virtual gate 104 includes: firstly, spin-coating photoresist onto the semiconductor substrate 100 to form a photoresist layer, i.e., the photoresist layer covers the sacrificial layer 103; then, sequentially exposing and developing the photoresist layer to pattern the photoresist layer, and using the patterned photoresist layer to form the virtual gate 104.
[0059] Step two, as Figure 4 As shown, a lightly doped ion implantation (LDD) process is performed using the virtual gate 104 as a mask to form lightly doped regions 105 in the semiconductor substrate 100 on both sides of the virtual gate 104. Specifically, the lightly doped regions 105 extend laterally from the well region 102 into the semiconductor substrate 100 outside the well region 102, and the depth of the lightly doped regions 105 is less than the depth of the well region 102. Furthermore, since a sacrificial layer 103 is formed on the semiconductor substrate 100, the exposed sacrificial layer 103 is also doped with ions during the lightly doped ion implantation process.
[0060] In this embodiment, the conductivity type of the dopant ions in the lightly doped region 105 is the same as the conductor type of the dopant ions in the subsequently formed source / drain regions 140. Since the formed semiconductor device is an NMOS transistor, the dopant ions in the lightly doped region 105 include N-type dopant ions, specifically arsenic ions, phosphorus ions, and antimony ions, preferably arsenic ions. This allows for a further acceleration of the deposition rate of the gate dielectric material layer 110 on the lightly doped region 105 during the subsequent gate dielectric material layer 110 deposition step.
[0061] Furthermore, the concentration of doped ions in the lightly doped region 105 is lower than the concentration of doped ions in the subsequently formed source / drain regions 140. For example, the concentration of doped ions in the lightly doped region 105 can be 1E14 / cm³. 3 ~1E16 / cm 3 .
[0062] Furthermore, the lightly doped ion implantation process can be vertical ion implantation, tilted ion implantation, or a combination of both.
[0063] Step 3, as Figure 5 As shown, the dummy gate 104 is removed to expose the semiconductor substrate 100 between the lightly doped regions 105. Exemplarily, the dummy gate 104 is removed by a wet cleaning process using a solution comprising sulfuric acid and hydrogen peroxide.
[0064] Continue to refer to Figure 5 As shown, after removing the virtual gate 104, the sacrificial layer 103 is also removed. The sacrificial layer 103 can be removed using a wet cleaning process, wherein the solution used in the wet cleaning process includes hydrofluoric acid.
[0065] Step four, as Figure 6 As shown, the gate dielectric material layer 110 is formed using a furnace tube process. The gate dielectric material layer 110 covers the lightly doped region 105 and the exposed semiconductor substrate 100. The thickness of the gate dielectric material layer 110 on the lightly doped region 105 is greater than the thickness of the gate dielectric material layer 110 on the semiconductor substrate 100. This allows the thickness of the first edge region 111a of the subsequently formed gate dielectric layer 111 to be greater than the thickness of the first central region 111b, thereby reducing the electric field strength of the first edge region 111a of the subsequently formed gate dielectric layer 111.
[0066] Specifically, during the formation of the gate dielectric material layer 110, the silicon in the lightly doped region 105 and the silicon in the semiconductor substrate 100 react with the process gas in the furnace tube process to form the gate dielectric material layer 110. Because the lightly doped region 105 contains dopant ions, the reaction rate between the silicon in the lightly doped region 105 and the process gas in the furnace tube process is accelerated, thereby increasing the growth rate of the gate dielectric material layer 110. Therefore, during the formation of the gate dielectric material layer 110, the deposition rate of the gate dielectric material layer 110 on the lightly doped region 105 is greater than the deposition rate of the gate dielectric layer 111 on the semiconductor substrate 100 (i.e., the region without lightly doped ion implantation), resulting in a greater thickness of the gate dielectric material layer 110 on the lightly doped region 105 than on the semiconductor substrate 100. Wherein, as... Figure 6 As shown, the gate dielectric material layer 110 on the lightly doped region 105 is the second edge region 110a, and the gate dielectric material layer 110 on the semiconductor substrate 100 is the second central region 110b.
[0067] Furthermore, before forming the gate dielectric material layer 110, a light-doped ion implantation process is performed to form a light-doped drain region 105. This allows the deposition rate of the gate dielectric material layer 110 on the light-doped region 105 to be greater than the deposition rate of the gate dielectric layer 111 on the semiconductor substrate 100 during the deposition of the gate dielectric material layer 110, thereby forming a gate dielectric material layer 110 with a thick second edge region 110a and a thin second center region 110b. Compared to forming the gate dielectric material layer 110 with a thick second edge region 110a and a thin second center region 110b through a combination of multiple deposition processes and etching, this method is simpler and can simplify the process flow.
[0068] In this embodiment, the gate dielectric material layer 110 is made of silicon oxide, and the furnace tube process for forming the gate dielectric material layer 110 is a rapid thermal oxidation (RTO) process to improve the density of the gate dielectric material layer 110. The process gas in the rapid thermal oxidation process includes oxygen, and the process temperature is 800℃~1100℃, for example, 950℃ or 1000℃.
[0069] In another embodiment, the furnace tube process for forming the gate dielectric material layer 110 is an in-situ steam generation (ISSG) process. By introducing process gases of hydrogen and oxygen onto the semiconductor substrate 100, water vapor is synthesized in situ on the lightly doped region 105 and the exposed surface of the semiconductor substrate 100, and then combines with silicon in the lightly doped region 105 and the exposed semiconductor substrate 100 to form the gate dielectric material layer 110.
[0070] In this embodiment, the thickness of the second central region 110b of the gate dielectric material layer 110 is 30 angstroms to 50 angstroms, for example, 40 angstroms or 45 angstroms, and the thickness difference between the second edge region 110a and the second central region 110b of the gate dielectric material layer 110 is 10 angstroms to 15 angstroms. It should be noted that if the thickness difference between the second edge region 110a and the second central region 110b of the gate dielectric material layer 110 is too large, it will result in a large height difference on the surface of the gate dielectric material layer 110, which will lead to a large height difference on the surface of the subsequently formed gate 121, thus affecting the device performance. Therefore, in this embodiment, the thickness difference between the second edge region 110a and the second central region 110b of the gate dielectric material layer 110 is 10 angstroms to 15 angstroms. By ensuring that the thickness of the second edge region 110a is greater than the thickness of the second central region 110b, a large height difference on the surface of the subsequent gate 121 can be avoided.
[0071] like Figure 7 As shown, after forming the gate dielectric material layer 110, a gate material layer 120 is formed on the gate dielectric material layer 111, and the gate material layer 120 covers the gate dielectric material layer 110. The gate material layer 120 is made of polysilicon and is formed using a furnace tube process.
[0072] Next, refer to Figure 8 As shown, a patterned photoresist layer 106 is formed on the gate material layer 120, and the patterned photoresist layer 106 covers the gate material layer 120 on the second central region 110b and a portion of the gate material layer 120 on the second edge region 110a (i.e., the portion of the gate material layer 120 on the second edge region 110a that is closer to the second central region 110b).
[0073] Next, refer to Figure 9As shown, using the patterned photoresist layer 106 as a mask, the gate material layer 120 is etched to form the gate 121. That is, a portion of the gate material layer 120 on the second edge region 110a is removed, and the gate 121 exposes a portion of the second edge region 110a of the gate dielectric material layer 110. Specifically, the gate 121 covers the second central region 110b of the gate dielectric material layer 110 and the portion of the second edge region 110a of the gate dielectric material layer 110 that is close to the second central region 110b. The width L2 of the gate 121 is greater than the width L1 of the virtual gate 104. Thus, during subsequent etching of the gate dielectric material layer 110, the portion of the second edge region 110a of the gate dielectric material layer 110 that is close to the second central region 110b can be retained, and the actual width of the gate 121 can be increased.
[0074] The gate material layer 120 can be etched using a dry etching process, and the etching gases used in the dry etching process include, for example, carbon tetrafluoride (CF4) and sulfur hexafluoride (SF6).
[0075] Afterwards, refer to Figure 9 As shown, using the patterned photoresist layer 106 as a mask, the exposed gate dielectric material layer 110 is etched to form the gate dielectric layer 111. Specifically, the second central region 110b of the gate dielectric material layer 110 is retained to form the first central region 111b of the gate dielectric layer 111, and the portion of the second edge region 110a of the gate dielectric material layer 110 near the second central region 110b is retained to form the first central region 111b of the gate dielectric layer 111. This results in the thickness of the first edge region 111a of the gate dielectric layer 111 being greater than the thickness of the first central region 111b, thereby reducing the electric field strength of the first edge region 111a of the gate dielectric layer 111, and consequently reducing the longitudinal electric field strength near the subsequently formed source / drain regions 140. The gate dielectric material layer 110 can be etched using a dry etching process.
[0076] Furthermore, the first central region 111b of the gate dielectric layer 111 is thin, which allows charge carriers to pass through the first central region 111b of the gate dielectric layer 111 more easily, thereby reducing the accumulation of hot charge carriers in the gate dielectric layer 111.
[0077] refer to Figure 10 As shown, after the gate dielectric layer 111 is formed, the patterned photoresist layer 106 is removed. The patterned photoresist layer 106 can be removed, for example, by an ashing process.
[0078] refer to Figure 11As shown, step S3 is performed to execute a source / drain ion implantation process to form source / drain regions 140 in the semiconductor substrates 100 on both sides of the gate dielectric layer 111. The source / drain region 140 on one side of the gate dielectric layer 111 can serve as a source region, and the source / drain region 140 on the other side of the gate dielectric layer 111 can serve as a drain region. Since the thickness of the first edge region 111a of the gate dielectric layer 111 is greater than the thickness of the first central region 111b, the electric field strength of the first edge region 111a of the gate dielectric layer 111 can be reduced, thereby reducing the longitudinal electric field strength near the source / drain regions 140, particularly reducing the longitudinal electric field strength near the drain region. Furthermore, this reduces the electron injection energy, increasing the difficulty for electrons to penetrate the first edge region 111a of the gate dielectric layer 111 and inject into the gate 121. This improves the hot carrier injection effect of the device, enhances the device's reliability, and reduces the risk of circuit failure in the device.
[0079] Specifically, the method for performing the source / drain ion implantation process includes: first, forming a sidewall layer 130, which covers the sidewalls of the gate dielectric layer 111 and the gate 121, wherein the sidewall layer 130 is made of silicon oxide and / or silicon nitride, and the sidewall layer 130 can be formed using a chemical vapor deposition process; then, using the sidewall layer 130 as a mask, performing the source / drain ion implantation process to form the source / drain region 140.
[0080] like Figure 11 As shown, this embodiment also provides a semiconductor device fabricated using the semiconductor device fabrication method described above. The semiconductor device includes: a semiconductor substrate 100; a gate dielectric layer 111 formed on the semiconductor substrate 100, the gate dielectric layer 111 including a first edge region 111a and a first central region 111b, the thickness of the first edge region 111a being greater than the thickness of the first central region 111b, the first edge region 111a being located on both sides of the first central region 111b, and the sides of the gate dielectric layer 111 exposing portions of the semiconductor substrate 100; a gate 121 covering the gate dielectric layer 111; and source / drain regions 140 located in the semiconductor substrate 100 on both sides of the gate dielectric layer 111. This reduces the electric field strength of the first edge region 111a of the gate dielectric layer 111, thereby reducing the longitudinal electric field strength near the source / drain regions 140, and thus improving the hot carrier injection effect of the device.
[0081] like Figure 11 As shown, the semiconductor device further includes a sidewall layer 130, which covers the sidewalls of the gate dielectric layer 111 and the sidewalls of the gate 121.
[0082] In this embodiment, the semiconductor device may include an NMOS (N-Metal Oxide Semiconductor) device.
[0083] In summary, in the semiconductor device and its fabrication method provided in this embodiment of the invention, the gate dielectric layer includes a first edge region and a first central region. The thickness of the first edge region is greater than the thickness of the first central region. The first edge region is located on both sides of the first central region, and the source / drain regions are formed in the semiconductor substrates on both sides of the gate dielectric layer. Because the thickness of the first edge region of the gate dielectric layer is greater than the thickness of the first central region, the electric field strength of the first edge region of the gate dielectric layer can be reduced, thereby reducing the longitudinal electric field strength near the source / drain regions and lowering the electron injection energy. This increases the difficulty for electrons to penetrate the first edge region of the gate dielectric layer and inject into the gate, thereby improving the hot carrier injection effect of the device, increasing the reliability of the device, and reducing the risk of circuit failure in the device.
[0084] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
[0085] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: Provide semiconductor substrates; A gate dielectric layer and a gate are sequentially formed on the semiconductor substrate. The gate covers the gate dielectric layer. The gate dielectric layer includes a first edge region and a first center region. The thickness of the first edge region is greater than the thickness of the first center region. The first edge region is located on both sides of the first center region, and the semiconductor substrate is partially exposed on both sides of the gate dielectric layer. A source / drain ion implantation process is performed to form source / drain regions in the semiconductor substrate on both sides of the gate dielectric layer.
2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The method of forming the gate dielectric layer and the gate includes: A gate dielectric material layer and a gate material layer are sequentially formed, wherein the gate material layer covers the gate dielectric material layer and the gate dielectric material layer covers the semiconductor substrate, and the gate dielectric material layer includes a second edge region and a second center region, wherein the thickness of the second edge region is greater than the thickness of the second center region, and wherein the second edge region is located on both sides of the second center region; A patterned photoresist layer is formed on the gate material layer, the patterned photoresist layer covering the gate material layer on the second central region and a portion of the gate material layer on the second edge region; Using the patterned photoresist layer as a mask, the gate material layer is etched to form the gate, and the gate exposes a portion of the second edge region of the gate dielectric material layer; Using the patterned photoresist layer as a mask, the exposed gate dielectric material layer is etched to form the gate dielectric layer; Remove the patterned photoresist layer.
3. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The method for forming the gate dielectric material layer includes: A virtual gate is formed on the semiconductor substrate, the virtual gate covering a portion of the semiconductor substrate; A lightly doped ion implantation process is performed using the virtual gate as a mask to form lightly doped regions in the semiconductor substrate on both sides of the virtual gate; Remove the dummy gate to expose the semiconductor substrate between the lightly doped regions; The gate dielectric material layer is formed by a furnace tube process, the gate dielectric material layer covers the lightly doped region and the exposed semiconductor substrate, the thickness of the gate dielectric material layer on the lightly doped region is greater than the thickness of the gate dielectric material layer on the semiconductor substrate, wherein the gate dielectric material layer on the lightly doped region is the second edge region, and the gate dielectric material layer on the semiconductor substrate is the second center region.
4. The method for fabricating a semiconductor device as described in claim 3, characterized in that, When the gate dielectric material layer is formed by furnace tube process, the deposition rate of the gate dielectric material layer on the lightly doped region is greater than the deposition rate of the gate dielectric layer on the semiconductor substrate.
5. The method for fabricating a semiconductor device as described in claim 3, characterized in that, The material of the virtual gate includes photoresist.
6. The method for fabricating a semiconductor device as described in claim 3, characterized in that, The width of the gate is greater than the width of the virtual gate.
7. The method for fabricating a semiconductor device as described in claim 3, characterized in that, The method for fabricating the semiconductor device further includes: Before forming the virtual gate, a sacrificial layer is formed on the semiconductor substrate, the sacrificial layer covering the semiconductor substrate, and the virtual gate is located on the sacrificial layer; After removing the virtual gate, the sacrificial layer is removed.
8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, A well region is formed in the semiconductor substrate, the gate dielectric layer is located on the well region, and the source / drain regions are located in the well region on both sides of the gate dielectric layer.
9. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The method for performing the source / drain ion implantation process includes: A sidewall layer is formed, which covers the sidewalls of the gate dielectric layer and the sidewalls of the gate. Using the sidewall layer as a mask, the source / drain ion implantation process is performed to form the source / drain region.
10. A semiconductor device, characterized in that, include: Semiconductor substrate; A gate dielectric layer is formed on the semiconductor substrate. The gate dielectric layer includes a first edge region and a first center region. The thickness of the first edge region is greater than the thickness of the first center region. The first edge region is located on both sides of the first center region, and the semiconductor substrate is partially exposed on both sides of the gate dielectric layer. Gate, covering the gate dielectric layer; The source and drain regions are located in the semiconductor substrate on both sides of the gate dielectric layer.