Asymmetric multi-step switch push non-destructive peeling method for flexible ultra-thin chip

Abstract

The application provides an asymmetric multi-step switching push non-destructive peeling method for a flexible ultrathin chip, and relates to the technical field of flexible electronics. The method comprises the following steps: obtaining the length of a substrate and the length of a chip, and determining the switching step number of a push pin; determining the relationship between a peeling health index and a crack propagation length according to the elastic modulus of the chip and the thickness of the chip, and determining the switching position corresponding to each switching step number of the push pin; determining the displacement of the push pin according to the switching position; controlling the push pin to push the chip according to the displacement of the push pin until the peeling of the chip is completed after the push is performed at all the switching positions. According to the application, the push position can be selected in a systematic and quantitative manner, the performance is close to the theoretical optimum, the operation steps are clear, the requirements for the equipment are reasonable, the integration and automation can be realized on the existing wafer-level packaging equipment, the stress state of the chip in the peeling process can be effectively managed, and the non-destructive and high-yield peeling of the ultrathin chip can be realized.

Description

Technical Field

[0001] This invention relates to the field of flexible electronics technology, and in particular to an asymmetric multi-step switching push-and-release method for non-destructive peeling of flexible ultrathin chips. Background Technology

[0002] Currently, the industry and academia generally use a combination of "pin pushing and vacuum suction" for chip peeling. This involves applying a pushing force from below the substrate using pins, causing localized deformation and detachment of the adhesive layer, while a vacuum nozzle simultaneously picks up the chip from above, completing the final transfer. However, existing peeling processes, especially the pin pushing strategy, have significant limitations: 1. Defects of the symmetrical fixed loading mode: Related technologies often use symmetrically arranged pins (e.g., symmetrically arranged on both sides of the chip) and keep the pin positions fixed throughout the peeling process. While this symmetrical fixed loading mode can effectively induce detachment initially, the stress state of the chip deteriorates rapidly as interface cracks propagate. Specifically, the energy release rate required for peeling increases slowly, while the stress inside the chip rapidly concentrates, easily leading to chip breakage in the latter half of the peeling process. This is essentially because the fixed-position pins cannot adapt to the dynamic changes in the optimal stress point during crack propagation. 2. Reliance on experience and trial and error: In actual operation, the determination of process parameters (such as pin position, pushing force / displacement) heavily relies on the operator's experience, requiring repeated trials to determine. This method is inefficient, costly, and struggles to guarantee process consistency and repeatability, failing to meet the demands of large-scale, high-throughput manufacturing. 3. Lack of dynamic optimization strategies: Although some research (such as multi-stage, multi-suction cup picking methods) has recognized the necessity of dynamically adjusting the loading point, a systematic and quantitative theoretical framework and process scheme for dynamically switching the ejector pin position based on real-time crack propagation has not yet been established in the crucial ejector pin pushing stage. Related technologies have failed to reveal the intrinsic relationship between the optimal ejector pin position and crack propagation length, nor have they proposed a quantifiable and executable dynamic switching strategy.

[0003] The information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] This invention provides an asymmetric multi-step switching push-off non-destructive peeling method for flexible ultrathin chips, which can solve the technical problem that existing technologies cannot reveal the intrinsic relationship between the optimal position of the push pin and the crack propagation length, nor can they propose a set of quantifiable and executable dynamic switching strategies.

[0005] According to a first aspect of the present invention, an asymmetric multi-step switching push-and-release method for non-destructive peeling of a flexible ultrathin chip is provided, comprising: Obtain the substrate length and chip length, and determine the number of pin switching steps; Based on the chip's elastic modulus and thickness, the relationship between the peel health index and crack propagation length was determined. Based on the number of pin switching steps and the relationship between the peel health index and the crack propagation length, determine the switching position corresponding to each number of pin switching steps; The displacement of the ejector pin is determined based on the switching position; The chip is pushed by the ejector pin according to the ejector pin displacement control until the chip is completely removed after pushing at all switching positions.

[0006] According to the present invention, obtaining the substrate length and chip length, and determining the number of pin switching steps, includes: Based on the length ratio between the substrate length and the chip length; Determine the preset range to which the length ratio belongs; The number of pin switching steps is determined based on the preset range to which the length ratio belongs.

[0007] According to the present invention, determining the relationship between the peel health index and the crack propagation length based on the elastic modulus and thickness of the chip includes: The energy release rate at the crack tip of the adhesive layer is determined based on the crack propagation length. Based on the chip's elastic modulus and thickness, as well as the energy release rate at the crack tip of the adhesive layer, a peel health index related to the crack propagation length is determined, thereby obtaining the relationship between the peel health index and the crack propagation length.

[0008] According to the present invention, a peel health index related to crack propagation length is determined based on the chip's elastic modulus and thickness, as well as the maximum tensile stress on the chip surface and the energy release rate at the tip of the adhesive layer crack, including: According to the formula Determine the peel health index related to crack propagation length ,in, The elastic modulus of the chip. For the thickness of the chip, The energy release rate at the tip of the adhesive layer crack. This represents the maximum tensile stress on the chip surface.

[0009] According to the present invention, the switching position corresponding to each pin switching step is determined based on the number of pin switching steps and the relationship between the peel health index and the crack propagation length, including: A relationship curve was obtained based on the relationship between the peeling health index and the crack propagation length; The intersection of two adjacent switching steps in the relationship curve is identified as a key node, and the number of nodes is consistent with the number of pin switching steps; The crack propagation length corresponding to each node is determined as the switching position where the ejector pin should act under that switching step.

[0010] According to the present invention, determining the ejector pin displacement based on the switching position includes: Obtain multiple integral constants in the process of solving the energy release rate at the crack tip of the adhesive layer; The displacement of the ejector pin is determined based on the integral constant and the switching position.

[0011] According to the present invention, determining the ejector pin displacement based on the integral constant and the switching position includes: According to the formula Determine the pin displacement corresponding to the j-th switching position, where, Let x be the x-coordinate of the position j of the action area of ​​the ejector pin. , , and All of these are the integral constants.

[0012] According to the present invention, the method for obtaining the integration constant includes: Construct a plane strain mechanical model of a three-layer structure consisting of a chip, adhesive layer, and substrate; The chip surface is divided into multiple regions; Based on the plane strain mechanics model of the chip-adhesive-substrate three-layer structure, the differential equations of the chip and substrate in each region are obtained; Obtain multiple boundary conditions and interface continuity conditions, and substitute them into the general solution of the differential equation to obtain a system of linear equations containing the integral constant. The integral constant is obtained by solving the system of linear equations using numerical methods.

[0013] According to a second aspect of the present invention, an asymmetric multi-step switching push-and-release system for flexible ultrathin chips is provided, comprising: The switching step module is used to obtain the substrate length and chip length, and determine the number of pin switching steps; The peel health index module is used to determine the relationship between the peel health index and the crack propagation length based on the chip's elastic modulus and chip thickness. The switching position module is used to determine the switching position corresponding to each switching step of the ejector pin based on the number of switching steps of the ejector pin and the relationship between the peeling health index and the crack propagation length. The ejector pin displacement module is used to determine the ejector pin displacement based on the switching position; The stripping module is used to control the pusher pins to push the chip according to the displacement of the pusher pins, until the chip is stripped after pushing at all switching positions.

[0014] According to a third aspect of the present invention, an asymmetric multi-step switching push-top non-destructive peeling device for a flexible ultrathin chip is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to execute the asymmetric multi-step switching push-top non-destructive peeling method for the flexible ultrathin chip.

[0015] According to a fourth aspect of the present invention, a computer-readable storage medium is provided having computer program instructions stored thereon, which, when executed by a processor, implement an asymmetric multi-step switching push-and-release method for non-destructive peeling of the flexible ultrathin chip.

[0016] By adopting the above technical solution, the present invention can achieve the following technical effects: According to this invention, based on a rigorous mechanical model and health index assessment, clear and quantitative design criteria are provided for the setting and switching of ejector pin positions. The intrinsic relationship between ejector pin position and crack propagation length is determined, allowing for systematic and quantitative selection of the ejector pin position. Performance approaches theoretical optimality, while the operation steps are clear, equipment requirements are reasonable, and integration and automation on existing wafer-level packaging equipment are easily achieved. It effectively manages the stress state of the chip during the peeling process, enabling non-destructive, high-yield peeling of ultra-thin chips. It avoids the problem of a sharp decline in the health index in the later stages of traditional symmetrical ejection, keeping the chip in a low-risk state throughout the peeling process, thus significantly reducing the probability of chip breakage. Furthermore, it is flexibly applicable to chip-substrate structures of different materials and geometries, exhibiting good universality. When determining the number of ejector pin switching steps, the range of the length ratio between the substrate length and the chip length can be used to determine the number of switching steps, ensuring that the chip's peeling health index remains within a healthy range each time the ejector pin position is switched, enhancing chip protection and improving the peeling success rate. When determining the switching position, the peeling health index at each stage can be maintained at a high level, reducing the probability of chip damage during each stage's push-up process and improving the peeling success rate. When determining the ejector pin displacement, reasonable push-up can be performed at each switching position, and the propagation of adhesive layer cracks can be properly controlled during the push-up process, maintaining the peeling health index at a high level and reducing the probability of chip damage during the push-up process, thereby improving the peeling success rate.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Other features and aspects of the invention will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort. Figure 1 An exemplary flowchart of an asymmetric multi-step switching push-and-release method for a flexible ultrathin chip according to an embodiment of the present invention is shown. Figure 2 A schematic diagram of an experimental system based on a wafer disk moving platform according to an embodiment of the present invention is shown as an example; Figure 3 An exemplary schematic diagram illustrates the application of the asymmetric multi-step switching push-and-release method for flexible ultrathin chips according to an embodiment of the present invention; Figure 4 and Figure 5 An exemplary schematic diagram comparing experimental results of various stripping strategies according to embodiments of the present invention is shown; Figure 6 A block diagram of an asymmetric multi-step switching push-and-release system for flexible ultrathin chips according to an embodiment of the present invention is shown as an example. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0021] Figure 1 An exemplary flowchart illustrates an asymmetric multi-step switching push-and-release method for a flexible ultrathin chip according to an embodiment of the present invention, the method comprising: Step S1: Obtain the substrate length and chip length, and determine the number of pin switching steps; Step S2: Determine the relationship between the peel health index and the crack propagation length based on the chip's elastic modulus and thickness. Step S3: Determine the switching position corresponding to each pin switching step based on the number of pin switching steps and the relationship between the peeling health index and the crack propagation length. Step S4: Determine the displacement of the ejector pin based on the switching position; Step S5: Control the ejector pin to push the chip according to the ejector pin displacement until the chip is pushed in all switching positions, and then the chip is peeled off.

[0022] The asymmetric multi-step switching push-to-remove method for flexible ultrathin chips according to embodiments of the present invention provides clear and quantitative design criteria for the setting and switching of push pin positions based on rigorous mechanical models and health index assessments. It determines the intrinsic relationship between push pin positions and crack propagation length, enabling systematic and quantitative selection of push positions. The performance is close to theoretical optimality, with clear operation steps, reasonable equipment requirements, and easy integration and automation on existing wafer-level packaging equipment. It effectively manages the stress state of the chip during the peeling process, achieving non-destructive, high-yield peeling of ultrathin chips. It avoids the problem of a sharp decline in health index in the later stages of traditional symmetrical push-to-remove methods, keeping the chip in a low-risk state throughout the peeling process, thus significantly reducing the probability of chip breakage. Furthermore, it is flexibly applicable to chip-substrate structures of different materials and geometries, exhibiting good universality.

[0023] Example 1: Figure 2 A schematic diagram of an experimental system based on a wafer disk moving platform according to an embodiment of the present invention is shown as an example.

[0024] According to one embodiment of the present invention, the wafer disk moving platform is a high-precision moving platform located in the xoy plane, controlled by a screw, used to support a substrate (UV film) with a chip attached, and can precisely move a specific chip to directly above the ejector pin according to a preset program. The experimental system also includes an ejector pin clamping and displacement control mechanism: this mechanism restricts the ejector pin to move only in the vertical direction (z-axis), and uses a high-precision displacement controller to perform closed-loop control of the ejector pin's lifting displacement, ensuring a stable and repeatable pushing process. The chip used in the experiment is a 20μm thick single-crystal silicon wafer, cut into square chips with dimensions of 8.0mm × 8.0mm. The substrate uses a 100μm thick polyolefin UV film as a temporary support substrate, with an elastic modulus of approximately 160MPa and a Poisson's ratio of 0.45. The UV film has a built-in pressure-sensitive adhesive layer. Through preliminary calibration experiments, the critical energy release rate (i.e., peel strength) of this adhesive layer was measured to be approximately 3.2N / m.

[0025] Example 2: According to one embodiment of the present invention, a plane strain mechanics model of a three-layer structure consisting of a chip, an adhesive layer, and a substrate can be constructed. The entire structure is divided into multiple regions based on the ejector pin position and the crack length in the adhesive layer. For each region, the chip and substrate layers are treated as Timoshenko beams, while the adhesive layer, which is much thinner than the chip and substrate, is simplified as a continuously distributed linear spring to simulate its normal and tangential bonding stiffness. Using this model, the stress field at the adhesive layer interface, the energy release rate, and the stress distribution within the chip can be accurately calculated at any ejector pin position and crack length.

[0026] Example 3: According to one embodiment of the present invention, using the above model as a theoretical model, the health of the peeling process can be evaluated based on the state of adhesive layer crack propagation during the peeling process. As the adhesive layer cracks propagate, the normal stress and shear stress at the crack tip change, leading to a change in the energy release rate at the crack tip, and consequently, a change in the health of the peeling process. The health of the peeling process can be assessed using a peeling health index. It is stated that the health index is stripped away. To promote the ratio of energy release rate during stripping to the critical stress that causes chip breakage, its mathematical expression is as follows (1): in, The elastic modulus of the chip. For the thickness of the chip, The energy release rate at the tip of the adhesive layer crack. This represents the maximum tensile stress on the chip surface. A higher value indicates that the adhesive layer is more easily debonded under the current conditions while avoiding chip breakage; in other words, the peeling process is "healthier." The energy release rate at the crack tip is related to the normal stress and shear stress at the crack tip, that is, it is related to the crack propagation length. In experiments, the relationship between the crack propagation length and the normal stress and shear stress at the crack tip can be measured. Therefore, by simply measuring the crack propagation length, the energy release rate at the crack tip can be obtained, and the peeling health index can be calculated. That is, by measuring the current length of the adhesive layer crack during the peeling process, the current peeling health index can be determined.

[0027] Example 4: According to one embodiment of the present invention, the propagation length of the adhesive layer crack and the peeling health index measured during the peeling process can be used to set a peeling scheme, improve the peeling success rate, and reduce the probability of chip damage.

[0028] According to one embodiment of the present invention, in step S1, the substrate length and the chip length can be measured, and then the number of pin switching steps can be determined based on the ratio between the substrate length and the chip length.

[0029] According to one embodiment of the present invention, obtaining the substrate length and the chip length, and determining the number of pin switching steps, includes: determining a preset range to which the length ratio belongs based on the length ratio between the substrate length and the chip length; and determining the number of pin switching steps based on the preset range to which the length ratio belongs.

[0030] According to one embodiment of the present invention, multiple preset ranges can be set, for example, four intervals [1.1, 1.21), [1.21, 1.35), [1.35, 1.85), and [1.85, 2) can be used as the preset ranges. The above four preset ranges correspond to 3 steps, 2 steps, 1 step, and 0 steps of pin switching, respectively. After measuring the substrate length and the chip length and calculating the length ratio, it can be determined which preset range the length ratio falls into, so that the pin switching steps corresponding to the preset range can be determined as the pin switching steps used when peeling off the chip.

[0031] In this way, the number of pin switching steps can be determined based on the range of the length ratio between the substrate length and the chip length, so that the chip peeling health index is in a healthy range each time the pin position is switched, thereby improving the protection of the chip and increasing the peeling success rate.

[0032] Example 5: According to one embodiment of the present invention, in step S2, the relationship between the peeling health index and the crack propagation length can be determined based on the above peeling health index.

[0033] According to one embodiment of the present invention, determining the relationship between the peel health index and the crack propagation length based on the elastic modulus and thickness of the chip includes: determining the energy release rate at the crack tip of the adhesive layer based on the crack propagation length; determining the peel health index related to the crack propagation length based on the elastic modulus and thickness of the chip and the energy release rate at the crack tip of the adhesive layer, thereby obtaining the relationship between the peel health index and the crack propagation length.

[0034] According to an embodiment of the present invention, as described above, the stress field, energy release rate, and stress distribution inside the chip can be determined at any pin position and crack length using a plane strain mechanics model of a chip-adhesive-substrate three-layer structure. For example, the energy release rate for various crack lengths can be experimentally obtained, and the peel health index can be determined based on this energy release rate and the above formula (1). Thus, the peel health index corresponding to various crack lengths can be determined as the relationship between the peel health index and the crack propagation length.

[0035] Example 6: According to one embodiment of the present invention, in step S3, the pin switching position corresponding to each step is determined based on the number of pin switching steps and the relationship between the peel health index and the crack propagation length. Specifically, this includes: obtaining a relationship curve based on the relationship between the peel health index and the crack propagation length; identifying the intersection of two adjacent switching steps in the curve as key nodes, the number of which is consistent with the number of pin switching steps; and determining the crack propagation length corresponding to each node as the position coordinate of the pin that should act under that switching step. The position coordinate is defined along the chip length direction (x-axis direction). In actual operation, the chip is aligned with this coordinate position by moving the wafer disk platform to achieve the push at that location.

[0036] In this way, during each stripping stage, the ejector pins are positioned to maintain a high level of stripping health index, thereby effectively controlling stress concentration inside the chip, reducing the risk of chip breakage during the push-up process, and improving the overall yield and reliability of the stripping process.

[0037] Example 7: According to an embodiment of the present invention, in step S4, after determining the switching position, the displacement of the ejector pin at each switching position can be determined, that is, the displacement of the ejector pin along the z-axis direction, in other words, the height by which the ejector pin lifts the substrate and the chip is determined.

[0038] According to one embodiment of the present invention, determining the ejector pin displacement based on the switching position includes: obtaining multiple integral constants in the process of solving the energy release rate at the tip of the adhesive layer crack; and determining the ejector pin displacement based on the integral constants and the switching position.

[0039] According to one embodiment of the present invention, in the process of determining the energy release rate at the tip of the adhesive layer crack, the relationship between the crack propagation length and the energy release rate can be determined by means of numerical simulation and other methods. In the process of numerical simulation, multiple integral constants can be obtained, and the displacement of the ejector pin at different switching positions can be determined by using these integral constants.

[0040] According to one embodiment of the present invention, determining the ejector pin displacement based on the integral constant and the switching position includes: determining the ejector pin displacement corresponding to the j-th switching position according to formula (2). (2) in, Let x be the x-coordinate of the position j of the action area of ​​the ejector pin. , , and All of these are the integral constants.

[0041] According to an embodiment of the present invention, the integral constant , , and In the mechanical model for solving the energy release rate at the crack tip of the adhesive layer, the integral constant is a constant coefficient determined by solving a system of equations simultaneously using boundary conditions and continuity conditions. The method for obtaining the integral constant includes: constructing a plane strain mechanical model of a three-layer structure (chip-adhesive layer-substrate); dividing the chip surface into multiple regions; obtaining the differential equations for the chip and substrate in each region based on the plane strain mechanical model of the three-layer structure; obtaining multiple boundary conditions and interface continuity conditions, and substituting them into the general solution of the differential equations to obtain a system of linear equations containing the integral constant; and solving the system of linear equations numerically to obtain the solution value of the integral constant.

[0042] According to an embodiment of the present invention, the specific calculation process of the integration constant is as follows: After establishing a plane strain mechanical model of the three-layer structure (chip-adhesive layer-substrate), the system is divided into multiple regions, and differential equations for the chip and substrate are listed for each region. The following boundary conditions and interface continuity conditions are then applied: 1. Displacement and rotation at the point of action of the ejector pin; 2. Interfacial stress continuity between the intact adhesive layer area and the peeled area; 3. Stress and displacement boundary conditions at the crack tip; 4. Mechanical constraints on the free and fixed ends of the chip.

[0043] Substituting the above conditions into the general solution of the differential equation yields a system of linear equations containing the integration constant. Solving this system of equations using numerical methods (such as matrix solving) will give the answer to the equation corresponding to the first... The integral constant of the area of ​​action of each pin , , and These constants are related to the geometry of the chip and substrate, material properties (such as elastic modulus and adhesive layer stiffness), and the current crack length, and need to be recalculated each time the ejector pin position changes. For the first The x-coordinate of the position of the pin within the area of ​​action of each pin.

[0044] Since the integral constants change dynamically with specific material parameters, geometric configurations and peeling stages, their values ​​are not listed here one by one. However, those skilled in the art can determine their specific values ​​through numerical calculations based on the above mechanical model and boundary conditions.

[0045] In this way, reasonable pushing can be performed at each switching position, and the expansion of adhesive layer cracks can be reasonably controlled during the pushing process, so as to keep the peeling health index at a high level and reduce the probability of chip damage during the pushing process, thereby improving the peeling success rate.

[0046] Example 8: According to an embodiment of the present invention, in step S5, the chip can be pushed according to the switching position and pin displacement determined above. That is, at the first switching position, the chip is pushed according to the pin displacement calculated by the formula (2) above. After the displacement of the pin along the z-axis reaches the above pin displacement, the pin is retracted and the moving wafer disk moving platform is controlled so that the second switching position of the chip is above the pin. Then, the chip is pushed again by the pin displacement calculated above. After the displacement of the pin along the z-axis reaches the above pin displacement, the pin is retracted and the moving wafer disk moving platform is controlled again so that the third switching position of the chip is above the pin... and so on, until the chip is pushed at all switching positions, and the chip can be peeled off.

[0047] The asymmetric multi-step switching push-to-remove method for flexible ultrathin chips according to embodiments of the present invention provides clear and quantitative design criteria for the setting and switching of push-pin positions based on rigorous mechanical models and health index assessments. It determines the intrinsic relationship between push-pin positions and crack propagation length, allowing for systematic and quantitative selection of push-pin positions. The performance is close to theoretical optimality, with clear operation steps, reasonable equipment requirements, and easy integration and automation on existing wafer-level packaging equipment. It effectively manages the stress state of the chip during the peeling process, achieving non-destructive, high-yield peeling of ultrathin chips. It avoids the problem of a sharp decline in the health index in the later stages of traditional symmetrical push-out peeling, keeping the chip in a low-risk state throughout the peeling process, thus significantly reducing the probability of chip breakage. It is also flexibly applicable to chip-substrate structures of different materials and geometries, exhibiting good universality. When determining the number of push-pin switching steps, the range of the length ratio between the substrate length and the chip length can be used to determine the number of push-pin switching steps, ensuring that the chip's peeling health index remains within a healthy range each time the push-pin position is switched, improving chip protection and increasing the peeling success rate. When determining the switching position, the peeling health index at each stage can be maintained at a high level, reducing the probability of chip damage during each stage's push-up process and improving the peeling success rate. When determining the ejector pin displacement, reasonable push-up can be performed at each switching position, and the propagation of adhesive layer cracks can be properly controlled during the push-up process, maintaining the peeling health index at a high level and reducing the probability of chip damage during the push-up process, thereby improving the peeling success rate.

[0048] Example 9: Figure 3An exemplary schematic diagram illustrates the application of the asymmetric multi-step switching push-and-release method for flexible ultrathin chips according to an embodiment of the present invention.

[0049] According to one embodiment of the present invention, the geometric parameters of the chip and the substrate, namely the substrate length ls and the chip length lc, can be determined first. Then, the number of pin switching steps can be determined according to the ratio of the substrate length and the chip length. Then, the switching position corresponding to each number of pin switching steps can be selected by comparing the peeling health index at each position, and the pin displacement at each switching position can be calculated according to formula (2). By controlling the wafer disk moving platform, the switching position is moved above the pin, and the distance the pin moves along the z-axis is equal to the pin displacement. After all switching positions have been pushed, the chip can be peeled off.

[0050] Example 10: Strategy I: Side-switching push strategy. When the crack extends to near the center of the chip, the ejector pin is switched from the initial side to the other side of the chip for ejection. This strategy improves the peeling process in the latter half by changing the force symmetry.

[0051] Strategy II: Optimal Ejector Position Switching Strategy. Theoretically, this is the optimal strategy, where the ejector position is tracked in real-time to find the optimal location as the crack propagates. This strategy consistently maintains the health index at its highest level, but it requires extremely high precision in dynamic equipment control and is difficult to operate.

[0052] Strategy III: Multi-step switching push-top strategy, i.e., the steps described in this invention. As an engineering simplification of Strategy II, the entire peeling process is divided into multiple steps based on the location of crack propagation. The action position of the push pin is adjusted step by step to promote the debonding of the adhesive layer while reducing the stress level on the chip surface, thus achieving a balance between chip peeling success rate and operational difficulty.

[0053] Figure 4 and Figure 5 An exemplary schematic diagram comparing experimental results of various stripping strategies according to embodiments of the present invention is shown.

[0054] For each strategy step to be tested, 10 brand-new chips are randomly selected as a sample. The ejection begins with a small initial displacement, and then the ejector displacement is gradually increased in increments of 0.1 mm until chip breakage or complete successful removal is observed. The maximum ejector displacement corresponding to the successful removal of all 10 chips in that step is recorded; this is the critical displacement for that step. If any chip breaks, the ejection displacement is considered the critical value. The critical displacements for different steps of each strategy are as follows: Figure 3 As shown, Strategy I consists of two steps: pushing from the initial side and pushing from the other side. Strategy III consists of three steps: pushing using three different switching positions. Figure 3 The critical displacements of each strategy determined in the process were used for final performance evaluation. Twenty new chips were then stripped, and their final yields were calculated. The statistical results are as follows: Figure 4 As shown, symmetrical pushing involves simultaneously using ejector pins at both ends of the chip along the x-axis. The measured critical displacements for each step of Strategy III (Step I: 6.0 mm, Step II: 7.8 mm, Step III: 3.0 mm) all fall within the theoretically calculated switching range. Furthermore, Strategy III has been experimentally proven to be optimal, with a significantly higher peeling success rate than traditional symmetrical ejection and unidirectional reverse ejection strategies. The experimental data are highly consistent with theoretical predictions, verifying the correctness of the theoretical model of this invention. This model can be used to accurately guide the setting of actual process parameters. Experiments demonstrate that dynamically adjusting the ejector pin position can effectively manage the stress state of the chip during the peeling process, providing an effective way to achieve non-destructive, high-yield peeling of ultra-thin chips.

[0055] Figure 6 An exemplary block diagram of an asymmetric multi-step switching push-and-release system for a flexible ultrathin chip according to an embodiment of the present invention is shown, the system comprising: The switching step module is used to obtain the substrate length and chip length, and determine the number of pin switching steps; The peel health index module is used to determine the relationship between the peel health index and the crack propagation length based on the chip's elastic modulus and chip thickness. The switching position module is used to determine the switching position corresponding to each switching step of the ejector pin based on the number of switching steps of the ejector pin and the relationship between the peeling health index and the crack propagation length. The ejector pin displacement module is used to determine the ejector pin displacement based on the switching position; The stripping module is used to control the pusher pins to push the chip according to the displacement of the pusher pins, until the chip is stripped after pushing at all switching positions.

[0056] According to one embodiment of the present invention, an asymmetric multi-step switching push-top non-destructive peeling device for flexible ultrathin chips is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to execute the asymmetric multi-step switching push-top non-destructive peeling method for the flexible ultrathin chips.

[0057] According to one embodiment of the present invention, a computer-readable storage medium is provided, on which computer program instructions are stored, wherein when the computer program instructions are executed by a processor, an asymmetric multi-step switching push-top non-destructive peeling method for the flexible ultrathin chip is implemented.

[0058] This invention can be a method, apparatus, system, and / or computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of the invention.

[0059] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the accompanying drawings are merely examples and do not limit the present invention. The objectives of the present invention have been fully and effectively achieved. The functions and structural principles of the present invention have been demonstrated and explained in the embodiments, and any variations or modifications may be made to the implementation of the present invention without departing from the stated principles.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An asymmetric multi-step switching push-and-release method for non-destructive peeling of flexible ultrathin chips, characterized in that, include: Obtain the substrate length and chip length, and determine the number of pin switching steps; Based on the chip's elastic modulus and thickness, the relationship between the peel health index and crack propagation length was determined. Based on the number of pin switching steps and the relationship between the peel health index and the crack propagation length, determine the switching position corresponding to each number of pin switching steps; The displacement of the ejector pin is determined based on the switching position; The chip is pushed by the ejector pin according to the ejector pin displacement control until the chip is completely removed after pushing at all switching positions.

2. The asymmetric multi-step switching push-and-release method for non-destructive peeling of flexible ultrathin chips according to claim 1, characterized in that, Obtain the substrate length and chip length, and determine the number of pin switching steps, including: Based on the length ratio between the substrate length and the chip length; Determine the preset range to which the length ratio belongs; The number of pin switching steps is determined based on the preset range to which the length ratio belongs.

3. The asymmetric multi-step switching push-and-release method for non-destructive peeling of flexible ultrathin chips according to claim 1, characterized in that, Based on the chip's elastic modulus and thickness, the relationship between the peel health index and crack propagation length is determined, including: The energy release rate at the crack tip of the adhesive layer is determined based on the crack propagation length. Based on the chip's elastic modulus and thickness, as well as the energy release rate at the crack tip of the adhesive layer, a peel health index related to the crack propagation length is determined, thereby obtaining the relationship between the peel health index and the crack propagation length.

4. The asymmetric multi-step switching push-and-release method for non-destructive peeling of flexible ultrathin chips according to claim 3, characterized in that, Based on the chip's elastic modulus and thickness, as well as the maximum tensile stress on the chip surface and the energy release rate at the crack tip of the adhesive layer, a peel health index related to crack propagation length is determined, including: According to the formula Determine the peel health index related to crack propagation length ,in, The elastic modulus of the chip. For the thickness of the chip, The energy release rate at the tip of the adhesive layer crack. This represents the maximum tensile stress on the chip surface.

5. The asymmetric multi-step switching push-and-release method for non-destructive peeling of flexible ultrathin chips according to claim 1, characterized in that, Based on the number of pin switching steps and the relationship between the peel health index and crack propagation length, the switching position corresponding to each pin switching step is determined, including: A relationship curve was obtained based on the relationship between the peeling health index and the crack propagation length; The intersection of two adjacent switching steps in the relationship curve is identified as a key node, and the number of nodes is consistent with the number of pin switching steps; The crack propagation length corresponding to each node is determined as the switching position where the ejector pin should act under that switching step.

6. The asymmetric multi-step switching push-and-release method for non-destructive peeling of flexible ultrathin chips according to claim 1, characterized in that, Determining the ejector pin displacement based on the switching position includes: Obtain multiple integral constants in the process of solving the energy release rate at the crack tip of the adhesive layer; The displacement of the ejector pin is determined based on the integral constant and the switching position.

7. The asymmetric multi-step switching push-and-release method for non-destructive peeling of flexible ultrathin chips according to claim 6, characterized in that, Determining the ejector pin displacement based on the integral constant and the switching position includes: According to the formula Determine the pin displacement corresponding to the j-th switching position, where, Let x be the x-coordinate of the position j of the action area of ​​the ejector pin. , , and All of these are the integral constants.

8. The asymmetric multi-step switching push-and-release method for non-destructive peeling of flexible ultrathin chips according to claim 7, characterized in that, The method for obtaining the integration constant includes: Construct a plane strain mechanical model of a three-layer structure consisting of a chip, adhesive layer, and substrate; The chip surface is divided into multiple regions; Based on the plane strain mechanics model of the chip-adhesive-substrate three-layer structure, the differential equations of the chip and substrate in each region are obtained; Obtain multiple boundary conditions and interface continuity conditions, and substitute them into the general solution of the differential equation to obtain a system of linear equations containing the integral constant. The integral constant is obtained by solving the system of linear equations using numerical methods.

9. An asymmetric multi-step switching push-and-release system for flexible ultrathin chips, the system being used to perform the method as described in any one of claims 1-8, characterized in that, include: The switching step module is used to obtain the substrate length and chip length, and determine the number of pin switching steps; The peel health index module is used to determine the relationship between the peel health index and the crack propagation length based on the chip's elastic modulus and chip thickness. The switching position module is used to determine the switching position corresponding to each switching step of the ejector pin based on the number of switching steps of the ejector pin and the relationship between the peeling health index and the crack propagation length. The ejector pin displacement module is used to determine the ejector pin displacement based on the switching position; The stripping module is used to control the pusher pins to push the chip according to the displacement of the pusher pins, until the chip is stripped after pushing at all switching positions.

10. An asymmetric multi-step switching push-and-release device for flexible ultrathin chips, characterized in that, include: processor; A memory for storing processor-executable instructions; wherein the processor is configured to invoke the instructions stored in the memory to perform the method as described in any one of claims 1-8.

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