Improved rewire structure for wafer level packaging

Abstract

The present application provides an improved re-distribution line structure of a wafer package, which includes a wafer, a plurality of re-distribution lines and a plurality of nickel-gold layers. Each of the re-distribution lines is horizontally formed on the surface of the wafer by a re-distribution layer process. Each of the nickel-gold layers is plated and formed on the surface of each of the re-distribution lines by a chemical nickel-gold process. Each of the nickel-gold layers is composed of a nickel layer and a gold layer, and the gold layer is located on the nickel layer. The present application solves the problem of uneven thickness of the nickel-gold layer and complicated process caused by using an electroplating process to form the nickel-gold layer in the prior art. In addition, each of the re-distribution lines can make the multiple pads on the wafer have the effect of XY plane electrical extension and interconnection, so that multiple pads can be formed around the wafer. Therefore, the design space and reliability of the wafer package can be effectively improved.

Description

Technical Field

[0001] This invention relates to an improved circuit structure for a chip package, and more particularly to an improved redistribution circuit structure for a chip package. Background Technology

[0002] An existing chip package includes a chip, multiple redistribution lines, and multiple nickel-gold layers. Each redistribution line is formed on the surface of the chip using redistribution layer technology, and each nickel-gold layer is deposited on the surface of each redistribution line using electroplating technology. Because the nickel-gold layers in this chip package are formed using electroplating, the nickel-gold layer thickness is uneven, and the manufacturing process becomes complex.

[0003] Furthermore, electroplating is a relatively energy-intensive and environmentally unfriendly production method, which does not align with the manufacturing trend towards green and environmentally friendly practices and makes it difficult for manufacturers to demonstrate social responsibility. Therefore, a chip packaging method that forms a nickel-gold layer without using electroplating technology is urgently needed by related industries. Summary of the Invention

[0004] The main objective of this invention is to provide an improved redistribution structure for a wafer package. This wafer package includes a wafer, multiple redistribution lines, and multiple nickel-gold layers. Each redistribution line is horizontally formed on the surface of the wafer using a redistribution layer process. Each nickel-gold layer is plated onto the surface of each redistribution line using an electroless nickel-gold plating process. Each nickel-gold layer is composed of a nickel layer and a gold layer, with the gold layer located on top of the nickel layer. This effectively solves the problems of uneven nickel-gold layer thickness and complex processes in existing wafer packages where the nickel-gold layer is formed using electroplating. Furthermore, each redistribution line enables multiple die pads on the wafer to achieve XY-planar electrical extension and interconnection, allowing for the formation of more dispersed die pads around the wafer. This effectively improves the design space and reliability of the wafer package.

[0005] To achieve the above objectives, the present invention provides an improved redistribution structure for a wafer package, the wafer package comprising a wafer, multiple redistribution lines, and multiple nickel-gold layers; wherein the surface of the wafer has multiple pads; and wherein each redistribution line utilizes a redistribution layer (RDL). The wafer surface is horizontally extended and formed using a redistribution layer process, and each redistribution line has a surface; wherein the wafer surface further includes at least one dielectric layer formed by the redistribution layer process, each dielectric layer having multiple horizontally extended grooves, each groove exposing each of the wafer's pads to the outside; wherein each redistribution line is further formed of a metal material within each groove and electrically connected to each of the pads; wherein each nickel-gold layer is disposed on the surface of each redistribution line within each groove, each nickel-gold layer being composed of a nickel (Ni) layer and a gold (Au) layer, with the gold layer of each nickel-gold layer located on top of the nickel layer; wherein the wafer is electrically connected to the outside via each pad, each redistribution line, and each nickel-gold layer in sequence; characterized in that: each nickel-gold layer is formed using electroless nickel immersion (ENIG). The manufacturing method of the wafer package includes the following steps: Step S1: Providing a wafer package, wherein the wafer package has a wafer, the surface of the wafer has multiple redistribution lines formed horizontally by a redistribution layer (RDL) process, and each redistribution line is electrically connected to multiple pads on the surface of the wafer, wherein the forming method of each redistribution line further includes first forming a dielectric layer on the surface of the wafer, then forming multiple grooves horizontally extending on each dielectric layer, and finally forming each redistribution line in each groove using a metal material, wherein each groove exposes each pad to the outside so that each redistribution line can be electrically connected to each pad, and each redistribution line has a surface; Step S2: Using an electroless nickel immersion process (ENIG)... Multiple nickel-gold layers are plated and formed on the surface of the redistribution lines in each of the grooves, wherein each nickel-gold layer is composed of a nickel (Ni) layer and a gold (Au) layer, and the gold layer of each nickel-gold layer is located on the nickel layer.

[0006] In a preferred embodiment of the present invention, each of the redistribution lines is further formed of copper (Cu) or aluminum (Al) metal material.

[0007] In a preferred embodiment of the present invention, the wafer further includes a first protective layer, and the sides of each of the crystal pads are surrounded by the first protective layer.

[0008] In a preferred embodiment of the present invention, the wafer further includes a second protective layer disposed on the first protective layer; wherein the second protective layer has an opening for each of the crystal pads to be exposed to the outside.

[0009] The present invention further provides an improved redistribution circuit structure for a wafer package, the wafer package comprising a wafer, multiple redistribution circuits, and multiple nickel-gold layers; wherein the surface of the wafer has multiple pads; wherein each redistribution circuit is formed horizontally on the surface of the wafer using a redistribution layer (RDL) process, and each redistribution circuit has one surface and two opposing side surfaces; wherein each redistribution circuit is electrically connected to each pad; wherein each nickel-gold layer is disposed on the surface and the two side surfaces of each redistribution circuit, each nickel-gold layer being composed of a nickel (Ni) layer and a gold (Au) layer, and the gold layer of each nickel-gold layer being located on the nickel layer; wherein the wafer is electrically connected to the outside via each pad, each redistribution circuit, and each nickel-gold layer in sequence; characterized in that: each nickel-gold layer is formed using electroless nickel immersion (ENIG). The wafer package is manufactured by depositing and forming redistribution lines on the surface and two sides of each redistribution line using a gold plating process; wherein the manufacturing method of the wafer package includes the following steps: Step S1: Providing a wafer package; wherein the wafer package has a wafer, the surface of the wafer has multiple redistribution lines formed horizontally using a redistribution layer (RDL) process, and each redistribution line is electrically connected to multiple pads on the surface of the wafer; wherein the forming method of each redistribution line further includes first... A dielectric layer is formed on the surface of the wafer. Then, multiple grooves are formed horizontally on each dielectric layer. Finally, a metal material is used to form each redistribution circuit in each groove. Each groove exposes each die pad so that each redistribution circuit can be electrically connected to each die pad. Each redistribution circuit has a surface. Step S2: Remove the dielectric layer around each redistribution circuit so that the two sides of each redistribution circuit are exposed. Step S3: Electroless nickel immersion gold (ENIG) process is used to plate and form multiple nickel-gold layers on the surface and the two sides of each redistribution circuit. Each nickel-gold layer is composed of a nickel (Ni) layer and a gold (Au) layer, and the gold layer of each nickel-gold layer is located on the nickel layer.

[0010] In a preferred embodiment of the present invention, in step S2, each of the dielectric layers is further removed from the surface of the wafer.

[0011] In a preferred embodiment of the present invention, each of the redistribution lines is further formed of copper (Cu) or aluminum (Al) metal material.

[0012] In a preferred embodiment of the present invention, the wafer further includes a first protective layer, and the sides of each of the crystal pads are surrounded by the first protective layer.

[0013] In a preferred embodiment of the present invention, the wafer further includes a second protective layer disposed on the first protective layer; wherein the second protective layer has an opening for each of the crystal pads to be exposed to the outside. Attached Figure Description

[0014] Figure 1 This is a side cross-sectional plan view of an embodiment of the wafer packaging of the present invention.

[0015] Figure 2 yes Figure 1 A cross-sectional view in one direction.

[0016] Figure 3 This is a side view of the cross-section of the groove formed on the dielectric layer of the present invention.

[0017] Figure 4 This is a side cross-sectional plan view of another embodiment of the wafer package of the present invention.

[0018] Figure 5 yes Figure 4 A cross-sectional view in one direction.

[0019] Figure 6 This is a side view of the cross-sectional plan of the re-laid circuit formed in the groove on the dielectric layer of the present invention.

[0020] Figure 7 It is Figure 6 A schematic diagram showing the complete removal of the dielectric layer.

[0021] Figure 8 This is a side cross-sectional plan view of another embodiment of the wafer package of the present invention.

[0022] Figure 9 It is Figure 6 A schematic diagram of the removal of the dielectric layer around the redistributed lines.

[0023] Explanation of reference numerals: 1-Chip package; 10-Chip; 11-Chip pad; 12-First protective layer; 13-Second protective layer; 131-Opening; 20-Relayed circuitry; 21-Dielectric layer; 22-Groove; 23-Surface; 24-Side; 30-Nickel-gold layer; 31-Nickel layer; 32-Gold layer. Detailed Implementation

[0024] The structure and technical features of the present invention will be described in detail below with reference to the accompanying drawings. The drawings are only used to illustrate the structural relationships and related functions of the present invention. Therefore, the dimensions of the components in the drawings are not drawn to actual scale and are not intended to limit the present invention.

[0025] Please refer to Figure 1 , Figure 4 and Figure 8 As shown, the present invention provides an improved redistribution circuit structure for a wafer package 1. The wafer package 1 includes a wafer 10, multiple redistribution circuits 20, and multiple nickel-gold layers 30. The wafer 10 has multiple pads 11 on its surface. Each redistribution circuit 20 is formed horizontally on the surface of the wafer 10 using a redistribution layer (RDL) process. Each redistribution circuit 20 is electrically connected to each pad 11. Each nickel-gold layer 30 is deposited on each redistribution circuit 20 using an electroless nickel immersion gold (ENIG) process. Each nickel-gold layer 30 is composed of a nickel (Ni) layer 31 and a gold (Au) layer 32, and the gold layer 32 of each nickel-gold layer 30 is located on the nickel layer 31 (e.g., ...). Figure 2 and Figure 5 (As shown) to prevent oxidation of the nickel layer 31; wherein the wafer 10 is electrically connected to the outside via each of the die pads 11, each of the redistribution lines 20 and each of the nickel-gold layers 30 in sequence. Each of the nickel-gold layers 30 formed by the chemical nickel-gold process is more flat and uniform than that formed by the electroplating process. In the embodiments shown in the accompanying drawings of this invention, for ease of reading and explanation, only one of each die pad 11, each of the redistribution lines 20 and each of the nickel-gold layers 30 is drawn for illustration, but is not intended to limit this patent.

[0026] Please refer to Figure 1 , Figure 4 and Figure 8 As shown, each of the redistributed circuits 20 is further formed from copper (Cu) or aluminum (Al) metal materials, but not limited to them, to facilitate diversified manufacturing.

[0027] Please refer to Figure 1 , Figure 4 and Figure 8 As shown, the chip 10 further includes a first protective layer 12, but is not limited thereto. The sides of each of the crystal pads 11 are surrounded by the first protective layer 12, which helps to increase the structural strength.

[0028] Please refer to Figure 1 , Figure 4 and Figure 8As shown, the wafer 10 further includes a second protective layer 13, but is not limited thereto, which is disposed on the first protective layer 12; wherein the second protective layer 13 has an opening 131 for each of the crystal pads 11 to be exposed to the outside, which helps to increase the structural strength.

[0029] Based on the different formation types of the redistributed lines 20 and the nickel-gold layers 30 in the wafer package 1 according to the present invention, and whether or not a dielectric layer is present on the surface of the wafer 10, the wafer package 1 of the present invention can be further divided into three embodiments, but not limited thereto, which are described below:

[0030] exist Figure 1 The wafer package 1 shown is a first embodiment of the present invention, wherein each of the redistribution lines 20 has a surface 23; wherein the surface of the wafer 10 further includes at least one dielectric layer 21 formed by the redistribution layer process, each of the dielectric layers 21 having a plurality of grooves 22 formed in a horizontal direction, each of the grooves 22 being for exposing each of the die pads 11 of the wafer 10 to the outside; wherein each of the redistribution lines 20 is further formed of metal material in each of the grooves 22 and electrically connected to each of the die pads 11; wherein each of the nickel-gold layers 30 is disposed on the surface 23 of each of the redistribution lines 20 in each of the grooves 22.

[0031] The manufacturing method of the wafer package 1 (first embodiment) includes the following steps:

[0032] Step S1: Provide a chip package 1 (e.g. Figure 3 (as shown); wherein the chip package 1 has a chip 10, the surface of the chip 10 has multiple redistribution lines 20 formed horizontally by a redistribution layer (RDL) process, and each of the redistribution lines 20 is electrically connected to multiple pads 11 on the surface of the chip 10 (e.g., Figure 3 (as shown); the forming method of each of the redistributed lines 20 further involves first forming a dielectric layer 21 on the surface of the wafer 10, then forming multiple grooves 22 extending horizontally on each of the dielectric layers 21, and finally forming each of the redistributed lines 20 in each of the grooves 22 using a metal material (as shown). Figure 3 (as shown); wherein each of the grooves 22 is for exposing each of the crystal pads 11 to the outside, so that each of the redistributed lines 20 can be electrically connected to each of the crystal pads 11 (as shown). Figure 3 (as shown); wherein each of the redistributed lines 20 has a surface 23 (as shown) Figure 3 (As shown).

[0033] Step S2: Using an electroless nickel immersion gold (ENIG) process, multiple nickel-gold layers 30 are plated and formed on the surface 23 of each of the redistributed lines 20 within each of the grooves 22. Figure 1 As shown; each of the nickel-gold layers 30 is composed of a nickel (Ni) layer 31 and a gold (Au) layer 32, and the gold layer 32 of each nickel-gold layer 30 is located on the nickel layer 31 (e.g., Figure 2 (As shown).

[0034] exist Figure 8 The embodiment shown is a second embodiment of the present invention, wherein each of the redistributed lines 20 has a surface 23 and two opposing side surfaces 24; wherein each of the nickel-gold layers 30 is disposed on the surface 23 and the two side surfaces 24 of each of the redistributed lines 20.

[0035] The manufacturing method of the wafer package 1 (second embodiment) includes the following steps:

[0036] Step S1: Provide a chip package 1 (e.g. Figure 6 (as shown); wherein the chip package 1 has a chip 10, the surface of the chip 10 has multiple redistribution lines 20 formed horizontally by a redistribution layer (RDL) process, and each of the redistribution lines 20 is electrically connected to multiple pads 11 on the surface of the chip 10 (e.g., Figure 6 (as shown); the forming method of each of the redistributed lines 20 further involves first forming a dielectric layer 21 on the surface of the wafer 10, then forming multiple grooves 22 extending horizontally on each of the dielectric layers 21, and finally forming each of the redistributed lines 20 in each of the grooves 22 using a metal material (as shown). Figure 6 (as shown); wherein each of the grooves 22 is for exposing each of the crystal pads 11 to the outside, so that each of the redistributed lines 20 can be electrically connected to each of the crystal pads 11 (as shown). Figure 6 (as shown); wherein each of the redistributed lines 20 has a surface 23 (as shown) Figure 6 (As shown).

[0037] Step S2: Remove the dielectric layer 21 surrounding each of the redistributed lines 20, so that the two sides 24 of each redistributed line 20 are exposed (e.g., Figure 9 (As shown).

[0038] Step S3: Using an electroless nickel immersion gold (ENIG) process, multiple nickel-gold layers 30 are plated and formed on the surface 23 and the two side surfaces 24 of each of the redistributed circuits 20 (e.g., ...). Figure 8 (As shown).

[0039] exist Figure 4 The embodiment shown is the third embodiment of the present invention. Each of the redistributed lines 20 has a surface 23 and two opposing side surfaces 24; wherein each of the nickel-gold layers 30 is disposed on the surface 23 and the two side surfaces 24 of each of the redistributed lines 20.

[0040] The manufacturing method of the wafer package 1 (third embodiment) includes the following steps:

[0041] Step S1: Provide a chip package 1 (e.g. Figure 6 (as shown); wherein the chip package 1 has a chip 10, the surface of the chip 10 has multiple redistribution lines 20 formed horizontally by a redistribution layer (RDL) process, and each of the redistribution lines 20 is electrically connected to multiple pads 11 on the surface of the chip 10 (e.g., Figure 6 (as shown); the forming method of each of the redistributed lines 20 further involves first forming a dielectric layer 21 on the surface of the wafer 10, then forming multiple grooves 22 extending horizontally on each of the dielectric layers 21, and finally forming each of the redistributed lines 20 in each of the grooves 22 using a metal material (as shown). Figure 6 (as shown); wherein each of the grooves 22 is for exposing each of the crystal pads 11 to the outside, so that each of the redistributed lines 20 can be electrically connected to each of the crystal pads 11 (as shown). Figure 6 (as shown); wherein each of the redistributed lines 20 has a surface 23 (as shown) Figure 6 (As shown).

[0042] Step S2: Remove the dielectric layer 21 surrounding each of the redistributed lines 20, so that the two sides 24 of each redistributed line 20 (e.g., Figure 7 As shown, the dielectric layer 21 is exposed to the outside, and each of the dielectric layers 21 is further completely removed from the surface 23 of the wafer 10.

[0043] Step S3: Using an electroless nickel immersion gold (ENIG) process, multiple nickel-gold layers 30 are plated and formed on the surface 23 and the two side surfaces 24 of each of the redistributed circuits 20 (e.g., ...). Figure 8 (As shown).

[0044] Compared with existing chip packages, the chip package 1 of the present invention has the following advantages:

[0045] (1) Each of the nickel-gold layers 30 of the present invention is plated and formed on each of the redistribution circuits 20 using an electroless nickel-gold (ENIG) process. Each of the nickel-gold layers 30 is composed of a nickel (Ni) layer 31 and a gold (Au) layer 32, and the gold layer 32 of each of the nickel-gold layers 30 is located on the nickel layer 31 (e.g., Figure 2 and Figure 5 As shown, this effectively solves the problems of uneven nickel-gold layer thickness and complex processes in existing chip packaging, which use electroplating to produce the nickel-gold layer. This not only improves product reliability but also saves manufacturing costs. In addition, the chemical nickel-gold process is more energy-efficient and environmentally friendly than the existing electroplating method used in chip packaging, which aligns with the manufacturing trend towards green and environmentally friendly practices.

[0046] (2) Each of the redistribution lines 20 is formed on the surface of the chip 10 by extending horizontally using a redistribution layer (RDL) process. Since each of the redistribution lines 20 is a process that is easy to implement precisely, the process is relatively simple, which is sufficient to enable each of the redistribution lines 20 to generate XY plane electrical extension and interconnection, while also enabling the finished chip package 1 to maintain or achieve a certain degree of thinness and small size.

[0047] (3) Each of the nickel-gold layers 30 in this invention is a metal stacked structure with a certain thickness (e.g., Figure 2 and Figure 5 As shown), this can enhance the structural strength of each of the redistributed circuits 20. If the chip package 1 chooses to generate electrical connections to the outside through wire bonding process, each of the nickel-gold layers 30 can help withstand the positive pressure generated from the wire bonding operation or the formation of solder joints, so that each of the redistributed circuits 20 is not easily damaged by the positive pressure.

[0048] The above description is merely a preferred embodiment of the present invention and is illustrative only, not restrictive. Those skilled in the art will understand that many changes, modifications, and even equivalent alterations can be made within the spirit and scope defined by the claims of the present invention, but all will fall within the protection scope of the present invention.

Claims

1. An improved redistribution structure for a wafer package, the wafer package comprising a wafer, multiple redistribution lines, and multiple nickel-gold layers; wherein the surface of the wafer has multiple pads; wherein each redistribution line utilizes a redistribution layer (RDL). The wafer is formed horizontally on its surface using a layered redistribution process, and each of the redistribution lines has a surface; the surface of the wafer further includes at least one dielectric layer formed by the redistribution layering process, each dielectric layer having multiple horizontally extending grooves, each groove exposing each of the wafer's pads to the outside; each redistribution line is further formed in each groove by a metal material and electrically connected to each of the pads; each nickel-gold layer is disposed on the surface of each redistribution line in each groove, each nickel-gold layer is composed of a nickel (Ni) layer and a gold (Au) layer, and the gold layer of each nickel-gold layer is located on the nickel layer; the wafer is electrically connected to the outside via each pad, each redistribution line and each nickel-gold layer in sequence; characterized in that: Each of the nickel-gold layers is plated and formed on the surface of each of the redistributed lines within each of the grooves using an electroless nickel immersion gold (ENIG) process. The manufacturing method of this wafer package includes the following steps: Step S1: Provide a wafer package; wherein the wafer package has a wafer, the surface of which has multiple redistribution lines formed horizontally using a redistribution layer (RDL) process, and each redistribution line is electrically connected to multiple pads on the surface of the wafer; wherein the redistribution lines are formed by first forming a dielectric layer on the surface of the wafer, then forming multiple grooves horizontally extending on each dielectric layer, and finally forming each redistribution line in each groove using a metal material; wherein each groove exposes each pad to the outside, so that each redistribution line can be electrically connected to each pad; wherein each redistribution line has a surface; and Step S2: Using an electroless nickel immersion gold (ENIG) process, multiple nickel-gold layers are deposited on the surface of each of the redistributed lines in each of the grooves; wherein each nickel-gold layer is composed of a nickel (Ni) layer and a gold (Au) layer, and the gold layer of each nickel-gold layer is located on the nickel layer.

2. The improved wafer package redistribution structure as described in claim 1, characterized in that: Each of these redistributed circuits is further formed from copper (Cu) or aluminum (Al) metal materials.

3. The improved wafer packaging redistribution structure as described in claim 1, characterized in that: The chip further includes a first protective layer, which surrounds the sides of each of the chip pads.

4. The improved wafer packaging redistribution structure as described in claim 3, characterized in that: The chip further includes a second protective layer disposed on the first protective layer; wherein the second protective layer has an opening for each of the die pads to be exposed to the outside.

5. An improved redistribution structure for a chip package, the chip package comprising a chip, multiple redistribution lines, and multiple nickel-gold layers; characterized in that: The wafer has multiple pads on its surface; each redistribution line is formed horizontally on the wafer surface using a redistribution layer (RDL) process, and each redistribution line has one surface and two opposing side surfaces; each redistribution line is electrically connected to each pad; each nickel-gold layer is disposed on the surface and the two side surfaces of each redistribution line, and each nickel-gold layer is composed of a nickel (Ni) layer and a gold (Au) layer, with the gold layer located on the nickel layer; the wafer is electrically connected to the outside via each pad, each redistribution line, and each nickel-gold layer in sequence; characterized in that: Each of the nickel-gold layers is plated and formed on the surface and two sides of each of the redistributed circuits using an electroless nickel immersion gold (ENIG) process. The manufacturing method for this wafer package includes the following steps: Step S1: Provide a wafer package; wherein the wafer package has a wafer, the surface of the wafer has multiple redistribution lines formed horizontally using a redistribution layer (RDL) process, and each redistribution line is electrically connected to multiple pads on the surface of the wafer; wherein the redistribution lines are formed by first forming a dielectric layer on the surface of the wafer, then forming multiple grooves horizontally extending on each dielectric layer, and finally forming each redistribution line in each groove using a metal material; wherein each groove exposes each pad to the outside so that each redistribution line can be electrically connected to each pad; wherein each redistribution line has a surface. Step S2: Remove the dielectric layer surrounding each of the redistributed lines, exposing both sides of each redistributed line to the outside; and Step S3: Using an electroless nickel immersion gold (ENIG) process, multiple nickel-gold layers are deposited on the surface and two sides of each of the redistributed circuits; wherein each nickel-gold layer is composed of a nickel (Ni) layer and a gold (Au) layer, and the gold layer of each nickel-gold layer is located on the nickel layer.

6. The improved wafer package redistribution structure as described in claim 5, characterized in that: In step S2, the dielectric layers are further removed from the surface of the wafer.

7. The improved wafer package redistribution structure as described in claim 5, characterized in that: Each of these redistributed circuits is further formed from copper (Cu) or aluminum (Al) metal materials.

8. The improved wafer package redistribution structure as described in claim 5, characterized in that: The chip further includes a first protective layer, which surrounds the sides of each of the chip pads.

9. The improved wafer package redistribution structure as described in claim 8, characterized in that: The chip further includes a second protective layer disposed on the first protective layer; wherein the second protective layer has an opening for each of the die pads to be exposed to the outside.

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