Secure access to memory in integrated circuits

Abstract

An integrated circuit (IC) chip includes a first memory storing first information and a second memory storing second information that needs to be protected against unauthorized access. A communication interface circuitry provides a processor external to the IC chip with read and / or write access to components of the IC chip. An embedded hardware security circuitry selectively provides the processor external to the IC chip with secure access to the second memory. Interconnect circuitry i) selectively grants the processor insecure access to the first memory via the communication interface circuitry, ii) selectively grants the processor secure access to the embedded hardware, and iii) restricts access to the second memory.

Description

Cross-references to related applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 537,668 entitled “Secure Address Space”, filed September 11, 2023, the disclosure of which is expressly incorporated herein by reference in its entirety for all purposes. Technical Field

[0002] This disclosure generally relates to communication networks, and more specifically, to providing secure access to the memory of network devices. Background Technology

[0003] The sophistication and effectiveness of cyberattacks continue to increase. Large amounts of critical information are contained in and / or pass through data centers, making them natural targets for hackers. Consequently, there is growing concern about the breach of data centers and the unauthorized interception and collection of critical, private information within them. The use of end-to-end encryption helps protect data centers from breaches and also helps safeguard information flowing through them.

[0004] Attackers can compromise communication networks, such as those in data centers, in a variety of ways. For example, they can eavesdrop on management messages between network switches to steal sensitive information, or send malicious packets masquerading as those from trusted network devices. As a more concrete example, attackers can exploit the use of Precise Time Protocol (PTP), a protocol commonly used to synchronize the actions of multiple different network devices within a network. One aspect of PTP involves network devices exchanging timing packets to synchronize their clocks. Communication networks using PTP can sometimes be compromised by illegally collecting information from such timing packets and using the stolen information to send malicious packets that prevent network devices from properly synchronizing.

[0005] One way to mitigate such attacks is to encrypt communication between network devices within a communication network. Media Access Control Security (MACsec) is a network security standard defined by the Institute of Electrical and Electronics Engineers (IEEE) that provides authentication and encrypted communication between devices connected via Ethernet. Using MACsec, two connected network devices exchange and verify security keys to establish a secure link, and use these keys to perform authentication, encryption, and decryption.

[0006] Cybersecurity keys (such as keys used for authentication, encryption, and / or decryption) are critical information, and misuse can have serious consequences, ranging from network outages that reduce throughput to the theft of sensitive data. Therefore, cybersecurity keys are typically stored in secure locations with restricted access. Summary of the Invention

[0007] In one embodiment, an integrated circuit (IC) chip includes: one or more first memories configured to store first information; one or more second memories configured to store second information, the second information to be protected against unauthorized access; a communication interface circuit arrangement configured to provide a processor external to the IC chip with read and / or write access to components of the IC chip; an embedded hardware security circuit arrangement coupled to the communication interface circuit arrangement configured to selectively provide a processor external to the IC chip with secure access to the one or more second memories; and an interconnect circuit arrangement coupled to i) the one or more first memories, ii) the communication interface circuit arrangement, and iii) the embedded hardware security circuit arrangement, the interconnect circuit arrangement being configured to i) selectively grant the processor insecure access to the one or more first memories via the communication interface circuit arrangement, ii) selectively grant the processor secure access to the embedded hardware, and iii) restrict access to the one or more second memories.

[0008] In another embodiment, a method for accessing an IC chip includes: receiving, at a communication interface circuit device of the IC chip, a first memory access request for accessing a first memory of the IC chip from a processor outside the IC chip; forwarding the first request to the first memory by an interconnect circuit device of the IC chip; serving the first memory access request by the first memory via the communication interface circuit device; at the interconnect circuit device, blocking direct access to the second memory of the IC chip via the communication interface circuit device in response to i) a request received at the communication interface circuit device and ii) a request for access to a second memory of the IC chip, the second memory being configured to store information protected against unauthorized external access; receiving, at the communication interface circuit device of the IC chip, a second memory access request for accessing the second memory of the IC chip from a processor outside the IC chip; forwarding the second request to an embedded hardware security circuit device of the IC chip by the interconnect circuit device of the IC chip; selectively providing secure access to the second memory by the embedded hardware security circuit device to serve the second memory access request; and serving the second memory access request by the second memory via the embedded hardware security circuit device and the communication interface circuit device. Attached Figure Description

[0009] Figure 1This is a simplified diagram of an example network device according to an embodiment, the network device including an integrated circuit (IC) chip communicatively coupled to a processor, wherein the IC chip includes a communication interface that provides the processor with two things: i) access to non-secure components of the IC chip, and ii) secure access to secure components of the IC chip.

[0010] Figure 2 This is a simplified diagram of another example network device according to another embodiment, wherein the IC chip includes a communication interface that provides a processor with: i) access to non-secure components of the IC chip, and ii) secure access to secure components of the IC chip.

[0011] Figure 3 This is a flowchart of an example method for accessing non-secure components of an IC chip and securely accessing secure components of an IC chip via the same communication interface of the IC chip, according to an embodiment. Detailed Implementation

[0012] In the embodiments described below, an integrated circuit (IC) chip has an architecture that provides a processor outside the IC chip with both of the following via a single communication interface: i) insecure access to one or more first components (e.g., first memory) of the IC chip, and ii) secure access to one or more second components (e.g., second memory). As an illustrative example, the one or more second components include one or more second memories configured to store second information protected against unauthorized external access, such as keys used to perform one or more of authentication, encryption, and decryption. Because the processor obtains both of the following via a single communication interface: i) insecure access to one or more first components and ii) secure access to one or more second components, compared to an architecture where the IC chip provides separate communication interfaces for insecure and secure access, at least in some embodiments, the cost, chip area, and / or pin count of the IC chip are reduced.

[0013] In some embodiments, the IC chip further includes an embedded hardware security circuitry coupled to a communication interface, the embedded hardware security circuitry being configured to i) authenticate a processor external to the IC chip, and ii) in response to authentication of the processor external to the IC chip, provide the processor external to the IC chip with secure access to one or more second components. In embodiments, the embedded hardware security circuitry is also configured to prevent the processor external to the IC chip from accessing one or more second components in response to failure to authenticate the processor external to the IC chip. In some embodiments, the embedded hardware security circuitry includes encryption circuitry and / or decryption circuitry, which the embedded hardware security circuitry uses to authenticate the processor external to the IC chip and / or provide encrypted communication between the IC chip and the processor when the processor is accessing one or more second components of the IC chip.

[0014] In some embodiments, the IC chip is used in the context of network devices (such as network switches, routers, etc.), and for illustrative purposes, the embodiments are described below in the context of network switches. In other embodiments, similar IC chips are used in other environments where the IC chip provides i) insecure access to one or more first components (e.g., first memory) and ii) secure access to one or more second components (e.g., second memory).

[0015] Figure 1 This is a simplified diagram of an example network device 100 according to an embodiment, which includes an IC chip 104 communicatively coupled to a processor 108. The network device 100 corresponds to a network switch, router, etc., and the IC chip 104 is sometimes referred to herein as a "switch chip". The switch chip 104 is included within a suitable chip package having suitable external interconnect structures, such as a ball grid array (BGA), pin grid array (PGA), planar grid array (LGA), etc., for inputting / outputting signals to and from the switch chip 104. In this embodiment, the processor is electrically connected to the switch chip 104 via the external interconnect structures of the chip package.

[0016] The switching chip 104 includes a plurality of network interfaces 112 communicatively coupled to ports (not shown) of the network device 100. The switching chip 104 also includes a memory 116 for storing packet data corresponding to packets received via the network interfaces 112, and a packet processor 120 configured to analyze packet header data of at least the packets received via the network interfaces 112 to determine which network interface 112 the packets will be forwarded via.

[0017] The switching chip 104 also includes one or more first components 124 (sometimes referred to herein as "(multiple) insecure components") and one or more second components 128 (sometimes referred to herein as "(multiple) secure components"). In an embodiment, the (multiple) insecure components 124 include one or more circuitry components to which the host processor 108 is provided insecure access, while the (multiple) secure components 128 include one or more circuitry components to which the host processor 108 is provided secure access. In an embodiment, providing secure access to the (multiple) secure components 128 includes: the switching chip 104 utilizing the processor 108 to perform an authentication process before allowing the processor 108 to access the secure components 128. In another embodiment, providing secure access to the (multiple) secure components 128 additionally or alternatively includes: the switching chip 104 i) encrypting information from the (multiple) secure components 128 and providing the encrypted information to the processor 108, and / or ii) decrypting information from the processor 108 and providing the decrypted information to the (multiple) secure components 128.

[0018] In one embodiment, the non-secure component 124 includes one or more first memories, and providing insecure access to the one or more first memories includes providing read and / or write access to the one or more first memories to the processor 108. Additionally or alternatively, in one embodiment, the secure component 128 includes one or more second memories, and providing secure access to the one or more second memories includes providing read and / or write access to the one or more second memories to the processor 108.

[0019] An embedded hardware security module (eHSM) 140 is configured to perform an authentication process with processor 108. In one embodiment, the authentication process involves eHSM 140 using a key associated with processor 108 to decrypt information received from processor 108 and comparing the decrypted information with information known to eHSM 140. In another embodiment, the authentication process additionally or alternatively involves eHSM 140 using a key associated with processor 108 to encrypt information received from processor 108 and comparing the encrypted information with information known to eHSM 140.

[0020] The authentication process additionally involves the processor 108 and eHSM 140 transmitting one or more keys, which the processor 108 and / or eHSM 140 use for encrypting / decrypting communication between the processor 108 and eHSM 140. In other embodiments, the authentication process performed by eHSM 140 additionally or alternatively includes one or more other suitable operations.

[0021] In an embodiment, eHSM 140 includes encryption / decryption circuitry (not shown), and eHSM 140 is configured to use the encryption / decryption circuitry to encrypt information output by switch chip 104 (e.g., output to processor 108) and decrypt information received by switch chip 104 (e.g., received from processor 108). eHSM 140 includes one or more memories (e.g., one or more of the following: i) one or more registers, ii) one or more random access memories (RAM), iii) one or more read-only memories (ROM), iv) solid-state memory, v) electronic fuses (eFuse, etc.), and one or more memories are configured to store keys for one or more of authentication, encryption, decryption, etc. In some embodiments, one or more memories are additionally configured to store unique identifiers (e.g., globally unique identifiers (GUIDs), media access control (MAC) addresses, etc.). In some embodiments, one or more memories are additionally configured to store boot code (i.e., firmware instructions) for a boot process executed by processor 108.

[0022] In some embodiments, the eHSM 140 includes an embedded processor (not shown) configured to execute machine-readable instructions (e.g., software and / or firmware instructions) stored in one or more memories. According to various embodiments, when executed by the embedded processor, the machine-readable instructions cause the embedded processor to perform one or more of the following operations: i) perform an authentication process with processor 108, ii) prompt encryption / decryption circuitry to encrypt information to be output by switch chip 104, iii) prompt encryption / decryption circuitry to decrypt information received by switch chip 104, and iv) provide boot code to processor 108 as part of a boot process performed by processor 108.

[0023] The switching chip 104 includes a communication interface circuitry 144 configured to facilitate communication between the processor 108 and the switching chip 104. In one embodiment, the communication interface circuitry 144 includes a Peripheral Component Interconnect Fast (PCIe) circuitry configured to operate according to the PCIe standard.

[0024] The switching chip 104 also includes an on-chip interconnect 156 that interconnects the various components of the switching chip 104 to facilitate the transfer of information between the various components of the switching chip 104. Additionally, the on-chip interconnect 156 is configured to restrict access to one or more other components of the switching chip 104. For example, the on-chip interconnect 156 is configured to restrict access to the security component(s) 128 to a subset of other components connected to the on-chip interconnect 156. As an illustrative example, the on-chip interconnect 156 is configured to disallow (i.e., block) direct access by the communication interface 144 to the security component(s) 128, but is configured to allow one or more other components of the switching chip 140 (such as the eHSM 140) to access the security component(s) 128.

[0025] Regarding communication interface 144, on-chip interconnect 156 is configured to: i) allow communication interface 144 to access a first subset of components of switching chip 104, such as (multiple) insecure components 124 and eHSM 140, and ii) block direct access to a second subset of components, such as (multiple) secure components 128. On the other hand, on-chip interconnect 156 is configured to allow eHSM 140 to access a second subset of components, such as (multiple) secure components 128. In an embodiment, when eHSM 140 has authenticated processor 108, eHSM 140 facilitates processor 108's access to (multiple) secure components 128 via communication interface 144, and when eHSM 140 fails to authenticate processor 108, it blocks processor 108's access to (multiple) secure components 128 via communication interface 144. In this way, in some embodiments, eHSM 140 helps prevent attackers from accessing security information in security components 128 by exploiting a malicious processor to replace or bypass processor 108 and attempting to extract security information from security components 128 via communication interface 144.

[0026] In embodiments where the security components 128 include one or more secure memories, after the eHSM 140 has authenticated the processor 108, the processor 108 provides a write request to the eHSM 140 via the communication interface 144 to write data to one or more secure memories 128. In an embodiment, the processor 108 encrypts the data to be written to the one or more secure memories before transmitting the data to the eHSM 140 via the communication interface 144, and the eHSM 140 decrypts the data. In response to receiving a write request from the processor 108 via the communication interface 144, the eHSM 140 accesses the one or more secure memories 128 via on-chip interconnects to write data to the one or more secure memories 128.

[0027] In another embodiment where the security components 128 include one or more secure memories, after the eHSM 140 has authenticated the processor 108, the processor 108 provides a request to the eHSM 140 via the communication interface 144 to read data from the one or more secure memories 128. In response to receiving the read request from the processor 108 via the communication interface 144, the eHSM 140 accesses the one or more secure memories 128 via the on-chip interconnect 156 to read data from the one or more secure memories 128. In this embodiment, the eHSM 140 encrypts the data before transmitting it to the processor 108 via the communication interface 144, and the processor 108 decrypts the data.

[0028] In some embodiments, packet processor 120 includes encryption / decryption circuitry configured to encrypt packet information in packets to be forwarded via network interface 112, and / or decrypt packet information in packets received via network interface 112. For example, the encryption / decryption circuitry may be used in conjunction with one or more of the following: i) the Internet Protocol Security (IPsec) protocol suite, which relates to encrypting the payload of Internet Protocol (IP) packets; ii) the Media Access Control Security (MACsec) network security standard; iii) another suitable protocol involving packet data encryption and decryption, etc.

[0029] In some such embodiments, one or more memories of the security components 128 store keys used for encryption and / or decryption by the encryption / decryption circuitry of the packet processor 120, and the packet processor 120 obtains the keys from one or more secure memories 128 via an on-chip interconnect 156. According to some embodiments, to facilitate the packet processor 120 obtaining keys from one or more secure memories 128, the packet processor 120 is connected to the on-chip interconnect 156, and the on-chip interconnect 156 allows the packet processor 120 to access one or more secure memories 128.

[0030] In other embodiments, each of at least some of the network interfaces 112 includes encryption / decryption circuitry configured to encrypt packet information in packets to be forwarded from the chip by the network interface 112, and / or decrypt packet information in packets received by the network interface 112 from outside the chip. For example, the encryption / decryption circuitry may be used in conjunction with one or more of the following: i) the IPsec protocol suite; ii) the MACsec network security standard; iii) another suitable protocol involving packet data encryption and decryption, etc.

[0031] In some such embodiments, one or more memories of the security components 128 store keys used for encryption and / or decryption by the encryption / decryption circuitry of the network interface 112, and at least some network interfaces 112 obtain keys from one or more secure memories 128 via on-chip interconnect 156. According to some embodiments, to facilitate key acquisition by at least some network interfaces 112 from one or more secure memories 128, at least some network interfaces 112 are connected to the on-chip interconnect 156, and the on-chip interconnect 156 allows at least some network interfaces 112 to access one or more secure memories 128.

[0032] In some embodiments of the exchange chip 104 encrypting and decrypting packet information, the key used for encryption / decryption will be updated from time to time (e.g., periodically). Therefore, in some embodiments, the key stored in one or more secure memories 128 and used for encryption / decryption is updated from time to time (e.g., periodically) by the processor 108, and the processor 108 uses techniques such as those described above via the eHSM 140 to update the key stored in one or more secure memories 128.

[0033] In some embodiments, one or more memories of the security components 128 store forwarding information used by the packet processor 120 to determine the network interface 112 through which packets should be forwarded. For example, in some scenarios, it is important to maintain secure access to the forwarding information. In such an embodiment, after the eHSM 140 has authenticated the processor 108, the processor 108 provides a request to the eHSM 140 via the communication interface 144 to read the forwarding information from one or more secure memories 128. In response to receiving the read request from the processor 108 via the communication interface 144, the eHSM 140 accesses one or more secure memories 128 via the on-chip interconnect 156 to read the forwarding information from one or more secure memories 128. In an embodiment, the eHSM 140 encrypts the forwarding information before transmitting it to the processor 108 via the communication interface 144, and the processor 108 decrypts the forwarding information.

[0034] In another embodiment, processor 108 additionally or alternatively provides a write request to eHSM 140 via communication interface 144 to write forwarded information to one or more secure memories 128 after eHSM 140 has authenticated processor 108. In this embodiment, processor 108 encrypts the forwarded information to be written to one or more secure memories before transmitting the forwarded information to eHSM 140 via communication interface 144, and eHSM 140 decrypts the forwarded information. In response to receiving a write request from processor 108 via communication interface 144, eHSM 140 accesses one or more secure memories 128 via on-chip interconnect to write the forwarded information to one or more secure memories 128.

[0035] In some embodiments, to facilitate packet processor 120 obtaining forwarding information from one or more secure memories 128, packet processor 120 is connected to on-chip interconnect 156, and according to some embodiments, on-chip interconnect 156 allows packet processor 120 to access one or more secure memories 128, such as in response to read and / or write requests from packet processor 120.

[0036] In some embodiments, one or more memories of the non-secure components 124 store forwarding information used by the packet processor 120 to determine which packets should be forwarded via the network interface 112 to which they are forwarded. For example, in some scenarios, it is not desirable to maintain secure access to the forwarding information. In such embodiments, the processor 108 provides a request to read forwarding information from one or more memories 124 via the communication interface 144, and in response to receiving a read request from the processor 108 via the communication interface 144, the on-chip interconnect provides access to the processor 108 to one or more memories 124. In some embodiments, the processor 108 provides a request to write forwarding information to one or more memories 124 via the communication interface 144, and in response to receiving a write request from the processor 108 via the communication interface 144, the on-chip interconnect provides access to the processor 108 to one or more memories 124. In embodiments, the processor 108 may receive forwarding information from another network device (e.g., as part of a process for sharing forwarding information between different network devices) and send a write request via the communication interface 144 to write the forwarding information to one or more memories 124.

[0037] As described above, processor 108 can access both i) (multiple) insecure components 124 and ii) (multiple) secure components 128 via the same communication interface 144. For example, in one embodiment, on-chip interconnect 156 directs access requests received via communication interface 144 for the multiple insecure components 124 to the multiple insecure components 124, and directs access requests received via communication interface 144 for the multiple secure components 128 to the eHSM 140. Processor 108's access to the multiple secure components 128 is only permitted after the eHSM 140 has authenticated processor 108, thus mitigating the threat of unauthorized access to the multiple secure components 128 at least in some embodiments. Additionally, in some embodiments, information transmitted via communication interface 144 in conjunction with processor 108's access to the multiple secure components 128 is encrypted. On the other hand, in some embodiments, information transmitted via communication interface 144 in conjunction with processor 108's access to the multiple insecure components 124 is unencrypted. Therefore, in at least some embodiments, processor 108 can access (a plurality of) insecure components 124 via communication interface 144 without processor 108 having to encrypt and / or decrypt data, and without exchange chip 104 having to encrypt and / or decrypt data, thus saving power and / or increasing transmission speed.

[0038] Figure 2 This is a simplified diagram of another example network device 200 according to another embodiment. Network device 200 is similar to... Figure 1 Network device 100, and for the sake of brevity, elements with the same number will not be described in detail.

[0039] In example network device 200, switching chip 104 includes additional interconnect 204 between eHSM 140 and security components 128, and eHSM 140 is configured to access security components 128 via additional interconnect 204, which is different from on-chip interconnect 156.

[0040] and Figure 1 Similar to the previous embodiment, when the eHSM 140 has authenticated the processor 108, the eHSM 140 facilitates the processor 108 to access the security components(s) 128 via the communication interface 144. More specifically, when the eHSM 140 has authenticated the processor 108, the eHSM 140 facilitates the processor 108 to access the security components(s) 128 via the communication interface 144 and via the additional interconnect 204.

[0041] In embodiments where the (multiple) security components 128 include one or more secure memories, after the eHSM 140 has authenticated the processor 108, the processor 108 provides a write request to the eHSM 140 via the communication interface 144 to write data to one or more secure memories 128. In an embodiment, the processor 108 encrypts the data to be written to the one or more secure memories before transmitting the data to the eHSM 140 via the communication interface 144, and the eHSM 140 decrypts the data. In response to receiving a write request from the processor 108 via the communication interface 144, the eHSM 140 accesses the one or more secure memories 128 via the additional interconnect 204 to write the data to the one or more secure memories 128. If an attacker captures the data transmitted via the communication interface 144, the captured data will be useless to the attacker because the transmitted data is encrypted. Therefore, encrypting the data transmitted via the communication interface 144 mitigates potential attacks involving the capture of data transmitted via the communication interface 144.

[0042] In another embodiment where the (multiple) security components 128 include one or more secure memories, after the eHSM 140 has authenticated the processor 108, the processor 108 provides the eHSM 140 with a request to read data from one or more secure memories 128 via the communication interface 144. In response to receiving the read request from the processor 108 via the communication interface 144, the eHSM 140 accesses one or more secure memories 128 via the additional interconnect 204 to read data from one or more secure memories 128. In this embodiment, the eHSM 140 encrypts the data before transmitting it to the processor 108 via the communication interface 144, and the processor 108 decrypts the data. If an attacker captures the data transmitted via the communication interface 144, the captured data will be useless to the attacker because the transmitted data is encrypted. Therefore, encrypting the data transmitted via the communication interface 144 mitigates potential attacks involving the capture of data transmitted via the communication interface 144.

[0043] Figure 3 This is a flowchart of an example method 300 for accessing an IC chip (such as an IC chip in a network device, e.g., a switching chip) according to an embodiment. According to various embodiments, method 300 is... Figure 1 Network device 100 or Figure 2 The network device 200 is used for implementation, and for illustrative purposes, refer to [reference needed]. Figure 1 and Figure 2Method 300 is described below. In other embodiments, method 300 is implemented by another suitable device different from network device 100 and network device 200. For example, according to an embodiment, method 300 is implemented by another suitable device that includes having multiple insecure components, multiple secure components, a communication interface, on-chip interconnects, and similar features as described in the reference citation. Figure 1 and Figure 2 The IC chip of the corresponding eHSM component is described. In other embodiments, Figure 1 The network device 100 implements another suitable method different from method 300, and / or Figure 2 The network device 200 implements an alternative method different from method 300.

[0044] At block 304, the communication interface circuitry of the IC chip receives a first access request from a processor external to the IC chip for accessing a first circuitry component of the IC chip. In this embodiment, the first access request is a first memory access request, and the first circuitry component of the IC chip is the first memory of the IC chip. For example, communication interface 144 receives a first memory access request from processor 108 for accessing insecure memory 124.

[0045] At block 308, the interconnect circuitry of the IC chip forwards the first request to a first circuitry component of the IC chip. For example, on-chip interconnect 156 forwards the first memory access request to insecure memory 124.

[0046] At block 312, the first circuitry component serves the first access request via a communication interface circuitry. For example, insecure memory 124 serves the first memory access request via on-chip interconnect 156 and communication interface 144. In an embodiment where the first circuitry component is memory and the first access request is a read request, serving the first access request at block 144 includes: i) retrieving information from memory in response to the read request, and ii) forwarding the retrieved information to the processor via the interconnect circuitry and communication interface. In an embodiment where the first circuitry component is memory and the first access request is a write request, serving the first access request at block 144 includes: i) receiving information to be written to memory from the processor via the interconnect circuitry and communication interface in conjunction with the write request, and ii) writing the information to memory.

[0047] At block 316, the interconnect circuitry blocks i) access requests received at the communication interface circuitry and ii) requests to access a security component of the IC chip. In this way, in this embodiment, unauthorized requests to access the security component are blocked. In this embodiment, blocking access at block 316 includes preventing the communication interface circuitry from directly accessing the security component, for example, preventing access requests and / or data received via the communication interface circuitry from being directly provided to the security component, and preventing data from the security component from being directly provided to the communication interface circuitry. In this embodiment, the security component is a secure memory configured to store information protected against unauthorized external access (e.g., via communication interface 144), and the interconnect circuitry blocks i) memory access requests received at the communication interface circuitry and ii) requests to access the secure memory. For example, on-chip interconnect 156 blocks i) access requests received at the communication interface circuitry 144 and ii) requests to access (a plurality of) security components 128.

[0048] At block 320, the communication interface circuitry receives a second access request from a processor outside the IC chip for access to secure components of the IC chip. For example, communication interface 144 receives a memory access request for access to secure memory 128.

[0049] At block 324, the interconnect circuitry of the IC chip forwards the second access request to the embedded hardware security circuitry of the IC chip. For example, on-chip interconnect 156 forwards a memory access request for access to secure memory 128 received via communication interface 144 to eHSM 140.

[0050] At block 328, in response to a second access request, the embedded hardware security circuitry provides secure access to a security component to serve the second access request. For example, eHSM 140 provides secure access to security component 128 to serve the access request. According to an embodiment, providing secure access to a security component at block 324 includes: the embedded hardware security circuitry performing an authentication process using a processor external to the IC chip; in response to the processor being authenticated, the embedded hardware security circuitry provides access to the security component to the processor; and in response to the processor failing to be authenticated, the embedded hardware security circuitry blocks the processor's access to the security component.

[0051] In one embodiment, providing secure access to the security component at block 324 includes: decrypting information received from the processor via a communication interface and corresponding to an access request at an embedded hardware security circuit device; and providing the decrypted information to the security component by the embedded hardware security circuit device. In another embodiment, providing secure access to the security component at block 324 additionally or alternatively includes: receiving information from the security component at the embedded hardware security circuit device in response to an access request; encrypting the information by the embedded hardware security circuit device; and transmitting the encrypted information to the processor via the communication interface by the embedded hardware security circuit device.

[0052] In an embodiment where the second circuitry component is memory and the second access request is a read request, providing secure access to the memory at block 324 includes: i) receiving information from the memory at an embedded hardware security circuitry device in response to the read request; encrypting the information by the embedded hardware security circuitry device; and transmitting the encrypted information to the processor via a communication interface by the embedded hardware security circuitry device. In an embodiment where the secure circuitry component is memory and the second access request is a write request, providing secure access to the memory at block 324 includes: decrypting information received from the processor via a communication interface and corresponding to the write request at an embedded hardware security circuitry device; and providing the decrypted information to the memory by the embedded hardware security circuitry device.

[0053] At block 332, the security circuitry component serves the second access request via embedded hardware security circuitry and communication interface circuitry. For example, the secure memory 128 serves the second access request via eHSM 140 and communication interface 144.

[0054] In one embodiment, serving the second access request at block 328 includes: the secure circuit device component sending information corresponding to the second access request to the embedded hardware secure circuit device via an interconnect circuit device. In another embodiment, serving the second access request at block 328 includes: the secure circuit device component sending information corresponding to the second access request to the embedded hardware secure circuit device via an additional interconnect circuit device (e.g., additional interconnect 204) separate from the interconnect circuit device. In one embodiment, serving the second access request at block 328 includes: the secure circuit device component receiving information corresponding to the second access request from the embedded hardware secure circuit device via an interconnect circuit device. In another embodiment, serving the second access request at block 328 includes: the secure circuit device component receiving information corresponding to the second access request from the embedded hardware secure circuit device via an additional interconnect circuit device (e.g., additional interconnect 204) separate from the interconnect circuit device.

[0055] In an embodiment where the second circuit device component is a memory and the second access request is a read request, serving the second access request at block 328 includes: i) receiving a read request at the memory, ii) retrieving information corresponding to the read request from the memory, and iii) transmitting the information to the embedded hardware security circuit device. In an embodiment where the security circuit device component is a memory and the second access request is a write request, serving the second access request at block 328 includes: i) receiving a write request and information corresponding to the write request at the memory, and ii) storing the information corresponding to the write request in the memory.

[0056] Refer again Figure 1 and Figure 2 In one embodiment, IC chip 104 corresponds to a single IC chip within a chip package, and processor 108 is located outside the chip package. In another embodiment, components of IC chip 104 are implemented across multiple IC chips included in a single chip package, and processor 108 is located outside the single chip package. For example, in one embodiment, the multiple IC chips correspond to a multi-chip module (MCM), and processor 108 is located outside the MCM. Therefore, the terms "IC chip" and "switch chip" as used herein can refer to multiple IC chips included in a single chip package.

[0057] Example 1: An integrated circuit (IC) chip for a network device, the IC chip comprising: one or more first memories of the network device, the one or more first memories configured to store first information; one or more second memories of the network device, the one or more second memories configured to store second information to be protected against unauthorized access; a communication interface circuit device configured to provide read and / or write access to components of the IC chip to a processor external to the IC chip; an embedded hardware security circuit device coupled to the communication interface circuit device, the embedded hardware security circuit device being configured to selectively provide secure access to the one or more second memories to a processor external to the IC chip; and an interconnect circuit device coupled to i) the one or more first memories, ii) the communication interface circuit device, and iii) the embedded hardware security circuit device, the interconnect circuit device being configured to: i) selectively grant the processor insecure access to the one or more first memories via the communication interface circuit device, ii) selectively grant the processor secure access to the embedded hardware, and iii) restrict access to the one or more second memories.

[0058] Example 2: According to the IC chip of Example 1, wherein the communication interface circuit device is configured to: receive a request from a processor outside the IC chip to access one or more first memories; in conjunction with the request received from the processor to access one or more first memories, transmit insecure first information between the processor outside the IC chip and the one or more first memories; receive a request from the processor outside the IC chip to access one or more second memories; and in conjunction with the request received from the processor to access one or more second memories, transmit encrypted second information between the processor outside the IC chip and the one or more second memories.

[0059] Example 3: According to the IC chip of Example 2, wherein the interconnect circuit device is configured to: forward a request from the processor outside the IC chip to access one or more first memories to the one or more first memories; transmit insecure first information between the communication interface circuit device and the one or more first memories in conjunction with the request received from the processor to access the one or more first memories; prevent the request from the processor outside the IC chip to access one or more second memories from directly proceeding to the one or more second memories; forward the request from the processor outside the IC chip to access the one or more second memories to the embedded hardware security circuit device; and transmit encrypted second information between the communication interface circuit device and the embedded hardware security circuit device in conjunction with the request received from the processor to access the one or more second memories.

[0060] Example 4: An IC chip according to any one of Examples 1 to 3, wherein the embedded hardware security circuit device is configured to: perform an authentication process using a processor external to the IC chip; in response to the embedded hardware security circuit device determining that the processor external to the IC chip is authorized to access the one or more second memories, provide secure access to the one or more second memories to the processor external to the IC chip; and in response to the embedded hardware security circuit device determining that the processor external to the IC chip is not authorized to access the one or more second memories, prevent the processor external to the IC chip from accessing the one or more second memories.

[0061] Example 5: An IC chip according to any one of Examples 1 to 4, wherein the interconnect circuit device is further coupled to the one or more second memories; wherein the interconnect circuit device is further configured to grant the embedded hardware security circuit device access to the one or more second memories; and wherein the embedded hardware security circuit device is configured to use the interconnect circuit device to provide a processor outside the IC chip with secure access to the one or more second memories.

[0062] Example 6: An IC chip according to any one of Examples 1 to 4, wherein the interconnect circuit device is a first interconnect circuit device; wherein the IC chip further includes a second interconnect circuit device coupled to the embedded hardware security circuit device and the one or more second memories; and wherein the embedded hardware security circuit device is configured to use the second interconnect circuit device to provide secure access to the one or more second memories to a processor outside the IC chip.

[0063] Example 7: An IC chip according to any one of Examples 1 to 6, wherein the interconnect circuitry is configured to prevent a request from the processor outside the IC chip to access the one or more second memories from directly proceeding to the one or more second memories.

[0064] Example 8: An IC chip according to any one of Examples 1 to 7, wherein the embedded hardware security circuit device is configured to provide secure access to the one or more second memories to a processor outside the IC chip by at least: i) authenticating the processor outside the IC chip, and ii) in response to authenticating the processor outside the IC chip, providing access to the one or more second memories to the processor outside the IC chip.

[0065] Example 9: According to the IC chip of Example 8, the embedded hardware security circuit device is further configured to provide secure access to the one or more second memories to a processor outside the IC chip by preventing access to the one or more second memories by the processor in response to failure to authenticate the processor outside the IC chip.

[0066] Example 10: An IC chip according to any one of Examples 1 to 9, wherein the embedded hardware security circuit device includes an encryption / decryption circuit device, and wherein the embedded hardware security circuit device is configured to provide secure access to the one or more second memories to a processor outside the IC chip by at least one or both of the following: the encryption / decryption circuit device decrypts first information from the processor corresponding to an access request received from the processor via the communication interface circuit device to generate decrypted information, and transmits the decrypted information to the one or more second memories; and the encryption / decryption circuit device encrypts second information from the one or more second memories corresponding to a response to an access request received from the processor via the communication interface circuit device to generate encrypted information, and transmits the encrypted information to the processor via the communication interface circuit device.

[0067] Example 11: An IC chip according to any one of Examples 1 to 10, wherein: the one or more second memories include a key memory configured to store a security key for encrypting data output by the IC chip and / or decrypting data received by the IC chip; the IC chip further includes an encryption / decryption circuit device configured to use the security key stored in the key memory to perform encryption of one or both of the data output by the IC chip and decryption of the data received by the IC chip; and the embedded hardware security circuit device is configured to provide the processor with secure access to the key memory to store the security key in the key memory.

[0068] Example 12: The IC chip according to any one of Examples 1 to 11 further includes: a plurality of network interfaces configured to be communicatively coupled to ports of a network device; and a packet processor configured to analyze the headers of packets received via the plurality of network interfaces to determine the network interface through which the packets are to be forwarded, the packet processor being coupled to the interconnect circuit device; wherein the interconnect circuit device is configured to selectively grant the packet processor insecure access to the one or more first memories in conjunction with determining that the packets are to be read from and / or written to the one or more first memories via the network interface through which they are to be forwarded.

[0069] Example 13: An IC chip according to any one of Examples 1 to 12, wherein: the one or more second memories include a forwarding database memory configured to store forwarding information used by the packet processor to determine the network interface through which the packet is to be forwarded; and the embedded hardware security circuitry is configured to provide the processor with secure access to the key memory to read the forwarding information from the forwarding database memory and to securely transmit the forwarding information to the processor via the communication interface circuitry.

[0070] Example 14: A method for accessing an integrated circuit (IC) chip of a network device, the method comprising: receiving, at a communication interface circuit device of the IC chip, a first memory access request from a processor external to the IC chip for accessing a first memory of the IC chip, the first memory storing information for use by the network device; forwarding the first request to the first memory by an interconnect circuit device of the IC chip; serving the first memory access request via the communication interface circuit device by the first memory; and at the interconnect circuit device, preventing access to the IC chip via the communication interface circuit device in response to i) a request received at the communication interface circuit device and ii) a request to access a second memory of the IC chip. Direct access to the second memory of the IC chip, the second memory being configured to store information for use by the network device and to be protected against unauthorized external access; at the communication interface circuitry of the IC chip, a second memory access request for accessing the second memory of the IC chip is received from a processor outside the IC chip; the interconnection circuitry of the IC chip forwards the second request to the embedded hardware security circuitry of the IC chip; the embedded hardware security circuitry selectively provides secure access to the second memory to serve the second memory access request; and the second memory serves the second memory access request via the embedded hardware security circuitry and the communication interface circuitry.

[0071] Example 15: The method for accessing the IC chip according to Example 14 further includes: transmitting insecure first information between a processor outside the IC chip and the one or more first memories via the communication interface circuit device, in conjunction with the request received from the processor for accessing the one or more first memories; and transmitting encrypted second information between a processor outside the IC chip and the one or more second memories via the communication interface circuit device, in conjunction with the request received from the processor for accessing the one or more second memories.

[0072] Example 16: The method for accessing the IC chip according to Example 15 further includes: transmitting insecure first information between the communication interface circuit device and the one or more first memories via the interconnect circuit device, in conjunction with the request received from the processor for accessing the one or more first memories; and transmitting encrypted second information between the communication interface circuit device and the embedded hardware security circuit device via the interconnect circuit device, in conjunction with the request received from the processor for accessing the one or more second memories.

[0073] Example 17: A method for accessing the IC chip according to any one of Examples 14 to 16, wherein selectively providing secure access to the second memory includes: the embedded hardware security circuitry device performing an authentication process using a processor external to the IC chip; in response to the embedded hardware security circuitry device determining that the processor external to the IC chip is authorized to access the one or more second memories, the embedded hardware security circuitry device providing secure access to the one or more second memories to the processor external to the IC chip; and in response to the embedded hardware security circuitry device determining that the processor external to the IC chip is not authorized to access the one or more second memories, the embedded hardware security circuitry device preventing the processor external to the IC chip from accessing the one or more second memories.

[0074] Example 18: The method for accessing the IC chip according to any one of Examples 14 to 17 further includes: granting the embedded hardware security circuit device access to the one or more second memories by the interconnect circuit device; and wherein providing secure access to the second memories to serve the second memory access request includes: the embedded hardware security circuit device using the interconnect circuit device to provide secure access to the one or more second memories to a processor outside the IC chip.

[0075] Example 19: A method for accessing the IC chip according to any one of Examples 14 to 17, wherein: the interconnect circuit device is a first interconnect circuit device; and providing secure access to the second memory to serve the second memory access request includes: the embedded hardware security circuit device using a second interconnect circuit device to provide secure access to the one or more second memories to a processor outside the IC chip, the second interconnect circuit device being different from the first interconnect circuit device.

[0076] Example 20: A method for accessing the IC chip according to any one of Examples 14 to 19, wherein providing secure access to the second memory to serve a second memory access request includes: authenticating a processor outside the IC chip; and in response to authenticating the processor outside the IC chip, the embedded hardware security circuitry provides access to the one or more second memories to the processor outside the IC chip.

[0077] Example 21: The method for accessing the IC chip according to Example 20, wherein providing secure access to the second memory to serve the second memory access request includes: in response to failure to authenticate the processor outside the IC chip, the embedded hardware security circuitry device blocks access to the one or more second memories by the processor.

[0078] Example 22: A method for accessing the IC chip according to any one of Examples 14 to 21, wherein providing secure access to the second memory to serve a second memory access request includes one or both of the following: i) decrypting first information from the processor corresponding to an access request received from the processor via the communication interface circuitry by the encryption / decryption circuitry of the embedded hardware security circuitry to generate decrypted information, and transmitting the decrypted information to the one or more second memories; and ii) encrypting second information from the one or more second memories corresponding to a response to an access request received from the processor via the communication interface circuitry by the encryption / decryption circuitry to generate encrypted information, and transmitting the encrypted information to the processor via the communication interface circuitry.

[0079] Example 23: A method for accessing the IC chip according to any one of Examples 14 to 22, wherein the one or more second memories include a key memory configured to store a security key, and wherein the method further includes: using an encryption circuit device of the IC chip to encrypt information output by the IC chip using a security key stored in the key memory; wherein providing secure access to the second memory to serve a second memory access request includes: providing secure access to the key memory to the processor by the embedded hardware security circuit device to store the security key in the key memory.

[0080] Example 24: A method for accessing the IC chip according to any one of Examples 14 to 23, wherein the one or more second memories include a key memory configured to store a security key, and wherein the method further includes: using a decryption circuit device of the IC chip to decrypt information received by the IC chip using a security key stored in the key memory; wherein providing secure access to the second memory to serve a second memory access request includes: providing secure access to the key memory to the processor by the embedded hardware security circuit device to store the security key in the key memory.

[0081] Example 25: The method for accessing the IC chip according to any one of Examples 14 to 24 further includes: receiving packets via a plurality of network interfaces of the IC chip; analyzing the headers of the packets received via the plurality of network interfaces at a packet processor to determine the network interface through which the packets are to be forwarded; and forwarding the packets by the packet processor to the network interface determined by the packet processor for transmission through the network interface.

[0082] Example 26: A method for accessing the IC chip according to Example 25, wherein: the one or more second memories include a forwarding database memory configured to store forwarding information used by the packet processor to determine the network interface through which the packet is to be forwarded; and wherein providing secure access to the second memory to serve a second memory access request includes: providing the processor with secure access to the key memory by the embedded hardware security circuitry to read forwarding information from the forwarding database memory.

[0083] Some of the various frameworks, operations, and techniques described above can be implemented using hardware, a processor executing firmware instructions, a processor executing software instructions, or any suitable combination thereof. When implemented using a processor executing software or firmware instructions, the software or firmware instructions can be stored in any suitable computer-readable storage medium. The software or firmware instructions may include machine-readable instructions that, when executed by one or more processors, cause one or more processors to perform the various actions described above.

[0084] When implemented in hardware, the hardware may include one or more of the following: discrete components, integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc.

[0085] Although the invention has been described with reference to specific examples, these examples are intended to be illustrative only and not to limit the invention. Changes, additions and / or deletions may be made to the disclosed embodiments without departing from the scope of the invention.

Claims

1. An integrated circuit (IC) chip for use in network devices, the IC chip comprising: One or more first memories of the network device are configured to store first information; One or more second memories of the network device are configured to store second information, which is to be protected against unauthorized access. A communication interface circuit device is configured to provide a processor external to the IC chip with read access and / or write access to components of the IC chip; An embedded hardware security circuit device is coupled to the communication interface circuit device, the embedded hardware security circuit device being configured to selectively provide secure access to the one or more second memories to the processor outside the IC chip; as well as Interconnect circuitry, coupled to i) the one or more first memories, ii) the communication interface circuitry, and iii) the embedded hardware security circuitry, the interconnect circuitry being configured to: i) selectively grant the processor insecure access to the one or more first memories via the communication interface circuitry, ii) selectively grant the processor secure access to the embedded hardware, and iii) restrict access to the one or more second memories.

2. The IC chip according to claim 1, wherein the communication interface circuit device is configured as follows: Receive a request to access the one or more first memories from the processor outside the IC chip; In conjunction with the request received from the processor for access to the one or more first memories, non-secure first information is transmitted between the processor, located outside the IC chip, and the one or more first memories; Receive a request to access the one or more second memories from the processor outside the IC chip; as well as In conjunction with the request received from the processor to access the one or more second memories, encrypted second information is transmitted between the processor, located outside the IC chip, and the one or more second memories.

3. The IC chip according to claim 2, wherein the interconnect circuit device is configured as follows: The request for access to the one or more first memories from the processor outside the IC chip is forwarded to the one or more first memories; In conjunction with the request received from the processor for access to the one or more first memories, non-secure first information is transmitted between the communication interface circuitry and the one or more first memories; Prevent requests from the processor outside the IC chip to access the one or more second memories from being directly forwarded to the one or more second memories; The request from the processor outside the IC chip to access the one or more second memories is forwarded to the embedded hardware security circuit device. as well as In conjunction with the request received from the processor for access to the one or more second memories, encrypted second information is transmitted between the communication interface circuitry and the embedded hardware security circuitry.

4. The IC chip according to claim 1, wherein the embedded hardware security circuit device is configured as follows: The authentication process is performed using the processor located outside the IC chip; In response to the embedded hardware security circuitry determining that a processor external to the IC chip is authorized to access the one or more second memories, secure access to the one or more second memories is provided to the processor external to the IC chip; and In response to the embedded hardware security circuitry determining that the processor outside the IC chip is not authorized to access the one or more second memories, the processor outside the IC chip is prevented from accessing the one or more second memories.

5. The IC chip of claim 1, wherein the interconnect circuitry is further coupled to the one or more second memories; The interconnect circuitry is further configured to grant the embedded hardware security circuitry access to the one or more second memories; and The embedded hardware security circuitry is configured to use the interconnect circuitry to provide secure access to the one or more second memories to the processor located outside the IC chip.

6. The IC chip according to claim 1, wherein the interconnect circuit device is a first interconnect circuit device; The IC chip further includes a second interconnect circuit device coupled to the embedded hardware security circuit device and the one or more second memories; and The embedded hardware security circuitry is configured to use the second interconnect circuitry to provide secure access to the one or more second memories to the processor outside the IC chip.

7. The IC chip of claim 1, wherein the interconnect circuitry is configured to prevent requests from the processor outside the IC chip to access the one or more second memories from directly proceeding to the one or more second memories.

8. The IC chip of claim 1, wherein the embedded hardware security circuitry is configured to provide secure access to the one or more second memories to the processor outside the IC chip at least by: i) authenticating the processor outside the IC chip, and ii) providing access to the one or more second memories to the processor outside the IC chip in response to authenticating the processor outside the IC chip.

9. The IC chip of claim 8, wherein the embedded hardware security circuitry is configured to further provide secure access to the one or more second memories to the processor outside the IC chip by: blocking access to the one or more second memories by the processor in response to failure to authenticate the processor outside the IC chip.

10. The IC chip of claim 1, wherein the embedded hardware security circuitry includes encryption / decryption circuitry, and wherein the embedded hardware security circuitry is configured to provide secure access to the one or more second memories to a processor external to the IC chip by at least one or both of the following: The encryption / decryption circuitry decrypts first information from the processor, corresponding to an access request received from the processor via the communication interface circuitry, to generate decrypted information, and transmits the decrypted information to the one or more second memories; and The encryption / decryption circuitry encrypts second information from the one or more second memories, corresponding to a response to an access request received from the processor via the communication interface circuitry, to generate encrypted information, and transmits the encrypted information to the processor via the communication interface circuitry.

11. The IC chip according to claim 1, wherein: The one or more second memories include a key memory configured to store security keys for encrypting data output by the IC chip and / or decrypting data received by the IC chip. The IC chip further includes an encryption / decryption circuitry configured to use a security key stored in the key memory to encrypt one or both of the data output by the IC chip and decrypt the data received by the IC chip; and The embedded hardware security circuitry is configured to provide the processor with secure access to the key memory to store a security key in the key memory.

12. The IC chip according to claim 1, further comprising: Multiple network interfaces are configured to be communicatively coupled to the ports of the network device; as well as A packet processor is configured to analyze the headers of packets received via the plurality of network interfaces to determine the network interface through which the packets are to be forwarded, the packet processor being coupled to the interconnect circuitry means. The interconnect circuitry is configured to selectively grant the packet processor insecure access to the one or more first memories in conjunction with determining whether the packet is to be read from and / or written to the one or more first memories via its forwarded network interface.

13. The IC chip according to claim 12, wherein: The one or more second memories include a forwarding database memory configured to store forwarding information used by the packet processor to determine the network interface through which the packet is to be forwarded; as well as The embedded hardware security circuitry is configured to provide the processor with secure access to the key memory to read forwarding information from the forwarding database memory and to securely transmit the forwarding information to the processor via the communication interface circuitry.

14. A method for accessing an integrated circuit (IC) chip of a network device, the method comprising: At the communication interface circuit device of the IC chip, a first memory access request for accessing the first memory of the IC chip is received from a processor outside the IC chip. The first memory stores information for use by the network device. The first request is forwarded to the first memory by the interconnect circuitry of the IC chip; The first memory serves the first memory access request via the communication interface circuit device; At the interconnect circuit device, in response to i) a request received at the communication interface circuit device and ii) a request to access the second memory of the IC chip, direct access to the second memory of the IC chip via the communication interface circuit device is blocked. The second memory is configured to store information for use by the network device and to be protected against unauthorized external access. At the communication interface circuit device of the IC chip, a second memory access request for accessing the second memory of the IC chip is received from the processor outside the IC chip; The interconnect circuit device of the IC chip forwards the second request to the embedded hardware security circuit device of the IC chip; The embedded hardware security circuitry selectively provides secure access to the second memory to serve the second memory access request; as well as The second memory serves access requests via the embedded hardware security circuitry and the communication interface circuitry.

15. The method for accessing the IC chip according to claim 14, further comprising: In conjunction with the request received from the processor to access the one or more first memories, non-secure first information is transmitted between the processor, which is located outside the IC chip, and the one or more first memories via the communication interface circuit device. Encrypted second information is transmitted between the processor (external to the IC chip) and the one or more second memories via the communication interface circuit device, in conjunction with the request received from the processor for access to the one or more second memories.

16. The method for accessing the IC chip according to claim 15, further comprising: In addition to the request for access to the one or more first memories received from the processor, non-secure first information is transmitted between the communication interface circuit device and the one or more first memories via the interconnect circuit device. as well as Encrypted second information is transmitted between the communication interface circuitry and the embedded hardware security circuitry via the interconnect circuitry, in conjunction with the request received from the processor for access to the one or more second memories.

17. The method for accessing the IC chip according to claim 14, wherein selectively providing secure access to the second memory comprises: The authentication process is performed by the embedded hardware security circuit device using the processor external to the IC chip; In response to the embedded hardware security circuitry determining that the processor outside the IC chip is authorized to access the one or more second memories, the embedded hardware security circuitry provides secure access to the one or more second memories to the processor outside the IC chip. as well as In response to the embedded hardware security circuitry determining that the processor outside the IC chip is not authorized to access the one or more second memories, the embedded hardware security circuitry prevents the processor outside the IC chip from accessing the one or more second memories.

18. The method for accessing the IC chip according to claim 14, further comprising: The interconnect circuitry device grants the embedded hardware security circuitry device access to the one or more second memories; and Providing secure access to the second memory to serve the second memory access request includes: the embedded hardware security circuitry device using the interconnect circuitry device to provide secure access to the one or more second memories to the processor outside the IC chip.

19. The method for accessing the IC chip according to claim 14, wherein: The interconnecting circuit device is a first interconnecting circuit device; and Providing secure access to the second memory to serve second memory access requests includes: the embedded hardware security circuitry device using a second interconnect circuitry device to provide secure access to the one or more second memories to the processor outside the IC chip, the second interconnect circuitry device being different from the first interconnect circuitry device.

20. The method for accessing the IC chip according to claim 14, wherein providing secure access to the second memory to serve the second memory access request comprises: Authenticate the processor external to the IC chip; as well as In response to authenticating the processor outside the IC chip, the embedded hardware security circuitry provides the processor outside the IC chip with access to the one or more second memories.

21. The method for accessing the IC chip according to claim 20, wherein providing secure access to the second memory to serve the second memory access request comprises: In response to the failure to authenticate the processor outside the IC chip, the embedded hardware security circuitry prevents the processor from accessing the one or more second memories.

22. The method for accessing the IC chip according to claim 14, wherein providing secure access to the second memory to serve the second memory access request comprises one or both of the following: i) The encryption / decryption circuitry of the embedded hardware security circuitry decrypts first information from the processor, corresponding to an access request received from the processor via the communication interface circuitry, to generate decrypted information, and transmits the decrypted information to the one or more second memories; and ii) The encryption / decryption circuitry encrypts second information from the one or more second memories, corresponding to a response to an access request received from the processor via the communication interface circuitry, to generate encrypted information, and transmits the encrypted information to the processor via the communication interface circuitry.

23. The method for accessing the IC chip according to claim 14, wherein the one or more second memories include a key memory configured to store a security key, and wherein the method further comprises: The encryption circuit device using the IC chip uses a security key stored in the key memory to encrypt the information output by the IC chip; Providing secure access to the second memory to serve the second memory access request includes: the embedded hardware security circuitry providing the processor with secure access to the key memory to store a security key in the key memory.

24. The method for accessing the IC chip according to claim 14, wherein the one or more second memories include a key memory configured to store a security key, and wherein the method further comprises: The decryption circuit device of the IC chip uses a security key stored in the key memory to decrypt the information received by the IC chip; Providing secure access to the second memory to serve the second memory access request includes: the embedded hardware security circuitry providing the processor with secure access to the key memory to store a security key in the key memory.

25. The method for accessing the IC chip according to claim 14, further comprising: Packets are received via multiple network interfaces of the IC chip; as well as The packet processor analyzes the headers of the packets received via the plurality of network interfaces to determine the network interface through which the packet is forwarded. as well as The packet processor forwards the packets to the network interface determined by the packet processor for transmission through the network interface.

26. The method for accessing the IC chip according to claim 25, wherein: The one or more second memories include a forwarding database memory configured to store forwarding information used by the packet processor to determine the network interface through which the packet is to be forwarded; and Providing secure access to the second memory to serve the second memory access request includes: the embedded hardware security circuitry providing the processor with secure access to the key memory to read forwarding information from the forwarding database memory.

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