Address processing apparatus, method, chip and electronic device

Abstract

The application relates to an address processing device, method, chip and electronic equipment. In the address processing device, a memory control module is used for detecting whether there is a free address in a memory module when the address processing device works in a memory control mode and a FIFO output module is not full, and if there is, the free address is written into the FIFO output module; a bitmap control module is used for detecting whether there is a free address in a bitmap register when the address processing device works in a bitmap control mode and the FIFO output module is not full, and if there is, the free address is written into the FIFO output module; and the FIFO output module is used for receiving an address allocation request and outputting the free address to a sending end of the address allocation request when the FIFO output module is not empty. The address allocation delay is greatly reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an address processing device, method, chip, and electronic device. Background Technology

[0002] The allocation and reclamation of free addresses are widely used in ASIC design. For example, a new command can be allocated an unused address to avoid conflicts with already used addresses. Currently, address allocation and reclamation are implemented using bitmap-type registers. Each bit in the register corresponds to an address. When an address is allocated, the corresponding bit is set to 0, and when an address is reclaimed, the corresponding bit is set to 1.

[0003] For register-type bitmaps, the bit width increases with the address, resulting in greater latency in selecting free bits from the bitmap. This affects critical timing paths and backend layout and routing, especially for addresses greater than 8K. To support 8K addresses, current technology requires two 4K bitmaps. Since a 4K bitmap is implemented in 2D, an 8K bitmap would be equivalent to allocating addresses from a 3D perspective, leading to even greater latency. Summary of the Invention

[0004] Therefore, it is necessary to provide an address processing apparatus, method, chip, and electronic device that can reduce address allocation latency in response to the above-mentioned technical problems.

[0005] In a first aspect, this application provides an address processing device, including: a bitmap control module, a bitmap register, a memory control module, a memory module, and a FIFO output module;

[0006] The Memory control module is used to detect whether there is a free address in the Memory module when the address processing device is working in Memory control mode and the FIFO output module is not full. If there is a free address, the free address is written into the FIFO output module.

[0007] The bitmap control module is used to detect whether there is a free address in the bitmap register when the address processing device is working in bitmap control mode and the FIFO output module is not full. If there is a free address, the free address is written into the FIFO output module.

[0008] The FIFO output module is used to receive address allocation requests, and when the FIFO output module is not empty, it outputs a free address to the address allocation request sender.

[0009] Secondly, this application also provides an address processing method applied to an address processing apparatus, the method comprising:

[0010] When the address processing device is operating in Memory control mode and the FIFO output module is not full, it detects whether there is a free address in the Memory module. If there is, it writes the free address into the FIFO output module.

[0011] When the address processing device is operating in bitmap control mode and the FIFO output module is not full, it checks whether there is a free address in the bitmap register. If there is, the free address is written into the FIFO output module.

[0012] Upon receiving an address allocation request, if the FIFO output module is not empty, output a free address to the address allocation request sender.

[0013] Thirdly, this application also provides a chip including the aforementioned address processing device.

[0014] Fourthly, this application also provides an electronic device, including the address processing device or the chip described above.

[0015] The aforementioned address processing apparatus, method, chip, and electronic device include: an address processing apparatus comprising a bitmap control module, a bitmap register, a memory control module, a memory module, and a FIFO output module. This address processing apparatus supports both memory control mode and bitmap control mode. The memory control module, when the address processing apparatus is operating in memory control mode and the FIFO output module is not full, detects whether a free address exists in the memory module. If a free address exists, it writes the free address into the FIFO output module, thus prefetching a free address from the memory module to the FIFO output module. The bitmap control module, when the address processing apparatus is operating in bitmap control mode and the FIFO output module is not full, detects whether a free address exists in the bitmap register. If a free address exists, it writes the free address into the FIFO output module, thus prefetching a free address from the bitmap register to the FIFO output module. The FIFO output module receives address allocation requests and, when the FIFO output module is not empty, outputs a free address to the address allocation request sender. The address processing device provided in this application supports both bitmap control mode and memory control mode. It can be flexibly configured to operate in an appropriate mode based on the bit width of the bitmap information. For example, when the bit width of the bitmap information is small, the address processing device can be configured to operate in bitmap control mode; when the bit width of the bitmap information is large, it can be configured to operate in memory control mode. This achieves compatibility between bitmap control mode and memory control mode, solving the latency problem caused by using bitmap control mode even when the bit width of the bitmap information is large in existing solutions. Furthermore, both bitmap control mode and memory control mode can prefetch free addresses into the FIFO output module, achieving the purpose of allocating free addresses from the FIFO output module. Compared with the traditional method of allocating free addresses based on bitmap information, this greatly reduces address allocation latency, allowing for immediate recycling and allocation regardless of the scale. Moreover, the solution in this application supports memory control mode, which can reduce the consumption of register resources and avoid the latency of scheduling free addresses from registers when there are many addresses. This solves the problem that traditional methods can only use registers as the storage medium for bitmap information. Different storage media can be used according to different scenarios, saving resources and facilitating backend implementation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the address processing device in one embodiment. Figure 1 ;

[0018] Figure 2 This is a schematic diagram of the address allocation method in one embodiment. Figure 1 ;

[0019] Figure 3 This is a schematic diagram of the address allocation method in one embodiment. Figure 2 ;

[0020] Figure 4 This is a schematic diagram of the address processing device in one embodiment. Figure 2 ;

[0021] Figure 5 This is a schematic diagram of the address processing device in one embodiment. Figure 3 ;

[0022] Figure 6 This is a schematic diagram of bitmap information and FIFO output module in one embodiment;

[0023] Figure 7 This is a schematic diagram of address mapping in one embodiment;

[0024] Figure 8 This is a schematic diagram of the address allocation process in one embodiment;

[0025] Figure 9 An example of address reclamation in one embodiment Figure 1 ;

[0026] Figure 10 An example of address reclamation in one embodiment Figure 2 ;

[0027] Figure 11 This is a schematic diagram of read latency in one embodiment;

[0028] Figure 12 This is a flowchart illustrating an address processing method in one embodiment. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0030] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0031] In some embodiments, see Figure 1 As shown, an address processing device is provided, comprising: a bitmap control module, a bitmap register, and a recycling control module. Based on this address processing device, the following can be used: Figure 2 or Figure 3 Address allocation is performed according to the indicated allocation method.

[0032] Figure 2 The method involves selecting allocatable addresses for each set through an arbiter within each set, then selecting an available set through another arbiter (by ORing the valid bits of each set, it can be determined that there are allocatable addresses in the current set), and then setting the corresponding bits to 0. When reclaiming addresses, the location of the corresponding address is found and set to 1. This method is an AND execution, and the output address is a combined output, resulting in poor timing. When the number of bits in the bitmap information increases to more than 512, it uses more scheduler and register resources.

[0033] Figure 3 The method involves: first, an arbiter selects a set of available addresses for scheduling (by ORing the valid bits of each set, it can be determined whether there are allocatable addresses in the current set); then, a scheduler schedules from the selected set to obtain allocatable addresses, and sets the corresponding bits to 0; when reclaiming addresses, the corresponding address is located and set to 1. This method is serial, and when the number of bits in the bitmap information increases to 512 or more, timing convergence is difficult. Step 1 requires pacing, increasing latency, and the final output address is a combined output, resulting in poor timing. Figure 2 It reduces scheduler time and uses more register resources.

[0034] Neither of the above two methods can support the use of SRAM to implement bitmap information, because the data in SRAM is unknown before it is read out. It is impossible to determine whether there is an allocatable address for a set by taking the OR of the valid bits of each set in SRAM and then schedule it.

[0035] In some embodiments, see Figure 4 As shown, an address processing device is provided, which includes: a bitmap control module, a bitmap register, a memory control module, a memory module, and a FIFO output module.

[0036] The Memory control module is used to detect whether there is a free address in the Memory module when the address processing device is working in Memory control mode and the FIFO output module is not full. If there is a free address, it is written into the FIFO output module.

[0037] The bitmap control module is used to detect whether there is a free address in the bitmap register when the address processing device is working in bitmap control mode and the FIFO output module is not full. If there is a free address, the free address is written into the FIFO output module.

[0038] The FIFO output module is used to receive address allocation requests. When the FIFO output module is not empty, it outputs a free address to the address allocation request sender.

[0039] The allocation and reclamation of free addresses are widely used in ASIC design. For example, a new command can be allocated an unused address, i.e., a free address, so as not to conflict with already used addresses.

[0040] Optionally, address allocation requests can come from the software-side / host-side Central Processing Unit (CPU).

[0041] Optionally, the address processing device can operate in either Memory control mode or bitmap control mode. The specific mode can be configured in advance according to actual needs.

[0042] Optionally, the bitmap information indicates whether the address is free.

[0043] Optionally, in Memory control mode, bitmap information is stored in the Memory module. In bitmap control mode, bitmap information is stored in the bitmap register.

[0044] Optionally, the bitmap information includes m groups, each group including n bits; each bit corresponds to an address, and when any bit is valued at a first preset value, it indicates that the corresponding address is occupied, and when any bit is valued at a second preset value, it indicates that the corresponding address is idle.

[0045] Optionally, the address processing device can be flexibly configured to operate in an adaptive mode based on the bit width of the bitmap information. For example, when the bit width of the bitmap information is less than or equal to 8K, the address processing device is configured to operate in bitmap control mode, and when the bit width of the bitmap information is greater than 8K, the address processing device is configured to operate in memory control mode.

[0046] For example, the first preset value can be 0, and the second preset value can be 1.

[0047] In the address processing device operating in Memory control mode, the Memory control module can be used to detect the status of the FIFO output module in real time. For example, it can detect the status of the FIFO output module at fixed time intervals, such as 1 second, 2 seconds, etc., which are not limited in this embodiment. If the Memory control module detects that the FIFO output module is not full, it can detect whether there is a free address in the Memory module. If so, it writes the free address into the FIFO output module, thereby prefetching a free address from the Memory module into the FIFO output module. If the Memory control module detects that the FIFO output module is full, it does not perform any processing.

[0048] In the bitmap control mode, the address processing device can detect the status of the FIFO output module in real time. For example, it can detect the status of the FIFO output module at fixed time intervals, such as 1 second or 2 seconds, which is not limited in this embodiment. If the bitmap control module detects that the FIFO output module is not full, it can check whether there is a free address in the bitmap register. If so, it writes the free address into the FIFO output module, thereby prefetching a free address from the bitmap register into the FIFO output module. If the bitmap control module detects that the FIFO output module is full, it does not perform any processing.

[0049] The FIFO output module receives address allocation requests. When the FIFO output module is not empty, it directly outputs a free address to the address allocation request sender. When the FIFO output module is empty, if the address processing device is operating in Memory control mode, it obtains a free address from the Memory module and sends it to the address allocation request sender; if the address processing device is operating in bitmap control mode, it obtains a free address from the bitmap register and sends it to the address allocation request sender.

[0050] Optionally, the FIFO output module can be defined at different depths depending on whether it is operating in Memory control mode or bitmap control mode, to absorb scheduling latency and read latency from the memory module.

[0051] In the above embodiments, the address processing device includes a bitmap control module, a bitmap register, a memory control module, a memory module, and a FIFO output module. This address processing device supports both memory control mode and bitmap control mode. The memory control module, when the address processing device is operating in memory control mode and the FIFO output module is not full, detects whether there is a free address in the memory module. If so, it writes the free address into the FIFO output module, thus prefetching a free address from the memory module to the FIFO output module. The bitmap control module, when the address processing device is operating in bitmap control mode and the FIFO output module is not full, detects whether there is a free address in the bitmap register. If so, it writes the free address into the FIFO output module, thus prefetching a free address from the bitmap register to the FIFO output module. The FIFO output module receives address allocation requests and, when the FIFO output module is not empty, outputs a free address to the address allocation request sender. The address processing device provided in this application supports both bitmap control mode and memory control mode. It can be flexibly configured to operate in an appropriate mode based on the bit width of the bitmap information. For example, when the bit width of the bitmap information is small, the address processing device can be configured to operate in bitmap control mode; when the bit width of the bitmap information is large, it can be configured to operate in memory control mode. This achieves compatibility between bitmap control mode and memory control mode, solving the latency problem caused by using bitmap control mode even when the bit width of the bitmap information is large in existing solutions. Furthermore, both bitmap control mode and memory control mode can prefetch free addresses into the FIFO output module, achieving the purpose of allocating free addresses from the FIFO output module. Compared with the traditional method of allocating free addresses based on bitmap information, this greatly reduces address allocation latency, allowing for immediate recycling and allocation regardless of the scale. Moreover, the solution in this application supports memory control mode, which can reduce the consumption of register resources and avoid the latency of scheduling free addresses from registers when there are many addresses. This solves the problem that traditional methods can only use registers as the storage medium for bitmap information. Different storage media can be used according to different scenarios, saving resources and facilitating backend implementation.

[0052] In some embodiments, see Figure 5As shown, a recycling control module is added to the address processing device provided in the above embodiment. That is, the address processing device includes: a bitmap control module, a bitmap register, a memory control module, a memory module, a FIFO output module, and a recycling control module. The recycling control module is used for:

[0053] Upon receiving an address reclamation request, determine whether the FIFO output module is not full. If so, write the address corresponding to the reclamation request into the FIFO output module. If the FIFO output module is full and the address processing device is operating in bitmap control mode, the bitmap control module controls the writing of the address corresponding to the reclamation request into the bitmap register. If the FIFO output module is full and the address processing device is operating in Memory control mode, the Memory control module controls the writing of the address corresponding to the reclamation request into the Memory module.

[0054] Optionally, address reclamation requests can originate from the software-side / host-side Central Processing Unit (CPU).

[0055] Optionally, after receiving an address reclamation request, the reclamation control module determines whether the FIFO output module is not full. If it is not full, the address corresponding to the reclamation request is directly written into the FIFO output module. If the FIFO output module is full and the address processing device is operating in bitmap control mode, the address corresponding to the reclamation request is written into the bitmap register through the bitmap control module. If the FIFO output module is full and the address processing device is operating in memory control mode, the address corresponding to the reclamation request is written into the memory module through the memory control module.

[0056] As described above, bitmap information indicates whether an address is free. Bitmap information can include m groups, each group containing n bits; each bit corresponds to an address. A value of any bit indicating the address is occupied signifies a first preset value, while a value of any bit indicating the address is free signifies a second preset value. In Memory control mode, bitmap information is stored in the Memory module. In bitmap control mode, bitmap information is stored in the bitmap register.

[0057] Optionally, after receiving an address reclamation request, the reclamation control module determines whether the FIFO output module is not in a full state. If the FIFO output module is in a full state and the address processing device is working in bitmap control mode, the bitmap control module determines the bit of the address corresponding to the reclamation request and updates the value of that bit in the bitmap information stored in the bitmap register to the second preset value, thereby completing the address reclamation.

[0058] Optionally, after receiving an address reclamation request, the reclamation control module determines whether the FIFO output module is not full. If the FIFO output module is full and the address processing device is operating in Memory control mode, the Memory control module determines the bit of the address corresponding to the reclamation request and updates the value of that bit in the bitmap information stored in the Memory module to the second preset value, thereby completing the address reclamation.

[0059] In the above embodiments, the address processing device further includes a recycling control module, which is used to: receive an address recycling request and determine whether the FIFO output module is not full; if so, write the address corresponding to the recycling request into the FIFO output module; if the FIFO output module is full and the address processing device is operating in bitmap control mode, the bitmap control module controls the writing of the address corresponding to the recycling request into the bitmap register; if the FIFO output module is full and the address processing device is operating in Memory control mode, the Memory control module controls the writing of the address corresponding to the recycling request into the Memory module. When the FIFO output module is not full, the address corresponding to the recycling request is preferentially written into the FIFO output module, and the written address can be immediately reallocated, thereby reducing the delay in scheduling free addresses from the bitmap register or the Memory module. For example, if the address processing device is operating in bitmap control mode, and neither the bitmap register nor the FIFO output module has any addresses available for allocation (i.e., no free addresses), and an address is reclaimed, rewriting it into the bitmap register and then allocating it to an external module would require at least three clock cycles (one cycle for writing to the bitmap register, one cycle for scheduling, and one cycle for writing to the FIFO output module). However, if the address is written directly into the FIFO output module, it can be allocated in the next clock cycle, requiring only one cycle. This significantly reduces the latency of address allocation.

[0060] In some embodiments, when the address processing device operates in Memory control mode, the Memory control module reads bitmap information from the Memory module. The bitmap information includes m groups, each group including n bits. Each bit corresponds to an address. When any bit has a value of a first preset value, it indicates that the corresponding address is occupied. When any bit has a value of a second preset value, it indicates that the corresponding address is idle. The Memory control module determines at least one group whose number of bits corresponding to the address being idle is greater than zero. The group identifier of at least one group is input to the first-level scheduling unit, which schedules out the target group identifier from the received group identifiers. The bit information of the group corresponding to the target group identifier is input to the second-level scheduling unit, which schedules out the target bit at the second preset value based on the bit information. The address corresponding to the target bit is written into the FIFO output module.

[0061] In this embodiment, when the address processing device operates in Memory control mode, the bitmap information is stored in the Memory module. The Memory control module monitors the status of the FIFO output module in real time. When the FIFO output module is not full, it reads the bitmap information from the Memory module. The bitmap information includes m groups, each group containing n bits. Each bit corresponds to an address. A value of 0 for any bit indicates that the corresponding address is occupied, and a value of 1 for any bit indicates that the corresponding address is idle. The settings of 0 and 1 are only one example and can be other values, which are not limited in this embodiment.

[0062] Optionally, the traditional bitmap information containing only one group can be expanded to m groups using a group-associative approach, reducing the number of bits in each group. Simultaneously, a first-in-first-out (FIFO) output module is used, pre-loaded with free addresses or pre-fetched free addresses based on the bitmap information. This ensures good timing even for 512*512 bitmap information.

[0063] For example, see Figure 6As shown, the bitmap information consists of two groups, each identified as set0 and set1. Each group contains 4 bits. The bits in each group are arranged in rows, and the two groups are arranged in columns. From right to left, the first column is identified by way0, the second by way1, the third by way2, and the fourth by way3. The bitmap is output through a FIFO output module, which stores two free addresses pre-fetched based on the bitmap information, named addr0 and addr1. Each bit corresponds to a specific address according to {set, way}. Therefore, the decimal address corresponding to each bit in the bitmap information and the decimal address stored in the FIFO output module are as follows: Figure 7 As shown. For example, {set=0, way=3} is represented in binary as 00_11, which is equal to decimal 3; {set=1, way=0} is represented in binary as 01_00, which is equal to decimal 4.

[0064] Optionally, the Memory control module can determine at least one group where the number of bits in the corresponding address that are in an idle state is greater than zero; input the group identifier of at least one group into the first-level scheduling unit, and the first-level scheduling unit schedules out the target group identifier from the received group identifier.

[0065] Optionally, the primary scheduling unit can be RR scheduling. The scheduling result of the primary scheduling unit can be in one-hot format, and the target group identifier can be determined based on the one-hot format scheduling result.

[0066] Optionally, the bit information in the group corresponding to the target group identifier can be obtained. This bit information can also be in one-hot format. The bit information is input to the secondary scheduling unit. The secondary scheduling unit can be RR scheduling or scheduling in the manner of finding the first second preset value (1). The scheduling result of the secondary scheduling unit can be in one-hot format. The target bit can be determined according to the scheduling result in one-hot format, the address corresponding to the target bit is obtained, and the address is written into the FIFO output module.

[0067] Optionally, each group corresponds to a second preset value counting unit, which is used to count the number of bits in the corresponding group that are in the second preset value (i.e., bits whose corresponding addresses are in an idle state). It can be determined whether the count value of the second preset value counting unit corresponding to each group is greater than zero, thereby determining at least one group in which the number of bits in the corresponding address that are in an idle state is greater than zero.

[0068] Optionally, after writing the address corresponding to the target bit into the FIFO output module, the value of the target bit can be updated to the first preset value. The count value of the second preset value counting unit corresponding to the target group identifier is decremented by one.

[0069] Optionally, the second preset value counting unit can be a counter used to count the number of second preset values ​​in the corresponding group. When the value of any digit in the group changes from the first preset value to the second preset value, or from the second preset value to the first preset value, the value of the counter will be incremented or decremented accordingly.

[0070] The above method uses a second preset value counting unit to count the number of allocable addresses in each set, instead of directly performing a bitwise OR operation to determine if there are available addresses. Therefore, when using the Memory module, even if there is a read delay, the available resources in each set can be accurately determined. This solves the pain point that the traditional method can only use registers as storage media, and different storage media can be used according to different scenarios, saving resources.

[0071] For example, with Figure 8 For example, the bitmap information includes two groups, each identified as set0 and set1. Each group contains 4 bits. The bits within each group are arranged in rows. The two groups are arranged in columns. From right to left, the first column is identified by way0, the second by way1, the third by way2, and the fourth by way3. The values ​​of the bits within each group are as follows: Figure 8 As shown. The first preset value is 0, and the second preset value is 1. The second preset value counting unit can be identified using cnt. The count value of the second preset value counting unit cnt0 corresponding to set0 is 2, and the count value of the second preset value counting unit cnt1 corresponding to set1 is 4. The FIFO output module stores two addresses, addr0 and addr1. After receiving an address allocation request from the outside, a free address addr0 is allocated from the FIFO output module, corresponding to... Figure 8 In step 1, the FIFO output module only has addr1 remaining. If the FIFO output module is detected to be less than full, free addresses are scheduled to be filled into the FIFO output module. Figure 8 In step 2, specifically, since the count values ​​of cnt0 and cnt1 are both greater than 0, both set0 and set1 can be input into the first-level scheduling unit to participate in RR scheduling. The RR scheduling result is in one-hot format. Assuming the scheduling result is 01, 01 indicates that set0 was scheduled. See [link to relevant documentation]. Figure 8The bit information in group set0 can be represented as 4'b1100. 4'b1100 can be input to the secondary scheduling unit. The secondary scheduling unit can perform RR scheduling or scheduling by finding the first 1. Assuming that the scheduling result output by the secondary scheduling unit is 4'b0100, this scheduling result indicates that the bit of way2 has been selected. Therefore, the final scheduled address is the address corresponding to {set=0, way=2}, which is decimal address 2. Finally, addr2 is stored in the FIFO output module, and the count value of the second preset value counting unit cnt0 corresponding to set0 is kept to 1, thereby realizing address prefetching.

[0072] For example, with Figure 9 For example, similarly, the bitmap information includes two groups, each identified as set0 and set1. Each group contains 4 bits. The bits within each group are arranged in rows. The two groups are arranged in columns. From right to left, the first column is identified by way0, the second by way1, the third by way2, and the fourth by way3. The current value of the bits in each group is as follows: Figure 9 As shown. The first preset value is 0, and the second preset value is 1. The second preset value counting unit can be identified using cnt. The count value of the second preset value counting unit cnt0 corresponding to set0 is 1, and the count value of the second preset value counting unit cnt1 corresponding to set1 is 4. The FIFO output module stores two addresses, addr1 and addr2. After receiving an address reclamation request, assuming that the reclamation address it carries is 0, based on the mapping method described in the previous embodiment, this reclamation address corresponds to the bit {set=0, way=0}. Since the FIFO output module is currently full, the bit {set=0, way=0} is set to 1, thus completing the address reclamation.

[0073] For example, with Figure 10 For example, similarly, the bitmap information includes two groups, each identified as set0 and set1. Each group contains 4 bits. The bits within each group are arranged in rows. The two groups are arranged in columns. From right to left, the first column is identified by way0, the second by way1, the third by way2, and the fourth by way3. The current value of the bits in each group is as follows: Figure 10As shown. The first preset value is 0, and the second preset value is 1. The second preset value counting unit can be identified using cnt. The count value of the second preset value counting unit cnt0 corresponding to set0 is 1, and the count value of the second preset value counting unit cnt1 corresponding to set1 is 4. In this example, the FIFO output module stores the address addr1. After receiving an address reclamation request, assuming that the reclamation address it carries is 0, since the FIFO output module is currently not full, the reclamation address 0 is directly stored in the FIFO output module.

[0074] The above embodiments describe a scheme for prefetching free addresses from the Memory module to the FIFO output module when the address processing device is operating in Memory control mode. This prefetching setting allows the address to be allocated directly from the FIFO output module after receiving an address allocation request, reducing the address allocation latency.

[0075] In some embodiments, when the address processing device is operating in Memory control mode, the Memory control module sends a read request for bitmap information to the Memory module. After receiving the bitmap information returned by the Memory module, it determines whether a write request for any bit in the bitmap information was sent to the Memory module between sending the read request and receiving the bitmap information. If so, the value of any bit in the bitmap information is replaced with the value corresponding to the write request. This achieves the acquisition of bitmap information.

[0076] In the case where the address processing device is operating in Memory control mode, the bitmap information is stored in the Memory module. The processing is somewhat different. After a read request for the bitmap information is issued, the read data cannot be read immediately because there may be subsequent write requests at the same address. This will result in the read data not being the latest value. Therefore, the data of the latest write request at the same address needs to be bypassed for the read request.

[0077] Optionally, the Memory control module can send a read request for bitmap information to the Memory module. After receiving the bitmap information returned by the Memory module, it can determine whether a write request for any bit in the bitmap information was sent to the Memory module during the process from sending the read request to receiving the bitmap information. If so, the value of that bit in the received bitmap information is replaced with the value corresponding to the write request.

[0078] For example, see Figure 11As shown, a request to read memory address 0 is issued at time P0. Assuming a read latency of 3 clock cycles, the data read from memory will only be effective at time P3. If address 0 is subsequently written to three more times, specifically at times P1, P2, and P3 during the read process, then the data written at time P3 (i.e., the latest data written by command (cmd2)) needs to bypass the aforementioned read request to obtain the latest value of address 0.

[0079] In the above embodiments, when the bitmap information is stored in the Memory module, the bypass scheme ensures that the read data is the latest value, thus guaranteeing the accuracy of the read bitmap information.

[0080] In some embodiments, when the address processing device operates in bitmap control mode, the bitmap control module reads bitmap information from the bitmap register. The bitmap information includes m groups, each group including n bits; each bit corresponds to an address, and when any bit has a value of a first preset value, it indicates that the corresponding address is occupied, and when any bit has a value of a second preset value, it indicates that the corresponding address is idle; the bitmap control module determines at least one group whose number of second preset values ​​is greater than zero; the group identifier of at least one group is input to the first-level scheduling unit, which schedules out the target group identifier from the received group identifiers; the bit information of the group corresponding to the target group identifier is input to the second-level scheduling unit, which schedules out the target bit at the second preset value based on the bit information; and the address corresponding to the target bit is written into the FIFO output module.

[0081] In this embodiment, when the address processing device operates in bitmap control mode, the bitmap information is stored in the bitmap register. The bitmap control module monitors the status of the FIFO output module in real time. When the FIFO output module is not full, it reads the bitmap information from the bitmap register. The bitmap information includes m groups, each group containing n bits. Each bit corresponds to an address. A value of 0 for any bit indicates that the corresponding address is occupied, and a value of 1 for any bit indicates that the corresponding address is idle. The settings of 0 and 1 are only one example and can be other values, which are not limited in this embodiment.

[0082] Optionally, the bitmap control module can determine at least one group whose number of second preset values ​​is greater than zero; input the group identifier of at least one group into the first-level scheduling unit, and the first-level scheduling unit schedules out the target group identifier from the received group identifiers.

[0083] Optionally, the primary scheduling unit can be RR scheduling. The scheduling result of the primary scheduling unit can be in one-hot format, and the target group identifier can be determined based on the one-hot format scheduling result.

[0084] Optionally, the bit information in the group corresponding to the target group identifier can be obtained. This bit information can also be in one-hot format. The bit information is input to the secondary scheduling unit. The secondary scheduling unit can be RR scheduling or scheduling in the manner of finding the first second preset value (1). The scheduling result of the secondary scheduling unit can be in one-hot format. The target bit can be determined according to the scheduling result in one-hot format, the address corresponding to the target bit is obtained, and the address is written into the FIFO output module.

[0085] Optionally, each group corresponds to a second preset value counting unit, which is used to count the number of bits in the corresponding group that are in the second preset value (i.e., bits whose corresponding addresses are in an idle state). It can be determined whether the count value of the second preset value counting unit corresponding to each group is greater than zero, thereby determining at least one group in which the number of bits in the corresponding address that are in an idle state is greater than zero.

[0086] Optionally, after writing the address corresponding to the target bit into the FIFO output module, the value of the target bit can be updated to the first preset value. The count value of the second preset value counting unit corresponding to the target group identifier is decremented by one.

[0087] Optionally, the second preset value counting unit can be a counter used to count the number of second preset values ​​in the corresponding group. When the value of any digit in the group changes from the first preset value to the second preset value, or from the second preset value to the first preset value, the value of the counter will be incremented or decremented accordingly.

[0088] The scheme of prefetching free addresses from the bitmap register to the FIFO output module is similar to the scheme of prefetching free addresses from the Memory module to the FIFO output module in the previous embodiment. For details, please refer to the previous embodiment, which will not be repeated here.

[0089] The above embodiments describe a scheme for prefetching free addresses from the bitmap register to the FIFO output module when the address processing device is operating in bitmap control mode. This prefetching setting allows the address to be allocated directly from the FIFO output module after receiving an address allocation request, reducing the address allocation latency.

[0090] In some embodiments, an address processing method is provided, which can be applied to an address processing apparatus, see [link to relevant documentation]. Figure 12 As shown, the method includes:

[0091] S1201. When the address processing device is operating in Memory control mode and the FIFO output module is not full, detect whether there is a free address in the Memory module. If there is, write the free address into the FIFO output module.

[0092] S1202. When the address processing device is operating in bitmap control mode and the FIFO output module is not full, check whether there is a free address in the bitmap register. If there is, write the free address into the FIFO output module.

[0093] S1203: Receive address allocation request, and output free address to address allocation request sender if FIFO output module is not empty.

[0094] The specific implementation process of each of the above steps can be found in the aforementioned embodiments, and will not be repeated here.

[0095] In some embodiments, the address processing method described above further includes:

[0096] Receive address reclamation requests and determine whether the FIFO output module is not in a full state;

[0097] If so, the address corresponding to the recycling request is written into the FIFO output module;

[0098] If the FIFO output module is full and the address processing device is operating in bitmap control mode, the address corresponding to the recycling request is written into the bitmap register.

[0099] If the FIFO output module is full and the address processing device is operating in Memory control mode, the address corresponding to the recycling request will be written into the Memory module.

[0100] For the specific implementation process, please refer to the aforementioned embodiments, which will not be repeated here.

[0101] In some embodiments, the address processing device operates in Memory control mode; detecting whether a free address exists in the Memory module, and if so, writing the free address into the FIFO output module, includes:

[0102] Read bitmap information from the Memory module. The bitmap information includes m groups, each group includes n bits. Each bit corresponds to an address. When any bit is valued at the first preset value, it indicates that the corresponding address is occupied. When any bit is valued at the second preset value, it indicates that the corresponding address is idle.

[0103] Identify at least one group where the number of bits in the corresponding address that are in an idle state is greater than zero; input the group identifier of at least one group into the first-level scheduling unit, which then schedules out the target group identifier from the received group identifiers; input the bit information of the group corresponding to the target group identifier into the second-level scheduling unit, which then schedules out the target bit at the second preset value based on the bit information; and write the address corresponding to the target bit into the FIFO output module.

[0104] For the specific implementation process, please refer to the aforementioned embodiments, which will not be repeated here.

[0105] In some embodiments, reading bitmap information from the Memory module includes:

[0106] Send a read request for bitmap information to the Memory module. After receiving the bitmap information returned by the Memory module, determine whether a write request for any bit in the bitmap information was sent to the Memory module during the period from sending the read request to receiving the bitmap information. If so, replace the value of any bit in the bitmap information with the value corresponding to the write request.

[0107] For the specific implementation process, please refer to the aforementioned embodiments, which will not be repeated here.

[0108] In some embodiments, the address processing device operates in bitmap control mode; detecting whether a free address exists in the bitmap register, and if so, writing the free address into the FIFO output module, includes:

[0109] Read bitmap information from the bitmap register. The bitmap information includes m groups, and each group includes n bits. Each bit corresponds to an address. When the value of any bit is the first preset value, it indicates that the corresponding address is occupied. When the value of any bit is the second preset value, it indicates that the corresponding address is idle.

[0110] Identify at least one group where the number of bits in the corresponding address that are in an idle state is greater than zero; input the group identifier of at least one group into the first-level scheduling unit, which then schedules out the target group identifier from the received group identifiers; input the bit information of the group corresponding to the target group identifier into the second-level scheduling unit, which then schedules out the target bit at the second preset value based on the bit information; and write the address corresponding to the target bit into the FIFO output module.

[0111] For the specific implementation process, please refer to the aforementioned embodiments, which will not be repeated here.

[0112] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0113] In some embodiments, a chip is provided, including the address processing apparatus provided in the foregoing embodiments.

[0114] In some embodiments, an electronic device is provided, including the address processing device or the chip provided in the foregoing embodiments.

[0115] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0117] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An address processing device, characterized in that, include: Bitmap control module, bitmap register, memory control module, memory module, and FIFO output module; The Memory control module is used to detect whether there is a free address in the Memory module when the address processing device is working in Memory control mode and the FIFO output module is not full. If there is a free address, the free address is written into the FIFO output module. The bitmap control module is used to detect whether there is a free address in the bitmap register when the address processing device is working in bitmap control mode and the FIFO output module is not full. If there is a free address, the free address is written into the FIFO output module. The FIFO output module is used to receive address allocation requests, and when the FIFO output module is not empty, it outputs a free address to the address allocation request sender.

2. The address processing apparatus according to claim 1, characterized in that, The device further includes a recycling control module, which is used for: Receive an address reclamation request and determine whether the FIFO output module is not in a full state; If so, the address corresponding to the recycling request is written into the FIFO output module; If the FIFO output module is full and the address processing device is operating in bitmap control mode, the bitmap control module controls the writing of the address corresponding to the recycling request into the bitmap register. If the FIFO output module is full and the address processing device is operating in Memory control mode, then the Memory control module controls the writing of the address corresponding to the recycling request into the Memory module.

3. The address processing apparatus according to claim 1, characterized in that, When the address processing device is operating in Memory control mode, the Memory control module reads bitmap information from the Memory module. The bitmap information includes m groups, each group including n bits. Each bit corresponds to an address. When the value of any bit is a first preset value, it indicates that the corresponding address is occupied. When the value of any bit is a second preset value, it indicates that the corresponding address is idle. The memory control module determines at least one group where the number of bits in the corresponding address that are in an idle state is greater than zero; the group identifier of the at least one group is input into the first-level scheduling unit, and the first-level scheduling unit schedules out the target group identifier from the received group identifier; The bit information of the group corresponding to the target group identifier is input to the secondary scheduling unit, which then schedules out the target bit at the second preset value based on the bit information; the address corresponding to the target bit is written into the FIFO output module.

4. The address processing apparatus according to claim 3, characterized in that, The Memory control module sends a read request for bitmap information to the Memory module. After receiving the bitmap information returned by the Memory module, it determines whether a write request for any bit in the bitmap information was sent to the Memory module during the process from sending the read request to receiving the bitmap information. If so, the value of any bit in the bitmap information is replaced with the value corresponding to the write request.

5. The address processing apparatus according to claim 1, characterized in that, When the address processing device is operating in bitmap control mode, the bitmap control module reads bitmap information from the bitmap register. The bitmap information includes m groups, each group including n bits. Each bit corresponds to an address. When the value of any bit is a first preset value, it indicates that the corresponding address is occupied. When the value of any bit is a second preset value, it indicates that the corresponding address is idle. The bitmap control module determines at least one group where the number of bits in the corresponding address that are in an idle state is greater than zero; the group identifier of the at least one group is input into the first-level scheduling unit, and the first-level scheduling unit schedules out the target group identifier from the received group identifier; The bit information of the group corresponding to the target group identifier is input to the secondary scheduling unit, which then schedules out the target bit at the second preset value based on the bit information; the address corresponding to the target bit is written into the FIFO output module.

6. An address processing method, characterized in that, Applied to an address processing device, the method includes: When the address processing device is operating in Memory control mode and the FIFO output module is not full, it detects whether there is a free address in the Memory module. If there is, it writes the free address into the FIFO output module. When the address processing device is operating in bitmap control mode and the FIFO output module is not full, it checks whether there is a free address in the bitmap register. If there is, the free address is written into the FIFO output module. Upon receiving an address allocation request, if the FIFO output module is not empty, output a free address to the address allocation request sender.

7. The method according to claim 6, characterized in that, The method further includes: Receive an address reclamation request and determine whether the FIFO output module is not in a full state; If so, the address corresponding to the recycling request is written into the FIFO output module; If the FIFO output module is full and the address processing device is operating in bitmap control mode, then the address corresponding to the recycling request is written into the bitmap register; If the FIFO output module is full and the address processing device is operating in Memory control mode, then the address corresponding to the recycling request is written into the Memory module.

8. The method according to claim 6, characterized in that, The address processing device operates in Memory control mode; the step of detecting whether there is a free address in the Memory module, and if so, writing the free address into the FIFO output module, includes: The bitmap information is read from the Memory module. The bitmap information includes m groups, each group including n bits. Each bit corresponds to an address. When the value of any bit is a first preset value, it indicates that the corresponding address is occupied. When the value of any bit is a second preset value, it indicates that the corresponding address is idle. Identify at least one group where the number of bits in the corresponding address that are in an idle state is greater than zero; input the group identifier of the at least one group into the first-level scheduling unit, which schedules out the target group identifier from the received group identifiers; input the bit information of the group corresponding to the target group identifier into the second-level scheduling unit, which schedules out the target bit at a second preset value based on the bit information; write the address corresponding to the target bit into the FIFO output module.

9. The method according to claim 8, characterized in that, The step of reading bitmap information from the Memory module includes: A read request for bitmap information is sent to the Memory module. After receiving the bitmap information returned by the Memory module, it is determined whether a write request for any bit in the bitmap information was sent to the Memory module during the process from sending the read request to receiving the bitmap information. If so, the value of any bit in the bitmap information is replaced with the value corresponding to the write request.

10. The method according to claim 6, characterized in that, The address processing device operates in bitmap control mode; the step of detecting whether there is a free address in the bitmap register, and if so, writing the free address into the FIFO output module, includes: Read bitmap information from the bitmap register. The bitmap information includes m groups, each group including n bits. Each bit corresponds to an address. When the value of any bit is a first preset value, it indicates that the corresponding address is occupied. When the value of any bit is a second preset value, it indicates that the corresponding address is idle. Identify at least one group where the number of bits in the corresponding address that are in an idle state is greater than zero; input the group identifier of the at least one group into the first-level scheduling unit, which schedules out the target group identifier from the received group identifiers; input the bit information of the group corresponding to the target group identifier into the second-level scheduling unit, which schedules out the target bit at a second preset value based on the bit information; write the address corresponding to the target bit into the FIFO output module.

11. A chip, characterized in that, Includes the address processing apparatus according to any one of claims 1-5.

12. An electronic device, characterized in that, It includes the address processing device according to any one of claims 1-5, or the chip according to claim 11.

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