A SiP chip-based transient radiation effect circuit level fault simulation system and method

Abstract

The application discloses a kind of based on SiP chip's transient radiation effect circuit level fault simulation system and method, including clock signal generation module, fault injection module, ADC simulation module, voltage comparator simulation module, FPGA simulation module, DAC simulation module and level driver simulation module;Clock signal generation module is connected with ADC simulation module, DAC simulation module and FPGA simulation module, and the output end of ADC simulation module and voltage comparator simulation module is connected with the input end of FPGA simulation module, and the input end of DAC simulation module and level driver simulation module is connected with the output end of FPGA simulation module;Each simulation module includes IBIS model and SPICE circuit level model / Verilog behavior level model;The present application establishes the SiP system level simulation model including each chip simulation module and signal transmission module in SiP interior.Given simulation model input signal and transient radiation excitation, the output signal of entire SiP system level simulation model can be obtained.

Description

Technical Field

[0001] This invention belongs to the field of chip analysis technology, specifically relating to a transient radiation effect circuit-level fault simulation system and method based on SiP chips. Background Technology

[0002] System-in-Package (SiP), as a novel packaging technology, encapsulates multiple semiconductor chips within a single small package. It offers advantages such as miniaturization, system integration, and high overall integration, making it crucial for applications in defense and aerospace. However, for electronic devices operating in the aerospace domain, transient radiation effects must be considered. The current generated by transient radiation can affect the normal operation of electronic devices, potentially causing them to burn out and severely impacting the normal functioning of the equipment they reside in.

[0003] Previous studies on the transient radiation effects of SiP chips primarily involved irradiating the chips with linear accelerators. However, this experimental method has several drawbacks: first, the irradiation environment is accompanied by strong electromagnetic interference, which severely interferes with signal monitoring; second, the available accelerator time is limited, failing to meet the needs of experimental research; and third, the systems within SiP chips are extremely complex, containing both low-frequency and high-frequency signals, as well as digital and analog signals. Therefore, conducting in-depth and thorough research on the transient radiation effects of SiP chips solely through irradiation experiments—such as obtaining information on sensitive modules and circuits within the SiP chip, the coupling relationships between various modules and circuits, the propagation patterns of radiation-induced faults within the SiP, and accurate system-level assessments of the transient radiation effects—presents a significant challenge. Thus, irradiation-based methods cannot meet the needs of SiP transient radiation effect research. Currently, there is also a lack of system-level simulation methods for SiP transient radiation effects. This invention addresses this technological deficiency by developing a circuit-level fault simulation system for SiP chip transient radiation effects. Summary of the Invention

[0004] This invention provides a circuit-level fault simulation system for transient radiation effects based on SiP chips, which can provide a faster and more accurate circuit-level simulation method for the study of transient radiation effects of SiP chips, and make up for the shortcomings of irradiation experimental research methods.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A transient radiation effect circuit-level fault simulation system based on SiP chip is characterized by comprising a clock signal generation module, a fault injection module, an ADC (Analog-to-Digital Converter) simulation module, a voltage comparator simulation module, an FPGA (Field Programmable Gate Array) simulation module, a DAC (Digital-to-Analog Converter) simulation module, and a level driver simulation module; the clock signal generation module is connected to the ADC simulation module, the DAC simulation module, and the FPGA simulation module; the output terminals of the ADC simulation module and the voltage comparator simulation module are connected to the input terminal of the FPGA simulation module through a signal transmission module; and the output terminal of the FPGA simulation module is connected to the input terminals of the DAC simulation module and the level driver simulation module through the signal transmission module, respectively. The ADC simulation module, voltage comparator simulation module, DAC simulation module, and level driver simulation module all include a SPICE (Simulation Program with Integrated Circuit Emphasis) circuit-level model and a corresponding IBIS (I / O Buffer Information Specification) model; the FPGA simulation module includes a Verilog behavioral-level model and an FPGA IBIS model. The ADC simulation module, voltage comparator simulation module, DAC simulation module, and level driver simulation module all include a SPICE circuit-level current source model for simulating transient radiation effects.

[0006] Furthermore, the fault injection module includes: The SPICE circuit-level current source model library for transient radiation effects is established by creating basic CMOS (Complementary Metal-Oxide-Semiconductor) unit models of various sizes, conducting irradiation simulations of these models under transient radiation of different intensities, extracting the variation characteristics of their port currents under different intensities of transient radiation, generating current source models that include transient radiation effects, and establishing the SPICE circuit-level current source model library for transient radiation effects. A Python program is used to calculate the magnitude of transient current based on user-defined radiation fault parameters, call the model in the SPICE circuit-level current source model library for transient radiation effects, and embed it into the target SPICE circuit-level model. The behavioral-level fault injection unit is used to inject behavioral-level faults of signal flipping or signal loss into the output signals of the FPGA simulation module.

[0007] Furthermore, the signal transmission module includes: The first S-parameter model is used to connect the IBIS model output port of the ADC to the IBIS model input port of the FPGA. The second S-parameter model is used to connect the IBIS model output port of the voltage comparator to the IBIS model input port of the FPGA. The third S-parameter model is used to connect the IBIS model output port of the FPGA to the IBIS model input port of the DAC. The fourth S-parameter model is used to connect the IBIS model output port of the FPGA to the IBIS model input port of the level driver. The fifth, sixth, and seventh S-parameter models are connected to the IBIS model output port of the clock signal generation module and the IBIS model input ports of the ADC, FPGA, and DAC, respectively.

[0008] Furthermore, the Verilog behavioral model of the FPGA simulation module includes: The data receiving module is used to sample and synchronize the first digital signal from the ADC simulation module and the second digital signal from the voltage comparator simulation module, respectively, to eliminate the effects of different clock domains or signal delays. The preprocessing module is used to format and extend the bit width of the first digital signal, and to perform logical inversion on the second digital signal. The arithmetic logic module is used to control the preprocessed first digital signal to enter the fast Fourier transform and inverse transform arithmetic logic for frequency domain and inverse transform processing; at the same time, it independently performs frequency division processing on the clock signal from the FPGA simulation module of the signal generation module. The result output module is used to extract the effective data bits of the output of the Fast Fourier Transform and Inverse Transform operations, generate and output the third digital signal; and output the clock signal of the FPGA simulation module after frequency division as the fourth digital signal.

[0009] Furthermore, it also includes a simulated graphical interface for display and settings.

[0010] Furthermore, the simulation graphical interface was developed using the Python language, including: The model management module is used to import and call SPICE circuit-level models, Verilog behavioral-level models, IBIS models and S-parameter models in the simulation system, and provides a unified model interface for users to select. The input parameter configuration module is used to set the input parameters of each simulation module, including input signal amplitude, frequency, power supply voltage, clock configuration and circuit operating mode. The simulation scheduling module is used to call the backend simulation tool to perform circuit-level or functional-level simulation after the user completes the parameter settings; The results processing and visualization module is used to analyze and visualize the output waveform data generated by the simulation.

[0011] Furthermore, the clock signal generation module includes a SPICE circuit-level model of a PLL (Phase-Locked Loop) or DLL (Delayed-Locked Loops) to generate multiple clock signals of different frequencies, which are then output to the ADC simulation module, DAC simulation module, and FPGA simulation module, respectively.

[0012] A method for simulating transient radiation effects at the circuit level based on SiP chips includes the following steps: Step S1: Build simulation models of each functional module inside the SiP, including clock signal generation module, ADC simulation module, voltage comparator simulation module, FPGA simulation module, DAC simulation module and level driver simulation module, where at least some modules adopt SPICE circuit level model and the FPGA simulation module adopts Verilog behavioral level model. Step S2: Establish a fault injection module. Based on Technology Computer-Aided Design (TCAD) simulation, establish CMOS basic cell models of various sizes. Conduct irradiation simulations of CMOS basic cell models of various sizes under transient radiation of different intensities, extract the variation characteristics of their port current under transient radiation of different intensities, generate current source models containing transient radiation effects, establish a SPICE circuit-level current source model library for transient radiation effects, and configure behavioral-level fault injection logic. Step S3: Obtain the S-parameter model of the interconnection between modules and construct the signal transmission module; Step S4: Connect each simulation module through the signal transmission module to form a system-level simulation model; Step S5: Build a simulation graphical interface, integrating parameter configuration, fault injection settings, and result visualization functions; Step S6: Set the simulation parameters and fault injection parameters in the simulation graphical interface, execute the simulation, and analyze the fault propagation pattern.

[0013] Furthermore, in step S2, the fault injection module calculates the transient current magnitude based on the radiation dose rate, simulation duration, and simulation step size set by the user, and embeds the corresponding transient radiation effect SPICE circuit-level current source model into the target SPICE circuit-level model.

[0014] Furthermore, in step S6, the fault injection parameters include: For SPICE circuit-level model fault injection parameters, the parameters include: radiation dose rate magnitude, transient current injection start and end time, and target circuit module. The fault injection parameters for the Verilog behavioral model of the FPGA simulation module include: output signal selection, fault type, and fault start and end time.

[0015] Compared with the prior art, the present invention has at least the following beneficial technical effects: This invention takes a domestically produced SiP (System-in-Package) as the research object, using its basic architecture as a simulation modeling reference. Utilizing the SPICE circuit-level simulation model, the Verilog behavioral-level simulation model, the IBIS (Input / Output Buffer Information Specification) model, and the transmission line S-parameter model, a SiP system-level simulation model is established, encompassing the simulation modules of each chip within the SiP and the signal transmission module. Given the input signal to the simulation model, the output signal of the entire SiP system-level simulation model can be obtained.

[0016] This invention targets ADC simulation modules, voltage comparator simulation modules, DAC simulation modules, and level driver simulation modules. Based on TCAD simulation, it establishes CMOS basic cell models of various sizes contained within these modules. Irradiation simulations are then performed on these CMOS basic cell models under transient radiation of different intensities. The variation characteristics of their port currents under different intensities of transient radiation are extracted, generating current source models that incorporate transient radiation effects. A SPICE circuit-level current source model library for transient radiation effects is established for simulating transient current models of transient radiation effects. This simulation system can conduct preliminary studies for SiP transient radiation effect irradiation experiments, locate sensitive modules and failure modes within SiPs, and provide guidance for irradiation experiments. Simulations can also be used to interpret and analyze irradiation experiment results.

[0017] This invention combines multiple electronic simulation models, including SPICE circuit-level models and Verilog behavioral-level models, overcoming the shortcomings of incomplete access to SiP internal circuit-level SPICE models and high simulation costs. The resulting model is highly accurate, ensuring simulation results closely match the actual performance of SiP devices and accurately reflect SiP operation, providing a reliable basis for radiation effect simulation and analysis. Simultaneously, an S-parameter model is used to establish an interconnection and communication model between SiP internal sub-modules, enabling simulation analysis of the propagation of transient radiation effect faults between SiP internal modules. Furthermore, the simulation system boasts rich functional expandability, allowing for easy customization of each simulation model's functions and flexible adjustment of simulation modules to meet specific needs. Even more conveniently, the system supports rapid addition and modification of simulation modules, providing users with a wider range of customization options to adapt to increasingly diverse simulation requirements.

[0018] Furthermore, an intuitive and user-friendly graphical interface for SiP transient radiation effect fault injection simulation was developed using the Python programming language. This platform allows for easy customization of simulation parameters and fault injection parameters, and also enables the intuitive plotting and display of the simulation system's output waveforms. This makes it easier for users to understand the various parameters of the simulation system, and the intuitive graphical displays facilitate easier understanding and analysis of the simulation results, thereby improving system usability and user experience. Attached Figure Description

[0019] Figure 1 This is a diagram of the internal system architecture of a domestically produced SiP (System-in-Package). Figure 2 Framework diagram of a simulation system for circuit-level fault injection and propagation in SiP transient radiation effects; Figure 3 A diagram showing the circuit-level clock fault injection settings in the interface of the SiP transient radiation effect circuit-level fault injection and propagation simulation system. Figure 4 A diagram showing the ADC signal input and fault injection simulation settings page in the interface of the SiP transient radiation effect circuit-level fault injection and propagation simulation system. Figure 5 A diagram showing the voltage comparator signal input and fault injection simulation settings page in the interface of the SiP transient radiation effect circuit-level fault injection and propagation simulation system. Figure 6 This is a diagram of the FPGA signal faults and SiP output pages in the simulation system interface for circuit-level fault injection and propagation of transient radiation effects in SiP. Detailed Implementation

[0020] To make the objectives and technical solutions of this invention clearer and easier to understand, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. The specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.

[0021] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0022] Example 1 A simulation system for transient radiation effect circuit-level fault injection and propagation based on SiP chip (hereinafter referred to as SiP simulation system) is based on a certain SiP chip (the internal structure of the chip is as follows). Figure 1 As shown, the internal architecture of the SiP simulation system is as follows: Figure 2As shown, the system mainly comprises eight modules: clock signal generation module, fault injection module, ADC simulation module, voltage comparator simulation module, FPGA simulation module, DAC simulation module, level driver simulation module, signal transmission module, and a simulation graphical interface. The ADC, voltage comparator, DAC, and level driver simulation modules each consist of their respective SPICE circuit-level models and IBIS models (containing the I / O input and output ports of the semiconductor chip). The FPGA simulation module consists of its Verilog behavioral-level model and IBIS model. The SPICE circuit-level model describes the internal circuit behavior of the module, the IBIS model is a standard interface model specifically for circuit design and simulation, used to simulate the electrical behavior of the input and output ports of the simulation module, and the Verilog behavioral-level model is a hardware description language model used to describe the functions of digital circuits, capable of accurately simulating the logical behavior of the FPGA simulation module. The combined use of these models enables the SiP simulation system to comprehensively and accurately simulate the circuit-level fault injection and propagation of each module under transient radiation effects, providing strong support for the reliability and stability analysis of the system. The connection relationships between modules are based on... Figure 2The topology shown is established as follows: For example, the output port of the IBIS model of the clock signal generation module is connected to the input port of the IBIS model of the ADC in the ADC simulation module, the input port of the IBIS model of the DAC in the DAC simulation module, and the input port of the IBIS model of the FPGA in the FPGA simulation module to distribute the clock signal; the first digital signal output by the ADC simulation module is transmitted to the input port of the IBIS model of the FPGA in the FPGA simulation module through the output port of the ADC's IBIS model; the comparison result (second digital signal) of the voltage comparator simulation module is also sent to the input port of the IBIS model of the FPGA in the FPGA simulation module through the output port of the voltage comparator's IBIS model; the processing result of the FPGA simulation module is then transmitted to the input ports of the IBIS model of the DAC in the DAC simulation module and the input ports of the IBIS model of the level driver in the level driver simulation module through the output ports of the FPGA's IBIS model, respectively, to realize analog signal recovery and power signal control; the signal interconnection between the above simulation modules is simulated through the first S-parameter model, second S-parameter model, third S-parameter model, fourth S-parameter model, fifth S-parameter model, sixth S-parameter model, and seventh S-parameter model in the signal transmission module to ensure accurate reproduction of the signal transmission process. The fault injection module connects to the Python program of the clock signal generation module, the input ports of the IBIS model of the ADC, the input ports of the IBIS model of the voltage comparator, and the input ports of the IBIS model of the FPGA. This allows for fault injection into the clock signal generation module, ADC simulation module, voltage comparator simulation module, FPGA simulation module, DAC simulation module, and level driver simulation module. The simulation graphical interface module is used for unified parameter configuration and simulation control.

[0023] The ADC simulation module, voltage comparator simulation module, DAC simulation module, and level driver simulation module all used SPICE circuit-level models for modeling and simulation. SPICE models are circuit-level simulation models whose circuits are identical to the actual chip circuit structure, enabling high-precision simulation of the actual circuit and obtaining simulation results consistent with the actual circuit function. For the FPGA simulation module, due to the excessively large circuit size, a Verilog behavioral-level simulation model of the FPGA was built.

[0024] The ADC simulation module, voltage comparator simulation module, DAC simulation module, and level driver simulation module each consist of a corresponding SPICE circuit-level model and an IBIS model (including input and output ports). The SPICE circuit-level models of these modules contain CMOS basic cells of various sizes present in the corresponding chips, but do not include simulation modules for radiation effects. Under transient radiation conditions, CMOS basic cells generate transient currents at their ports, interfering with the voltage signals and causing malfunctions in the circuit-level models. To simulate the transient radiation response of each module, a fault injection module is established: First, models of CMOS basic cells of various sizes are built using TCAD software. Simulations of transient radiation effects at different intensities are then performed on these models. The transient current variation characteristics at the ports of each CMOS basic cell model under different intensities of transient radiation are extracted, generating a current source model that includes transient radiation effects. The models of CMOS basic cells of various sizes serve as modeling intermediates and do not exist directly in the final SiP simulation system. Instead, the simulation results (the characteristics of transient current changes at the ports under different intensities of transient radiation) are extracted as current sources and converted into transient radiation effect SPICE circuit-level current source models, forming a transient radiation effect SPICE circuit-level current source model library. The fault injection module can use a Python program to calculate the magnitude of the transient current based on the radiation fault injection parameters set by the user in the simulation graphical interface, and call the corresponding transient radiation effect SPICE circuit-level current source model from the transient radiation effect SPICE circuit-level current source model library. Based on the injection start and end times of the transient current set by the user in the simulation graphical interface, the model from the transient radiation effect SPICE circuit-level current source model library is embedded into each SPICE circuit-level model as a current source for fault injection. For example... Figure 2As shown, the SiP simulation system contains five SPICE circuit-level models: a clock signal generation module, an ADC simulation module, a voltage comparator simulation module, a DAC simulation module, and a level driver simulation module. In this simulation system, models from the transient radiation effect SPICE circuit-level current source model library may be embedded in the SPICE circuit-level models of the clock signal generation module, ADC simulation module, and / or voltage comparator simulation module. For the FPGA simulation module, since it uses a Verilog behavioral-level model instead of a SPICE circuit-level model, the transient radiation effect SPICE circuit-level current source model cannot be directly embedded into the FPGA simulation module. Instead, behavioral-level fault injection is performed on the FPGA. Users can select different types (signal flipping or signal loss) of behavioral-level fault injection into the output signal (third digital signal or fourth digital signal) of the FPGA simulation module in the simulation graphical interface, and set the start and end times of the fault injection. This allows for behavioral-level fault injection of the FPGA simulation module's output signal through a Python program.

[0025] Furthermore, to investigate the transmission characteristics of fault signals caused by transient radiation effects between modules within a SiP, a signal transmission module was established in the simulation system, including an S-parameter transmission line model (hereinafter referred to as the "S-parameter model") used to simulate the characteristics of interconnection lines between modules. The S-parameter model can be used to characterize the frequency domain characteristics of high-speed interconnection transmission lines between modules.

[0026] The first S-parameter model is used to represent the frequency domain characteristics of the high-speed interconnect transmission line between the ADC simulation module and the FPGA simulation module; the second S-parameter model is used to represent the frequency domain characteristics of the high-speed interconnect transmission line between the voltage comparator simulation module and the FPGA simulation module; the third S-parameter model is used to represent the frequency domain characteristics of the high-speed interconnect transmission line between the FPGA simulation module and the DAC simulation module; the fourth S-parameter model is used to represent the frequency domain characteristics of the high-speed interconnect transmission line between the FPGA simulation module and the level driver simulation module; the fifth S-parameter model is used to represent the frequency domain characteristics of the high-speed interconnect transmission line between the clock signal generation module and the ADC simulation module; the sixth S-parameter model is used to represent the frequency domain characteristics of the high-speed interconnect transmission line between the clock signal generation module and the FPGA simulation module; and the seventh S-parameter model is used to represent the frequency domain characteristics of the high-speed interconnect transmission line between the clock signal generation module and the DAC simulation module.

[0027] In the ADC simulation module, one end of the input port of the ADC's IBIS model is connected to the output port of the clock module's IBIS model in the clock signal generation module through the fifth S-parameter model, and the other end is connected to the SPICE circuit-level model of the ADC simulation module. One end of the output port of the ADC's IBIS model is connected to the input port of the FPGA's IBIS model in the FPGA simulation module through the first S-parameter model, and the other end is also connected to the SPICE circuit-level model of the ADC simulation module. In the DAC simulation module, one end of the input port of the DAC's IBIS model is connected to the output port of the FPGA's IBIS model in the FPGA simulation module and the output port of the clock module's IBIS model in the clock signal generation module through the third S-parameter model and the sixth S-parameter model, respectively. The other end is connected to the SPICE circuit-level model of the DAC simulation module. One end of the output port of the DAC's IBIS model is connected to the SPICE circuit-level model of the DAC simulation module, and the other end is connected to the graphical interface. In the voltage comparator simulation module, one end of the output port of the voltage comparator's IBIS model is connected to the SPICE circuit-level model of the voltage comparator simulation module, and the other end is connected to the input port of the FPGA's IBIS model in the FPGA simulation module through the second S-parameter model. In the level driver simulation module, one end of the input port of the IBIS model of the level driver is connected to the SPICE circuit-level model of the level driver simulation module, and the other end is connected to the output port of the IBIS model of the FPGA in the FPGA simulation module through the fourth S-parameter model. One end of the output port of the IBIS model of the level driver is connected to the SPICE circuit-level model of the level driver simulation module, and the other end is linked to the graphical interface. In the FPGA simulation module, one end of the input port of the FPGA's IBIS model is connected to the output port of the ADC's IBIS model in the ADC simulation module and the output port of the voltage comparator's IBIS model in the voltage comparator simulation module through the first S-parameter model and the second S-parameter model, respectively. The other end is connected to the Verilog behavioral level model of the FPGA simulation module. One end of the output port of the FPGA's IBIS model is connected to the Verilog behavioral level model of the FPGA simulation module. The other end is connected to the input port of the DAC's IBIS model in the DAC simulation module and the input port of the level driver's IBIS model in the level driver simulation module through the third S-parameter model and the fourth S-parameter model, respectively.

[0028] As described above, the S-parameter model and the IBIS model in each simulation module connect the various SPICE circuit-level models and Verilog behavioral-level models to form a complete system. The IBIS model and the S-parameter model can be used to simulate and analyze the propagation and coupling of fault signals generated by transient radiation effects within the SiP.

[0029] Example 2 Building upon Example 1, to facilitate users in simulating and visually analyzing the response behavior of various modules in a SiP system under transient radiation environments, this invention provides a graphical interface for simulating transient radiation effect fault injection at the SiP circuit level, developed using Python and running on the Windows platform. The simulation graphical interface includes the following functional modules: 1. Model Management Module: Used to import and call various simulation models created in the SiP system, including SPICE circuit-level models, Verilog behavioral-level models, IBIS models, and S-parameter models. The model management module provides a unified model interface, allowing users to select the required model and add it to the simulation flow through the simulation graphical interface; 2. Input Parameter Configuration Module: This module is used to set the input parameters for each simulation module, including input signal amplitude, frequency, power supply voltage, clock configuration, and circuit operating mode. Users can select and edit parameters through the simulation graphical interface without manually modifying the simulation input file. 3. Simulation Scheduling Module: After the user completes various parameter settings, the simulation scheduling module supports the platform in automatically generating simulation input scripts and calling backend simulation tools to complete circuit-level or functional-level simulations. The simulation scheduling module supports one-click execution, reducing the complexity of simulation operations; 4. Result Processing and Visualization Module: This module analyzes and visualizes the output waveform data generated during simulation. The platform supports plotting curves of response signals such as voltage and current, allowing users to observe the output changes of different modules and the overall system response. 5. Signal Propagation Analysis Module: Based on simulation, this module analyzes the propagation path of fault signals caused by transient radiation between modules. By combining the interconnection structure of the IBIS model and the S-parameter model, the platform can assess the coupling degree, propagation delay, and impact range of fault signals, providing a reference for system radiation-resistant design.

[0030] The platform in this embodiment is implemented using the Python programming language and combined with a graphical interface library to construct a simulation graphical interface, possessing good interactivity and scalability. The platform's workflow includes: model import → parameter setting → fault injection → simulation scheduling → result visualization and propagation analysis. Through this integrated process, users can quickly achieve joint simulation of transient radiation effects at the circuit, behavioral, interface, and functional levels in SiP systems, effectively improving the efficiency and accuracy of radiation reliability simulation. Compared with traditional manual simulation environment setup and analysis processes, the platform provided by this invention has high integration and automation characteristics in model calling, fault modeling, simulation scheduling, and result analysis, significantly reducing simulation complexity and enhancing the observability and controllability of complex SiP system behavior under irradiation environments.

[0031] Example 3 A method for simulating transient radiation effects at the circuit level based on SiP chips includes the following steps: Step 1: First, construct simulation circuit-level models for each module within the SiP. Based on the types and functions of the internal chips in the SiP, divide the SiP into different functional modules. Simulate each module using SPICE circuit-level or Verilog behavioral-level models to obtain simulation modules for each functional module. These functional modules include: a clock signal generation module, an ADC module, a voltage comparator module, an FPGA module, a DAC module, and a level driver module. Correspondingly, construct simulation modules for clock signal generation, ADC, voltage comparator, FPGA, DAC, and level drivers. The clock signal generation, ADC, voltage comparator, DAC, and level driver simulation modules are modeled using SPICE circuit-level models and their corresponding IBIS models, providing high-precision simulation capabilities consistent with the actual circuit structure. The IBIS models are obtained from the official documentation based on the SiP's internal chip model, representing the I / O port circuits. The FPGA simulation module uses Verilog language to build a behavioral-level model, which is mainly used for the simulation and verification of control logic. The Verilog behavioral-level model of the FPGA simulation module and the IBIS model of the FPGA together form the FPGA simulation module. In addition, there is a signal transmission module, which uses S-parameter modeling to simulate the characteristics of signal transmission paths between modules. Step 2: Establish the fault injection module. After establishing the simulation models corresponding to each module within the SiP, create basic CMOS cell models of various sizes within the corresponding SPICE circuit-level models in TCAD. Perform transient radiation effect simulations on these CMOS basic cell models of different sizes to obtain the current changes at the ports of each CMOS basic cell model. Extract these current changes to establish a transient radiation effect SPICE circuit-level current source model library. Use Python to write fault injection related programs in the fault injection module. This program can calculate the magnitude of the transient current based on the radiation fault injection parameters set by the user in the simulation graphical interface, call the corresponding transient radiation effect SPICE circuit-level current source model in the transient radiation effect SPICE circuit-level current source model library, and embed the corresponding transient radiation effect SPICE circuit-level current source model into the SPICE circuit-level models of the clock signal generation module, ADC simulation module, and / or voltage comparator simulation module according to the transient current injection start and end times set by the user in the simulation graphical interface. For the FPGA simulation module, since the FPGA simulation module uses a Verilog behavioral-level model instead of a SPICE circuit-level model, the transient radiation effect SPICE circuit-level current source model cannot be directly embedded into the FPGA simulation module. Instead, behavioral-level fault injection is performed on the FPGA. Users can select different types of behavioral-level fault injection for the output signal of the FPGA simulation module in the simulation graphical interface and set the start and end times of the fault injection. Behavioral-level fault injection for the output signal of the FPGA simulation module can be achieved through Python programs. Step 3: Extract the transmission line S-parameter model of the internal interconnect structure from the SiP design file using the professional software Ansys SIWave. Based on the actual circuit interconnections between modules, connect the IBIS model of each module with the corresponding S-parameter model to form the signal transmission module in the simulation system; Step 4: Using the signal transmission module, connect the clock signal generation simulation module, ADC simulation module, voltage comparator simulation module, DAC simulation module, and level driver simulation module to the FPGA simulation module respectively, and connect the clock signal generation simulation module to the ADC simulation module and DAC simulation module respectively to form a SiP transient radiation effect system-level simulation model. Step 5: After the circuit-level model and connections are constructed, a simulation graphical interface is built using Python. This interface links all simulation models built in the SiP transient radiation effect circuit-level fault injection and propagation simulation system, including the SPICE circuit-level model, Verilog behavioral-level model, IBIS model, and S-parameter transmission line model. The interface enables functions such as setting simulation circuit functions, configuring input and output parameters, setting transient radiation effect injection parameters, and visualizing simulation results. Users can flexibly set key parameters such as the functional logic of each module, input signal amplitude and frequency, irradiation time window, and irradiation intensity through the interface. After the simulation, the system output signal and the response of each module are displayed intuitively in the interface, enabling visual analysis of fault behavior under transient radiation effects. Step 6: After the SiP chip transient radiation effect circuit-level fault simulation system is established, the simulation and analysis of SiP transient radiation effects can be performed. The specific simulation process is as follows.

[0032] First, the user enters the circuit-level clock fault injection settings page in the simulation graphical interface (e.g., Figure 3 This settings page has three subpages, used to configure the clock signal parameters for the FPGA simulation module, the ADC simulation module, and the DAC simulation module, respectively. The steps for configuring the clock signal parameters in the FPGA simulation module's settings page are as follows: The user first determines the clock signal type as either a Delay-Locked Loop (DLL) or a Phase-Locked Loop (PLL), and then selects the clock module to be injected with the fault, including any one or all three of the following: Charge Pump Circuit (C_CH), Phase-to-Frequency Detector (PFD), and Voltage-Controlled Delay Chain (VCDL). Based on this, the user inputs the radiation dose rate of the clock signal to be injected into the FPGA simulation module in the dose rate setting box, and sets the simulation duration, simulation step size, and simulation frequency. The Python program in the fault injection module automatically calculates the corresponding transient current based on the user-set radiation dose rate, simulation duration, and simulation step size parameters, and displays the calculation results in the corresponding input box on the simulation graphical interface. Subsequently, the user sets the start and end times of the transient current injection. The fault injection module then embeds the SPICE circuit-level current source model corresponding to the displayed transient current magnitude into the corresponding SPICE circuit-level model in the clock signal generation module as a current source for fault injection. After clicking "Run," the simulation graphical interface reads these parameters and passes the clock signal type, clock signal frequency, simulation duration, and simulation step size of the FPGA simulation module to the Python program of the clock signal generation module. Simultaneously, the fault injection module, based on user-set or selected clock modules for fault injection, injects the fault into the Python program of the clock signal generation module. After reading the parameters, the Python program of the clock signal generation module modifies the corresponding parameters of the SPICE circuit-level model of the DLL or the SPICE circuit-level model of the PLL, and executes the simulation, generating the clock signal of the FPGA simulation module under fault injection. This signal is output from the output port of the IBIS model of the clock signal generation module and passed to the input port of the IBIS model of the FPGA through the sixth S-parameter model. The waveform of the clock signal under fault injection in the FPGA simulation module is then displayed in the simulation graphical interface. Among the parameters mentioned above, the clock module to be injected, the magnitude of the radiation dose rate to be injected, the magnitude of the transient current, and the injection start and end times of the transient current are all fault injection parameters. The clock signal type, simulation duration, simulation step size, and simulation frequency are simulation parameters.

[0033] The setup steps for the clock signal settings pages of the ADC and DAC simulation modules are the same as those for the clock signal parameter settings page of the FPGA simulation module. The only difference is that the target is either the clock signal of the FPGA simulation module or the clock signal of the ADC or DAC simulation module. If it is the clock signal of the ADC simulation module, the clock signal is output from the output port of the IBIS model of the clock signal generation module and then transmitted to the input port of the IBIS model of the ADC through the fifth S-parameter model. If it is the clock signal of the DAC simulation module, the clock signal is output from the output port of the IBIS model of the clock signal generation module and then transmitted to the input port of the IBIS model of the DAC through the seventh S-parameter model.

[0034] After setting the clock signal parameters for the FPGA simulation module, ADC simulation module, and DAC simulation module, the user switches to the ADC and voltage comparator signal input and fault injection simulation settings page. The ADC and voltage comparator signal input and fault injection simulation settings page has two subpages: the ADC signal input and fault injection simulation settings page and the voltage comparator signal input and fault injection simulation settings page.

[0035] In the ADC signal input and fault injection simulation settings page (such as...) Figure 4The input waveform parameters of the ADC simulation module can be set: select the ADC input waveform type (sine wave or custom waveform). If a sine wave is selected, set its bias, amplitude, and frequency; if a custom waveform is selected, upload the waveform file of the custom waveform. After setting the input waveform parameters of the ADC simulation module, click "Run". The input waveform parameters of the ADC simulation module are transmitted to the IBIS model input port of the ADC. After running the simulation, the output waveform of the ADC can be displayed on the simulation graphical interface. Then, set the simulation duration and simulation step size of the ADC simulation module, as well as the fault injection parameters of the ADC simulation module: select the fault injection channel (since the analog-to-digital conversion accuracy of this ADC simulation module is 1...). (6 bits, therefore having 16 output channels) The user sets the radiation dose rate of the selected channel to be injected. The Python program in the fault injection module automatically calculates the corresponding transient current based on the radiation dose rate, simulation duration, and simulation step size parameters set by the user, and displays the calculation results in the corresponding input box of the simulation graphical interface. Then, the user sets the injection start time and end time of the transient current. The fault injection module then prepares to embed the transient radiation effect SPICE circuit-level current source model corresponding to the displayed transient current magnitude into the SPICE circuit-level model of the ADC simulation module as a current source for fault injection, based on the injection start time and end time set by the user in the simulation graphical interface. After clicking "Run," the simulation graphical interface reads these parameters and transmits the input waveform parameters, simulation duration, and simulation step size of the ADC simulation module to the input port of the ADC's IBIS model. Simultaneously, the fault injection module, based on user settings or the selected channel for fault injection, injects the fault into the input port of the ADC's IBIS model. These parameters are then entered into the SPICE circuit-level model, and simulation is executed, generating the ADC simulation output signal under fault injection, i.e., the first digital signal. The first digital signal is the digital signal output by the ADC simulation module, converting the external analog signal into a corresponding 16-bit digital quantity. It is output from the output port of the ADC's IBIS model and transmitted to the input port of the FPGA's IBIS model through the first S-parameter model. The waveform of the ADC simulation output signal under fault injection is then displayed in the simulation graphical interface. The channel for fault injection, the radiation dose rate of the selected channel, the transient current magnitude, and the injection start and end times of the transient current are all fault injection parameters. The input waveform parameters, simulation duration, and simulation step size of the ADC simulation module are the simulation parameters.

[0036] Then enter the voltage comparator signal input and fault injection simulation settings page (e.g.) Figure 5To configure the input waveform parameters of the voltage comparator simulation module: First, set the input waveform of the voltage comparator (constant 0, constant 1, a custom waveform, or a square wave). If a square wave is selected, set its frequency and peak value; if a custom waveform is selected, upload the waveform file. After setting, click "Run" to display the output waveform of the voltage comparator on the simulation graphical interface. Next, set the simulation duration and step size, as well as the fault parameters for the output signal of the voltage comparator simulation module: Set the radiation dose rate to be injected into the voltage comparator simulation module. The Python program in the fault injection module automatically calculates the corresponding transient current based on the user-set radiation dose rate, simulation duration, and step size parameters, and displays the calculation results in the corresponding input box on the simulation graphical interface. Then, the user sets the injection start and end times for the transient current. The fault injection module then prepares to embed the SPICE circuit-level current source model corresponding to the displayed transient current magnitude into the SPICE circuit-level model of the voltage comparator simulation module as a current source for fault injection, based on the injection start and end times set by the user in the simulation graphical interface. After clicking "Run," the simulation graphical interface reads these parameters and combines the input waveform parameters of the voltage comparator simulation module with the simulation duration, simulation step size, and input port of the IBIS model of the input voltage comparator. Simultaneously, the fault injection module injects a fault into the input port of the IBIS model of the voltage comparator, transmits it to the SPICE circuit-level model of the voltage comparator simulation module, and executes the simulation, generating the voltage comparator simulation output signal (second digital signal) under fault injection. The second digital signal is a 1-bit digital signal output by the voltage comparator, used to characterize the comparison result between the compared voltage and the reference voltage. It is output from the output port of the IBIS model of the voltage comparator and then transmitted to the input port of the IBIS model of the FPGA through the second S-parameter model. The waveform of the voltage comparator simulation output signal under fault injection is displayed in the simulation graphical interface. The radiation dose rate, transient current magnitude, and the injection start and end times of the transient current in the voltage comparator simulation module are all fault injection parameters, while the input waveform, simulation duration, and simulation step size of the voltage comparator are simulation parameters.

[0037] Finally, enter the FPGA signal fault and SiP output page (e.g.) Figure 6The steps involve setting parameters for the FPGA simulation module, including simulation time, simulation step size, and fault injection parameters. These parameters include setting whether to inject faults into the third digital signal passed to the DAC simulation module and the fourth digital signal passed to the level driver simulation module, the fault type (signal loss or signal flip) of the third and / or fourth digital signals to be injected, and the start and end times of the injected fault. The Python program in the fault injection module generates a behavioral-level fault based on the user-selected signal (either the third or fourth digital signal, both can be selected simultaneously, neither can be selected, or only one can be selected), the start and end times of the fault injection. Additionally, the user needs to set simulation parameters such as simulation duration and simulation step size. After clicking "Run" on the simulation graphical interface, the simulation time and simulation step size of the FPGA simulation module are transmitted to the input port of the FPGA's IBIS model and then to the Verilog behavioral-level model of the FPGA simulation module. The FPGA simulation module will then execute the simulation according to the parameters set by the user. After the simulation is completed, the third and fourth digital signals are output from the output port of the FPGA's IBIS model. At this time, the fault injection module performs behavioral-level fault injection on the signal selected by the user (the third and / or fourth digital signals can be selected) to obtain the third and fourth digital signals after fault injection.

[0038] In this simulation system, the FPGA simulation module is responsible for parallel processing of the first digital signal, the second digital signal, and the clock signal of the FPGA simulation module. Internally, the FPGA simulation module uses Verilog to construct a behavioral-level model. This Verilog behavioral-level model includes a data receiving module, a preprocessing module, an arithmetic logic module, and a result output module. The data receiving module samples and synchronizes the first and second digital signals to eliminate the effects of different clock domains or signal delays.

[0039] The preprocessing module formats and expands the bit width of the synchronized first digital signal (e.g., padding with zeros to 32 bits), and simultaneously performs logical inversion on the synchronized second digital signal. Under the control of the timing control module, the first digital signal, after bit width expansion, is fed into the Fast Fourier Transform (FFT) and Inverse IFFT (IFFT) operation logic for frequency domain analysis and inverse transform processing. Simultaneously, this module independently performs frequency division processing on the clock signal from the FPGA simulation module originating from the signal generation module, generating a clock signal of a preset frequency. The FFT / IFFT operation logic is written in hardware logic and supports pipelined parallel computation of multiple data streams. The result output module extracts the valid data bits from the FFT / IFFT operation output to generate a third digital signal; outputs the frequency-divided clock signal from the FPGA simulation module as a fourth digital signal; outputs the logically inverted second digital signal; and directly outputs the signal obtained after logically inverting the second digital signal to the graphical interface.

[0040] The third digital signal is digital data used for digital-to-analog conversion, with a bit width of 28 bits (adapted to a dual-port DAC). After the FPGA simulation module performs amplitude calculation, quantization, and bit width mapping on the FFT / IFFT output results, the third digital signal is output by the result output module through the output port of the FPGA's IBIS model and sent to the input port of the DAC's IBIS model via the third S-parameter model. The DAC simulation module, based on the received 28-bit third digital signal, converts the digital quantity into a corresponding analog voltage signal and outputs it from the output port of the DAC's IBIS model to the simulation graphical interface. The fourth digital signal is a clock control signal generated by the FPGA simulation module after frequency division of the clock signal from the signal generation module's FPGA simulation module. Its logic high-level voltage is 3.3V. After the fourth digital signal is transmitted to the input port of the level driver's IBIS model through the fourth S-parameter model, the level driver simulation module performs voltage level conversion on the input signal, generating a corresponding continuous high-level signal, which is output from the output port of the level driver simulation model's IBIS model to the simulation graphical interface. Its logic high-level voltage is 5.0V, enabling the drive control of external devices or interface circuits. During signal transmission, based on the fault parameters set by the user in the FPGA simulation module, the user-defined fault is injected into the third and / or fourth digital signals through the output port of the FPGA's IBIS model.

[0041] When the third digital signal is passed to the SPICE circuit-level model of the DAC simulation module through the input port of the IBIS model of the DAC, and the fourth digital signal is passed to the SPICE circuit-level model of the level driver simulation module through the input port of the IBIS model of the level driver, the simulation of the DAC simulation module and the level driver simulation module is executed. After the simulation is completed, the waveform of the conversion result (analog signal) of the DAC simulation module is output to the graphical interface through the output port of the IBIS model of the DAC, and the waveform of the output signal of the level driver is output to the simulation graphical interface through the output port of the IBIS model of the level driver. Finally, the waveforms of the third and fourth digital signals, as well as the output waveforms of the DAC simulation module and the level driver simulation module are displayed in the simulation graphical interface.

[0042] A simulation system for circuit-level fault injection and propagation in SiP chips with transient radiation effects includes: Based on the actual internal architecture of the SiP chip, the overall architecture is divided into modules. Using SPICE circuit-level modeling and Verilog behavioral-level modeling methods, simulation models for each module are established, including a clock signal generation simulation module, an ADC simulation module, a voltage comparator simulation module, an FPGA simulation module, a DAC simulation module, a fault injection module, and a level driver simulation module. According to the SiP chip's system architecture, the FPGA simulation module, as the core control module, is responsible for the comprehensive processing of the output signals from the ADC and voltage comparator simulation modules, including digital judgment, logical judgment, and timing control. Based on the processing results, it generates digital control signals, which are then transmitted to the DAC and level driver simulation modules as input control signals to drive subsequent analog signal recovery and level output operations. Regarding the interconnections between modules, the clock signal generation module provides a unified timing reference signal to the ADC simulation module, DAC simulation module, and FPGA simulation module simultaneously. The ADC simulation module and voltage comparator simulation module respectively acquire the input analog signals and directly send the processed level signals or logic judgment results to the input terminal of the FPGA simulation module. The FPGA simulation module performs logical processing on these input signals and outputs digital control signals, which are connected to the input terminals of the DAC simulation module and the level driver simulation module to realize analog output or level-driven output control. The entire signal transmission path is interconnected through signal transmission modules constructed using the IBIS model and the S-parameter model to ensure signal integrity and timing consistency.

[0043] The signal transmission module adopts an S-parameter model and is connected to the IBIS model in each simulation module to realize the interconnection and signal transmission between the SPICE circuit-level models and the Verilog behavioral-level models, thus realizing the construction from the module to the system level.

[0044] The simulation graphical interface is built using Python based on the circuit simulation module and the interconnection module. The established circuit simulation module is encapsulated, and the relevant parameters of the simulation system can be defined and the input and output signal waveforms can be visualized through the simulation graphical interface.

[0045] The specific details of each module are as follows.

[0046] 1. Clock signal generation simulation module Clock signals are the most widely used signals in SiP systems, required by ADC, DAC, and FPGA modules, each with different clock frequencies. In actual chips, clock signals are generated by internal phase-locked loops (PLLs) or delay-locked loops (DLLs). To achieve high-fidelity clock signal modeling consistent with the actual chip structure, this simulation system constructs SPICE circuit-level simulation models of DLL and PLL clocks based on the structural principles of PLLs and DLLs. These models are used to simulate the frequency synthesis, phase control, and output characteristics of actual clock circuits. The SPICE simulation circuits of the PLLs or DLLs serve as... Figure 2 This is part of the simulation model of the clock signal generation module, constituting the core functional unit of the clock signal generation simulation module. Multiple clock signals output from the clock signal generation simulation module are connected to the input terminals of the FPGA simulation module, ADC simulation module, and DAC simulation module, respectively, providing synchronous clock drive signals of different frequencies for each sub-module, thus enabling the coordinated operation of each sub-functional module in the time domain.

[0047] 2. Fault Injection Module Because the SPICE circuit-level models of the clock signal generation module, ADC simulation module, voltage comparator simulation module, DAC simulation module, and level driver simulation module contain CMOS basic cells of different sizes, but do not include a simulation module for irradiation effects, transient radiation effect simulations were performed on the models of each CMOS basic cell size using TCAD software. The transient current change characteristics at the ports of each CMOS basic cell size under irradiation were extracted. The models of each CMOS basic cell size serve as modeling intermediates and do not exist directly in the final SiP simulation system. Instead, the simulation results (transient current change characteristics at the ports under irradiation) are extracted as current sources into a transient radiation effect SPICE circuit-level current source model library. The models in this library can be called according to the radiation fault injection parameters set by the user in the simulation graphical interface. These models are then embedded into the SPICE circuit-level models of the clock signal generation module, ADC simulation module, and / or voltage comparator simulation module as current sources for fault injection. After establishing a SPICE circuit-level current source model library for transient radiation effects, users can configure radiation fault injection parameters in the simulation graphical interface, including the start and end times of fault injection, and the magnitude of the injected radiation dose rate. The fault injection module can then use the SPICE circuit-level models from the embedded clock signal generation module, ADC simulation module, and / or voltage comparator simulation module within the SPICE circuit-level model library as current sources for fault injection, based on the user-defined radiation fault injection parameters.

[0048] 2. ADC simulation module The ADC simulation module, a sub-module within a domestically produced SiP chip, primarily functions to convert analog signals into digital signals. In the simulation system, the SPICE circuit-level model of the ADC simulation module (referred to as the ADC simulation module) is used to achieve the conversion between analog and digital signals. The analog input signal to the ADC simulation module can be a sinusoidal signal, with its waveform determined by defining information such as amplitude, frequency, and bias. Waveform files can also be imported to customize the waveform. The ADC clock signal generated in the clock simulation module drives the ADC module's simulation. Therefore, faults contained in the clock signal will affect the normal function of the ADC module. Furthermore, the transient radiation effect of the ADC is studied by introducing a transient current model used to simulate optical transient radiation effects into the ADC module for fault injection simulation. The transient radiation response of the ADC simulation module is obtained and displayed at the output of the graphical interface.

[0049] 3. Voltage comparator simulation module As a module within a SiP chip, the voltage comparator primarily compares an external input signal with a specific voltage to obtain a result. Its output then serves as the input signal for the FPGA module. In the simulation system, a SPICE circuit-level model of the voltage comparator simulation module was established. The input signal of the voltage comparator module can be defined as a constant 0 state, a constant 1 state, a square wave, or a custom waveform. Previous research has found that only the input module, output module, and power supply module in a voltage comparator are susceptible to transient radiation effects. Therefore, in the simulation system, transient current models for simulating optical transient radiation effects can be introduced individually or simultaneously into these three modules to study the responses of each module within different voltage comparators and display them at the graphical interface output.

[0050] 4. FPGA simulation module As one of the most crucial modules in a SiP chip, the FPGA module's functionality determines the overall functionality of the SiP chip. The FPGA simulation module cannot be implemented using Python code; instead, it is written in the Verilog hardware programming language, establishing its Verilog behavioral-level model and performing simulations by calling Modelsim simulation software. Embedding this software into the simulation system platform makes the simulation results more reliable and faster. During simulation, the output signals of the ADC simulation module and the voltage comparator simulation module can be used as input signals for the FPGA simulation module. After internal processing by the FPGA simulation module, digital signals are generated and passed to the DAC module and the level driver module for subsequent simulation by these two modules. Simultaneously, the clock signal required for FPGA simulation is provided by the clock signal generation module. Fault signals contained in the clock signal will affect the normal function of the FPGA simulation module. Furthermore, the simulation system can also inject faults such as signal toggling and signal loss into the multiple digital signals generated by the FPGA simulation module.

[0051] 5. DAC simulation module The DAC, a submodule within a domestically produced SiP chip, primarily converts analog signals to digital signals. In the simulation system, the SPICE circuit-level model of the DAC simulation module is used to implement the conversion between analog and digital signals. The DAC clock signal generated in the clock signal generation module is used to drive the DAC simulation module. Therefore, faults contained in the clock signal will affect the normal functioning of the DAC simulation module.

[0052] 6. Level driver simulation module A SPICE circuit simulation model of the level driver module within the SiP was also established. This simulation module converts the fourth digital signal output from the FPGA simulation module into a voltage signal, obtaining output signals under different voltage conditions, which are then displayed in the graphical interface. Therefore, if the FPGA output contains a fault signal, the final output of the level driver will also be a fault signal.

[0053] 7. Signal transmission module The signal transmission module employs an S-parameter model. The S-parameters connect the output port of one module's IBIS model to the input port of another's IBIS model. The IBIS models are then connected to either the SPICE circuit-level model or the Verilog behavioral-level model. In this configuration, the output port of the clock signal generation IBIS model is connected to the input ports of the ADC simulation module, FPGA simulation module, and DAC's IBIS models via the fifth, sixth, and seventh S-parameter models, respectively. The output ports of the ADC simulation module and voltage comparator's IBIS models are connected to the input ports of the FPGA's IBIS model via the first and second S-parameter models, respectively. The output port of the FPGA's IBIS model is connected to the input ports of the DAC simulation module and level driver's IBIS models via the third and fourth S-parameter models, respectively. The signal transmission module, constructed using the S-parameter model, is connected to the clock signal generation module, ADC simulation module, voltage comparator simulation module, DAC simulation module, and level driver's IBIS models, achieving interconnection between the SPICE circuit-level models and the Verilog behavioral-level models of the FPGA simulation module, thus forming the overall SiP simulation system.

[0054] 8. Simulated graphical interface After completing the model building for each module, a simulation graphical interface was constructed using Python to integrate the various simulation modules. Through this interface, the functions, input signal waveforms, frequencies, transient radiation dose rates, and time parameters of each simulation module (i.e., all parameters mentioned in the simulation parameters and fault injection parameters described above) can be set. The interface also allows for the simulation of transient radiation effects using single or multiple modules, and displays the output signals of each module and the overall system. The simulation graphical interface primarily serves to facilitate use and result observation, making the setting of simulation parameters for each module more intuitive and convenient.

[0055] The SiP transient radiation effect circuit-level fault injection and propagation simulation system described in this invention can be used to study the propagation law and sensitive location of transient radiation faults in miniaturized SiP chips. This system can simulate transient radiation effects for each module in the SiP, obtaining the transient radiation effect response of each module. Furthermore, the response can propagate throughout the entire system, revealing the propagation law of the fault signal. Simultaneously, as this is a circuit-level simulation system, its simulation results show a consistency of over 80% with actual experimental results, and a simulation can be completed within 10 minutes. This significantly improves efficiency compared to transient radiation irradiation experiments. Therefore, different fault injections can be performed on different modules in a short time, completing a large number of simulations, identifying sensitive locations, and providing a reference for irradiation experiments.

[0056] This invention has been applied to the study of transient radiation effects in a domestically produced SiP chip. Before conducting the transient radiation irradiation experiment on the chip, a fault injection simulation was first performed using this simulation system, obtaining the sensitive circuits and modules in the simulation. During the irradiation experiment, this part of the circuit was studied in detail, improving the experimental efficiency by 40% and reducing the time consumption. Simultaneously, after obtaining the irradiation experiment results of the chip, the failure mechanism of the SiP chip was analyzed and explained using the simulation system.

[0057] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A transient radiation effect circuit-level fault simulation system based on SiP chip, characterized in that, It includes a clock signal generation module, a fault injection module, an ADC simulation module, a voltage comparator simulation module, an FPGA simulation module, a DAC simulation module, and a level driver simulation module. The clock signal generation module is connected to the ADC simulation module, the DAC simulation module, and the FPGA simulation module. The output terminals of the ADC simulation module and the voltage comparator simulation module are connected to the input terminal of the FPGA simulation module through a signal transmission module. The output terminal of the FPGA simulation module is connected to the input terminals of the DAC simulation module and the level driver simulation module through the signal transmission module, respectively. The ADC simulation module, voltage comparator simulation module, DAC simulation module, and level driver simulation module all include SPICE circuit-level models and corresponding IBIS models; the FPGA simulation module includes Verilog behavioral-level models and FPGA IBIS models. The ADC simulation module, voltage comparator simulation module, DAC simulation module, and level driver simulation module all include a SPICE circuit-level current source model for simulating transient radiation effects.

2. The transient radiation effect circuit-level fault simulation system based on SiP chip according to claim 1, characterized in that, The fault injection module includes: The SPICE circuit-level current source model library for transient radiation effects is established by creating CMOS basic cell models of various sizes and conducting irradiation simulations of CMOS basic cell models of various sizes under transient radiation of different intensities. The variation characteristics of their port current under transient radiation of different intensities are extracted, and current source models containing transient radiation effects are generated, thus establishing the SPICE circuit-level current source model library for transient radiation effects. A Python program is used to calculate the magnitude of transient current based on user-defined radiation fault parameters, call the model in the SPICE circuit-level current source model library for transient radiation effects, and embed it into the target SPICE circuit-level model. The behavioral-level fault injection unit is used to inject behavioral-level faults of signal flipping or signal loss into the output signals of the FPGA simulation module.

3. The transient radiation effect circuit-level fault simulation system based on SiP chip according to claim 1, characterized in that, The signal transmission module includes: The first S-parameter model is used to connect the IBIS model output port of the ADC to the IBIS model input port of the FPGA. The second S-parameter model is used to connect the IBIS model output port of the voltage comparator to the IBIS model input port of the FPGA. The third S-parameter model is used to connect the IBIS model output port of the FPGA to the IBIS model input port of the DAC. The fourth S-parameter model is used to connect the IBIS model output port of the FPGA to the IBIS model input port of the level driver. The fifth, sixth, and seventh S-parameter models are connected to the IBIS model output port of the clock signal generation module and the IBIS model input ports of the ADC, FPGA, and DAC, respectively.

4. The transient radiation effect circuit-level fault simulation system based on SiP chip according to claim 1, characterized in that, The Verilog behavioral model of the FPGA simulation module includes: The data receiving module is used to sample and synchronize the first digital signal from the ADC simulation module and the second digital signal from the voltage comparator simulation module, respectively, to eliminate the effects of different clock domains or signal delays. The preprocessing module is used to format and extend the bit width of the first digital signal, and to perform logical inversion on the second digital signal. The arithmetic logic module is used to control the preprocessed first digital signal to enter the fast Fourier transform and inverse transform arithmetic logic for frequency domain and inverse transform processing; at the same time, it independently performs frequency division processing on the clock signal from the FPGA simulation module of the signal generation module. The result output module is used to extract the effective data bits of the output of the Fast Fourier Transform and Inverse Transform operations, generate and output the third digital signal; and output the clock signal of the FPGA simulation module after frequency division as the fourth digital signal.

5. The transient radiation effect circuit-level fault simulation system based on SiP chip according to claim 1, characterized in that, It also includes a simulated graphical interface for display and settings.

6. The transient radiation effect circuit-level fault simulation system based on SiP chip according to claim 5, characterized in that, The simulation graphical interface is developed using the Python language and includes: The model management module is used to import and call SPICE circuit-level models, Verilog behavioral-level models, IBIS models and S-parameter models in the simulation system, and provides a unified model interface for users to select. The input parameter configuration module is used to set the input parameters of each simulation module, including input signal amplitude, frequency, power supply voltage, clock configuration and circuit operating mode. The simulation scheduling module is used to call the backend simulation tool to perform circuit-level or functional-level simulation after the user completes the parameter settings; The results processing and visualization module is used to analyze and visualize the output waveform data generated by the simulation.

7. The transient radiation effect circuit-level fault simulation system based on SiP chip according to claim 1, characterized in that, The clock signal generation module includes a SPICE circuit-level model of a PLL or DLL, used to generate multiple clock signals of different frequencies, which are output to the ADC simulation module, DAC simulation module and FPGA simulation module respectively.

8. A method for simulating transient radiation effects at the circuit level based on SiP chips, characterized in that, Includes the following steps: Step S1: Build simulation models of each functional module inside the SiP, including clock signal generation module, ADC simulation module, voltage comparator simulation module, FPGA simulation module, DAC simulation module and level driver simulation module, where at least some modules adopt SPICE circuit level model and the FPGA simulation module adopts Verilog behavioral level model. Step S2: Establish a fault injection module. Based on computer-aided design simulation, establish CMOS basic cell models of various sizes. Conduct irradiation simulations of CMOS basic cell models of various sizes under transient radiation of different intensities, extract the variation characteristics of port current under transient radiation of different intensities, generate a current source model containing transient radiation effects, establish a SPICE circuit-level current source model library for transient radiation effects, and configure behavioral-level fault injection logic. Step S3: Obtain the S-parameter model of the interconnection between modules and construct the signal transmission module; Step S4: Connect each simulation module through the signal transmission module to form a system-level simulation model; Step S5: Build a simulation graphical interface, integrating parameter configuration, fault injection settings, and result visualization functions; Step S6: Set the simulation parameters and fault injection parameters in the simulation graphical interface, execute the simulation, and analyze the fault propagation pattern.

9. A method for simulating transient radiation effects at the circuit level based on a SiP chip according to claim 8, characterized in that, In step S2, the fault injection module calculates the transient current magnitude based on the radiation dose rate, simulation duration, and simulation step size set by the user, and embeds the corresponding transient radiation effect SPICE circuit-level current source model into the target SPICE circuit-level model.

10. A method for simulating transient radiation effects at the circuit level based on a SiP chip according to claim 8, characterized in that, In step S6, the fault injection parameters include: For SPICE circuit-level model fault injection parameters, the parameters include: radiation dose rate magnitude, transient current injection start and end time, and target circuit module. The fault injection parameters for the Verilog behavioral model of the FPGA simulation module include: output signal selection, fault type, and fault start and end time.

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