A method for directly integrating a selected area epitaxy GaN-on-Si HEMT

Abstract

The application discloses a kind of selected area epitaxy GaN-on-Si HEMT direct drive single-chip integration method, belong to semiconductor device technical field.The specific inclusion includes: selecting silicon substrate and dividing GaN device area and silicon MOSFET device area;Etching recess window in GaN device area, utilize selected area epitaxy technology and grow GaN HEMT epitaxial structure in recess window;Subsequently, silicon MOSFET device and GaN MIS-HEMT device are prepared in corresponding area respectively;Finally, the drain electrode of silicon MOSFET device and the source electrode of GaN MIS-HEMT device are connected by on-chip metal interconnection process.The application realizes normally open type GaN MIS-HEMT and normally off type silicon MOSFET monolithic cascade integration, shortens the device spacing to micron level, greatly reduces parasitic inductance and capacitance, effectively suppresses switch oscillation and overshoot, reduces switch loss, and the gate of GaN MIS-HEMT device is independently extracted to realize direct drive, avoiding reverse recovery charge loss;The method of the application does not need to be bonded, and the process compatibility is good, which significantly improves the high-frequency characteristics, reliability and integration of high-performance power electronic devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a method for direct-drive single-chip integration of GaN-on-Si HEMT with selected area epitaxy. Background Technology

[0002] As power electronics technology advances towards higher frequencies, higher efficiency, and higher power density, gallium nitride (GaN), a third-generation semiconductor material, has become an ideal material for fabricating high-frequency power devices due to its excellent properties such as wide bandgap, high electron saturation drift velocity, and high breakdown field strength. Currently, GaN high electron mobility transistors (HEMTs) based on silicon substrates have attracted much attention due to the low cost of silicon substrates, good heat dissipation performance, and compatibility with large-size wafer processes. However, since GaN HEMTs are typically depletion-mode devices, meaning they are in a conducting state at zero gate voltage, this poses a safety hazard in power switching applications, and the drive circuit design is relatively complex.

[0003] To address the issues arising from the normally-on characteristic of depletion-mode devices, the industry typically employs enhancement-mode techniques or cascading solutions. While enhancement-mode GaN HEMTs can be achieved using techniques such as gate trench and P-type gate, these techniques often involve complex fabrication processes, poor threshold voltage stability, and reliability challenges. In contrast, cascading solutions connect normally-on GaN HEMTs with normally-off silicon MOSFETs, utilizing the normally-off characteristic of the silicon MOSFETs to achieve the normally-off function of the entire device. This approach not only offers high reliability but also leverages mature silicon driver circuitry, making it one of the mainstream commercial solutions currently available.

[0004] However, existing cascading solutions mainly rely on traditional dual-chip co-packaging technology (primarily using Cascode Kelvin connections), which involves connecting discrete GaN HEMT chips and silicon MOSFET chips together using bonding wires. This packaging method has significant drawbacks: First, the interconnection distance between chips is relatively long (typically on the millimeter level), resulting in large parasitic inductance and capacitance, severely limiting the switching speed of the device and increasing switching losses; second, during high-frequency switching, parasitic inductance can lead to severe voltage overshoot and ringing, increasing electromagnetic interference (EMI) and potentially causing device breakdown; furthermore, the reliability of the bonding wire connections is also challenged under thermal cycling and mechanical vibration environments. Although Cascode Kelvin connections improve dynamic performance to some extent, they cannot fundamentally eliminate the influence of package parasitic parameters. Therefore, how to achieve close-range, low-parasitic-parameter monolithic integration of GaN HEMTs and silicon MOSFETs has become a key technical problem that urgently needs to be solved in the field of GaN power devices. Summary of the Invention

[0005] To address the problems of long interconnect distances, large parasitic parameters, high switching losses, and insufficient reliability in existing dual-chip co-package cascade solutions, this invention provides a selective epitaxial GaN-on-Si HEMT direct-drive single-chip integration method. By selectively growing GaN HEMTs and integrating silicon MOSFETs on the same silicon substrate, on-chip direct interconnection and independent gate direct drive of the two devices are achieved, thereby improving switching speed, reducing losses, and simplifying packaging.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A method for selecting region epitaxial GaN-on-Si HEMT direct-drive single-chip integration includes:

[0008] A silicon substrate is provided, on which a GaN device region and a silicon MOSFET device region are defined, with the two device regions spaced 30~50μm apart;

[0009] A recessed window is etched to form the GaN device region on the silicon substrate, and a GaN HEMT epitaxial structure is grown within the recessed window by selective epitaxy.

[0010] A silicon MOSFET device is fabricated in the silicon MOSFET device region of the silicon substrate;

[0011] Fabricate a GaN MIS-HEMT device on the GaN HEMT epitaxial structure;

[0012] The drain of the silicon MOSFET device is electrically connected to the source of the GaN MIS-HEMT device through on-chip metal interconnect technology to form a cascaded single-chip integration.

[0013] The silicon MOSFET device is normally off, the GaN MIS-HEMT device is normally on, and the gate of the GaN MIS-HEMT device is independently led out as the main control electrode of the single chip for direct driving.

[0014] Specifically, the depth of the recessed window is adapted to the thickness of the GaN HEMT epitaxial structure, so that the surface of the GaN HEMT epitaxial structure and the surface of the silicon substrate are at the same level or approximately at the same level.

[0015] The fabrication process of the recessed window includes: depositing a mask layer on the surface of a silicon substrate, forming the recessed window through photolithography and dry etching processes, and performing wet etching on the bottom surface of the window to remove the damaged layer.

[0016] Specifically, the growth process of the GaN HEMT epitaxial structure adopts MOCVD process, and from bottom to top includes: AlN nucleation layer, AlGaN stress relief layer with multiple gradient composition, carbon-doped GaN layer, unintentionally doped GaN channel layer, AlN space charge isolation layer, AlGaN barrier layer, GaN capping layer, and in-situ grown SiN layer; wherein, the aluminum composition of the AlGaN stress relief layer is set in a gradient decreasing manner along the growth direction, which is used to buffer the lattice mismatch and thermal mismatch stress between GaN and silicon substrate.

[0017] Specifically, after the GaN HEMT epitaxial structure is grown, the process further includes:

[0018] An Al2O3 passivation layer was deposited on the surface of the GaN HEMT epitaxial structure using atomic layer deposition (ALD).

[0019] The GaN epitaxial material and mask layer on the surface of the silicon MOSFET device region are removed by etching process to expose the surface of the silicon substrate;

[0020] An insulating isolation region between devices is formed in the GaN device region by ion implantation. The insulating isolation region is formed by Fe+ ion implantation, and the implantation depth covers the unintentionally doped GaN channel layer.

[0021] Specifically, the fabrication process of the silicon MOSFET device includes:

[0022] A trench isolation process is performed in the silicon MOSFET device region to form an active region;

[0023] P-well regions are formed by ion implantation and then activated by annealing.

[0024] A gate oxide layer is grown by thermal oxidation, and a polysilicon layer is deposited and patterned to form a gate structure;

[0025] N+ heavily doped regions for the source and drain regions are formed by ion implantation, followed by rapid thermal annealing.

[0026] Deposit and pattern metal electrode material to form the source, gate, and drain of the silicon MOSFET device.

[0027] Specifically, the gate metal electrode material of the silicon MOSFET device is a TiN / Ti / Al / TiN stacked structure, and the source and drain metal electrode materials are Ti / Al / Ti / TiN stacked structures;

[0028] The silicon MOSFET device has B+ implanted impurities in the P-well region with a resistivity of 0.5~2 Ω·cm; and P+ and As+ implanted impurities in the N+ heavily doped region with an implantation depth of 0.2~0.3μm.

[0029] Specifically, the fabrication process of the GaN MIS-HEMT device includes:

[0030] A passivation dielectric layer is deposited on the GaN HEMT epitaxial structure;

[0031] The passivation dielectric layer is etched until the Al2O3 passivation layer of the gate region is exposed, and gate metal is deposited to form the gate electrode;

[0032] The passivation dielectric layer and Al2O3 passivation layer are etched until the GaN capping layer of the source and drain regions is exposed. Source metal and drain metal are deposited to form source electrodes and drain electrodes, respectively, and then annealed and alloyed.

[0033] Specifically, the gate electrode of the GaN MIS-HEMT device is a TiN / Ti / Al / TiN stacked structure, and the source and drain electrodes are Ti / Al / Ti / TiN stacked structures.

[0034] Specifically, the on-chip metal interconnect process includes:

[0035] The interlayer medium is deposited and then subjected to chemical mechanical polishing planarization.

[0036] Etching forms contact vias, exposing the drain of the silicon MOSFET device and the source of the GaN MIS-HEMT device, respectively;

[0037] Fill the contact through-hole with through-hole metal;

[0038] Interconnect metal is deposited and patterned to form a metal interconnect line connecting the drain of the silicon MOSFET device and the source of the GaN MIS-HEMT device. The interconnect metal line is arranged parallel to the surface of the silicon substrate, and its length corresponds to the spacing between the two device regions.

[0039] Specifically, the selected area epitaxial GaN-on-Si HEMT direct drive single-chip integration method further includes fabricating lead electrodes, wherein the gate of the silicon MOSFET device is led out as the enable control terminal of the single chip, and the gate of the GaN MIS-HEMT device is led out as the high-speed drive terminal of the single chip.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] (1) This invention realizes the monolithic integration of GaN MIS-HEMT devices and silicon MOSFET devices through selective epitaxy technology, shortening the interconnection distance between devices from the millimeter level of traditional packaging to the micrometer level (e.g., 30~50μm), which is only about 3% of the length of traditional bonding wires. This significantly reduces parasitic inductance and parasitic capacitance, effectively eliminates ringing and voltage overshoot in the high-frequency switching process, and significantly improves the stability and switching speed of the system.

[0042] (2) The present invention adopts a direct-drive cascade architecture, with the gate of the GaN MIS-HEMT device independently led out as the main control terminal, realizing direct drive control of the GaN device. Compared with the traditional cascade scheme, this architecture avoids the reverse recovery charge loss of silicon MOSFET devices, reduces switching losses, and allows independent optimization of the gate circuit, improving the flexibility of circuit design.

[0043] (3) This invention utilizes a recessed window to grow GaN HEMT epitaxial structures and controls the growth thickness to make the epitaxial layer surface coplanar with the silicon substrate surface, effectively solving the surface step problem in GaN-on-Si integration, facilitating subsequent wiring processes, and improving process compatibility and yield. At the same time, selective epitaxy technology is beneficial for releasing the overall stress of the epitaxial layer of large-size wafers, reducing warpage and bending, and is suitable for large-scale manufacturing of 6-8 inch wafers.

[0044] (4) This invention integrates the low driving voltage advantage of silicon MOSFET devices with the high withstand voltage and low on-resistance advantage of GaN MIS-HEMT devices, achieving a combination of normally off characteristics and high reliability, and eliminating the need for expensive wafer bonding processes, thus significantly reducing the manufacturing cost and package size of the devices. Attached Figure Description

[0045] Figure 1 This is a cross-sectional view of a single-chip integrated structure in an embodiment of the present invention.

[0046] Figure 2 This is a schematic diagram of the cross-sectional structure of the electrodes and leads integrated on a single chip in an embodiment of the present invention.

[0047] Figure 3 This is a schematic diagram of the layer structure of the epitaxial structure in an embodiment of the present invention.

[0048] Figure 4 This is a cross-sectional structural diagram of the recessed window etching step in an embodiment of the present invention.

[0049] Figure 5 This is a cross-sectional structural diagram of the selected area epitaxial growth step in an embodiment of the present invention.

[0050] Figure 6This is a cross-sectional structural schematic diagram of the silicon MOSFET device fabrication steps in an embodiment of the present invention.

[0051] Figure 7 This is a cross-sectional structural schematic diagram of the fabrication steps of the GaN MIS-HEMT device in an embodiment of the present invention.

[0052] In the above figures, the component names corresponding to the reference numerals are as follows:

[0053] 100 - Silicon substrate, 110 - P-well region, 120 - N+ heavily doped region, 121 - Source doped well, 122 - Drain doped well, 130 - Gate oxide layer, 140 - Polysilicon layer, 150 - MOSFET metal electrode, 151 - Source, 152 - Gate, 153 - Drain, 160 - Trench isolation dielectric layer, 170 - MOSFET via metal, 180 - MOSFET lead electrode, 181 - MOSFET source lead, 182 - MOSFET gate lead

[0054] 200 - Recessed window, 210 - GaN buffer layer, 211 - AlN nucleation layer, 2121 - First AlGaN stress relief layer, 2122 - Second AlGaN stress relief layer, 2123 - Third AlGaN stress relief layer, 213 - Carbon-doped GaN layer, 214 - Unintentionally doped GaN channel layer, 220 - Main AlGaN barrier layer, 221 - AlN space charge isolation layer, 222 - AlGaN barrier layer, 223 - GaN capping layer, 224 - In-situ grown SiN layer, 230 - Al2O3 passivation layer, 240 - Insulating isolation region, 250 - GaN HEMT metal electrode, 251 - Source electrode, 252 - Gate electrode, 253 - Drain electrode, 260 - Passivation dielectric layer, 270 - GaN HEMT via metal, 280 - GaN HEMT lead electrode, 282 - GaN HEMT gate lead, 283-GaN HEMT drain lead

[0055] 300 - Metallic interconnect wire, 400 - Insulating medium. Detailed Implementation

[0056] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0057] Example

[0058] like Figures 1 to 7As shown, this embodiment provides a method for integrating a selected-area epitaxial GaN-on-Si HEMT direct-drive single-chip. This single-chip integrates a normally-off silicon MOSFET device and a normally-on GaN MIS-HEMT device, which are cascaded via on-chip metal interconnects to form a four-terminal normally-off power switch. The drain of the GaN MIS-HEMT device is the high-potential loading terminal of the single-chip, and its gate is the main control direct-drive terminal of the single-chip. The gate of the silicon MOSFET device is the series on / off terminal of the single-chip, providing node clamping and protection, and is connected to a pulse width modulation (PWM) circuit. Its source is the ground terminal or a low-potential terminal of the single-chip.

[0059] The specific construction of this single-chip integrated structure is as follows:

[0060] The silicon MOSFET device, from bottom to top, includes: a high-resistivity silicon substrate 100, a P-well region 110, an N+ heavily doped region 120, a gate oxide layer 130, a polysilicon layer 140, a MOSFET metal electrode 150, a trench isolation dielectric layer 160, a MOSFET via metal 170, and a MOSFET lead electrode 180. The GaN MIS-HEMT device, from bottom to top, includes: a recessed window 200 etched into the silicon substrate, a GaN buffer layer 210, a main AlGaN barrier layer 220 and an Al2O3 passivation layer 230, an insulating isolation region 240, a GaN HEMT metal electrode 250, a passivation dielectric layer 260, a GaN HEMT via metal 270, and a GaN HEMT lead electrode 280. The single-chip integration also includes on-chip metal interconnects 300 and an insulating dielectric 400 for the silicon MOSFET device and the GaN MIS-HEMT device.

[0061] The N+ heavily doped region 120 includes a source region doped well 121 and a drain region doped well 122; the MOSFET metal electrode 150 includes a source 151, a gate 152 and a drain 153; the MOSFET lead electrode 180 includes a MOSFET source lead 181 and a MOSFET gate lead 182.

[0062] The GaN HEMT metal electrode 250 includes a source electrode 251, a gate electrode 252, and a drain electrode 253; the GaN HEMT lead electrode 280 includes a GaN HEMT gate lead 282 and a GaN HEMT drain lead 283.

[0063] The GaN buffer layer 210 includes, from bottom to top, an AlN nucleation layer 211, three sets of AlGaN stress relief layers with gradient compositions, a carbon-doped GaN layer 213, and an unintentionally doped GaN channel layer 214. The three sets of AlGaN stress relief layers, from bottom to top, are a first AlGaN stress relief layer 2121, a second AlGaN stress relief layer 2122, and a third AlGaN stress relief layer 2123, with aluminum compositions of 0.75, 0.50, and 0.25, respectively. The main AlGaN barrier layer 220 includes, from bottom to top, an AlN space charge isolation layer 221, an AlGaN barrier layer 222, a GaN capping layer 223, and an in-situ grown SiN layer 224.

[0064] The specific configuration of each layer is as follows:

[0065] The AlN nucleation layer 211 has a thickness of 200 nm; the three AlGaN stress relief layers each have a thickness of 1.3 μm; the carbon-doped GaN layer 213 has a thickness of 1.1 μm and a carbon doping concentration of 3 × 10⁻⁶. 19 / cm 3 The unintentionally doped GaN channel layer 214 is an unintentionally doped n-type conductive layer with a thickness of 250 nm; the AlN space charge isolation layer 221 has a thickness of 1 nm; the AlGaN barrier layer 222 has an aluminum composition of 0.22-0.25 and a thickness of 18-20 nm; the GaN capping layer 223 is lightly n-type doped (1~3×10⁻⁶). 17 / cm 3 The thickness of the 224 in-situ grown SiN layer is 3nm; the thickness of the in-situ grown SiN layer 224 is 10nm.

[0066] In this embodiment, the active area of ​​the silicon MOSFET device is 350 μm. 2 The gate length, gate width, gate-drain spacing, and gate-source spacing are 1 μm, 50 μm, 1 μm, and 1 μm, respectively. The active area of ​​the GaN MIS-HEMT device is 1400 μm. 2 Its gate length, gate width, gate-drain spacing, and gate-source spacing are 1μm, 50μm, 2μm, and 15μm, respectively. The interconnect distance between the two devices is 40μm. This single-chip integrated wiring circuit includes the drain and gate terminals of the GaN MIS-HEMT device as high-voltage, high-speed power switches, also known as direct-drive terminals; and the gate terminal of the silicon MOSFET device as a low-voltage, logic-level controlled series switch, providing node clamping and protection.

[0067] The specific preparation process is as follows:

[0068] First, select a high-resistivity silicon substrate 100, which can be represented as HR-Si(111), with a resistivity of 4000-15000Ω·cm and a size of 6 inches or 8 inches. This crystal orientation is suitable for the epitaxial growth of GaN materials, and the high-resistivity characteristics help reduce substrate loss in radio frequency applications.

[0069] II. Recessed Window Etching: The silicon substrate undergoes standard cleaning. A SiO2 layer with a thickness of approximately 100 nm is deposited on the silicon substrate surface using chemical vapor deposition (CVD) as a mask layer. Subsequently, an amorphous silicon layer with a thickness of approximately 20–50 nm is sputtered as a hard mask auxiliary layer. Photolithography is then applied to define the window pattern of the GaN device region. Dry etching is performed using deep silicon etching techniques (such as the Bosch process), with the etching depth controlled at approximately 5.5 μm, forming the recessed window 200. In this embodiment, the window size is 60 μm × 80 μm.

[0070] After etching, wet oxidation etching is used to remove the plasma damage layer at the bottom of the window, followed by resist removal, cleaning, and drying. During this process, the mask layer effectively protects the silicon substrate surface in the non-window area (i.e., the silicon MOSFET device area) from damage.

[0071] Selective epitaxial growth of GaN HEMT structures: An etched silicon substrate is fed into a metal-organic chemical vapor deposition (MOCVD) reaction chamber for selective epitaxial growth. Because GaN material is grown only within the recessed window, the non-window areas are masked, thus achieving targeted deposition of the material.

[0072] The epitaxial growth process, from bottom to top, is as follows:

[0073] First, an AlN nucleation layer 211 with a thickness of approximately 200 nm is grown to initialize crystal growth;

[0074] Then, three sets of AlGaN stress relief layers with gradient compositions were grown, with aluminum compositions of 0.75, 0.50 and 0.25, respectively, and each set having a thickness of about 1.3 μm. This layer gradient configuration effectively buffered the stress caused by the difference in lattice constant and thermal expansion coefficient between GaN and Si.

[0075] Next, a carbon-doped GaN layer 213 with a thickness of about 1.1 μm is grown to improve the breakdown voltage of the device and suppress leakage current in the buffer layer.

[0076] Subsequently, an unintentionally doped GaN channel layer 214 with a thickness of approximately 250 nm was grown to form a channel with high electron mobility.

[0077] Next, an AlN space charge isolation layer 221 with a thickness of about 1 nm is grown sequentially, an AlGaN barrier layer 222 with an aluminum composition of 0.22-0.25 and a thickness of 18-20 nm is grown, a GaN capping layer 223 with a thickness of about 3 nm is grown, and finally a SiN layer 224 with a thickness of about 10 nm is grown in situ.

[0078] By precisely controlling the epitaxial growth parameters, the total thickness of the GaN HEMT epitaxial structure is matched with the depth of the recessed window. After growth, the surface of the GaN HEMT epitaxial structure is basically at the same level as the original surface of the silicon substrate.

[0079] III. Surface Treatment and Isolation: After epitaxial growth, an Al2O3 passivation layer 230 with a thickness of approximately 10 nm is deposited on the entire wafer surface using an atomic layer deposition (ALD) device. This layer serves as both part of the gate insulating dielectric layer of the GaN MIS-HEMT device and as an etch stop layer in subsequent processes. Annealing in an oxidizing atmosphere is then performed to improve the quality of the dielectric film.

[0080] Next, photolithography and dry etching processes are used to remove all dielectric thin film materials deposited on the non-window area (silicon MOSFET device area), including Al2O3 passivation layer, in-situ SiN layer, GaN-type deposits, amorphous silicon layer, mask layer, etc., until the original silicon substrate surface is completely exposed, and wet etching is used to remove any possible ionic damage to the surface.

[0081] Subsequently, an isolation process was performed on the GaN device region. Photolithography was used to coat the active region of the GaN MIS-HEMT device, preserving the active region pattern. Fe+ ion implantation was then performed around the active region to form an insulating isolation region 240. In this embodiment, the active region size was defined as 28 μm × 50 μm, the implantation energy as 40 keV, and the implantation dose as 2 × 10⁻⁶. 14 / cm 2 The implantation depth was 0.3 μm. Fe+ ions were chosen because they have a high thermal budget, enabling them to withstand the high-temperature processes of subsequent silicon MOSFETs without performance degradation, and ensuring effective electrical isolation between devices.

[0082] IV. Fabrication of Silicon MOSFET Devices: On the exposed silicon substrate area and the existing GaN area, silicon MOSFET devices are fabricated according to the standard CMOS process flow.

[0083] The specific process is as follows:

[0084] First, a trench isolation dielectric layer 160 is prepared by thermal oxidation and CVD deposition, and then a trench isolation structure is formed by photolithography etching to define the MOSFET active region, which has a size of 7μm×50μm.

[0085] Then, B+ ion implantation and annealing are performed to form a P-well region 110 with a resistivity of about 1 Ω·cm. The annealing temperature is controlled below 850°C and the time does not exceed 1 hour.

[0086] Next, a gate oxide layer 130 with a thickness of approximately 10 nm is grown by thermal oxidation. The material is SiO2, and considering the thermal budget, the oxidation temperature does not exceed 850℃. Then, a polysilicon layer 140 with a thickness of approximately 2 μm is deposited on the gate oxide layer by CVD at a deposition temperature of 650℃. Finally, the gate structure is formed by annealing, photolithography, and etching processes. In this embodiment, the gate length is 1 μm and the gate width is 50 μm.

[0087] Subsequently, high-dose P+ and As+ ion implantation and annealing are performed to form an N+ heavily doped region 120, containing a source region doped well 121 and a drain region doped well 122. The P+ ion implantation depth is relatively deep, while the As+ ion implantation is shallow. The overall implantation depth is controlled at 0.2-0.3 μm, and the annealing temperature does not exceed 900℃, with an annealing time not exceeding 1 hour. This process requires strict control of the thermal budget to avoid excessive thermal shock to the GaN material.

[0088] Finally, MOSFET metal electrodes 150 were fabricated. SiO2 was deposited via PECVD as the interlayer dielectric, and vias were created using photolithography. Metals were then deposited to form the source 151, gate 152, and drain 153. The gate metal electrode material was a TiN / Ti / Al / TiN stacked structure with thicknesses of 40 / 20 / 150 / 20 nm, while the source and drain metal electrodes were Ti / Al / Ti / TiN stacked structures with thicknesses of 20 / 100 / 20 / 30 nm. After deposition, rapid annealing was performed at approximately 550°C for no more than 60 seconds to form good ohmic contacts.

[0089] V. Fabrication of GaN MIS-HEMT Devices: After the silicon MOSFET devices are fabricated, the GaN MIS-HEMT devices are fabricated on the GaN HEMT epitaxial structure.

[0090] The specific process is as follows:

[0091] First, a Si3N4 layer with a thickness of approximately 120 nm was deposited by PECVD as a passivation medium layer 260.

[0092] Then, Si3N4 was removed from the gate window by photolithography and dry etching, with the etching stopping at the surface of the Al2O3 passivation layer. After cleaning, TiN / Ti / Al / TiN (thickness 20 / 60 / 100 / 20nm) was deposited by PVD sputtering as the gate electrode 252, followed by photolithography etching, and then Si3N4 was deposited by PECVD to passivate the gate electrode.

[0093] Next, photolithography and etching were performed on the source and drain windows to remove the Si3N4 and Al2O3 layers in the corresponding areas until the GaN capping layer 223 was exposed. Then, Ti / Al / Ti / TiN (thickness 20 / 120 / 20 / 20 nm) was deposited by PVD sputtering as the source electrode 251 and drain electrode 253. Subsequently, alloying was achieved by annealing at 550°C for approximately 60 seconds in a nitrogen atmosphere to improve the ohmic contact resistance of the electrodes. Finally, Si3N4 was deposited by PECVD for passivation protection of the electrodes.

[0094] VI. On-chip metal interconnect technology: Perform on-chip metal interconnects to achieve cascaded integration.

[0095] The specific process is as follows:

[0096] First, SiO2 was deposited via PECVD and silicon glass (SOG) was spin-coated for planarization and filling, followed by chemical mechanical polishing (CMP) to flatten the wafer surface. Electrode contact vias for silicon MOSFET devices and GaN MIS-HEMT devices were then etched using photolithography.

[0097] Then, Ti / TiN is sputtered into the channel and annealed. Next, tungsten seed crystals are deposited by CVD and tungsten metal is deposited to fill the through holes. The tungsten metal on the surface is then smoothed by chemical mechanical polishing (CMP) to form MOSFET through hole metal 170 and GaN HEMT through hole metal 270, exposing the tungsten metal connection points at the through hole locations.

[0098] Next, an Al-Si-Cu alloy layer (98.5% Al, 1% Si, and 0.5% Cu) is deposited by PVD, and then metal interconnect 300 is formed by photolithography etching. This metal interconnect 300 directly connects the drain 153 of the silicon MOSFET device to the source electrode 251 of the GaN MIS-HEMT device. At this point, the spacing between the two devices is determined solely by the process design; in this embodiment, it is controlled to be 30-50 μm, significantly shortening the current path.

[0099] Subsequently, the dielectric deposition, via fabrication, channel filling, and alloy layer deposition processes were repeated to fabricate a second layer of metal leads as single-chip lead electrodes. These include a MOSFET source lead 181 serving as the chip source, a MOSFET gate lead 182 serving as the auxiliary control terminal, a GaN HEMT gate lead 282 serving as the main drive terminal, and a GaN HEMT drain lead 283 serving as the chip drain. Finally, a surface passivation layer was deposited to form an insulating dielectric 400, and vias were created to form chip electrode pads.

[0100] The direct-drive single-chip fabricated using the above process not only achieves heterogeneous integration of GaN and silicon devices, but also significantly reduces parasitic parameters through extremely short on-chip interconnects. This solves the problems of high switching losses and severe voltage overshoot caused by parasitic inductance in traditional packaged cascade solutions, thereby improving the high-frequency performance and reliability of power devices.

[0101] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any changes made based on the design principles of the present invention, or any non-creative modifications made thereon, shall fall within the scope of protection of the present invention.

Claims

1. A method for selecting region epitaxial GaN-on-Si HEMT direct-drive single-chip integration, characterized in that, include: A silicon substrate is provided, on which a GaN device region and a silicon MOSFET device region are defined, with the two device regions spaced 30~50μm apart; A recessed window is etched to form the GaN device region on the silicon substrate, and a GaN HEMT epitaxial structure is grown within the recessed window by selective epitaxy. A silicon MOSFET device is fabricated in the silicon MOSFET device region of the silicon substrate; Fabricate a GaN MIS-HEMT device on the GaN HEMT epitaxial structure; The drain of the silicon MOSFET device is electrically connected to the source of the GaN MIS-HEMT device through on-chip metal interconnect technology to form a cascaded single-chip integration. The silicon MOSFET device is normally off, the GaN MIS-HEMT device is normally on, and the gate of the GaN MIS-HEMT device is independently led out as the main control electrode of the single chip for direct driving.

2. The selected area epitaxial GaN-on-Si HEMT direct-drive single-chip integration method according to claim 1, characterized in that, The depth of the recessed window is adapted to the thickness of the GaN HEMT epitaxial structure, so that the surface of the GaN HEMT epitaxial structure and the surface of the silicon substrate are at the same level or approximately at the same level. The fabrication process of the recessed window includes: depositing a mask layer on the surface of a silicon substrate, forming the recessed window through photolithography and dry etching processes, and performing wet etching on the bottom surface of the window to remove the damaged layer.

3. The selected-area epitaxial GaN-on-Si HEMT direct-drive single-chip integration method according to claim 2, characterized in that, The growth process of the GaN HEMT epitaxial structure adopts MOCVD technology, and from bottom to top includes: an AlN nucleation layer, multiple sets of AlGaN stress relief layers with gradient composition, a carbon-doped GaN layer, an unintentionally doped GaN channel layer, an AlN space charge isolation layer, an AlGaN barrier layer, a GaN capping layer, and an in-situ grown SiN layer; wherein, the aluminum composition of the AlGaN stress relief layer is set in a gradient decreasing manner along the growth direction to buffer the lattice mismatch and thermal mismatch stress between GaN and silicon substrate.

4. The selected-area epitaxial GaN-on-Si HEMT direct-drive single-chip integration method according to claim 3, characterized in that, After the GaN HEMT epitaxial structure is grown, the following steps are also included: An Al2O3 passivation layer was deposited on the surface of the GaN HEMT epitaxial structure using atomic layer deposition (ALD). The GaN epitaxial material and mask layer on the surface of the silicon MOSFET device region are removed by etching process to expose the surface of the silicon substrate; An insulating isolation region between devices is formed in the GaN device region by ion implantation. The insulating isolation region is formed by Fe+ ion implantation, and the implantation depth covers the unintentionally doped GaN channel layer.

5. The selected-area epitaxial GaN-on-Si HEMT direct-drive single-chip integration method according to claim 1, characterized in that, The fabrication process of the silicon MOSFET device includes: A trench isolation process is performed in the silicon MOSFET device region to form an active region; P-well regions are formed by ion implantation and then activated by annealing. A gate oxide layer is grown by thermal oxidation, and a polysilicon layer is deposited and patterned to form a gate structure; N+ heavily doped regions for the source and drain regions are formed by ion implantation, followed by rapid thermal annealing. Deposit and pattern metal electrode material to form the source, gate, and drain of the silicon MOSFET device.

6. The selected-area epitaxial GaN-on-Si HEMT direct-drive single-chip integration method according to claim 5, characterized in that, The gate metal electrode material of the silicon MOSFET device is a TiN / Ti / Al / TiN stacked structure, and the source and drain metal electrode materials are Ti / Al / Ti / TiN stacked structures. The silicon MOSFET device has B+ implanted impurities in the P-well region with a resistivity of 0.5~2 Ω·cm; and P+ and As+ implanted impurities in the N+ heavily doped region with an implantation depth of 0.2~0.3μm.

7. The selected-area epitaxial GaN-on-Si HEMT direct-drive single-chip integration method according to claim 4, characterized in that, The fabrication process of the GaN MIS-HEMT device includes: A passivation dielectric layer is deposited on the GaN HEMT epitaxial structure; The passivation dielectric layer is etched until the Al2O3 passivation layer of the gate region is exposed, and gate metal is deposited to form the gate electrode; The passivation dielectric layer and Al2O3 passivation layer are etched until the GaN capping layer of the source and drain regions is exposed. Source metal and drain metal are deposited to form source electrodes and drain electrodes, respectively, and then annealed and alloyed.

8. The selected-area epitaxial GaN-on-Si HEMT direct-drive single-chip integration method according to claim 7, characterized in that, The gate electrode of the GaN MIS-HEMT device is a TiN / Ti / Al / TiN stacked structure, and the source and drain electrodes are Ti / Al / Ti / TiN stacked structures.

9. The selected area epitaxial GaN-on-Si HEMT direct-drive single-chip integration method according to any one of claims 1-8, characterized in that, The on-chip metal interconnect process includes: The interlayer medium is deposited and then subjected to chemical mechanical polishing planarization. Etching forms contact vias, exposing the drain of the silicon MOSFET device and the source of the GaN MIS-HEMT device, respectively; Fill the contact through-hole with through-hole metal; Interconnect metal is deposited and patterned to form a metal interconnect line connecting the drain of the silicon MOSFET device and the source of the GaN MIS-HEMT device. The interconnect metal line is arranged parallel to the surface of the silicon substrate, and its length corresponds to the spacing between the two device regions.

10. The selected-area epitaxial GaN-on-Si HEMT direct-drive single-chip integration method according to claim 9, characterized in that, It also includes the fabrication of lead electrodes, wherein the gate of the silicon MOSFET device is led out as the enable control terminal of the single chip, and the gate of the GaNMIS-HEMT device is led out as the high-speed drive terminal of the single chip.

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