Circuit for detecting short-circuit in full-bridge class-d amplifier and corresponding method

Abstract

The present disclosure relates to a circuit for detecting a short circuit in a full-bridge class-D amplifier and a corresponding method. A full-bridge class-D amplifier comprises a first branch having a first high-side switch and a first low-side switch coupled in series between a supply voltage and ground at a first output node, and a second branch having a second high-side switch and a second low-side switch coupled in series between the supply voltage and ground at a second output node. A circuit for detecting an electrical short circuit in an amplifier comprises a measurement circuit configured to provide a first measurement of high-side switch operation in one branch and a second measurement of low-side switch operation in the other branch, a check circuit configured to determine an imbalance between the first and second measurements to generate an imbalance signal, and a detection circuit configured to detect a presence of the electrical short circuit in response to the imbalance signal.

Description

[0001] Priority requirements

[0002] This application claims priority to Italian Patent Application No. 102024000027702, filed on December 6, 2024, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This description relates to a circuit for detecting short circuits in a full-bridge Class D amplifier.

[0004] One or more embodiments may be associated with circuitry used to detect short circuits in a full-bridge Class D amplifier via an imbalance check. Background Technology

[0005] Known Class D amplifiers for car radios typically include a full-bridge output stage coupled with two LC filters, and a single power supply usually included in the car battery.

[0006] Figure 1 The diagram illustrates a known structure 5 of a full-bridge Class D output stage, which has a short circuit applied to its output.

[0007] Figure 1 The full-bridge output stage of structure 5 illustrated in the figure includes: a first high-side switch HP, implemented, for example, via a first field-effect transistor (FET), coupled to a power supply (e.g., an automotive battery) configured to provide voltage VCC and the first output node Out of the output stage. P Between; a second high-side switch HM, for example implemented via a second FET, is coupled to a power supply (e.g., an automotive battery) configured to provide voltage VCC and the second output node Out of the output stage. M Between; the first low-side switch LP, for example, implemented via a third FET, is coupled to this first output node Out of the output stage. P Between the ground node GND and the second low-side switch LM, for example, implemented via a fourth FET, coupled to this second output node Out of the output stage. M Between and the ground node GND.

[0008] This output stage can be coupled to two LC filters: the first LC filter is Lfilt. P Second LC filter Lfilt M .

[0009] First LC filter Lfilt P Includes: the first output node Out coupled to the output stage P With the first output node OutLC of the LC filter stage P The first inductor L1 betweenP ; and the first output node OutLC coupled to the LC filter stage. P The first capacitor C between the ground node GND and the ground node GND P .

[0010] Second LC filter Lfilt M Includes: the second output node Out coupled to the output stage M With the second output node OutLC of the LC filter stage M The second inductor L2 M ; and the second output node OutLC coupled to the LC filter stage. M The second capacitor C between the ground node GND and the ground node GND M .

[0011] It should be noted that the load LD can be coupled to the first output node OutLC of the LC filter stage. P With the second output node OutLC of the LC filter stage M between.

[0012] The first high-side switch HP, the second high-side switch HM, the first low-side switch LP, and the second low-side switch LM can be implemented using N-DMOS (N-type "double-diffused MOS transistor"), N or P-DMOS types, GaN FET ("gallium nitride FET"), or any other available semiconductor technology.

[0013] To protect power audio amplifiers and other output stages that utilize pulse width modulation (PWM), such as Figure 1 The output of the device (as shown in the diagram, a full-bridge output stage) is designed to prevent short circuits.

[0014] For example, such a short circuit might be caused by one of the output terminals (after the LC filter) being connected to ground node GND, connected to a power supply configured to provide voltage VCC, or connected to another output terminal different from the load LD. The output terminal could be, for example, the first output node OutLC of the LC filter stage. P (like Figure 1 (As shown in the diagram) or the second output node OutLC of the LC filter stage M They are typically coupled to the load LD under normal driving conditions (i.e., without short circuits).

[0015] For example, such a connection can be implemented via an impedance ZS (such as a resistor) having a (even very) low value, for example, an impedance ZS on the order of a few milliohms (“mΩ”); or via RL in series, i.e., a resistor-inductor circuit having a resistor R coupled in series with an impedance L.

[0016] Another possible short circuit is due to the first output node Out. P Or the second output node Out M This is caused by connecting to ground node GND (before the LC filter), connecting to a power supply configured to provide voltage VCC, or connecting to another output terminal.

[0017] In this case, the time associated with the rise of the current flowing in the output stage may depend on the impedance ZS of the short-circuit connection.

[0018] For example, in applications without filters (also used in audio systems), this additional short circuit may exist, namely, in a full-bridge output stage not coupled to an LC filter, where the first output node Out... P Second output node Out M Directly drives the load LD.

[0019] In a full-bridge Class D amplifier, the detection of such a short circuit is typically achieved by comparing a sensed signal to a reference signal, such as a sensed voltage (e.g., the voltage drop across one of the transistors included in the output stage or the voltage drop across a resistor) that is proportional to the output current used to drive the load LD, and a reference signal such as a reference voltage (e.g., obtained by injecting a reference current into an element that matches the transistor or resistor in question).

[0020] Figure 2 The diagram illustrates a known circuit 10 for detecting output current overload SD by sensing the Vds voltage, where Vds voltage is the absolute FET voltage between the current sink (drain) terminal and the current supply (source) terminal of the low-side transistor LM or LP of the full-bridge Class D output stage.

[0021] The sensed Vds voltage of the low-side transistor LM or LP in the full-bridge Class D output stage is considered to be related to the output current I used to drive the load LD. out Proportional sensing signal V sens .

[0022] Figure 2 The low-side transistor LM or LP illustrated is driven by driver 102 via its control (gate) terminal and has an output current I for driving the load LD. out The output current I out Current flows between the current sink (drain) terminal and the current supply (source) terminal of the low-side transistor LM or LP.

[0023] The Vds voltage V of the low-side transistor LM or LP in the full-bridge Class D output stage sensThe current is sensed by coupling the current sink (drain) terminal of the low-side transistor LM or LP to the first input terminal of the comparator 100.

[0024] The second input terminal of comparator 100 is configured to receive a reference voltage V. ref For example, the reference voltage is related to the reference transistor L. ref (with width value W) ref and channel length value L min The reference transistor L corresponds to the Vds voltage of ) ref Compared to low-side transistors LM or LP (with, for example, a typical ratio W) ref A width value W that is 100 times larger main and the same channel length value L min This reference transistor L is matched and coupled between the power supply at voltage VCC and ground GND. ref An injected reference current I flows between its current sink (drain) terminal and its current supply (source) terminal. ref .

[0025] It is important to note that this reference current I ref With this reference transistor L ref The maximum current allowed to flow corresponds to this, and, due to this reference transistor L ref It is matched with the low-side transistor LM or LP, and therefore corresponds to the maximum current allowed to flow in the low-side transistor LM or LP.

[0026] Therefore, the reference voltage V ref Acting as a threshold, compared with the reference transistor L ref The maximum allowable Vds voltage corresponds to this, and again, due to this reference transistor L ref It is matched with the low-side transistor LM or LP, and therefore corresponds to the maximum Vds voltage allowed in the low-side transistor LM or LP.

[0027] Therefore, comparator 100 is configured to receive the sensed Vds voltage V sens (at the first input terminal) and reference voltage V ref (At the second input terminal); compare such voltages to determine the sensed Vds voltage V. sens Is it higher than the reference voltage V that serves as the threshold? ref (i.e., the maximum allowable Vds voltage); and output logic variables, for example, when this sensed Vds voltage V sens When the voltage is above the reference voltage Vref, the logic variable has a high logic level; otherwise, it has a low logic level.

[0028] A logic variable is provided to a logic AND block 104, which is configured to receive such a logic variable and a signal from a driver 102. For example, if the driver 102 drives the low-side transistor LM or LP to the on state, then the logic AND block 104 has a high logic level, otherwise it has a low logic level.

[0029] Therefore, this logic AND block 104 is configured to detect short circuits, for example, by if the logic variable indicates the sensed Vds voltage V sens Higher than the reference voltage V ref (i.e., above the maximum allowable Vds voltage) and if a signal from driver 102 indicates that driver 102 is driving the low-side transistor LM or LP to the on state, then a short-circuit detection signal SD set to a high logic level is provided as an output.

[0030] It is important to note that the logic variable indicates the response to the current I supplied by the full-bridge Class D amplifier as the output. out This is equal to the maximum current I allowed to flow in this type of full-bridge Class D amplifier. OCP The sensed Vds voltage V sens Higher than the reference voltage V ref .

[0031] The maximum current I allowed to flow in this type of full-bridge Class D amplifier can be obtained using the following equation. OCP :

[0032]

[0033] Where I ref The reference current mentioned above, W main It is the width value of the low-side transistor LM or LP, and W ref It is the reference transistor L ref The width value.

[0034] In response to a short circuit detected by logic AND block 104, protection measures are enabled to prevent the full-bridge output stage from operating under unsafe conditions. For example, the full-bridge output stage can be placed in a tri-state condition, or cycle-by-cycle protection can be activated to reduce the current flowing in such an output stage.

[0035] As an alternative to the aforementioned Vds sensing, the voltage drop across the source metallization of a transistor (e.g., a DMOS transistor) included in a full-bridge Class D amplifier can be sensed. In this case, the voltage drop can be used as a voltage signal for current sensing and current reference measurement.

[0036] Traditional overcurrent protection (OCP) (such as Figure 2The problem with the known solutions is that the output current I provided by the full-bridge output stage for driving the load LD is... out The maximum permissible current (usually corresponding to the maximum absolute rating) must be reached, i.e., the aforementioned reference current I. ref Only when a short circuit is detected can the output stage of a full-bridge Class D amplifier be forced to operate under near-unsafe conditions.

[0037] Therefore, according to Figure 2 The solution must react (very) quickly in order to prevent the output current I used to drive the load LD from flowing out. out The value rises to a dangerous level, causing the full-bridge output stage to operate under unsafe conditions.

[0038] It is important to note that, according to Figure 2 The solution is used in applications such as car radio amplifiers that are supplied with, for example, a battery of about 14.4V (volts), where short-circuit protection is required as a standard.

[0039] In systems with higher supply voltages, such as up to approximately 48V, standards for short-circuit detection are not available, and according to Figure 2 The solution may not be able to activate short-circuit protection in a timely manner (i.e., before the full-bridge output stage enters unsafe operating conditions).

[0040] Typically, in such cases, some deviation from full compliance with short-circuit protection is accepted because the occurrence of destructive events under critical conditions (e.g., at high supply voltages, high temperatures, etc.) may be judged by the customer to be sufficiently low.

[0041] In fact, in applications such as car radio amplifiers that are supplied with higher supply voltages, such tests include, for example, connecting one of the outputs of the full-bridge output stage to a power supply at voltage VCC or to ground GND under several driving conditions, considering different impedances and temperatures, across the entire supply voltage range (i.e., for voltages included between zero and the higher supply voltages considered).

[0042] Therefore, in applications with higher supply voltages (i.e., supply voltages higher than battery voltages, for example, supply voltages above 14.4V), known solutions do not provide an acceptable trade-off between maximum operating conditions and reliable short-circuit protection.

[0043] Therefore, it would be beneficial to provide a solution that simplifies reliable short-circuit protection even for supply voltages with high values ​​(e.g., values ​​above 14.4V), in order to improve safety and prevent dangerous or fault conditions.

[0044] Accordingly, there is a need in the art to provide solutions that facilitate reliable short-circuit protection even for supply voltages with high values, in order to improve the safety of full-bridge Class D amplifiers and prevent dangerous or fault conditions. Summary of the Invention

[0045] One or more embodiments relate to a circuit for detecting a short circuit in a full-bridge Class D amplifier.

[0046] One or more embodiments relate to corresponding methods.

[0047] The solution described herein addresses the aforementioned limitations via circuitry for detecting short circuits in a full-bridge Class D amplifier. This circuitry is configured to: check for an imbalance between measurements associated with the high-side switches of one branch of the full-bridge and measurements associated with the low-side switches of another branch of such a full-bridge; and, in response to an indication that an imbalance exists, detect the presence of a short circuit.

[0048] Therefore, the solution described herein relates to a circuit for detecting electrical short circuits in a full-bridge Class D amplifier.

[0049] The full-bridge Class D amplifier includes: a first branch including a first high-side switch configured to couple between a supply voltage and a first output node and a first low-side switch configured to couple between such first output node and ground; and a second branch including a second high-side switch configured to couple between such supply voltage and a second output node and a second low-side switch configured to couple between such second output node and ground.

[0050] The circuit according to the solution described herein includes: a measurement circuit configured to provide: a first measurement result of a first operating characteristic (e.g., current, voltage, or time delay) of a high-side switch included in one of the first and second branches of a full-bridge Class D amplifier; and a second measurement result of a second operating characteristic (e.g., current, voltage, or time delay) of a low-side switch included in the other of the first and second branches of the full-bridge Class D amplifier; a checking circuit configured to receive the first and second measurement results from the measurement circuit and provide an imbalance signal indicating the presence of an imbalance between the first and second measurement results; and a detection circuit configured to receive the imbalance signal from the checking circuit and detect the presence of an electrical short circuit in response to the imbalance signal indicating an imbalance between the first and second measurement results.

[0051] The solutions described in this article can be implemented through different methods.

[0052] The first method involves detecting short-circuit conditions based on current measurements.

[0053] In the solution based on this first method, a current sensor is added to each of the four switches HP, LP, HM and LM of the full bridge.

[0054] A short circuit to the supply voltage or to ground can be detected when there is an imbalance between the current measured in the high-side switch (i.e., HP or HM) of one branch of the full bridge and the current measured in the low-side switch (i.e., LM or LP, respectively) of the other branch of the full bridge.

[0055] Current sensors can be implemented in different ways.

[0056] For example, one way to implement a current sensor involves using a reference voltage as a reference for a flash ADC and converting the sensed voltage, which is proportional to the current flowing in the corresponding switch, via this flash ADC. In this case, an imbalance can be detected when the converted values ​​for two different switches in the on state are above a threshold.

[0057] For example, a second way to implement such a current sensor involves level shifting to a common internal voltage or ground and comparing the sensed voltage with the current flowing in the corresponding switch when it is in the ON state. In this case, an imbalance can be detected when the difference between the two sensed voltages is above a threshold.

[0058] The second method involves detecting short-circuit conditions again based on current measurement results.

[0059] In the solution according to this second method, the current sensor is placed on the output of each of the two half-bridges.

[0060] In this situation, a short circuit to the supply voltage or to ground can be detected when there is an imbalance between the currents measured in the two half-bridges.

[0061] In the solution according to the second method, the current sensor can be made of a shunt resistor or by the Hall effect.

[0062] Other methods include detecting short-circuit conditions based on time-based measurements.

[0063] The solution according to this alternative method includes measuring the following current-dependent time delays in each pulse width modulation (PWM) cycle (where a PWM cycle is the cycle of a PWM signal generated for driving a half-bridge included in a full bridge via a respective driver configured to operate a respective switch included in such a half-bridge): these time delays correspond to the time lap between the input signal provided to the driver coupled to the respective half-bridge included in the full bridge and the PWM output signal provided by a branch of such full bridge (i.e., the half-bridge): a first time delay indicating the delay from the rise of the input signal provided to the driver associated with the branch of the full bridge (i.e., the half-bridge of the full bridge) to the corresponding rise of the PWM output signal provided by such branch of the full bridge (e.g., by the high-side switch of such branch); a second time delay indicating the delay from the fall of the input signal provided to the driver associated with such branch of the full bridge (i.e., the half-bridge of the full bridge) to the corresponding fall of the PWM output signal provided by such branch of the full bridge (e.g., by the low-side switch of such branch); and a third time delay indicating... The delay from the rise of the input signal provided to the driver associated with the other branch of the full bridge (i.e., the other half-bridge of the full bridge) to the corresponding rise of the PWM output signal provided as an output by such another branch of the full bridge (e.g., the high-side switch of such another branch); and the fourth time delay indicating the delay from the fall of the input signal provided to the driver associated with the other branch of the full bridge (i.e., the other half-bridge of the full bridge) to the corresponding fall of the PWM output signal provided as an output by such another branch of the full bridge (e.g., the low-side switch of such another branch).

[0064] Furthermore, solutions based on this alternative method include detecting a short circuit to the supply voltage or to ground when there is an imbalance between the third time delay and the second time delay or between the first time delay and the fourth time delay.

[0065] It is important to note that in "BD" type modulation, the time delay can be stored in a capacitor through voltage conversion and then processed; while in "AD" type modulation, this time delay can be processed directly.

[0066] Therefore, the solution described herein facilitates reliable short-circuit detection and protection. For example, the solution described herein also facilitates reliable short-circuit detection in the presence of supply voltages with high values ​​(e.g., values ​​above 14.4V). Thus, the solution described herein improves the trade-off between safety and performance (i.e., maximum operating supply voltage and maximum load current) and can prevent dangerous or fault conditions in full-bridge Class D amplifiers due to the presence of such short circuits. Attached Figure Description

[0067] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0068] As mentioned above, Figure 1 The diagram illustrates a known structure of a full-bridge Class D output stage, with a short circuit applied to the output of this structure;

[0069] As mentioned above, Figure 2 The diagram illustrates a known circuit for detecting output current overload by sensing the Vds voltage of the low-side transistor in the full-bridge Class D output stage.

[0070] Figure 3 The illustration shows a first exemplary circuit for detecting short circuits based on current sensing.

[0071] Figure 4 The diagram illustrates the following: Figure 3 An exemplary current sensing block used in the embodiments and configured to perform conversion operations via an analog-to-digital converter (ADC) circuit;

[0072] Figure 5 The diagram illustrates the following: Figure 3 Another exemplary current sensing block used in the embodiments and configured to perform a comparison operation via a comparator block;

[0073] Figure 6 The illustration shows a second exemplary circuit for detecting short circuits based on current sensing;

[0074] Figure 7A and Figure 7B The diagram illustrates the following: Figure 6 The exemplary current sensing block used in the embodiments;

[0075] Figure 8 An exemplary circuit is illustrated for managing a pulse width modulation (PWM) signal used to drive a full-bridge Class D amplifier;

[0076] Figure 9 The diagram illustrates the time delay behavior of the output current supplied by the full-bridge Class D amplifier to the load coupled to it.

[0077] Figure 10A and Figure 10B The diagram illustrates a full-bridge Class D amplifier with a short circuit to ground;

[0078] Figure 11A and Figure 11B The diagram illustrates a full-bridge Class D amplifier with a short circuit to the supply voltage;

[0079] Figure 12A , Figure 12B and Figure 12CThe diagram illustrates the behavior of the leading edge of the signal supplied as the output by a full-bridge Class D amplifier;

[0080] Figure 13 The diagram illustrates a third exemplary circuit for detecting short circuits based on time measurements under "BD" type modulation conditions; and

[0081] Figure 14 The diagram illustrates another exemplary circuit for detecting short circuits based on time measurements under “AD” type modulation conditions. Detailed Implementation

[0082] Unless otherwise indicated, the corresponding numbers and symbols in different figures generally refer to the corresponding parts.

[0083] The accompanying drawings are provided to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0084] The edges of features drawn in a diagram do not necessarily indicate the end of the feature's range.

[0085] In the following description, one or more specific details are set forth to provide a thorough understanding of examples of embodiments described herein. Embodiments may be obtained without one or more of these specific details or using other methods, components, materials, etc. In other instances, known structures, materials, or operations are not described in detail so as not to obscure certain aspects of the embodiments.

[0086] References to "embodiment" or "one embodiment" within the framework of this description are intended to indicate that a particular configuration, structure, or feature described in relation to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more places in this description do not necessarily refer to the same embodiment.

[0087] Furthermore, specific configurations, structures, or features can be combined in any suitable manner in one or more embodiments.

[0088] The title / figure references used herein are provided for convenience only and do not define the degree of protection or the scope of the embodiments.

[0089] For the sake of simplicity and ease of explanation, similar parts or elements are indicated by similar reference numerals in the various figures unless the context otherwise indicates, and the corresponding description will not be repeated for each figure.

[0090] As previously stated, the solutions disclosed herein facilitate the provision of reliable short-circuit detection and protection features even in the presence of supply voltages with high values ​​(e.g., values ​​above 14.4V), thereby improving the trade-off between safety and performance (i.e., maximum operating supply voltage and maximum load current) and preventing dangerous or fault conditions due to the presence of such short circuits.

[0091] Therefore, the solutions described herein aim to improve the robustness of full-bridge Class D amplifiers (e.g., used in car radio systems) to prevent short circuits to the supply voltage VCC, ground GND, or battery voltage (if different from the supply voltage VCC).

[0092] Furthermore, the solution described herein can advantageously distinguish between a short circuit to ground (GND) or to the supply voltage (VCC) for a (even very) short time (e.g., within a few periods of the pulse width modulation (PWM) signal used to drive a full-bridge Class D amplifier) ​​relative to normal driving conditions (i.e., driving conditions without short circuits).

[0093] The detection of this short circuit can be independent of the output current I supplied by the full-bridge Class D amplifier to its coupled load LD. out The value (i.e., independent of the output current I) out It is performed relative to the maximum current allowed to flow in the switches of the full bridge.

[0094] Therefore, there exists an output current I that is lower than the maximum current allowed to flow in the transistors of a full-bridge Class D amplifier. out Even under these conditions, a short circuit can be detected; this is the maximum allowable current I. OCP This is obtained via the equation described above, that is, by measuring the width value W of the transistors included in the full-bridge Class D amplifier. main Divided by reference transistor L ref Width value W ref Thus, the value is obtained. Then the value Multiply by the reference current I described earlier ref The value of .

[0095] It is important to note that this maximum current I allowed to flow in the transistors of a full-bridge Class D amplifier is... OCP A threshold is typically defined for enabling overcurrent protection (OCP), thus allowing more time for such short-circuit protection measures to be activated before the full-bridge output stage enters unsafe operating conditions.

[0096] For example, there exists an output current I that is equal to or less than half the value of the maximum current allowed to flow in the transistors of a full-bridge Class D amplifier. outWhen the value is set, a short circuit can be detected.

[0097] It should be noted that even though some descriptions focus on full-bridge Class D amplifiers used in audio applications, the solutions described herein can also be applied to any full-bridge Class D amplifier that must detect a short circuit to ground (GND) or to the supply voltage (VCC) at the output.

[0098] The solution described herein relates to circuitry for detecting short circuits in a full-bridge Class D amplifier based on the following operations: a check operation to verify the presence of an imbalance between measurements associated with the high-side switches of one branch of the full bridge (i.e., with the first high-side switch HP or the second high-side switch HM) and measurements associated with the low-side switches of the other branch of such a full bridge (i.e., with the second low-side switch LM or the first low-side switch LP, respectively); and a detection operation to detect a short circuit to ground GND or to the supply voltage VCC (or battery voltage, if different) if the check operation indicates an imbalance between such measurements.

[0099] Therefore, the solution described herein refers to the method for detecting full-bridge Class D amplifiers (such as...) Figure 1 The circuitry of the full-bridge Class D amplifier 5 shown in the figure includes electrical short circuits (e.g., short circuits to ground GND, to the supply voltage VCC, or to the battery voltage (if different from the supply voltage VCC)).

[0100] Therefore, this full-bridge Class D amplifier 5 includes: a first branch, the first branch including components configured to be coupled to the supply voltage VCC and a first output node Out. P The first high-side switch HP is configured to be coupled to this first output node Out. P A first low-side switch LP is connected to ground GND; and a second branch includes components configured to couple to the second output node Out at this supply voltage VCC. M The second high-side switch HM between them is configured to be coupled to this second output node Out. M The second low-side switch LM between GND and ground.

[0101] The circuit according to the solution described herein includes: a measurement circuit configured to provide a first measurement result (e.g., current, voltage, or time measurement result) of a first operating characteristic of a high-side switch (e.g., HP or HM) in one of the first and second branches of a full-bridge Class D amplifier 5, and a second measurement result (e.g., current, voltage, or time measurement result) of a second operating characteristic of a low-side switch (e.g., LM or LP, respectively) in the other of the first and second branches of the full-bridge Class D amplifier 5; a checking circuit configured to receive the first and second measurement results from the measurement circuit and provide an imbalance signal indicating the presence of an imbalance between the first and second measurement results; and a detection circuit configured to receive the imbalance signal from the checking circuit and detect the presence of an electrical short circuit in response to the imbalance signal indicating an imbalance between the first and second measurement results.

[0102] As previously mentioned, the solutions disclosed herein can be implemented through different methods, such as current-based methods or time-based methods.

[0103] Therefore, the measurements associated with the high-side switches of one branch of the full bridge and the measurements associated with the low-side switches of the other branch of this full bridge can be current measurements.

[0104] The measurement results associated with the high-side switch of one branch of the full bridge are the measurement results of the current flowing in this high-side switch, and the measurement results associated with the low-side switch of the other branch of this full bridge are the measurement results of the current flowing in this low-side switch.

[0105] Alternatively, the measurements associated with the high-side switches of one branch of the full bridge and the measurements associated with the low-side switches of the other branch of such a full bridge can be time measurements.

[0106] In this case, the measurement results associated with the high-side switches of the full bridge branches are the measured time delays from the rising edge of the drive signal provided to the driver configured to drive such high-side switches to the corresponding rising edge of the output signal provided by such high-side switches.

[0107] Similarly, the measurement results associated with the low-side switch of another branch of this full bridge are the measured time delays from the falling edge of the drive signal provided to the driver configured to drive such a low-side switch to the corresponding falling edge of the output signal provided by such a low-side switch.

[0108] Therefore, in view of the above, the solution described herein can refer to the first and second measurement results as current-based measurement results.

[0109] For example, a first measurement result may indicate the current flowing in the high-side switch HP or HM included in one of the first and second branches of the full-bridge Class D amplifier 5; and a second measurement result may indicate the current flowing in the low-side switch LM or LP included in the other of the first and second branches of the full-bridge Class D amplifier 5.

[0110] Similarly, the solution described herein can refer to a first measurement result and a second measurement result as time-based measurements.

[0111] In this configuration, the first and second branches of the full-bridge Class D amplifier 5 can be driven via corresponding drivers 102 configured to receive corresponding drive signals, such as the first input signal D described below. INP Or the second input signal D INM .

[0112] Therefore, for example, the first measurement result can indicate the time delay (denoted by the reference numeral T in the following description). d_r_P or T d_r_M (Reference): From the driver 102 provided to drive the high-side switch HP or HM included in one of the first and second branches of the full-bridge Class D amplifier 5. HP Or 102 HM The driving signal D INP Or D INM The rising edge of the signal is transmitted to the output signal provided by the high-side switch HP or HM (e.g., via the first output node Out). P Or via the second output node Out M The corresponding rising edge of the provided signal.

[0113] Similarly, for example, a second measurement result can indicate a time delay (denoted by reference numeral T in the following description). d_f_P or T d_f_M (Reference): From the driver 102 provided to drive the low-side switch LM or LP in another of the first and second branches of the full-bridge Class D amplifier 5. LP Or 102 LM The driving signal D INP Or D INM The falling edge of the signal is transmitted to the output signal provided by the low-side switch LM or LP (e.g., via the first output node Out). P Or via the second output node Out M The corresponding falling edge of the provided signal.

[0114] The first method involves detecting short-circuit conditions based on current measurements, for example, by the output terminals of the full bridge (i.e., by the first output node Out). P Or the second output node Out M The result is the measurement of the current supplied as the output.

[0115] This first method is based on reference. Figure 3 The first exemplary circuit 15 illustrated herein is described, which is configured to detect a short circuit based on current sensing according to an embodiment of the present description, for example, via control logic CL.

[0116] It is important to note that even in Figure 3 The transistors included in the full-bridge circuit in the other diagrams are n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but p-type MOSFETs can also be considered, as well as different types of FETs such as N-DMOS (N-type "double-diffused MOS transistors"), N or P-DMOS types, GaN FETs ("gallium nitride FETs"), or any other available semiconductor technology.

[0117] In the solution based on this first method, a current sensor I is added to each of the four switches HP, LP, HM, and LM included in the full bridge. sens .

[0118] Therefore, the first current sensor I sensHP It can be configured to sense the current flowing in the first high-side switch HP and send a signal indicating this sensed current to the control logic circuit CL. For this purpose, such a first current sensor I... sensHP It may have a first terminal coupled to a current sink (drain) terminal of a first high-side switch HP and a second terminal coupled to a current supply (source) terminal of such a first high-side switch HP.

[0119] Similarly, the second current sensor I sensHM It can be configured to sense the current flowing in the second high-side switch HM and send a signal indicating this sensed current to the control logic circuit CL. For this purpose, this second current sensor I... sensHM It may have a first terminal coupled to a current sink (drain) terminal of a second high-side switch HM and a second terminal coupled to a current supply (source) terminal of such a second high-side switch HM.

[0120] Third current sensor I sensLP It can be configured to sense the current flowing in the first low-side switch LP and send a signal indicating this sensed current to the control logic circuit CL. For this purpose, this third current sensor I... sensLPIt may have a first terminal coupled to a current sink (drain) terminal of a first low-side switch LP and a second terminal coupled to a current supply (source) terminal of such a first low-side switch LP.

[0121] Similarly, the fourth current sensor I sensLM It can be configured to sense the current flowing in the second low-side switch LM and send a signal indicating this sensed current to the control logic circuit CL. For this purpose, this fourth current sensor I... sensLM It may have a first terminal coupled to a current sink (drain) terminal of a second low-side switch LM and a second terminal coupled to a current supply (source) terminal of such a second low-side switch LM.

[0122] It is important to note that each of these current sensors I sens It may include an analog-to-digital (fast) converter for converting the sensed analog current flowing in the corresponding switch into a digital value indicating such sensed analog current so that it can be sent to control logic circuit CL, for example, via such a signal indicating the sensed current.

[0123] The control logic circuit CL can be configured to: detect the existence of an imbalance between the current sensed in the high-side switch of one branch of the full bridge (i.e., the current flowing in the first high-side switch HP or the second high-side switch HM) and the current sensed in the low-side switch of the other branch of the full bridge (i.e., the current flowing in the second low-side switch LM or the first low-side switch LP, respectively); and determine the existence of a short circuit to the supply voltage VCC (or to the battery voltage, if different) or to ground GND in response to such detection operation indicating the existence of an imbalance.

[0124] For example, an imbalance can be detected if the absolute difference between the current sensed in the high-side switch of one branch of the full bridge, either directly or via another conversion, and the current sensed in the low-side switch of the other branch of the full bridge is greater than a threshold.

[0125] In fact, a short circuit to the supply voltage VCC or to ground GND can cause one of the output terminals of the full bridge (i.e., the first output node Out) to short-circuit. P Or the second output node Out M An increase or decrease in the current in the bridge creates an imbalance between the current flowing in the high-side switch and the current flowing in the low-side switch, both of which are simultaneously in the on state.

[0126] Therefore, in the standard modulation of the full bridge, the first current sensor I is considered. sensHP The sensed current flowing in the first high-side switch HP and the current sensed by the fourth current sensor I sensLMThe imbalance between the sensed currents flowing in the second low-side switch LM, or by the second current sensor I. sensHM The sensed current flowing in the second high-side switch HM and the current sensed by the third current sensor I sensLP The imbalance between the currents sensed flowing in the first low-side switch LP.

[0127] It is important to note that this threshold can be set between 1 / 10 and 2 / 10 of the maximum rated output current that can be provided by the branches of the full bridge, taking into account the current ripple. In fact, the current flowing in each switch during conduction can be obtained as the sum of the current flowing in the load LD and the ripple current with a triangular wave shape.

[0128] Therefore, the aforementioned checking circuit (e.g., implemented via control logic circuit CL) of the circuit according to the solution described herein can be configured to check for the existence of an imbalance between the first measurement result and the second measurement result by the following steps: determining the absolute value of the difference between the first measurement result and the second measurement result; checking whether the absolute value of the difference is higher than a threshold, such as a current, voltage, or time threshold; and if the absolute value of the difference is higher than the threshold, then determining that an imbalance exists.

[0129] For example, such as Figure 3 The measurement circuit included in the circuit according to the scheme described herein, as illustrated in the figure, may include: a first current sensor I sensHP Coupled to a first high-side switch HP and configured to sense the current flowing therein; a second current sensor I sensHM It is coupled to the second high-side switch HM and configured to sense the current flowing therein; the third current sensor I sensLP Coupled to a first low-side switch LP and configured to sense the current flowing therein; and a fourth current sensor I sensLM It is coupled to a second low-side switch LM and configured to sense the current flowing therein.

[0130] In this case, the first measurement result can be obtained via the first current sensor I. sensHP Or the second current sensor I sensHM The detection, and the second measurement result can be respectively transmitted via the fourth current sensor I. sensLM Or the third current sensor I sensLP Testing.

[0131] First current sensor I sensHP Second current sensor I sensHM Third current sensor I sensLP and the fourth current sensor I sensLMIt can be achieved in different ways.

[0132] For example, Figure 4 The diagram illustrates a first method for implementing a current sensor, which includes: using a reference voltage V. ref As a reference for the flash ADC 200, and via this flash ADC 200, the current I flowing in the corresponding switch is... out The sensed voltage V is proportional sens Perform the conversion.

[0133] If we consider based on Figure 4 The current sensor can detect an imbalance when the absolute value of the difference between the converted values ​​of two different switches in the on state (i.e., the high-side switch of one branch of the full bridge and the low-side switch of the other branch of the full bridge) is above a threshold.

[0134] therefore, Figure 4 The diagram at reference mark 20 illustrates the following: Figure 3 An exemplary current sensing block I used in the embodiments and configured to perform conversion operations via analog-to-digital converter (ADC) 200 sens .

[0135] Current sensing block I sens (that is, according to) Figure 4 The current sensor may include a reference sensing element L ref (For example, a reference transistor), the reference sensing element is coupled to such a current sensing block I. sens The corresponding switches (i.e., the first high-side switch HP, the second high-side switch HM, the first low-side switch LP, or the second low-side switch LM) are matched.

[0136] For example, Figure 4 The diagram illustrates a reference sensing element L that is matched with either the first low-side switch LP or the second low-side switch LM. ref Because of this reference sensing element L ref Reference ground GND and in which reference current I has been injected ref The current flows between the current sink (drain) terminal and the current supply (source) terminal of the reference sensing element.

[0137] Reference current I ref Again, with respect to the maximum current I allowed to flow in the transistors of a full-bridge Class D amplifier. OCP Correspondingly, the maximum current I allowed to flow in this transistor... OCP It is obtained according to the above equation, because this reference sensing element L ref Matches the corresponding HP, HM, LP or LM switches.

[0138] Current sensing block I sens It can be configured to receive from one of the output terminals of the full bridge (i.e., the first output node Out). P Or the second output node Out M The current I is provided as an output and flows in the corresponding switches (i.e., the first high-side switch HP, the second high-side switch HM, the first low-side switch LP, or the second low-side switch LM) driven by the corresponding driver 102. out The sensed voltage V is proportional sens .

[0139] To reiterate, Figure 4 Exemplary current sensing block I sens It is configured to be coupled to either a first low-side switch LP or a second low-side switch LM. The structure of the first high-side switch HP and the second high-side switch HM can be achieved by using a reference sensing element L that matches such a high-side switch. ref To obtain.

[0140] Included in current sensing block I sens The flash ADC 200 in the middle is configured to receive this sensed voltage V sens and from the reference sensing element L ref Sensed reference voltage V ref and this sensed voltage V sens Converted to a reference voltage V based on the sensed voltage. ref The digital value of the reference voltage V ref Used as the reference voltage for the flash ADC 200.

[0141] The digital value obtained from the flash ADC 200 is provided to the control logic circuit CL, which is configured to respond to the current sensor I from the high-side switch coupled to the branch of the full bridge. sens The received digital value is transmitted from the current sensor I to the low-side switch coupled to another branch of the full bridge. sens If the received digital values ​​differ from each other by more than a given number of ADC levels (e.g., more than 2 ADC levels), then an imbalance is detected.

[0142] It is important to note that this is used in accordance with Figure 4 Current sensor I sens The resolution of the flash ADC 200 in the image can also be low; for example, it can include 8 levels. Furthermore, it can be used in applications based on... Figure 4 Current sensor I sens The conversion time of this flash ADC 200 can be in the range of about 1 / 4 or less of the PWM signal period.

[0143] Therefore, the current sensor I according to the solution described herein sensHP I sensHM I sensLP and I sensLM It may include, preferably, a flash analog-to-digital converter (ADC) 200.

[0144] This analog-to-digital converter (ADC) 200 can be configured to sense a voltage V proportional to the current flowing in the corresponding switch (i.e., HP, HM, LP, or LM). sens These switches are coupled to the current sensor under consideration (i.e., to current sensor I, respectively). sensHP I sensHM I sensLP Or I sensLM ); senses a reference switch that matches the corresponding switch (e.g., the previously described reference transistor L). ref The maximum acceptable current flowing in (e.g., the reference current I described earlier) ref A proportional reference voltage V ref ; and based on the sensed reference voltage V ref The sensed voltage V sens Convert it into a numerical value, which is either the first or second measurement result mentioned above.

[0145] It should be noted that since only two of the four switches included in the full bridge (i.e., HP and LM or HM and LP) can be turned on simultaneously, only two flash ADCs 200 can be considered and their inputs can be multiplexed.

[0146] Therefore, for example, the high-side current sensor can be coupled to the first high-side switch HP or the second high-side switch HM via a multiplexing circuit in order to detect the current flowing in the high side of the full bridge.

[0147] Similarly, the low-side current sensor can be coupled again, for example via a multiplexing circuit, to the first low-side switch LP or the second low-side switch LM, in order to detect the current flowing in the low side of the full bridge.

[0148] Therefore, the measurement circuit according to the solution described herein may include: a high-side current sensor configured to be coupled to a first high-side switch HP or a second high-side switch HM and to sense the current flowing in the coupled high-side switch HP or HM; and a low-side current sensor configured to be coupled to a second low-side switch LM or a first low-side switch LP and to sense the current flowing in the coupled low-side switch LM or LP.

[0149] In this case, the first measurement result can be detected via the high-side current sensor, and the second measurement result can be detected via the low-side current sensor.

[0150] For example, Figure 5 The diagram illustrates a second method for implementing a current sensor, which includes: connecting the current I flowing in a corresponding switch in the on state. outP and I outM The sensed voltage V is proportional sensP and V sensM The level is shifted to a common internal voltage or ground GND, and the sensed voltage V after the level shift is compared. sensP With V sensM To obtain the difference.

[0151] If we consider based on Figure 5 For a current sensor, the sensed voltage V after two level shifts... sensP With V sensM An imbalance can be detected when the difference between them is above a threshold.

[0152] therefore, Figure 5 The illustration at reference mark 25 shows the situation according to... Figure 3 Another exemplary current sensing block I used in the embodiments and configured to perform a comparison operation via comparator block 252 sens .

[0153] Current sensing block I sens (that is, according to) Figure 5 The current sensor may include a comparator block 252 coupled to ground (GND) and a level shifter 250.

[0154] Level shifter 250 is configured to receive a signal with a first current I. outP The first sensed voltage V is proportional sensP The first current I outP The output terminals of the full bridge branches (e.g., the first output node Out) P ) is provided as output and in this branch via the corresponding first driver 102 P The current flows into the corresponding drive switch (e.g., the first high-side switch HP or the first low-side switch LP); and this received first sensed voltage V sensP The level is shifted to a common internal voltage, for example, if the first sensed voltage V sensP If it is sensed from the first high-side switch HP, then the high-side level is shifted to the low side, and if the first sensed voltage V sensP It is sensed from the first low-side switch LP, so the level is shifted from the low side to the high side.

[0155] In the solution according to this description, current sensing block I sens It may include additional level shifters ( Figure 5 (Not shown in the diagram, but corresponding to shifter 250), this level shifter is configured to receive a second current I. outM The proportional second sensed voltage V sensM The second current I outM The output terminals of another branch of the full bridge (e.g., the second output node Out) M ) is provided as output and in this other branch via the corresponding second driver 102 M The flow is in the corresponding driven switch (e.g., the second high-side switch HM or the second low-side switch LM).

[0156] If such an additional level shifter exists, then the first sensed voltage V sensP The second sensed voltage V sensM It can be level-shifted to any common internal voltage or ground GND.

[0157] The comparator block 252, coupled to ground GND, is configured to receive a first level-shifted voltage and a second sensed voltage V provided as output by the level shifter 250. sensM (or a second level-shifted voltage provided as output by an additional level shifter, if present); and this first level-shifted voltage is compared with this second sensed voltage V. sensM (or the voltage after the second level shift, if an additional level shifter is present) are compared to obtain the (absolute) voltage difference.

[0158] Therefore, as described above, an imbalance can be detected when the (absolute) voltage difference provided by comparator block 252 is above a threshold.

[0159] It is important to note that if we consider based on Figure 5 If it's a current sensor, then a reference voltage V is not needed. ref However, the first high-side switch HP and the second low-side switch LM or the first low-side switch LP and the second high-side switch HM are matched in terms of thermal performance and relative to process expansion.

[0160] Therefore, the measurement circuitry included in the circuitry of the solution described herein may include a level shifter 250, which is configured to sense a voltage V. sensP and voltage V sensM The voltage in the middle, voltage V sensP The voltage V is proportional to the current flowing in the high-side switch HP or HM included in one of the first and second branches of the full-bridge Class D amplifier 5.sensM The sensed voltage V is proportional to the current flowing in the low-side switches LM or LP, respectively, included in the first and second branches of the full-bridge Class D amplifier 5; sensP or V sensM Level shift to select voltage V sensP and voltage V sensM The other voltage (respectively V) sensM or V sensP The voltage level of ), where voltage V sensP The voltage V is proportional to the current flowing in the high-side switch HP or HM included in one of the first and second branches of the full-bridge Class D amplifier 5. sensM The voltage V in response to the sensed voltage is proportional to the current flowing in the low-side switch LM or LP, respectively, included in one of the first and second branches of the full-bridge Class D amplifier 5; the voltage V in response to the sensed voltage is proportional to the current flowing in the high-side switch HP or HM, included in one of the first and second branches of the full-bridge Class D amplifier 5. sensP The sensed voltage after this level shift is provided as the first measurement result mentioned above, and is a voltage V proportional to the current flowing in the low-side switch LM or LP included in the other of the first and second branches of the full-bridge Class D amplifier 5. sensM Provided as the second measurement result above; and in response to the sensed voltage being a voltage V proportional to the current flowing in the low-side switch LM or LP included in the other of the first and second branches of the full-bridge Class D amplifier 5. sensM The voltage V is proportional to the current flowing in the high-side switch HP or HM included in one of the first and second branches of the full-bridge Class D amplifier 5. sensP As provided as the first measurement result, the sensed voltage after this level shift is provided as the second measurement result.

[0161] Alternatively, the measurement circuitry included in the circuitry of the solution described herein may include: a first level shifter configured to sense a voltage V proportional to the current flowing in such a high-side switch HP or HM included in one of the first and second branches of the full-bridge Class D amplifier 5. sensP ; to sense this voltage V sensP The level is shifted to a voltage level, such as ground (GND) or any other voltage level; and this level-shifted voltage is provided as the first measurement result described above. The solution may also include a second level shifter configured to sense a voltage V proportional to the current flowing in the low-side switch LM or LP, respectively, included in the other of the first and second branches of the full-bridge Class D amplifier 5.sensM ; to sense this voltage V sensM The level is shifted to such a voltage level, for example, ground (GND) or any other voltage level; and the sensed voltage after this level shift is provided as the second measurement result described above.

[0162] The second method involves detecting short-circuit conditions again based on current measurement results, such as those obtained from the output terminals of the full bridge (i.e., from the first output node Out). P Or the second output node Out M The current I supplied as the output outP and I outM The measurement results.

[0163] This second method is based on reference. Figure 6 The second exemplary circuit 30 illustrated herein is described, which is configured to detect a short circuit based on current sensing.

[0164] It should be noted that this has been referenced. Figure 1 The parts, elements, and / or components described are indicated by the same reference numerals previously used in such figures. Therefore, to avoid making this description too lengthy, descriptions of such previously described parts, elements, and / or components will not be repeated below.

[0165] In the solution based on this second method, current sensor I sens It is placed on the output of each of the two half-bridges of the full bridge, that is, on each of its branches.

[0166] In this situation, a short circuit to the supply voltage VCC or to ground GND can be detected when there is an imbalance between the currents measured in the two half-bridges.

[0167] For example, if placed on a branch of the full bridge (e.g., if it exists, then coupled to the first output node Out). P With the first inductor L1 P The first current sensor I between (between) sensP Sensed current I outP And placed on another branch of the full bridge (e.g., if present, then coupled to the second output node Out). M With the second inductor L2 M The second current sensor I between (between) sensM Sensed current I outM If the absolute value of the difference is above a threshold, then this imbalance can be identified. It should be noted that this difference can be obtained via an analog comparator or via digital conversion, preferably by considering a margin due to the presence of the final differential ripple.

[0168] Otherwise, this imbalance can be determined by the first current sensor I placed on a branch of the full bridge. sensP Sensed current I outP A first single-ended comparison is obtained by comparing the current sensor I with ground (GND) or any internal power supply; this comparison is then performed by a second current sensor I placed on another branch of the full bridge. sensM Sensed current I outM A second single-ended comparison is obtained by comparing the first single-ended comparison with ground (GND) or with an internal power supply; and it is determined whether the absolute value of the difference between the first single-ended comparison and the second single-ended comparison is higher than a threshold, for example, via an analog comparator or via digital conversion, preferably by taking into account a margin due to the presence of the final differential ripple.

[0169] Therefore, the measurement circuit included in the circuit according to the solution described herein may include: a first branch current sensor, for example, a first current sensor I. sensP Coupled to the first output node Out P (For example, in the first output node Out) P With the first inductor L1 P (or between load LD) and configured to sense the current I flowing therein. outP ; and a second branch current sensor, for example, a second current sensor I sensM Coupled to the second output node Out M (For example, in the second output node Out) M With the second inductor L2 M (or between load LD) and configured to sense the current I flowing therein. outM .

[0170] In this case, the aforementioned first measurement result can be obtained via a sensor selected from the first branch current sensor I. sensP Second branch current sensor I sensM One of the current sensors is used for detection, and the second measurement result can be obtained via a current sensor selected from the first branch current sensor I. sensP Second branch current sensor I sensM Another current sensor is used for detection.

[0171] In the solution based on the second method, the current sensor can be implemented via a shunt resistor (typically a MOS parasitic metal resistor), metal sensing, or the Hall effect.

[0172] Figure 7A and Figure 7B The figure illustrates such an embodiment, showing an implementation according to the present description. Figure 6 The exemplary current sensing block I used in the embodimentssensP and I sensM .

[0173] Figure 7A The diagram illustrates a parasitic or shunt resistor RS, with one of the output terminals of the full bridge supplying the output current I. outP Or I outM It flows into the resistor.

[0174] This current I outP Or I outM The current I flowing in the parasitic or shunt resistor RS can be sensed via comparator 300, which has a first input terminal coupled to a first terminal of the parasitic or shunt resistor RS and a second input terminal coupled to a second terminal of the parasitic or shunt resistor RS. This comparator 300 is configured to provide a current I that is correlated with the current flowing in the parasitic or shunt resistor RS. outP Or I outM proportional current KI out As output.

[0175] It should be noted that this comparator 300 is advantageously a fully differential amplifier with a high common-mode rejection ratio (CMRR).

[0176] Figure 7B The diagram illustrates a Hall effect sensor 302, with one of the output terminals of the full-bridge circuit providing the output current I. outP Or I outM It flows into the sensor.

[0177] This Hall sensor 302 is coupled to an analog front end (AFE) 304, which is configured to provide a current I flowing in the Hall sensor 302. outP Or I outM proportional current KI out As output.

[0178] It should be noted that this Hall sensor 302 advantageously includes temperature compensation, offset cancellation, and amplification features.

[0179] Therefore, the aforementioned first branch current sensor I sensP Second branch current sensor I sensM It can be achieved via a shunt resistor, preferably via MOS parasitic metal resistance, metal sensing or Hall effect sensing.

[0180] The solution based on the second method can be advantageously used in Class D amplifiers that do not have an integrated current sensor.

[0181] In fact, when a full-bridge Class D amplifier is not equipped with an internal (integrated) current sensing element, a current sensor according to this second method can be applied externally (e.g., at the printed circuit board (PCB) level) by placing such a current sensor between the output terminal (PWM output) of the full bridge and the LC filter; or between the LC filter and the load LD.

[0182] In this case, the external signal circuitry system of the full-bridge Class D amplifier can be used to perform conditioning, analog-to-digital conversion, and comparison operations.

[0183] It is important to note that both the first and second methods can detect short circuits before the maximum current allowed to flow in the full-bridge switches is reached. Therefore, short circuits are detected faster than known solutions before the full-bridge output stage is brought close to unsafe operating conditions.

[0184] Another approach involves detecting short-circuit conditions based on time-based measurements.

[0185] To describe this alternative method, Figure 8 The diagram illustrates the pulse width modulation (PWM) signal D used to manage the pulse width modulation signal used to drive the full-bridge Class D amplifier. INP and D INM Example circuit 35.

[0186] It should be noted that this has been referenced. Figure 1 The parts, elements, and / or components described are indicated by the same reference numerals previously used in such figures. Therefore, to avoid making this description too lengthy, descriptions of such previously described parts, elements, and / or components will not be repeated below.

[0187] Each switch included in the full-bridge Class D amplifier can be driven by a corresponding driver (DR) 102.

[0188] Therefore, the first high-side switch HP can be driven by the first high-side driver 102. HP Drive, the first high-side driver 102 HP Coupled to the first low-side to high-side level shifter (LS) 350 P This first high-side driver 102 HP Configured to receive from this first low-side to high-side level shifter 350 P The first level shifted control signal is used to drive the first high-side switch HP based on this received first level shifted control signal.

[0189] First low-side to high-side level shifter 350 P It can be configured to receive a first dead time (DT) adjustment block 352 PThe first control signal is level-shifted to obtain a level-shifted control signal, which is then provided to the first high-side driver 102. HP .

[0190] First dead zone time adjustment block 352 P It can be configured to receive the first input signal D INP For example, a PWM signal, which will be provided to either the high-side driver or the low-side driver, and the first dead-time adjustment block is based on this received first input signal D. INP Whether the output is provided to the high-side driver or the low-side driver, the output will be supplied to the first low-side to high-side level shifter 350. P The first control signal and will be provided to the first low-side driver 102 LP The second control signal.

[0191] The first low-side switch LP can be coupled to the first dead-time adjustment block 352. P This first low-side driver 102 LP Drive, this first low-side driver 102 LP Configured to receive from this first dead-time adjustment block 352 P The second control signal is received and the first low-side switch LP is driven based on this received second control signal.

[0192] Similarly, the second high-side switch HM can be coupled to the second low-side to high-side level shifter 350. M Second high-side driver 102 HM Drive, this second high-side driver 102 HM Configured to receive from this second low-side to high-side level shifter 350 M The second level shifted control signal is used to drive the second high-side switch HM based on this received second level shifted control signal.

[0193] Second low-side to high-side level shifter 350 M It can be configured to adjust the second dead time block 352 M The system receives another first control signal, performs a level shift on this received first control signal to obtain a second level-shifted control signal, and provides this second level-shifted control signal to the second high-side driver 102. HM .

[0194] Second dead time adjustment block 352 M It can be configured to receive a second input signal D INMFor example, a PWM signal, which will be provided to either the high-side driver or the low-side driver, and the second dead-time adjustment block is based on this received second input signal D. INM Whether the output is provided to the high-side driver or the low-side driver, the output will be supplied to the second low-side to high-side level shifter 350. M The other first control signal will be provided to the second low-side driver 102 LM The other second control signal.

[0195] The second low-side switch LM can be coupled to the second dead-time adjustment block 352. M This second low-side driver 102 LM Drive, this second low-side driver 102 LM Configured to receive from this second dead-time adjustment block 352 M The second control signal is received and the second low-side switch LM is driven based on this second control signal.

[0196] To be provided to the first high-side driver 102 HP Or the first low-side driver 102 LP The first input signal D INP (e.g., PWM signal) and to be provided to the second high-side driver 102 HM Or the second low-side driver 102 LM The second input signal D INM (For example, the same PWM signal) can be generated by the PWM modulation block 354 based on the reference input signal IS and the clock Ck.

[0197] In view of the above, the PWM period can be defined as the period of a pulse width modulation (PWM) signal generated for driving the half-bridge included in the full-bridge via driver 102, so as to operate the switch pair HP and LP or HM and LM included therein. This PWM signal can be the first input signal D. INP Or the second input signal D INM .

[0198] Therefore, the solution according to this alternative method involves measuring the current-dependent time delay in each PWM cycle, which is the input signal D to be provided to the driver 102 coupled to the corresponding switch of the half-bridge included in the full bridge. INP and D INM The rising or falling edge of the signal is related to the PWM signal provided as the output by the branch of this full bridge (i.e., half bridge) (i.e., at the first output node Out). P Or the second output node Out M The time interval between the measured PWM signals corresponds to the time interval between them.

[0199] Such measured current-dependent time delays include a first time delay T. d_r_P Second time delay T d_f_P Third time delay T d_r_M and the fourth time delay T d_f_M .

[0200] First time delay T d_r_P With the first high-side driver 102 to be supplied HP Or the first low-side driver 102 LP The first input signal D INP The power supply rises to the first high-side switch HP via the first output node Out. P The corresponding rise delay corresponds to the PWM signal provided as the output.

[0201] Second time delay T d_f_P With the first high-side driver 102 to be supplied HP Or the first low-side driver 102 LP The first input signal D INP The drop to the first low-side switch LP via the first output node Out P The corresponding dropout delay corresponds to the PWM signal provided as the output.

[0202] Third time delay T d_r_M With the second high-side drive 102 to be supplied HM Or the second low-side driver 102 LM The second input signal D INM The rise is caused by the second high-side switch HM via the second output node Out. M The corresponding rise delay corresponds to the PWM signal provided as the output.

[0203] Fourth time delay T d_f_M With the second high-side drive 102 to be supplied HM Or the second low-side driver 102 LM The second input signal D INM The drop to the second low-side switch LM via the second output node Out M The corresponding dropout delay corresponds to the PWM signal provided as the output.

[0204] Furthermore, solutions based on this alternative method include those with a third time delay T. d_r_M With the second time delay T d_f_P Between or the first time delay T d_r_P With the fourth time delay T d_f_MWhen an imbalance exists, that is, when there is an imbalance between the time delay associated with the high-side switch HP or HM of one branch and the time delay associated with the low-side switch LM or LP of the other branch respectively, a short circuit to the supply voltage VCC or to ground GND is detected.

[0205] For example, when this third time delay T d_r_M With this second time delay T d_f_P Or this first time delay T d_r_P With this fourth time delay T d_f_M This imbalance can be detected when the absolute value of the difference between them is above a time threshold.

[0206] It's important to note that in "BD" type modulation, the time delay can be stored in a capacitor via voltage conversion and then processed; while in "AD" type modulation (often called out-of-phase modulation), this time delay can be processed directly, for example, by measuring the output from the first output node Out. P Second output node Out M The signal (rising and / or falling) leading edge delay between the leading edges of the PWM signal provided as output is measured by checking whether this measured signal leading edge delay exceeds a threshold.

[0207] Figure 9 The illustration shows the previously described time delay T according to an embodiment of this description. d_r_M T d_f_P T d_r_P and T d_f_M With the output current I supplied by the full-bridge Class D amplifier to its coupled load LD out Behavior 40.

[0208] It is important to note that Figure 9 The time axis t (in seconds) and the current axis I out The values ​​and scales reported in this document (in amperes (A)) are presented only by way of example, and therefore, different values ​​and scales may be considered without affecting the behavior 40 described below and the related conclusions. In fact, such values ​​and scales can be varied based on the technology used to implement the full-bridge switch.

[0209] In addition to the previously described time delay T d_r_M T d_f_P T d_r_P and T d_f_M In addition, a dead time delay DT corresponding to the following delays can be defined: from the first (or second) dead time adjustment block 352 P (or 352) MThe rise / fall of the aforementioned (additional) first control signal provided by the first (or second) dead time adjustment block 352 is controlled by this first (or second) dead time adjustment block. P (or 352) M The subsequent drop / rise of the aforementioned (additional) second control signal provided by ).

[0210] It is important to note that this dead time delay (DT) is considered to prevent the high-side switches (i.e., HP or HM) and low-side switches (i.e., LP or LM, respectively) included in the same branch of the full bridge from being set to the on state simultaneously.

[0211] It is important to note that for the output current I out The value is close to zero (i.e., for low output current I). out (value), the aforementioned time delay T d_r_M T d_f_P T d_r_P and T d_f_M The values ​​are close to each other, for example, close to the value DTZ, which depends on the dead time delay DT and the value of the ripple current (e.g., when the current flowing in the load LD is zero).

[0212] It should also be noted that, with the output current I out The increase in the absolute value of the aforementioned time delay T d_r_M T d_f_P T d_r_P and T d_f_M The value deviates from the value DTZ obtained at zero output load current.

[0213] In this regard, the third time delay T d_r_M Second time delay T d_f_P Similar behavior was shown for the value: for the output current I out The negative value (i.e., when the output current I) out From the first output node Out P Flow to the second output node Out M (when), the value decreases relative to the time delay DTZ; and for the output current I out The positive value (i.e., when the output current I) out From the second output node Out M Flow to the first output node Out P (When), the value increases relative to the time delay DTZ.

[0214] Similarly, the first time delay T d_r_P and the fourth time delay T d_f_M It also shows similar behavior, with the following values: for the output current I out The positive value decreases relative to the time delay DTZ; and for the output current Iout The negative value of DTZ increases relative to the time delay.

[0215] Therefore, under normal driving conditions, i.e., without short circuits, the third time delay T d_r_M The behavior (sum value) is almost equal to the second time delay T. d_f_P The behavior (sum value), and the first time delay T d_r_P The behavior (sum value) is almost equal to the fourth time delay T. d_f_M The behavior (and value).

[0216] It is important to note that the time delay measured on the same branch of the entire bridge (i.e., the first time delay T) d_r_P Second time delay T d_f_P Or a third time delay T d_r_M and the fourth time delay T d_f_M The behavior of ) is almost symmetrical, and the output current I out The symbol changes.

[0217] It is important to note that Figure 9 The behavior illustrated in the figure is in "BD" type modulation (i.e., when the first input signal D...). INP The leading edge and the second input signal D INM The phenomenon exists when the leading edge is out of sync, and it also exists in "AD" type modulation (i.e., the first input signal D). INP The leading edge and the second input signal D INM When the leading edge is synchronized, for example, in response to the first input signal D INP Equal to the second input signal D INM The inverse (e.g., obtained by logical negation) exists.

[0218] also, Figure 9 The behavior illustrated in the figure can also exist in zero switching loss (ZSL) Class D amplifiers. Therefore, by treating them as amplifiers with “AD” class modulation, the solution described in this paper can also be applied to such amplifiers, since the time delay is the same in the case of outgoing current and incoming current, and decreases or increases in response to a decrease or increase in output current, especially in the case of low positive output current and negative current.

[0219] A short circuit to the supply voltage VCC or to ground GND is detected when there is an imbalance among the following: third time delay T d_r_M With the second time delay T d_f_P Under normal driving conditions (i.e., without short circuits), they exhibit almost identical behavior; or the first time delay T d_r_P With the fourth time delay T d_f_MUnder normal driving conditions, they exhibit almost identical behavior.

[0220] This third time delay T can be detected when the absolute value of the difference between the values ​​of two considered time delays (which are assumed to be almost identical since their behavior is almost identical) is above a time threshold. d_r_M With this second time delay T d_f_P Between or such first time delay T d_r_P With this fourth time delay T d_f_M The imbalance between them.

[0221] Figure 10A and Figure 10B The figure illustrates a full-bridge Class D amplifier 45 in an embodiment considering the other methods described above, the amplifier having an output when the amplifier 45 outputs out P and Out M When not saturated (i.e., when the first input signal D) INP Second input signal D INM An exemplary short circuit to ground (GND) applied during switching. GND .

[0222] Short circuit to ground (GND) Sh GND The existence of the second output node Out breaks the flow. M Current I FM With the flow into the first output node Out P Current I FP Symmetry, current I FL The current flows through the load LD, therefore, in response to this short circuit Sh GND The existence of such currents results in different values.

[0223] For example, in Figure 10A and Figure 10B In an exemplary scenario, after the LC filtering stage (e.g., in the first LC filter Lfilt) P (After that) and corresponding to the first output node OutLC of the LC filter stage P Consider one of the output nodes of the full bridge (e.g., in the current I). FP The first output node to enter (Out) P (above) Short circuit to ground (GND) Sh GND .

[0224] In addition, Figure 10A and Figure 10B In an exemplary scenario, it is assumed that: in a short circuit Sh GND After the event, the load LD remains coupled to the first output node OutLC of the LC filter stage. P With the second output node OutLC of the LC filter stageM Between, and in the short circuit Sh GND The current I flowing through the load LD before the event FL If positive, that is, from the second output node Out M Flow to the first output node Out P .

[0225] It is important to note that, in Figure 10A In the middle, during the short circuit to ground (GND) Sh GND Before the event, the flow into the first output node Out P Current I FP It has a positive value because the output current I out (From the second output node Out) M The provided current I FM and the first output node Out P Absorbed current I FP (Composition) from the second output node Out M Flow to the first output node Out P .

[0226] Therefore, it is assumed that the first input signal D INP Corresponding to the falling edge, the signal switches from a high logic level to a low logic level; and the second input signal D INM Corresponding to the rising edge, the transition from low logic level to high logic level: the measured second time delay T d_f_P With the measured third time delay T d_r_M They are (almost) equal, and according to Figure 9 The behavior illustrated herein has a time delay value greater than DTZ as previously stated.

[0227] In response to a short circuit to ground (GND) Sh GND The event flows into the first output node, Out. P Current I FP It begins to decrease, and after a given time, changes its sign (polarity), that is, by changing the sign (polarity) from the first output node Out. P Flowing out to Earth I Sh Change its flow direction (refer to) Figure 10B ).

[0228] In response to the output from the first output node P Outflowing current I FP The change in flow direction, the measured second time delay T d_f_P The value decreases from a value higher than the time delay DTZ to a value lower than this time delay DTZ.

[0229] In fact, in response to the short circuit to ground GND, Sh GND Event, Current IFP From the first output node Out P Provided as output (without being absorbed) (see reference) Figure 10B Therefore, this current I FP It has a negative value because the output current I out From the first output node Out P Flowing out to Earth I Sh .

[0230] The difference is that the current I FM Still by the second output node Out M Provided as output, and due to this second output node Out M Short circuit with ground (GND) Sh GND There is a load LD that increases (slowly).

[0231] Therefore, although the measured second time delay T d_f_P The value decreases, but the measured third time delay T d_r_M Due to current I FM Still by the second output node Out M As an output, its value is maintained above the time delay DTZ value, and due to the second output node Out M Short circuit with ground (GND) Sh GND There is a load LD in response to this current I FM The (slow) increase and the (slow) increase.

[0232] Therefore, the measured second time delay T d_f_P With the measured third time delay T d_r_M There is an imbalance between them.

[0233] By assuming: the first input signal D INP Corresponding to the rising edge, the logic level switches from low to high, and the second input signal D... INM Corresponding to the falling edge, switching from a high logic level to a low logic level, a similar conclusion can be drawn.

[0234] In this case, the measured first time delay T d_r_P The measured fourth time delay T d_f_M They are (almost) equal, and according to Figure 9 The behavior illustrated in the figure has a value lower than the time delay DTZ.

[0235] In response to a short circuit to ground (GND) Sh GND The event flows into the first output node, Out. P Current I FPIt begins to decrease, and after a given time, changes its sign (polarity), that is, by changing the sign (polarity) from the first output node Out. P Flowing out to Earth I Sh Change its flow direction (refer to) Figure 10B ).

[0236] In response to the output from the first output node P Outflowing current I FP The change in flow direction, the first time delay T measured d_r_P The value increases from a value below the time delay DTZ to a value above that time delay DTZ.

[0237] In fact, in response to the short circuit to ground GND, Sh GND Event, Current I FP From the first output node Out P Provided as output (without being absorbed) (see reference) Figure 10B Therefore, due to the output current I out From the first output node Out P Flowing out to Earth I Sh This current I FP It has negative values.

[0238] The difference is that current IFM Still by the second output node Out M Provided as output, and due to this second output node Out M Short circuit with ground (GND) Sh GND There is a load LD that increases (slowly).

[0239] Therefore, when the measured first time delay T d_r_P As the value increases, the measured fourth time delay T d_f_M Due to current I FM Still by the second output node Out M As an output, its value is maintained below the time delay DTZ value, and due to the second output node Out M Short circuit with ground (GND) Sh GND There is a load LD in response to this current I FM It increases (slowly) and decreases (slowly).

[0240] Therefore, in this case, the measured first time delay T d_r_P The measured fourth time delay T d_f_M There is also an imbalance between them.

[0241] In both of the above cases, this imbalance can be obtained by performing a subtraction operation on the following: the measured second time delay T. d_f_P With the measured third time delay T d_r_M Or the measured first time delay T d_r_P The measured fourth time delay T d_f_M And obtain the time delay difference as the absolute value of the result of the subtraction operation.

[0242] Therefore, by comparing the obtained time delay difference with a threshold, it is possible to: detect the presence of a short circuit when the time delay difference is higher than (or eventually equal to) the threshold; and detect the absence of a short circuit when the time delay difference is lower than the threshold.

[0243] For example, in solutions using other methods described herein, the threshold can be on the order of a quarter of the dead time delay DT (e.g., in...). Figure 9 In an exemplary scenario, the threshold can be equal to 5 nanoseconds.

[0244] It is important to note that if the current I FM The second output node that leaves M There is a short circuit to ground (GND) Sh GND For example, in the second LC filter Lfilt M Then, and with the second output node OutLC of the LC filter stage. M Correspondingly, we can consider the same conclusion.

[0245] In fact, in this case, the measured second time delay T d_f_P With the measured third time delay T d_r_M Between or the first time delay T measured d_r_P The measured fourth time delay T d_f_M There is also an imbalance between them.

[0246] In response to the second output node Out M Short circuit to ground (GND) Sh GND The event occurs because the load LD exists in this first output node Out. P Short circuit with ground (GND) Sh GND Between, the water flows into the first output node Out. P Current I FP The time delay T begins to decrease (slowly), therefore, the measured second time delay T decreases (slowly). d_f_P and (slowly) increase the measured first time delay T d_r_P .

[0247] In addition, the second output node Out MThe current I supplied as output FM Increase, therefore, increase the measured third time delay T d_r_M And reduce the measured fourth time delay T d_f_M .

[0248] It should also be noted that, Figure 10A and Figure 10B The exemplary scenario considers "AD" type modulation; however, the above conclusion is also considered valid in solutions using "BD" type modulation, provided that the measured time delay T is... d_f_P T d_r_M T d_r_P and T d_f_M The voltage is converted and stored, for example, in a corresponding capacitor, and then processed via the previously described subtraction and comparison operations. In fact, the measured time delay T is stored... d_f_P T d_r_M T d_r_P and T d_f_M This can overcome the fact that pulses are asynchronous and do not overlap in "BD" type modulation.

[0249] Figure 11A and Figure 11B The figure illustrates a full-bridge Class D amplifier 50 in an embodiment considering the alternative methods described above, the amplifier having an output Out of amplifier 50. P and Out M When not saturated (i.e., when the first input signal D) INP Second input signal D INM During switching, an exemplary short circuit Sh to the supply voltage VCC is applied. VCC .

[0250] Short circuit Sh of supply voltage VCC VCC The existence of the second output node Out M Outflowing current I FM With the flow into the first output node Out P Current I FP Symmetry, current I FL The current flows through the load LD, thus resulting in different values ​​of this current.

[0251] In fact, the short circuit Sh of the supply voltage VCC VCC This presence results in current being injected into both output terminals of the full bridge. P or Out M One of them, namely, injecting current into the output node of the full bridge that is currently coupled to ground (GND) and receives incoming current, thereby increasing the current flowing in such output node by an amount equal to the injected current I. Sh; and at the other output of the full bridge (i.e., currently coupled to the supply voltage VCC and providing the output current I). out The reduction in the current flowing through the output nodes of the full bridge reduces the current leaving the other output node and changes its polarity (symbol) after a given time.

[0252] For example, in Figure 11A and Figure 11B In an exemplary scenario, after the LC filtering stage (e.g., in the first LC filter Lfilt) P (After that) and with the first output node OutLC of the LC filter stage P Correspondingly, consider one of the output nodes of the full bridge (e.g., in the current I). FP The first output node to enter (Out) P The short circuit Sh to the supply voltage VCC (above) VCC .

[0253] In addition, Figure 11A and Figure 11B In an exemplary scenario, suppose that in a short circuit Sh VCC After the event, the load LD remains coupled to the first output node OutLC of the LC filter stage. P With the second output node OutLC of the LC filter stage M Between, and in the short circuit Sh VCC The current I flowing through the load LD before the event FL If positive, that is, from the second output node Out M Flow to the first output node Out P .

[0254] Therefore, it is important to note that in this situation... Figure 11A and Figure 11B In the exemplary scenario illustrated: the first output node Out P The output node currently coupled to ground (GND) has incoming current; therefore, this is due to a short circuit in Sh. VCC The positive current I generated by the event Sh The injected output node increases the current I flowing within it. FP And the second output node Out M It is the output node currently coupled to the supply voltage VCC and provides the output current I. out Therefore, it is the current I flowing within it. FM Output nodes that are reduced and whose polarity changes after a given time (see reference) Figure 11B ).

[0255] Therefore, in response to the short circuit Sh of the supply voltage VCC VCCThe event flows into the first output node, Out. P Current I FP Increase, thus measuring the second time delay T d_f_P The first time delay T was increased and measured. d_r_P Decrease.

[0256] In response to a short circuit to the supply voltage VCC, Sh VCC The event is generated by the second output node, Out. M The provided current I FM Decrease, and after a given time, change polarity to begin entering the second output node (Out). M .

[0257] Therefore, the measured third time delay T d_r_M The value decreases from a value higher than the time delay DTZ to a value lower than this time delay DTZ, and the measured fourth time delay T d_f_M The value increases from a value below the time delay DTZ to a value above that time delay DTZ.

[0258] Therefore, the measured second time delay T d_f_P With the measured third time delay T d_r_M Between or the first time delay T measured d_r_P The measured fourth time delay T d_f_M There is an imbalance between them.

[0259] This imbalance can be measured by the second time delay T. d_f_P With the measured third time delay T d_r_M Between or the first time delay T measured d_r_P The measured fourth time delay T d_f_M The time delay difference is obtained by performing a subtraction operation between the two operations and obtaining the absolute value of the result of the subtraction operation.

[0260] Therefore, by comparing the obtained time delay difference with a threshold, it is possible to: detect the presence of a short circuit in response to the time delay difference being higher than (or eventually equal to) the threshold; and detect the absence of a short circuit in response to the time delay difference being lower than the threshold.

[0261] For example, in the case of a short circuit to the supply voltage VCC and in solutions using other methods described herein, the threshold can also be approximately one-quarter of the dead time delay DT (e.g., in...). Figure 9 In an exemplary scenario, the threshold can be equal to 5 nanoseconds.

[0262] It is important to note that if the current I FM The second output node that leaves MThere is a short circuit Sh to the supply voltage VCC. VCC For example, in the second LC filter Lfilt M Then, and with the second output node OutLC of the LC filter stage. M Correspondingly, we can consider the same conclusion.

[0263] Generally, in solutions using "AD" type modulation and the other time-based methods described above, it is not necessary to separately measure and then compare (e.g., via the subtraction operation and the comparison with the threshold operation) the time delay T. d_f_P and T d_r_M or T d_r_P and T d_f_M .

[0264] In this case, the measurement may be performed by the first high-side switch HP or the first low-side switch LP via the first output node Out. P The switching of the PWM signal provided as the output is achieved by the second high-side switch HM or the second low-side switch LM via the second output node Out. M The PWM delay between switching of the PWM signal provided as output is sufficient, and vice versa.

[0265] It should be noted that temperature mismatch of the switches included in the full bridge or the presence of non-negligible substrate injection may cause a systematic current-dependent delay in the leading edge of the PWM signal, which can be compensated for during PWM delay measurement.

[0266] Figure 12A , Figure 12B and Figure 12C The figures illustrate the behavior of the leading edge of the PWM signal provided as output by a full-bridge Class D amplifier according to an embodiment of this description, in relation to "AD" type modulation. a 55 b and 55 c .

[0267] Figure 12A The diagram illustrates the operation of either the first high-side switch HP or the first low-side switch LP via the first output node Out during normal drive conditions (i.e., in the absence of a short circuit). P The switching (rising and falling) of the PWM signal provided as output and the switching via the second high-side switch HM or the second low-side switch LM through the second output node Out M The corresponding switching (falling and rising) of the PWM signal provided as the output.

[0268] It is important to note that under these normal driving conditions, i.e., when there is no short circuit and the full-bridge Class D amplifier is operated via "AD" modulation, the output from the first output node Out... PThe rising (or falling) of the provided PWM signal is related to the output of the second output node Out. M The corresponding falling (or rising) phases of the provided PWM signal are synchronized.

[0269] Figure 12B The diagram illustrates the short circuit Sh to ground (GND). GND During the event, the first high-side switch HP or the first low-side switch LP is connected via the first output node Out. P The switching (rising and falling) of the PWM signal provided as output and the switching via the second high-side switch HM or the second low-side switch LM through the second output node Out M The corresponding switching (falling and rising) of the PWM signal provided as the output.

[0270] It is important to note that in the presence of a short circuit to ground (GND), Sh GND Under the conditions of the event, the first output node Out P The rising edge of the provided PWM signal is relative to the second output node Out M The falling edge of the provided PWM signal is delayed and is output by the second output node Out. M The rising edge of the provided PWM signal is relative to the first output node Out P The falling edge of the provided PWM signal is delayed.

[0271] In this case, the first time delay T d_r_P With the fourth time delay T d_f_M The absolute value of the difference between them is equal to that in the output by the second output node Out. M The falling edge of the provided PWM signal and the output from the first output node Out P The first PWM delay T measured between the rising edges of the provided PWM signal d_fM_rP .

[0272] If this first PWM delay T d_fM_rP Above a threshold (e.g., about a quarter of the dead time delay DT, e.g., 5 nanoseconds), then a short circuit to ground (GND) is determined to exist. GND event.

[0273] Similarly, the third delay T d_r_M With the second delay T d_f_P The absolute value of the difference between them is equal to that between the first output node Out. P The falling edge of the provided PWM signal and the output from the second output node Out M The second PWM delay T measured between the rising edges of the provided PWM signal d_fP_rM .

[0274] Therefore, if this second PWM delay T d_fP_rM Above this threshold (e.g., about a quarter of the dead time delay DT), then a short circuit to ground GND is confirmed. GND event.

[0275] Figure 12C The diagram illustrates the short circuit Sh to the supply voltage VCC. VCC During the event, the first high-side switch HP or the first low-side switch LP is connected via the first output node Out. P The switching (rising and falling) of the PWM signal provided as output and the switching via the second high-side switch HM or the second low-side switch LM through the second output node Out M The corresponding switching (falling and rising) of the PWM signal provided as the output.

[0276] It is important to note that in the presence of a short circuit to the supply voltage VCC, Sh VCC Under the conditions of the event, the first output node Out P The falling edge of the provided PWM signal is relative to the second output node Out M The rising edge of the provided PWM signal is delayed and is output by the second output node Out. M The falling edge of the provided PWM signal is relative to the first output node Out P The rising edge of the provided PWM signal is delayed.

[0277] In this case, the first time delay T d_r_P With the fourth time delay T d_f_M The absolute value of the difference between them is equal to that between the first output node Out. P The rising edge of the provided PWM signal and the output from the second output node Out M The third PWM delay T measured between the falling edges of the provided PWM signal d_rP_fM .

[0278] If this third PWM delay T d_rP_fM Above this threshold (e.g., a threshold of about a quarter of the dead time delay DT), then a short circuit Sh to the supply voltage VCC is determined to exist. VCC event.

[0279] Similarly, the third time delay T d_r_M With the second time delay T d_f_P The absolute value of the difference between them is equal to that in the output by the second output node Out. M The rising edge of the provided PWM signal and the output from the first output node Out P The fourth PWM delay T measured between the falling edges of the provided PWM signal d_rM_fP.

[0280] Therefore, if this fourth PWM delay T d_rM_fP Above this threshold (e.g., about a quarter of the dead time delay DT), then a short circuit Sh to the supply voltage VCC is determined to exist. VCC event.

[0281] Generally, different implementation methods can be used in solutions employing both "BD" type modulation and the other time-based methods mentioned above, provided that the time delay T is constant. d_f_P and T d_r_M Or T d_r_P and T d_f_M The value is stored before the comparison operation, for example, performed via the subtraction operation and the comparison operation with the threshold.

[0282] Therefore, the measurement circuit included in the circuit according to the solution described herein may include: a first storage circuit, for example, a storage circuit having the structure of storage circuit 604 described below, configured to store the first measurement result; and a second storage circuit, for example, a storage circuit also having the structure of storage circuit 604 described below, configured to store the second measurement result.

[0283] In this case, the aforementioned inspection circuit can be configured to receive a first measurement result and a second measurement result from the first storage circuit and the second storage circuit included in the measurement circuit, respectively.

[0284] Furthermore, the first storage circuit may be a first capacitor configured to store a voltage indicating a first measurement result, and the second storage circuit may be a second capacitor configured to store a voltage indicating a second measurement result.

[0285] It should be noted that, in this case, the checking circuit can be configured to receive voltages indicating the first measurement result and voltages indicating the second measurement result from the first storage circuit and the second storage circuit included in the measurement circuit, respectively.

[0286] Figure 13 A third exemplary circuit 60 for detecting short circuits based on time measurement results is illustrated according to an embodiment of a solution using "BD" class modulation. It should be noted that, as described above, Figure 13 The implementation shown in the figure is just one possible implementation of the solution using both "BD" type modulation and the other time-based methods described above.

[0287] According to Figure 13 In the solution, the first output node Out PThe provided PWM signal is converted into a first logic signal by the first comparator Cmp1.

[0288] This first comparator Cmp1 can be configured to receive signals from the first output node Out. P The provided PWM signal, along with a voltage reference threshold (e.g., a threshold having a value equal to VCC / 2), is based on the received signal from the first output node Out. P The first logic signal is provided as an output by comparing the provided PWM signal with a voltage reference threshold.

[0289] For example, the first logic signal may have: in response to the first output node Out P The provided PWM signal is above the voltage reference threshold, at a high logic level; and in response to the first output node Out P The provided PWM signal is below the voltage reference threshold, which is a low logic level.

[0290] Similarly, from the second output node Out M The provided PWM signal is converted into a second logic signal via the second comparator Cmp2.

[0291] This second comparator Cmp2 can be configured to receive output from the second output node Out. M The provided PWM signal and voltage reference threshold, based on the received signal from the second output node Out... M This second logic signal is provided as an output by comparing the provided PWM signal with a voltage reference threshold.

[0292] For example, the second logic signal may have: in response to the second output node Out M The provided PWM signal is above the voltage reference threshold, at a high logic level; and in response to the output from the second output node Out... M The provided PWM signal is below the voltage reference threshold, which is a low logic level.

[0293] The first logic signal, the second logic signal, and other driver control signals (e.g., the driver minimum signal DM and the driver pin signal DP) are provided to the logic circuit 602.

[0294] Logic circuit 602 can be configured to generate an indication of a corresponding time delay T based on the received signal. d_r_M T d_f_P T d_r_P and T d_f_M The logic pulse signals Pls_r_M, Pls_f_P, Pls_r_P and Pls_f_M, for example, have a width equal to this corresponding time delay.

[0295] The logic pulse signals Pls_r_M, Pls_f_P, Pls_r_P and Pls_f_M can be provided to the storage circuit 604, which can be configured according to two possible implementations.

[0296] In a first embodiment, this storage circuit 604 can be configured to use a reference current I for the duration of the corresponding width of the logic pulse signal under consideration. x Charging the corresponding capacitor C (which has been previously discharged) converts such logic pulse signals into delay-related voltages V_r_M, V_f_P, V_r_P, and V_f_M, and stores these delay-related voltages.

[0297] It is important to note that this reference current I x It is a current with a constant value, which can be obtained from any type of known constant current source, for example, by using such... Figure 13 The constant current generator is illustrated in the storage circuit 604.

[0298] For example, an exemplary circuit that can be used to charge and / or discharge a corresponding capacitor C may include: a first switch SW1, coupled between a specific supply voltage VDD of the capacitor and a node, and configured to close to allow a reference current I... x A second switch SW2, coupled between this supply voltage VDD and the node, is configured to close to allow the reference current I to flow between the node and ground GND. x A current flows between this node and ground (GND); a corresponding capacitor C, coupled between this node and ground (GND), is configured to use this reference current I. x To charge or discharge; and a third switch res, coupled between this node and ground GND, and configured to close to discharge this capacitor C.

[0299] It is important to note that for the time delay T to be stored... d_r_M T d_f_P T d_r_P and T d_f_M Each of these can have a corresponding capacitor C and a corresponding circuit, as described above.

[0300] Alternatively, for the high-side switch of one branch of the full bridge, there may be a first capacitor C and a first exemplary circuit, and for the low-side switch of the other branch of such a full bridge, there may be a second capacitor C and a second exemplary circuit, which are coupled to, for example, corresponding multiplexing circuits to receive logic pulse signals Pls_r_M or Pls_f_P and Pls_r_P or Pls_f_M, respectively.

[0301] Once such corresponding capacitors C (e.g., consider capacitor C for each time delay) store the delay-related voltages V_r_M, V_f_P, V_r_P, and V_f_M, they can be compared by any known circuit configured to perform voltage comparison operations via a voltage comparator, a switched-capacitor, a current mirror (after voltage-to-current conversion), etc. (e.g., Figure 13 The comparator circuit 606) calculates the voltage difference between V_r_M and V_f_P or between V_r_P and V_f_M.

[0302] This voltage difference between V_r_M and V_f_P or between V_r_P and V_f_M is used to detect imbalances, thereby detecting the presence of a short circuit, for example, by checking whether the absolute value of either of these voltage differences is above a voltage threshold.

[0303] For example, the operation of detecting imbalance may include comparing the absolute value of one of the voltage differences between V_r_M and V_f_P or between V_r_P and V_f_M with a voltage threshold, and indicating a short circuit if the absolute value of the considered voltage difference V_r_M-V_f_P or V_r_P-V_f_M is above the voltage threshold, or indicating no short circuit if the absolute value of the considered voltage difference is below the voltage threshold.

[0304] It should be noted that under normal driving conditions (i.e., without short circuits), this second delay-related voltage V_f_P is equal to the third delay-related voltage V_r_M.

[0305] It should also be noted that, under normal driving conditions, this fourth delay-related voltage V_f_M is equal to the first delay-related voltage V_r_P.

[0306] In the second embodiment, capacitor C is pre-charged to a given voltage, for example, equal to half of the capacitor's supply voltage, VDD / 2. Reference current I x The capacitor C can be charged by considering the logic pulse Pls_r_M, and then discharged by considering the logic pulse Pls_f_P with the reference current Ix, thereby obtaining an initial capacitor voltage equal to VDD / 2 + V_r_M - V_f_P.

[0307] Similarly, the second capacitor can be charged by considering the logic pulse Pls_f_M and then discharged by considering the logic pulse Pls_r_P, thereby obtaining a second capacitor voltage equal to VDD / 2 + V_f_M - V_r_P.

[0308] The voltages of the first and second capacitors can be compared with at least one voltage threshold, for example: a high voltage threshold VTP equal to half the supply voltage VCC plus a given margin VX (i.e., Compare with, and with, the low voltage threshold VTN (which is equal to half the supply voltage VCC minus a given margin VX) (i.e., (Compare)

[0309] For example, such a comparison operation can be performed via comparator 608, which is configured to: receive a first capacitor voltage or a second capacitor voltage at a first input terminal via a fourth switch SW3; and receive a voltage threshold, for example, a voltage threshold plus a given margin or a voltage threshold minus a given margin, at a second input terminal via a fifth switch SW4; and compare it with the received input to provide a short-circuit detection signal SD as an output.

[0310] The short-circuit detection signal SD indicates the presence of a short circuit if either of the following conditions is met: the received voltage of the first capacitor or the second capacitor is above the high voltage threshold VTP, i.e., above the voltage threshold plus a given margin; or the received voltage of the first capacitor or the second capacitor is below the low voltage threshold VTN, i.e., below the voltage threshold minus a given margin.

[0311] Otherwise, the short-circuit detection signal SD indicates that there is no short circuit.

[0312] It should be noted that logic circuit 602, storage circuit 604 and comparison circuit 606 can be controlled via state machine logic 600.

[0313] Therefore, for example, the operation of determining the absolute value of the difference between the first measurement result and the second measurement result may include: pre-charging the capacitor C to a reference voltage, preferably having a value equal to half of the supply voltage VCC; charging the capacitor C with a first voltage, which indicates the first measurement result; discharging the capacitor C with a second voltage, which indicates the second measurement result, thereby obtaining a capacitor voltage; and providing a first capacitor voltage equal to the capacitor voltage plus a margin and a second capacitor voltage equal to the capacitor voltage minus the margin as the absolute value of the difference between the first measurement result and the second measurement result.

[0314] In this case, the operation of checking whether the absolute value of the difference is higher than the aforementioned threshold may include, for example, checking via the corresponding comparator 608 whether the voltage of the first capacitor is lower than the voltage reference, i.e., whether the voltage of the capacitor is lower than the voltage reference minus a margin, or whether the voltage of the second capacitor is higher than the voltage reference, i.e., whether the voltage of the capacitor is higher than the voltage reference plus a margin.

[0315] Generally speaking, solutions using "AD" type modulation and the other time-based methods mentioned above can also be implemented via different circuits.

[0316] Figure 14 An additional exemplary circuit 60 for detecting a short circuit based on time measurement results under "AD" type modulation conditions, according to an embodiment of this description, is illustrated. It should be noted that, as described above, Figure 14 The implementation shown in the figure is just one possible implementation of the solution using both "AD" type modulation and the other time-based methods described above.

[0317] In fact, as mentioned earlier, for "AD" type modulation with a short circuit to ground (GND), the first PWM delay T d_fM_rP Second PWM delay T d_fP_rM Third PWM delay T d_rP_fM and the fourth PWM delay T d_rM_fP It can be achieved through the first output node Out P The provided PWM signal and the output from the second output node Out M The measurement is performed by direct logic processing of the provided PWM signal. The same conclusion holds true when the supply voltage VCC is short-circuited.

[0318] The first implementation converts the delay into a voltage and compares the obtained voltage with a reference voltage generated by a known time pulse. Figure 14 (Not shown in the figure) can be obtained through circuitry configured to evaluate the width of such PWM delay.

[0319] Figure 14 A simpler implementation is illustrated, which can be used if high accuracy is not required.

[0320] According to Figure 14 In the solution, the first output node Out P The provided PWM signal is converted into a first logic signal by the first comparator Cmp1.

[0321] This first comparator Cmp1 can be configured to receive signals from the first output node Out. P The provided PWM signal, along with a voltage reference threshold (e.g., a threshold having a value equal to VCC / 2), is based on the received signal from the first output node Out. P The comparison between the provided PWM signal and the voltage reference threshold provides this first logic signal as an output, for example, by the first output node Out. PWhen the provided PWM signal is higher than the voltage reference threshold, a high logic level is provided as the output; otherwise, a low logic level is provided as the output.

[0322] Similarly, from the second output node Out M The provided PWM signal is converted into a second logic signal via the second comparator Cmp2.

[0323] This second comparator Cmp2 can be configured to receive output from the second output node Out. M The provided PWM signal and voltage reference threshold, based on the received signal from the second output node Out... M The comparison between the provided PWM signal and the voltage reference threshold provides this second logic signal as an output, for example, by the second output node Out. M When the provided PWM signal is higher than the voltage reference threshold, a high logic level is provided as the output; otherwise, a low logic level is provided as the output.

[0324] A first logic signal and a second logic signal are provided to a logic XOR block 650, which is configured to perform a logic XOR operation on the first logic signal and the second logic signal.

[0325] It is important to note that in the first PWM delay T d_fM_rP Second PWM delay T d_fP_rM Third PWM delay T d_rP_fM and the fourth PWM delay T d_rM_fP During this period, the XOR of the first and second logic signals provided by the logic XOR block 650 as output can be at a low logic level (therefore, indicating that there is no short circuit to the supply voltage VCC or to ground), otherwise, the result of this XOR operation can be at a high logic level (therefore, indicating that there is a short circuit).

[0326] The XOR of the first logic signal and the second logic signal provided as output by the logic XOR block 650 can be filtered via an RC circuit including resistor 652 and capacitor 654 to determine whether the duration of the high logic level of such signal provided as output by the logic XOR block 650 is above a certain threshold.

[0327] The signal provided by the filter stage RC as output is provided as input to the inverter 656 (e.g., a CMOS buffer).

[0328] This inverter 656 is configured to provide a short-circuit detection signal SD as an output, indicating the presence of a short circuit if the signal provided by the filter stage as an output indicates that the duration is above a certain threshold, or indicating the absence of a short circuit if the signal provided by the filter stage as an output indicates that the duration is below the certain threshold.

[0329] Therefore, according to Figure 14 or Figure 12A , Figure 12B and Figure 12C In the embodiments (i.e., embodiments using "AD" type modulation), and in accordance with Figure 13 In embodiments related to the use of "BD" type modulation, the check operation for verifying a current imbalance between measurements related to the high-side switches of one branch of the full bridge and measurements related to the low-side switches of another branch of such a full bridge can be performed by considering the first node Out. P The voltage rise provided by the second node Out M The delay in the dropout of the provided voltage output, or conversely, the Out P Decrease relative to Out M The rise is delayed, as described above.

[0330] Output node Out P and Out M Normally, no logic signals are output (this is true for both voltage rail affixation and irregular frontal lines), so their outputs are converted into logic signals, for example, by using voltage comparators Cmp1 and Cmp2, with a threshold equal to, for example, VCC / 2 as described above.

[0331] For example, in relation to "BD" class modulation and according to Figure 13 In an exemplary embodiment, the output node of the full-bridge Class D amplifier can be connected to the output node of the full-bridge Class D amplifier. P and Out M The provided output signal is compared with a voltage reference threshold (e.g., a value equal to VCC / 2) to obtain a representation from node Out. P and Out M Two logic signals are provided to check for the existence of imbalance by providing the timing behavior of such output signals.

[0332] These two logic signals are provided as outputs by comparators Cmp1 and Cmp2 and sent to logic circuit 602 to generate an indication of the corresponding time delay T. d_r_M 、Td_f_P、T d_r_P and T d_f_MThe logic pulse signals Pls_r_M, Pls_f_P, Pls_r_P and Pls_f_M, for example, have a width equal to such a corresponding time delay.

[0333] In order to perform asynchronous comparison, such logic pulse signals are converted into voltage levels by charging and then discharging capacitor C according to the first and second embodiments described above.

[0334] For example, in relation to "AD" type modulation and according to Figure 14 In an exemplary embodiment, the existence of an imbalance can be checked by directly coupling the outputs of comparators Cmp1 and Cmp2 to the aforementioned logic XOR block 650; and if the resulting logic output provided by the logic XOR block 650 has a duration above a certain value, then an imbalance is determined to exist. To verify whether this duration is above the specific value, RC circuits 652 and 654, followed by an inverter 656, can be used.

[0335] Therefore, in a circuit according to the solution described herein, the first and second measurement results can be time-based measurements obtained from voltage-based measurements, preferably performed via fast comparators Cmp1 and Cmp2.

[0336] It is important to note that such comparators Cmp1 and Cmp2 should be designed to have a time response TC_rise to the rising edge and a time response TC_fall to the falling edge, such that the differences between the values ​​of the time responses TC_rise and TC_fall, and between these values ​​of TC_rise and TC_fall, are included in the output signal Out. P or Out M Within a pulse width resolution Tres (which is typically about 1 nanosecond).

[0337] Furthermore, such comparators Cmp1 and Cmp2 should be well matched, for example, with a time response difference smaller than that of the pulse width resolution Tres.

[0338] Instead, according to Figure 14 In embodiments, the checking circuit can be configured to check for an imbalance between the first and second measurement results by verifying (preferably via a logic XOR operator 650 and an RC filter stage including resistors 652 and capacitors 654 coupled to inverter 656) one of the following logic signals: a first logic signal indicating via node Out P or OutM The time behavior of the output signal provided by the high-side switch HP or HM included in one of the first and second branches of the full-bridge Class D amplifier 5 is preferably obtained via a first comparator Cmp1 having a reference voltage threshold equal to half the supply voltage VCC. This first logic signal indicates one of the first and second measurement results; and a second logic signal indicates the result via node Out. M or Out P The time behavior of the output signal provided by the low-side switch LM or LP in another of the first and second branches of the full-bridge Class D amplifier 5 is preferably obtained via a second comparator Cmp2 having a reference voltage threshold equal to half the supply voltage VCC. This second logic signal indicates whether the other of the first and second measurement results takes a specific logic level (e.g., a high logic level) for a duration higher than a duration threshold. An imbalance is determined to exist if a verification operation indicates that either the first or second logic signal takes such a specific logic level (e.g., a high logic level) for a duration higher than such a duration threshold.

[0339] It is important to note that when there is a non-negligible asymmetry in the dynamic behavior of the low-side and high-side switches of the full bridge, this asymmetry causes the rising edge of the PWM signal provided by the full bridge as an output to be delayed relative to the falling edge of another PWM signal provided by the full bridge as an output during normal drive conditions (i.e., in the absence of a short circuit). A short circuit can be detected by considering the occurrence of two consecutive pulses from the output buffer, i.e., the occurrence of two consecutive short circuit indications in the short circuit detection signal SD.

[0340] Therefore, it is important to note that by using the other methods described (or Figure 13 and Figure 14 The voltage-based method described in [the document] can also detect short circuits faster than known solutions, before the maximum current allowed to flow in the switches of the full bridge is reached, thus preventing the full bridge output stage from operating close to unsafe operating conditions.

[0341] Given the above, it should be noted that the solutions described herein facilitate the use of the asymmetry of the dynamic variables of the full-bridge Class D amplifier (i.e., current, voltage, and time delay) due to the presence of a short circuit to detect short-circuit conditions.

[0342] The solutions described herein facilitate the acquisition of methods for detecting full-bridge Class D amplifiers (such as...). Figure 1 The circuit of the full-bridge Class D amplifier 5) shown in the figure is an electrical short circuit, such as a short circuit to ground event Sh. GND Short circuit event to supply voltage ShVCC Or, in the event of a short circuit in response to a battery voltage (if different from the supply voltage VCC), this full-bridge Class D amplifier 5 includes: a first branch comprising components configured to couple between the supply voltage VCC and a first output node Out. P The first high-side switch HP is configured to be coupled to this first output node Out. P A first low-side switch LP is connected to ground GND; and a second branch includes components configured to couple to the second output node Out at this supply voltage VCC. M The second high-side switch HM between them is configured to be coupled to this second output node Out. M The second low-side switch LM between GND and ground.

[0343] The circuit according to the solution described herein includes: a measurement circuit (e.g., a current sensor I). sens Logic circuit 602 and storage circuit 604, or Figure 14 The measurement circuit (components 650-654) is configured to provide: a first measurement result (e.g., current, voltage, or time measurement result) of a first operating characteristic of a high-side switch (e.g., HP or HM) included in one of the first and second branches of the full-bridge Class D amplifier 5; and a second measurement result (e.g., also current, voltage, or time measurement result) of a second operating characteristic of a low-side switch (e.g., LM or LP, respectively) included in the other of the first and second branches of the full-bridge Class D amplifier 5; a check circuit (e.g., control logic circuit CL, comparator circuit 606, or inverter 656) configured to receive the first and second measurement results from the measurement circuit and provide an imbalance signal (e.g., a short-circuit detection signal SD) indicating the presence of an imbalance between the first and second measurement results; and a detection circuit configured to receive the imbalance signal SD from the check circuit and detect the presence of an electrical short circuit in response to the imbalance signal SD indicating the presence of an imbalance between the first and second measurement results.

[0344] Furthermore, the checking circuit according to the solution described herein can be configured to check for the existence of an imbalance between the first measurement result and the second measurement result by: determining the absolute value of the difference between the first measurement result and the second measurement result; checking whether the absolute value of the difference is higher than a threshold, such as a current, voltage, or time threshold; and if the checking operation indicates that the absolute value of the difference is higher than such a threshold, then an imbalance is determined to exist.

[0345] Therefore, the solution described herein facilitates reliable short-circuit detection and protection even in the presence of high supply voltages (e.g., supply voltages above 14.4V), thereby improving safety and preventing dangerous or fault conditions due to the presence of such short circuits. This improves the robustness of the full-bridge Class D amplifier against short circuits to supply voltage VCC, to ground GND, or to battery voltage (if different from supply voltage VCC).

[0346] Furthermore, the solution described herein facilitates the differentiation of the presence of a short circuit to ground (GND) or to the supply voltage (VCC) relative to normal driving conditions for (even very) short periods of time, such as within a few periods of the pulse width modulation (PWM) signal used to drive a full-bridge Class D amplifier.

[0347] The aforementioned short-circuit detection is performed in conjunction with the output current I supplied by the full-bridge Class D amplifier to its coupled load LD. out The value is independent of the output current I, that is, it is independent of the output current I. out It is independent of the maximum current allowed to flow in the switches of the full bridge.

[0348] In this regard, there exists an output current I that is below the maximum current allowed to flow in the transistors of a full-bridge Class D amplifier (generally considered to be the threshold for enabling overcurrent protection (OCP)). out Even with a certain value, a short circuit can still be detected.

[0349] Therefore, in the solution described herein, more time is available to enable short-circuit protection measures (i.e., OCP) before the full-bridge output stage enters unsafe operating conditions.

[0350] In fact, in each of the above methods, a short circuit can be detected before the maximum current allowed to flow in the switches of the full bridge is reached, thus preventing the full bridge output stage from operating close to unsafe operating conditions, and therefore short circuit detection is faster.

[0351] It should be noted that the solutions described in this article also refer to the detection of full-bridge Class D amplifiers (such as...). Figure 1 The diagram illustrates a method for electrical short circuits in a full-bridge Class D amplifier (5), where an electrical short circuit, for example, is a short circuit to ground (Sh). GND Short circuit event to supply voltage Sh VCC Or a short circuit event affecting the battery voltage (if it differs from the supply voltage VCC).

[0352] The full-bridge Class D amplifier 5 includes: a first branch, the first branch including components configured to be coupled to the supply voltage VCC and a first output node Out. P The first high-side switch HP is configured to be coupled to this first output node Out.P A first low-side switch LP is connected to ground GND; and a second branch includes components configured to couple to the second output node Out at this supply voltage VCC. M The second high-side switch HM between them is configured to be coupled to this second output node Out. M The second low-side switch LM between GND and ground.

[0353] The method according to the solution described herein includes: via a measurement circuit (e.g., a current sensor I) sens Logic circuit 602 and storage circuit 604, or Figure 14 Components 650-654 provide: a first measurement result (e.g., current, voltage, or time measurement result) of a first operating characteristic of a high-side switch HP or HM included in one of the first and second branches of the full-bridge Class D amplifier 5; and a second measurement result (e.g., also current, voltage, or time measurement result) of a second operating characteristic of a low-side switch LM or LP included in the other of the first and second branches of the full-bridge Class D amplifier 5; receiving the first and second measurement results from the measurement circuit at a check circuit (e.g., control logic circuit CL, comparator circuit 606, or inverter 656); providing an imbalance signal, such as the aforementioned short-circuit detection signal SD, indicating the existence of an imbalance between the first and second measurement results via the check circuit; receiving the imbalance signal SD from the check circuit at the detection circuit; and detecting the presence of an electrical short circuit via the detection circuit in response to the imbalance signal SD indicating the existence of an imbalance between the first and second measurement results.

[0354] Furthermore, the method according to the solution described herein may include checking for the existence of an imbalance between a first measurement result and a second measurement result via a checking circuit by: determining the absolute value of the difference between the first measurement result and the second measurement result; checking whether the absolute value of the difference is higher than a threshold, such as a current, voltage, or time threshold; and if the checking operation indicates that the absolute value of the difference is higher than such a threshold, then determining that an imbalance exists.

[0355] It should also be noted that the method described herein may also include any other steps to implement the operations performed by the circuit described above.

[0356] Without prejudice to the fundamental principles, details and embodiments may vary, even significantly, relative to the content described as merely an example, without departing from the scope of the embodiments.

[0357] The claims are an integral part of the technical teachings provided with respect to the embodiments.

[0358] The extent of protection is determined by the appended claims.

Claims

1. A circuit for detecting an electrical short circuit in a full-bridge Class D amplifier, wherein, The full-bridge Class D amplifier includes: a first branch, the first branch including a first high-side switch configured to be coupled between a supply voltage and a first output node and a first low-side switch configured to be coupled between the first output node and ground; and a second branch, the second branch including a second high-side switch configured to be coupled between the supply voltage and a second output node and a second low-side switch configured to be coupled between the second output node and ground; The circuit includes: A measurement circuit configured to provide a first measurement result of a first operating characteristic of a high-side switch included in one of the first and second branches of a full-bridge Class D amplifier, and a second measurement result of a second operating characteristic of a low-side switch included in the other of the first and second branches of a full-bridge Class D amplifier. A checking circuit is configured to receive a first measurement result and a second measurement result from a measurement circuit and determine an imbalance between the first measurement result and the second measurement result to provide an imbalance signal; and A detection circuit is configured to receive the imbalance signal from a check circuit and detect the presence of an electrical short circuit in response to the imbalance signal.

2. The circuit according to claim 1, wherein, The inspection circuit is configured to determine the imbalance between the first measurement result and the second measurement result by: Determine the absolute value of the difference between the first measurement result and the second measurement result; Check whether the absolute value of the difference is higher than a threshold; and It provides an imbalance signal in response to the inspection operation.

3. The circuit according to claim 1, wherein, The first measurement result and the second measurement result are based on current measurements, wherein: The first measurement result indicates the current flowing in the high-side switch; and The second measurement result indicates the current flowing in the low-side switch.

4. The circuit according to claim 1, wherein, The measurement circuit includes: A first current sensor is coupled to a first high-side switch and configured to sense the current flowing therein; A second current sensor is coupled to a second high-side switch and configured to sense the current flowing therein; A third current sensor, coupled to a first low-side switch and configured to sense current flowing therein; and A fourth current sensor, coupled to a second low-side switch and configured to sense current flowing therein; and Specifically, the first measurement result is detected by a first current sensor or a second current sensor, and the second measurement result is detected by a fourth current sensor or a third current sensor.

5. The circuit according to claim 4, wherein, Each of the first, second, third, and fourth current sensors includes an analog-to-digital converter configured to perform the following operations: The voltage sensed is proportional to the current flowing in the corresponding switch coupled to the current sensor; A reference voltage proportional to the maximum acceptable current flowing in a reference switch matched with the corresponding switch is sensed; as well as The sensed voltage is converted into a digital value based on the sensed reference voltage, and the digital value is either a first measurement result or a second measurement result.

6. The circuit according to claim 1, wherein, The measurement circuit includes: A high-side current sensor, configured to be coupled to a first high-side switch or a second high-side switch and to sense the current flowing in the coupled high-side switch; and A low-side current sensor, configured to be coupled to a second low-side switch or a first low-side switch and to sense the current flowing in the coupled low-side switch; and The first measurement result is detected by a high-side current sensor, and the second measurement result is detected by a low-side current sensor.

7. The circuit according to claim 6, wherein, Each of the high-side and low-side current sensors includes an analog-to-digital converter configured to perform the following operations: The voltage sensed is proportional to the current flowing in the corresponding switch coupled to the current sensor; A reference voltage proportional to the maximum acceptable current flowing in a reference switch matched with the corresponding switch is sensed; as well as The sensed voltage is converted into a digital value based on the sensed reference voltage, and the digital value is either a first measurement result or a second measurement result.

8. The circuit according to claim 1, wherein, The measurement circuit includes a level shifter configured to perform the following operations: The voltage is selected from one of the voltages that is proportional to the current flowing in the high-side switch included in one of the first and second branches of the full-bridge Class D amplifier and the voltage that is proportional to the current flowing in the low-side switch included in the other of the first and second branches of the full-bridge Class D amplifier. The sensed voltage level is shifted to a voltage level selected from one of the voltages proportional to the current flowing in the high-side switch included in one of the first and second branches of the full-bridge Class D amplifier and the voltage proportional to the current flowing in the low-side switch included in the other of the first and second branches of the full-bridge Class D amplifier. The sensed voltage, after level shifting, is provided as the first measurement result in response to the sensed voltage being a voltage proportional to the current flowing in the high-side switch included in one of the first and second branches of the full-bridge Class D amplifier; the sensed voltage, after level shifting, is provided as the second measurement result in response to the sensed voltage being a voltage proportional to the current flowing in the low-side switch included in the other of the first and second branches of the full-bridge Class D amplifier; and In response to the sensed voltage being a voltage proportional to the current flowing in the low-side switch included in the first branch and the second branch of the full-bridge Class D amplifier, a voltage proportional to the current flowing in the high-side switch included in the first branch and the second branch of the full-bridge Class D amplifier is provided as a first measurement result, and the level-shifted sensed voltage is provided as a second measurement result.

9. The circuit according to claim 1, wherein, The measurement circuit includes: The first level shifter is configured as follows: The voltage is sensed in proportion to the current flowing in the high-side switch included in one of the first and second branches of the full-bridge Class D amplifier; Shift the sensed voltage level to a voltage level; and The sensed voltage after level shifting is provided as the first measurement result; and The second level shifter is configured as follows: The voltage is sensed in proportion to the current flowing in the low-side switch included in the other of the first and second branches of the full-bridge Class D amplifier; Shift the sensed voltage level to the voltage level; and The sensed voltage after level shifting is provided as the second measurement result.

10. The circuit according to claim 1, wherein, The measurement circuit includes: A first branch current sensor, coupled to a first output node and configured to sense current flowing therein; and A second branch current sensor, coupled to a second output node and configured to sense the current flowing therein; and The first measurement result is detected by a current sensor selected from the first branch current sensor and the second branch current sensor, and the second measurement result is detected by the other current sensor selected from the first branch current sensor and the second branch current sensor.

11. The circuit according to claim 10, wherein, The first branch current sensor and the second branch current sensor are implemented via one of the following: shunt resistor, metal sensing or Hall effect sensing.

12. The circuit according to claim 1, wherein: The first and second measurement results are time-based measurements, and the first and second branches of the full-bridge Class D amplifier are driven via respective drivers configured to receive corresponding drive signals; and The first measurement result indicates the time delay from the rising edge of the drive signal provided to the driver of the high-side switch included in one of the first and second branches of the full-bridge Class D amplifier to the corresponding rising edge of the output signal provided by the high-side switch; and The second measurement result indicates the time delay from the falling edge of the drive signal provided to the driver of the low-side switch included in the first branch and the other branch of the full-bridge Class D amplifier to the corresponding falling edge of the output signal provided by the low-side switch.

13. The circuit according to claim 12, wherein, The measurement circuit includes: A first storage circuit, configured to store the first measurement result; and A second storage circuit, configured to store the second measurement result; and The inspection circuit is configured to receive a first measurement result and a second measurement result from the first storage circuit and the second storage circuit included in the measurement circuit, respectively.

14. The circuit according to claim 13, wherein: The first storage circuit is a first capacitor configured to store a voltage indicating a first measurement result; The second storage circuit is a second capacitor configured to store a voltage indicating the second measurement result; as well as The inspection circuit is configured to receive a voltage indicating a first measurement result and a voltage indicating a second measurement result from the first storage circuit and the second storage circuit included in the measurement circuit, respectively.

15. The circuit according to claim 12: in, The inspection circuit is configured to determine the imbalance between the first measurement result and the second measurement result by: Determine the absolute value of the difference between the first measurement result and the second measurement result; Check whether the absolute value of the difference is higher than a threshold; as well as Provides an imbalance signal in response to an inspection operation; as well as The operation of determining the absolute value of the difference between the first measurement result and the second measurement result includes: The capacitor is pre-charged to the reference voltage using a reference current; The capacitor is charged with the reference current to increase the capacitor voltage to a first voltage indicating the first measurement result; Discharging the capacitor with the reference current to reduce the capacitor voltage to a second voltage indicating the second measurement result; and Provide a first capacitor voltage equal to the capacitor voltage plus a margin and a second capacitor voltage equal to the capacitor voltage minus the margin, as the absolute value of the difference between the first measurement result and the second measurement result; and The operation of checking whether the absolute value of the difference is higher than a threshold includes checking whether the voltage of the first capacitor is lower than the voltage reference or whether the voltage of the second capacitor is higher than the voltage reference.

16. The circuit according to claim 15: in, The first voltage, indicating the first measurement result, is obtained through the following operation: Preferably, the output signal provided by the high-side switch included in one of the first and second branches of the full-bridge Class D amplifier is converted into a first logic signal indicating the time behavior of the output signal via a first comparator having a reference voltage threshold equal to half the supply voltage; as well as Preferably, the first logic signal is converted into a first voltage indicating a first measurement result by charging the first capacitor based on the first logic signal; and The second voltage, which indicates the second measurement result, is obtained through the following operation: The output signal provided by the low-side switch included in the first branch and the other of the second branches of the full-bridge Class D amplifier is converted into a second logic signal indicating the time behavior of the output signal, preferably via a second comparator having a reference voltage threshold equal to half the supply voltage; as well as Preferably, the second logic signal is converted into a second voltage indicating a second measurement result by charging the second capacitor based on the second logic signal.

17. The circuit according to claim 12, wherein, The checking circuit is configured to check for an imbalance between the first measurement result and the second measurement result by: Verify whether the logic signal takes a logic level for a duration higher than the duration threshold. as well as If the verification operation instruction logic signal takes the logic level for a duration higher than the duration threshold, then an imbalance is determined to exist. The logic signal includes one of the following: A first logic signal, indicating the time behavior of an output signal provided by a high-side switch included in one of the first and second branches of a full-bridge Class D amplifier, preferably obtained via a first comparator having a reference voltage threshold equal to half the supply voltage, and indicating one of a first measurement result and a second measurement result. The second logic signal indicates the time behavior of the output signal provided by the low-side switch included in the other of the first and second branches of the full-bridge Class D amplifier. The second logic signal is preferably obtained via a second comparator having a reference voltage threshold equal to half the supply voltage. The second logic signal indicates the other of the first and second measurement results.

18. A method for detecting an electrical short circuit in a full-bridge Class D amplifier, wherein, A full-bridge Class D amplifier includes: a first branch, the first branch including a first high-side switch configured to be coupled between a supply voltage and a first output node and a first low-side switch configured to be coupled between the first output node and ground; and a second branch, the second branch including a second high-side switch configured to be coupled between the supply voltage and a second output node and a second low-side switch configured to be coupled between the second output node and ground; the method includes: A first measurement result is provided via a measurement circuit for a first operating characteristic of a high-side switch included in one of the first and second branches of a full-bridge Class D amplifier. A second measurement result is provided via a measurement circuit to provide a second measurement result of a second operating characteristic of a low-side switch included in another of the first and second branches of a full-bridge Class D amplifier; The first and second measurement results from the measurement circuit are received at the inspection circuit. The imbalance between the first measurement result and the second measurement result is determined by the inspection circuit and an imbalance signal is generated. The imbalance signal from the inspection circuit is received at the detection circuit; and The presence of an electrical short circuit is detected by a detection circuit in response to the unbalanced signal.

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