An amorphous oxide semiconductor-based memory and sensing integrated device and method

Abstract

This invention relates to the field of semiconductor and circuit technology, and discloses an integrated sensing, storage, and computing device and method based on amorphous oxide semiconductors (AOS). The device includes a substrate, a back gate electrode, a gate dielectric layer, an AOS active layer, and source / drain electrodes. The AOS active layer responds to an externally input optical signal to generate photogenerated carriers and trigger charge trapping, causing a controllable shift in the transistor threshold voltage. This shift is stored non-volatilely as analog weighting information. During the computation phase, the device utilizes the transistor's transfer characteristics and the principle of array bit-line current superposition to perform vector-matrix multiplication operations in situ without analog-to-digital conversion. This invention achieves deep integration of optical sensing, analog storage, and in-situ computing within a single physical unit, eliminating the data transfer path between the sensor and memory, significantly reducing the power consumption and latency of the edge computing system, and its low-temperature fabrication process is compatible with back-end complementary metal-oxide-semiconductor (CMOS) integration.

Description

Technical Field

[0001] This invention relates to the field of semiconductor and circuit technology, specifically to an integrated sensing, storage, and computing device and method based on amorphous oxide semiconductors. Background Technology

[0002] With the rapid development of artificial intelligence, the Internet of Things, and edge computing technologies, smart terminal devices are placing stringent demands on their real-time processing capabilities for external physical information, especially visual information. To meet the low latency and high energy efficiency requirements of applications such as machine vision, autonomous driving, and intelligent monitoring, building a sensing and computing system capable of efficiently acquiring and processing massive amounts of image data has become a research hotspot in the field of information technology.

[0003] In existing visual information processing technologies, a hardware architecture that physically separates sensing, storage, and computing functions is typically employed. Optical signals are first converted into analog electrical signals by an image sensor, then into digital signals by an analog-to-digital converter and written into memory. Finally, the processor reads the data from memory for logical operations. Even in the recently proposed in-memory computing architecture, although the distance between storage and computing has been shortened, the sensing function is usually still independent of the in-memory computing unit. The optical signal must first undergo a complete photoelectric conversion and signal conditioning process, and then be transmitted to the in-memory array in the form of an electrical signal via a data bus before subsequent storage and computing operations can be performed.

[0004] The most critical shortcoming of the existing technology system lies in the physical isolation between the sensing module and the subsequent in-memory computing module. This forces the raw sensing data to undergo complex analog-to-digital conversion and be transferred over long distances across different units via physical interfaces. This architecture results in a significant amount of energy and time being consumed in data transmission and format conversion rather than in actual information processing, creating a difficult-to-overcome data transmission bottleneck that severely limits the system's ability to achieve ultra-low power consumption and real-time response at the edge. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an integrated sensing, storage, and computing device and method based on amorphous oxide semiconductors, which solves the problems mentioned in the background section.

[0006] To achieve the above objectives, the present invention provides the following technical solution: an integrated sensing, memory, and computing device and method based on amorphous oxide semiconductors.

[0007] The first aspect of the present invention provides an integrated sensing, memory, and computing device based on amorphous oxide semiconductor.

[0008] The device includes a substrate, a back gate electrode disposed on the substrate, a gate dielectric layer covering the back gate electrode and the substrate, an amorphous oxide semiconductor active layer disposed on the gate dielectric layer, and a source electrode and a drain electrode disposed on the amorphous oxide semiconductor active layer and forming an ohmic contact therewith.

[0009] In this process, the amorphous oxide semiconductor active layer serves as the functional entity for photoelectric conversion and charge trapping. In response to an externally input optical signal, it generates photogenerated carriers and triggers charge trapping behavior, resulting in a controllable shift in the threshold voltage of the transistor. This shift in threshold voltage is stored as analog weighting information and participates in in-situ simulation calculations based on the transistor's transfer characteristics.

[0010] Furthermore, the amorphous oxide semiconductor material is selected from one or more combinations of indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, c-axis oriented crystalline indium gallium zinc oxide, indium zinc oxide, zinc oxide, or indium tin oxide, and the material contains indium, gallium, zinc, tin, or tungsten. These materials have wide bandgap and low leakage current characteristics, which are beneficial for maintaining the storage state.

[0011] Furthermore, the integrated sensing, memory, and computing device includes memory cells arranged in an array, with the memory cells having a circuit topology of 2T0C, 1T1C, 2T1C, or 3T1C. When a 2T0C structure is used, the memory cell includes a write transistor and a read transistor. The channel layer of the read transistor uses the aforementioned amorphous oxide semiconductor active layer, and an optical signal illuminates the channel region of the read transistor to modulate its threshold voltage.

[0012] Furthermore, the device also includes a passivation layer covering the source electrode, drain electrode, and amorphous oxide semiconductor active layer, as well as an optical window formed in the passivation layer and located above the amorphous oxide semiconductor active layer. The optical window is used to define the incident path of the optical signal, allowing the optical signal to be coupled to the amorphous oxide semiconductor active layer without obstruction.

[0013] Furthermore, the integrated sensing-memory-computing device employs a differential pair structure, which consists of two physical storage units, used to store the positive and negative weight components respectively. The device acquires the output current of the two physical storage units through a differential readout circuit and outputs the current difference to achieve four-quadrant analog multiplication.

[0014] Furthermore, the integrated sensing, memory, and computing device is configured as an array structure. In the array structure, the output terminals of multiple memory cells in the same column are connected to the same bit line. The bit line converges the drain currents of multiple memory cells, and the total current on the bit line is the algebraic sum of the output currents of each memory cell, thereby realizing vector-matrix multiplication operations at the physical level.

[0015] The second aspect of the present invention provides an integrated sensing, memory, and computing device and method based on amorphous oxide semiconductor.

[0016] This method is applied to the aforementioned integrated sensing, storage, and computing device, including a sensing stage, a storage stage, a computing stage, and a reset stage.

[0017] During the sensing phase, an externally input light signal illuminates the active layer of an amorphous oxide semiconductor, exciting photogenerated electron-hole pairs and inducing charge trapping, causing a shift in the threshold voltage of the transistor.

[0018] During the storage phase, the optical signal is removed, and the threshold voltage offset is maintained by utilizing the binding effect of deep-level defects in the amorphous oxide semiconductor material on the charge.

[0019] During the calculation phase, a bias voltage is applied between the source and drain electrodes, and the drain current flowing through the amorphous oxide semiconductor active layer is detected. The drain current is the result of calculation using the input bias and the weights represented by the threshold voltage.

[0020] During the reset phase, a negative voltage pulse or photoelectric combined excitation is applied to the back gate electrode to release the trapped charge and restore the threshold voltage to the initial state.

[0021] Specifically, during the calculation phase, when the control transistor is operating in the linear region, the drain current... With gate-source voltage and threshold voltage It satisfies the following linear relationship:

[0022] in, For carrier mobility, For unit area gate dielectric capacitance, The width-to-length ratio of the channel. This is the drain-source voltage. At this point, the drain current represents the product of the input bias and the weight represented by the threshold voltage.

[0023] Alternatively, the transistor can be controlled to operate in the saturation region, with the drain current proportional to the square of the overdrive voltage, to perform nonlinear square law calculations.

[0024] Furthermore, the calculation stage also includes threshold decision and comparison functions: the gate-source voltage applied to the gate is used as a reference voltage; when the reference voltage is less than the threshold voltage, the transistor is in the off state and the output current is close to zero; when the reference voltage is greater than the threshold voltage, the transistor is turned on and outputs current; the device determines whether the threshold voltage after optical signal modulation exceeds the reference voltage based on the on / off state of the drain current.

[0025] Furthermore, the computation phase also includes performing convolution operations: mapping the convolution kernel weights to a voltage signal sequence; applying the voltage signal sequence to the drain or source electrode of the memory cell; generating a drain current by multiplying the channel conductance of the amorphous oxide semiconductor active layer with the voltage signal sequence, the channel conductance being determined by the stored image pixel value, i.e., the threshold voltage; and pooling the drain currents of multiple memory cells on the same line to complete the multiply-accumulate operation.

[0026] This invention provides an integrated sensing, storage, and computing device and method based on amorphous oxide semiconductors, achieving deep integration of optical sensing, analog storage, and in-situ computing functions within a single device structure. By directly modulating the threshold voltage of the transistor using light illumination, the analog-to-digital conversion and data writing processes after photoelectric conversion in traditional architectures are eliminated, removing the data transfer bottleneck between the sensor and the memory. Simultaneously, utilizing the transistor's inherent transfer characteristics for analog computation significantly reduces computational power consumption and improves processing speed, making it particularly suitable for edge computing and neural network inference applications. Furthermore, the device is fabricated using a low-temperature process, compatible with backend complementary metal-oxide-semiconductor (CMOS) processes, facilitating high-density three-dimensional monolithic integration.

[0027] This invention provides an integrated sensing, memory, and computing device and method based on amorphous oxide semiconductors. It offers the following advantages: 1. This invention utilizes the photoresponse characteristics of amorphous oxide semiconductors to achieve a deep integration of optical signal sensing, analog information storage, and in-situ computing functions at the physical level of a single device. This architecture completely eliminates the data transfer path between sensors, memory, and processors in traditional vision processing systems, avoids the delay and power consumption caused by multi-level signal conversion, breaks through the transmission bottleneck of the von Neumann architecture, and significantly improves the overall energy efficiency of edge computing systems.

[0028] 2. This invention establishes a mapping relationship between light dose and transistor threshold voltage, and directly stores analog weights using the non-volatile charge retention capability of memory cells. During the computation phase, vector-matrix multiplication operations are performed in parallel at the physical level by utilizing the conductance modulation characteristics of transistors and the principle of current superposition on the array bit lines. This mode eliminates the need for external analog-to-digital conversion circuits, significantly reducing the number of logic gate toggles and achieving high parallelism and low power consumption in analog computation.

[0029] 3. This invention utilizes amorphous oxide semiconductor materials that can be fabricated at low temperatures, ensuring that the fabrication process is fully compatible with the thermal budget of the back-end complementary metal-oxide-semiconductor (CMOS) process. This method supports the stacking of three-dimensional sensing-in-memory-computing (SIMC) arrays on top of logic circuits, achieving high-density vertical integration. This not only significantly reduces the planar footprint of the chip but also reduces signal delay caused by parasitic resistance and capacitance by shortening the interlayer interconnect length, enhancing the device's integration and scalability. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the overall structure of the integrated sensing, memory, and computing device based on amorphous oxide semiconductor in this invention. Figure 2 This is a schematic diagram of the structure after substrate cleaning in step 401 of the device fabrication process. Figure 3 This is a schematic diagram of the structure after the back gate electrode deposition and patterning are completed in step 402 of the device fabrication process. Figure 4 This is a schematic diagram of the structure after the back gate dielectric layer deposition is completed in step 403; Figure 5 This is a schematic diagram of the structure after the deposition of amorphous oxide semiconductor channel material in step 404; Figure 6 This is a schematic diagram of the structure after the trench isolation zone is defined and etched in step 405. Figure 7 This is a schematic diagram of the structure after the through-hole definition and etching are completed in step 406; Figure 8 This is a schematic diagram of the structure after the source / drain electrodes and interconnect metal deposition are completed in step 407.

[0031] Among them, 1 is the substrate; 2 is silicon oxide; 3 is the back gate electrode; 4 is the back gate oxide layer; 5 is the oxide semiconductor; and 6 is the source / drain contact electrode. Detailed Implementation

[0032] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Please see the appendix Figure 1 - Appendix Figure 8 This invention provides a sensing-memory-computing integrated device and method based on amorphous oxide semiconductors, which integrates optical signal sensing, information storage, and in-situ simulation computing functions at the physical level. The sensing-memory-computing integrated device includes memory units arranged in an array or independently, which serve as pixel units that perform basic functions of sensing, storage, and computing.

[0034] The core structure of a memory cell includes at least one transistor with photoresponse characteristics. The transistor includes a gate electrode, a source electrode, a drain electrode, a gate dielectric layer, and a channel layer. The channel layer is fabricated from an amorphous oxide semiconductor material. Specifically, the amorphous oxide semiconductor material is selected from one or more combinations of oxides formed from indium (In), gallium (Ga), zinc (Zn), tin (Sn), and tungsten (W). In specific implementations, the amorphous oxide semiconductor material includes, but is not limited to, indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (IAZO), indium tin zinc oxide (ITZO), c-axis oriented crystalline indium gallium zinc oxide, indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin oxide (ITO). Amorphous oxide semiconductor materials possess wide bandgap characteristics and photosensitive properties, enabling them to respond to optical signals in the visible or ultraviolet light bands, providing a physical basis for photoelectric state modulation.

[0035] The circuit topology of a memory cell employs different combinations of transistors and capacitors depending on the application requirements. These topologies include, but are not limited to, 1T1C, 2T0C, 2T1C, or 3T1C structures. For structures without explicit capacitors, such as the 2T0C structure, the memory cell utilizes the gate parasitic capacitance or channel capacitance of the transistors to maintain its charge state; for structures with explicit capacitors, information can be characterized through the charge state of the memory node.

[0036] The operation of an integrated sensing, storage, and computing device follows the timing sequence of direct photoelectric modulation and in-situ processing. The workflow of an integrated sensing, storage, and computing device mainly includes the sensing stage, storage stage, computing stage, and reset stage.

[0037] In step S100, during the sensing phase, the externally input optical signal directly acts on the amorphous oxide semiconductor channel region in the memory cell. Specifically, the optical signal enters the channel layer through a transparent electrode positioned above the transistor, or through lateral coupling into the channel layer via an integrated optical waveguide structure, or, in the case of a back-gate structure, directly irradiates the exposed channel region. The photon energy of the optical signal is greater than the optical bandgap of the amorphous oxide semiconductor material, and the photons excite electrons in the valence band of the channel layer material to transition to the conduction band, generating photogenerated carriers. Simultaneously, oxygen vacancies (…) present in the amorphous oxide semiconductor material… ) and interface defects undergo ionization or charge trapping behavior under light excitation, leading to the threshold voltage of the transistor ( ) drifts in the negative or positive direction, or causes the channel conductivity ( The threshold voltage changes. ) or the change in channel conductivity ( ) and the illumination intensity of the incident light signal ( ), wavelength of light ( ) and duration of illumination ( There is a mapping relationship. Therefore, the analog information carried by the optical signal is converted into changes in the physical parameters of the transistor, thus completing the modulation of electrical parameters by the optical signal, without the need for an external analog-to-digital converter circuit.

[0038] In step S200, during the storage stage, after the light signal irradiation is removed, due to the low leakage current characteristics of the amorphous oxide semiconductor material and the binding effect of deep-level defects on the charge carriers, the photogenerated charge carriers or ionized defect state charges generated in the sensing stage cannot recombine and be retained inside the channel layer, at the interface, or in the storage node capacitance within a short period of time. This charge retention effect allows the threshold voltage offset state or conductivity state formed in the sensing stage to remain stable for a preset retention time. At this time, the storage cell is in a non-volatile or quasi-non-volatile state after light writing, which represents the stored information. The stored information is not in binary digital form, but in the form of continuous analog electrical quantities.

[0039] In step S300, during the calculation phase, the inductive-memory-computing device directly participates in the calculation using analog electrical quantities stored in the memory cell. A predetermined read bias voltage, including the gate-source voltage, is applied to the transistors of the memory cell. ) and drain-source voltage ( According to the transfer characteristics of transistors, the drain current flowing through the channel ( Controlled by the threshold voltage maintained during the storage phase ( Depending on the transistor's operating region, such as the linear region, saturation region, or subthreshold region, the drain current and threshold voltage satisfy a specific functional relationship. Taking a transistor operating in the linear region as an example, the drain current... With threshold voltage The relationship can be approximated by formula (1):

[0040] in, For carrier mobility, For unit area gate dielectric capacitance, The width of the channel. The length of the channel. The voltage applied between the gate and the source. The voltage applied between the drain and source. This is the actual threshold voltage after optical signal modulation.

[0041] From formula (1), it can be seen that, since The output current signal already carries the information of the optical signal. This refers to the physical result of mathematical operations performed on optical signal information and electrical bias conditions. Alternatively, a differential pair structure composed of multiple transistors can be used to perform calculations based on the differential conductance changes caused by illumination. When an integrated inductive-memory-computing device contains multiple parallel-connected memory cells, the current output from each memory cell converges on a common bit line or is connected through a shared node. According to Kirchhoff's current law, the total current is the algebraic sum of the currents in each branch, thus achieving weighted summation calculations in the analog domain at the physical level. This calculation method is in-memory computation, eliminating the data movement process.

[0042] In the reset phase of step S400, in order to perform the next sensing and processing of the optical signal, it is necessary to clear the currently held charge state in the storage cell. By applying a large negative voltage pulse, reverse bias voltage, or a specific photoelectric reset signal to the gate of the transistor, the trapped charge carriers are caused to be released or recombine with charge carriers of opposite polarity, thereby reducing the threshold voltage. The device is restored to its initial state. For reset operations involving a negative voltage pulse applied to the gate, those skilled in the art can set the pulse amplitude and width according to the specific hysteresis characteristics of the device. The specific pulse generation circuit is well-known in the art and will not be described in detail here.

[0043] Through the cyclic operation of S100 to S400 described above, the integrated sensing, storage, and computing device completes the acquisition, storage, and processing of optical information in a closed loop within a single device structure, thus forming a functional unit with integrated sensing, storage, and computing characteristics.

[0044] Based on the aforementioned integrated sensing, memory, and computing architecture, integrated sensing, memory, and computing devices employ specific layered structures and material systems at the physical level to establish the foundation for photoelectric response characteristics and in-memory computing functions. The main hardware components of an integrated sensing, memory, and computing device consist of a substrate layer, a back electrode structure, a gate dielectric layer, an amorphous oxide semiconductor active layer, and a source / drain contact electrode system.

[0045] The in-memory computing device, consisting of a substrate and a back electrode structure, is built upon a substrate. The choice of substrate determines the rigidity or flexibility of the device. The substrate is selected from materials with excellent electrical insulation properties, including but not limited to rigid or flexible substrates. Specific materials for rigid substrates include glass, silicon dioxide (Si / SiO2), silicon carbide (SiC), or diamond; specific materials for flexible substrates include polyimide (PI) or polyethylene terephthalate (PET). A back gate electrode is disposed on the substrate to provide a bottom gate control voltage to modulate the channel conductivity. The material for the back gate electrode is selected from titanium (Ti), nickel (Ni), gold (Au), platinum (Pt), palladium (Pd), titanium nitride (TiN), or tungsten (W). The thickness of the back gate electrode is set between 10 nanometers and 50 nanometers. In embodiments employing bottom-light-attribution, both the substrate and the back gate electrode are made of transparent materials, or the back gate electrode is designed as a patterned structure with a light-transmitting window to allow light to pass through. In embodiments employing top-light-attribution, the back gate electrode can be made of an opaque metallic material to block stray light interference from the substrate side. The patterned structure of the back gate electrode is defined by electron beam lithography or photolithography processes and deposited by electron beam evaporation or magnetron sputtering processes.

[0046] The gate dielectric layer system covers the back gate electrode and the substrate, serving to isolate the gate electrode from the subsequently deposited channel layer and provide gate-controlled electric field coupling. The gate dielectric layer employs a high-dielectric-constant material or a conventional silicon oxide material, specifically selected from one or more stacked combinations of silicon dioxide (SiO2), silicon nitride (SiNx), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrOx), hafnium aluminum oxide (HfAlOx), hafnium silicon oxide (HfSiOx), hafnium lanthanum oxide (HfLaOx), hafnium zirconium lanthanum oxide (HfZrLaOx), hafnium zirconium aluminum oxide (HfZrAlOx), zirconium aluminum oxide (ZrAlOx), or zirconium lanthanum oxide (ZrLaOx). The gate dielectric layer is prepared using plasma-enhanced atomic layer deposition (PEALD), utilizing plasma-activated deposition to improve film density and reduce interface defect density, thereby suppressing leakage current and enhancing the controllability and reliability of the threshold voltage.

[0047] The active layer, located above the gate dielectric layer, serves as the photosensitive and electrical transport channels for integrated sensing, memory, and computing devices. The active layer is made of amorphous oxide semiconductor materials, specifically indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (IAZO), indium tin zinc oxide (ITZO), c-axis oriented crystalline indium gallium zinc oxide, indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin oxide (ITO). By adjusting the molar ratio of metal cations such as indium (In), gallium (Ga), zinc (Zn), tin (Sn), or tungsten (W) in the amorphous oxide semiconductor material, the carrier concentration of the material can be precisely controlled. For example, adjusting the indium ratio controls electron mobility, while adjusting the gallium or tungsten ratio controls oxygen vacancy generation and device stability. The thickness and composition ratio of the active layer are specifically configured to generate photogenerated carriers or trigger defect state charge trapping / release mechanisms at the target light wavelength, thereby establishing the response relationship between light intensity and threshold voltage offset. The active layer is formed into independent active islands through photolithography and etching processes, achieving electrical isolation between devices.

[0048] The source and drain electrodes are located on opposite sides of the active layer, forming ohmic contacts with the active layer via vias or direct contact. The materials for the source and drain electrodes are selected from metals such as titanium (Ti), nickel (Ni), gold (Au), platinum (Pt), palladium (Pd), titanium nitride (TiN), or tungsten (W) and their alloys. To reduce contact resistance, the contact area is plasma-treated before metal deposition or a low work function metal is used as the contact layer. The source and drain electrodes also serve as interconnects, connecting multiple memory cells into an array structure.

[0049] The circuit topology unit structure realizes the storage unit of the integrated sensing, storage, and computing device. Based on the aforementioned material system, a specific circuit topology structure is constructed, utilizing light illumination to change the threshold voltage of the transistor or the potential of the storage node to achieve information storage. When a 2T0C (two-transistor zero-capacitance) structure is used, the storage unit includes a write transistor and a read transistor. The read transistor uses the aforementioned amorphous oxide semiconductor active layer. When a light signal illuminates the channel region of the read transistor, it induces charge trapping at the channel layer or interface, causing a non-volatile or quasi-non-volatile drift in the threshold voltage of the read transistor. This drifted threshold voltage state is the stored analog weight information, which directly affects the current flowing through the read transistor in subsequent calculations. When a 1T1C (one-transistor-one-capacitor) structure is used, the storage unit includes a gating transistor and a storage capacitor. The gating transistor uses the aforementioned amorphous oxide semiconductor active layer. In one operating mode, the optical signal illuminates the gating transistor, changing its threshold voltage and thus altering the charging or discharging characteristics of the storage capacitor. In another operating mode, the optical signal directly acts on the capacitive structure serving as the storage node or the photosensitive region connected to it, changing the amount of charge on the storage node and consequently altering the potential state of the storage cell. For multi-transistor structures such as 2T1C or 3T1C, additional transistors are used to control the reset path of the storage node or to construct a differential pair structure to achieve accurate reading or differential calculation of the photoinduced threshold voltage offset.

[0050] To ensure effective optical signal transmission to the active layer, the optical coupling and passivation structure of the integrated sensing-memory-computing device (IMC) incorporates specific optical path configurations. When using top-incidence illumination, the passivation layer and interlayer dielectric layer above the active layer are made of insulating materials transparent to the operating wavelength, such as silicon oxide or aluminum oxide. If a metal interconnect layer exists above the device, a light window is created in the region corresponding to the transistor channel to prevent light blockage. In another embodiment, a transparent conductive oxide is used as the source / drain electrode or top gate electrode to achieve a fully transparent device structure, maximizing light absorption efficiency. When using bottom-incidence illumination, a transparent substrate and a transparent back gate electrode are required.

[0051] The material system and structural configuration described above utilize the low-temperature fabrication process characteristics of amorphous oxide semiconductors, enabling compatibility with back-end processes and supporting monolithic three-dimensional integration on silicon-based CMOS circuits, thereby realizing a high-density integrated array chip for sensing, storage, and computing.

[0052] Based on the aforementioned device structure and material system, the integrated sensing, storage, and computing device utilizes the bandgap modulation and carrier transport characteristics of amorphous oxide semiconductors under the influence of optical and electric fields to cascade sensing, storage, and computing functions within a single physical unit. The following section provides a detailed explanation of the physical implementation mechanisms in the aforementioned overall workflow S100 to S400.

[0053] Sub-step S110: Photoelectric response and defect dynamics mechanism in the sensing stage.

[0054] As a specific physical layer implementation of the sensing stage in step S100, the integrated sensing, storage, and computing device utilizes the photoelectric response characteristics of amorphous oxide semiconductor materials to convert photon energy into changes in internal charge state.

[0055] When a light signal with a specific wavelength shines on the active layer of an amorphous oxide semiconductor, if the photon energy ( The optical band gap of amorphous oxide semiconductor materials is greater than that of amorphous oxide semiconductor materials. Photons excite valence band electrons to jump to the conduction band, generating non-equilibrium photogenerated electron-hole pairs.

[0056] Based on this, illumination triggers a metastable charge trapping process within the material. Taking indium gallium zinc oxide (IGZO) as an example, the deep-level defects existing in amorphous oxide semiconductor materials are specifically manifested as neutral oxygen vacancies (…). Under photoexcitation, an ionization reaction occurs. Neutral oxygen vacancies release electrons and transform into positively charged doubly ionized oxygen vacancies (…). This process is accompanied by relaxation changes in the crystal lattice structure. Simultaneously, under the influence of the built-in electric field or the negative bias electric field applied by the gate, photogenerated holes drift towards the gate dielectric layer interface and are captured by deep-level traps at the interface. This physical process establishes a mapping relationship between light intensity and the amount of trapped charge.

[0057] Sub-step S210: Charge retention and threshold voltage modulation during the storage phase.

[0058] As a physical layer implementation of the storage stage in step S200, the inductive-memory-computing integrated device utilizes the deep energy level characteristics and barrier effect of the defect state to achieve non-volatile or quasi-non-volatile retention of information.

[0059] Due to double-ionized oxygen vacancies ( Structural relaxation occurs, forming energy level barriers, and interface traps exert a strong binding effect on charges. The trapped positive charges generated in step S110 cannot recombine with electrons immediately after the light is removed. These trapped positive charges form stable positive charge centers in the channel region or at the interface.

[0060] According to the principles of semiconductor physics, the positive charge center generates electrostatic induction and shielding effect on the channel energy band, causing a shift in the flat-band voltage of the transistor, which macroscopically manifests as the threshold voltage of the transistor. The threshold voltage drifts in the negative direction. The cumulative exposure of the incident light signal (light intensity) With time The integral of the signal exhibits a monotonic functional relationship. Therefore, the input analog optical signal is directly converted into the threshold voltage parameter of the transistor. The value represents the stored simulated weight information.

[0061] Sub-step S310: Implementation of unit-level operation mode in the calculation stage.

[0062] As a specific implementation of the calculation stage in step S300 at the unit level, the inductive-memory-computing integrated device utilizes the transfer characteristics of transistors in different working regions (linear region, saturation region, cutoff region) to perform different types of mathematical operations or logical decisions.

[0063] Mode 1: Linear multiplication operation.

[0064] When the transistor is biased in the linear region, the drain-source voltage is controlled ( The voltage is constant and small, and the channel is equivalent to a voltage-controlled variable resistor. At this time, the drain current flowing through the memory cell ( ) and gate-source voltage ( ) and stored threshold voltage ( The relationship between the drain current and the drain current follows the formula (1) described above. In this mode, the drain current... Physically, it represents the input bias ( ) and storage weight ( The product of related items.

[0065] Mode 2: Non-linear operation.

[0066] When the transistor is biased in the saturation region, the drain current and the overdrive voltage ( The current is proportional to the square of the current, and the physical implementation of the square law calculation shows the current relationship as shown in formula (2):

[0067] Utilizing the nonlinear characteristics of formula (2), the integrated sensing, storage, and computing device can construct a hardware unit for calculating Euclidean distance.

[0068] Mode 3: Threshold decision and comparison function.

[0069] Threshold determination and comparison at the physical level are achieved by utilizing the switching characteristics of transistors. When the applied gate-source voltage... Less than the storage threshold voltage When the transistor is in the off state, the output current is close to zero, representing logic 0; when When the transistor is turned on and outputs a significant current, it represents a logic 1. This mechanism allows the device to directly determine the state after photo-induced drift. Does it exceed the reference voltage? The threshold truncation operation of the activation function is performed within the cell.

[0070] Sub-step S320: Implementation of array-level vector-matrix multiplication in the computation phase.

[0071] As a specific implementation of the calculation stage in step S300 at the array level, multiple storage cells are arranged as follows: An array of columns is used to perform parallel computations. Input data is encoded as voltage signals and applied in parallel to the word lines or source lines of the array.

[0072] For any column in the array, all memory cells connected to the bit lines of that column operate simultaneously. According to Kirchhoff's current law, the total current on the bit lines ( The sum of the drain currents of all the turn-on cells in the column is the physical superposition of the drain currents, as shown in formula (3):

[0073] in, For the first Total output current of the column For the first Unit current. Total output current. Physically, it represents the result of the dot product operation between the input vector and the column weight vector.

[0074] Sub-step S330: Implementation of the differential computation architecture in the computation phase To handle matrix operations involving negative weights and suppress common-mode noise at the physical level, inductive-memory-computing (IMC) devices employ a differential pair structure. Two physical memory cells constitute one logical computation bit, storing the positive weight components respectively. ) and negative weighted components ( ).

[0075] The system uses a differential readout circuit to simultaneously acquire the current of two corresponding bit lines and outputs the current difference ( As shown in formula (4):

[0076] By adjusting the relative magnitudes of the threshold voltages of the two units, even if the physical conductivity of the transistor is only positive, the output differential current can be adjusted. It can still be represented as a positive value, a negative value, or zero, thus realizing a complete four-quadrant analog multiplication operation.

[0077] Sub-step S410: Charge release mechanism during the reset phase.

[0078] As a specific physical layer implementation of the reset phase in step S400, it is necessary to restore the charge state in the amorphous oxide semiconductor channel to its initial level.

[0079] By applying a large negative voltage pulse to the transistor gate, a strong electric field is established at the gate dielectric layer interface, causing trapped holes to tunnel back into the channel or injected electrons to neutralize; or by applying a reverse bias voltage and supplementing it with short-wavelength light, photon energy is provided to excite double-ionized oxygen vacancies to trap electrons and restore them to a neutral state. This reset operation eliminates the positive charge centers formed in step S110, reducing the transistor's threshold voltage. Return to the initial high-level state to prepare for the next sensing and storage cycle.

[0080] To fabricate devices with integrated sensing, memory, and computing capabilities, this specific embodiment provides a low-temperature fabrication method. This method is compatible with existing complementary metal-oxide-semiconductor (CMOS) back-end processes (BEOL) and is suitable for three-dimensional monolithic integration on silicon-based logic circuits or flexible substrates. The fabrication process is illustrated below using a 2T0C dynamic random access memory cell based on a bottom-gate structure as an example.

[0081] Process step S401: Substrate cleaning and pretreatment.

[0082] The fabrication process begins with substrate preparation. The substrate can be selected from rigid or flexible materials. Rigid materials include glass, silicon wafers (Si), silicon carbide (SiC), or diamond; flexible materials include polyimide (PI) films. Taking a silicon-based silica (Si / SiO2) substrate with good electrical insulation as an example, standard RCA-1 cleaning solution is used to remove surface particles and organic contaminants. A mixture of deionized water, ammonia, and hydrogen peroxide in a 1:1:1 volume ratio is prepared, and the substrate is immersed in the cleaning solution at 70°C for 10 minutes. Subsequently, the substrate is ultrasonically cleaned in deionized water for 10 minutes, and finally dried using a high-purity nitrogen gun to obtain a clean process substrate.

[0083] Process step S402: Deposition and patterning of the back gate electrode.

[0084] Back gate electrodes were fabricated on a clean substrate. First, an electron beam photoresist, polymethyl methacrylate (PMMA 950K A4), was spin-coated onto the substrate surface at a spin speed of 3000 rpm for 60 seconds, followed by baking on a hot plate at 170°C for 180 seconds. The back electrode area was then exposed using an electron beam exposure system (e.g., Raith 150) with an exposure dose of 400 microcoulombs per square centimeter (μC / cm²). Development was performed using a mixture of methyl isobutyl ketone (MIBK) and isopropanol (IPA) at a ratio of 1:3 for 60 seconds, followed by fixing in isopropanol for 60 seconds and drying with nitrogen. On the patterned substrate, a metal material was deposited using electron beam evaporation or magnetron sputtering. The metal material was selected from titanium (Ti), nickel (Ni), gold (Au), platinum (Pt), palladium (Pd), titanium nitride (TiN), or tungsten (W), with a deposition thickness controlled between 10 nm and 50 nm. After deposition, the sample was immersed in a 90°C resist remover for 120 minutes for a lift-off operation to remove the photoresist and its attached metal layer, leaving only the back gate electrode structure deposited on the substrate surface. Finally, the sample was cleaned sequentially with acetone and isopropanol and then dried.

[0085] Process step S403: Growth of a high-quality gate dielectric layer.

[0086] A gate dielectric layer is deposited on the back gate electrode, using materials selected from silicon dioxide (SiO2), silicon nitride (SiNx), or high dielectric constant materials. This embodiment employs plasma-enhanced atomic layer deposition (PEALD). Before deposition, the sample is placed in a plasma generator, with argon (Ar) at a flow rate of 40 sccm and oxygen (O2) at 10 sccm. The radio frequency power is set to 30 watts (W), and the processing time is 3 minutes to improve the hydrophilicity of the substrate surface. Subsequently, the sample is transferred to the PEALD reaction chamber, where the plasma power is set to 100 W, and metal precursors and oxidants are alternately introduced to grow the gate dielectric film layer by layer. This step utilizes the plasma enhancement properties to improve film density and reduce interface defect density.

[0087] Process step S404: Deposition and control of the active layer of amorphous oxide semiconductor.

[0088] An amorphous oxide semiconductor thin film is deposited on the gate dielectric layer as the active layer. The active layer material is specifically selected from indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (IAZO), indium tin zinc oxide (ITZO), C-axis oriented crystalline indium gallium zinc oxide (CAAC-IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin oxide (ITO). The deposition process employs PEALD technology, with a plasma power set to 100W. In this step, the stoichiometry of the channel material is controlled by precisely adjusting the pulse ratio of the indium (In), gallium (Ga), and zinc (Zn) metal precursors to balance the device's carrier mobility and threshold voltage characteristics.

[0089] Process step S405: Device isolation and active region definition.

[0090] Patterned etching was performed on the continuously deposited semiconductor thin film to form independent active area islands. Electron beam photoresist was spin-coated at 6000 rpm for 60 seconds, followed by baking at 150°C for 180 seconds. Channel isolation regions were defined using an electron beam exposure system with an exposure dose set to 150 μC / cm². The development process involved 60 seconds of development with methyl isobutyl ketone and 40 seconds of fixing with isopropanol. A wet etching process was employed, using a dilute hydrochloric acid solution with a 1:100 ratio of concentrated hydrochloric acid to deionized water. The sample was immersed in the solution for 30 seconds. After etching, the photoresist was removed by immersing the sample in an N-methylpyrrolidone remover solution at 120°C for 3 hours, followed by rinsing and drying.

[0091] Process step S406: Etching of through-hole contact holes.

[0092] Vias were created in the dielectric layer to expose the underlying metal. Electron beam photoresist was spin-coated at 4000 rpm for 60 seconds, followed by baking at 150°C for 180 seconds. The via regions were defined using a dose of 140 μC / cm² and developed. The dielectric layer in the via regions was removed using an inductively coupled plasma dry etching system. Finally, the photoresist was removed using NMP stripper.

[0093] Process step S407: Fabrication of source / drain electrodes and interconnect metal.

[0094] PMMA 950K photoresist was spin-coated at 4000 rpm for 60 seconds, followed by baking at 170°C for 180 seconds. Electron beam lithography was used to define interconnect lines and contact metal patterns at a dose of 450 μC / cm². After development, metal layers were deposited using electron beam evaporation or sputtering processes. The metals were selected from titanium, nickel, gold, tungsten, etc., with a thickness of 10-50 nanometers. A stripping process was performed by immersion in a 90°C resist remover for 120 minutes to form the source / drain electrodes and interconnect network.

[0095] Process step S408: Passivation layer deposition and photosensitive area definition.

[0096] To protect the device and define the incident path of optical signals, a passivation layer is deposited on top of the interconnect metal layer. The passivation layer material is an insulating material with high transmittance to the operating light wavelength, such as silicon oxide or aluminum oxide. After deposition, photolithography or electron beam lithography is used to define the photosensitive window region, and dry etching is used to remove part or all of the passivation layer above the photosensitive area, forming a light window that leads directly to the amorphous oxide semiconductor channel. This step ensures that external optical signals can be coupled to the transistor channel without obstruction, completing the final fabrication of the integrated sensing, memory, and computing device.

[0097] Based on the aforementioned device fabrication processes and physical principles, integrated sensing, storage, and computing devices have specific application implementation methods in the fields of visual edge computing and neural network inference. The following examples demonstrate how the devices work collaboratively at the array level to accomplish specific tasks.

[0098] Example 1: Image edge feature extraction based on integrated sensing, storage, and computing array: This embodiment utilizes the sensing and storage characteristics of integrated sensing, storage, and computing devices to record images, and directly extracts image edges using in-situ computing characteristics.

[0099] In the sensing and storage phase of image light field information, an optical image containing the information to be processed is projected onto the surface of an integrated sensing-memory-computing array via an optical system. Each storage unit in the array corresponds to a pixel in the image. According to the photoelectric response principle, the threshold voltage offset in the active layer of the amorphous oxide semiconductor is positively correlated with the incident light intensity. The light intensity distribution at different locations in the image is converted into the spatial distribution of the threshold voltages of each transistor in the array. After illumination, due to the charge retention characteristics of the device, the image information is non-volatilely stored in the array in the form of an analog conductance matrix, without the need for analog-to-digital conversion or external memory writing.

[0100] Voltage Mapping and In-Situ Computation of Convolution Kernel Operator: To perform edge detection, the inductive-memory-acrylonitrile (IMCA) array performs analog convolution operations based on Ohm's law and Kirchhoff's laws. The weight values ​​of the convolution kernel are mapped to an input voltage vector. During the computation phase, a voltage signal sequence representing the convolution kernel weights is applied to the drain (or source) drive lines of the memory cells, while the gate voltage is controlled to operate the transistors in the linear resistance region. The current flowing through each memory cell is the product of the cell's channel conductance (determined by the stored image pixel value, i.e., the threshold voltage) and the drain-source voltage (determined by the convolution kernel weights). The output currents of multiple memory cells connected to the same bit line are physically and automatically added together, completing the multiply-accumulate (MAC) operation in the convolution operation. The total current output by the bit line directly characterizes the gradient features of the image in the corresponding region. Through the parallel operation of the array, the device directly outputs pre-processed feature map data.

[0101] Example 2: In this embodiment, an integrated sensing, storage, and computing device is used as the hardware acceleration unit of the neural network, and optical signals are used to configure the network weights.

[0102] In the network deployment phase, optical programming of synaptic weights utilizes a sequence of light pulses of controllable intensity to address and illuminate the integrated sensing, memory, and computing array. By adjusting the cumulative exposure of the light pulses, the threshold voltage of the transistors in each memory cell is precisely modulated. Different threshold voltage states correspond to the trained synaptic weight values ​​in the neural network model. This process completes the mapping from software weights to hardware physical parameters.

[0103] Input vector loading and array-level analog inference: During the inference phase, the data vector to be processed (such as feature vectors) is converted into a voltage signal and loaded in parallel onto the word lines or data lines of the array. The input voltage signal acts directly on the gate or drain of the memory cell. The input voltage physically interacts with the weight parameters in the memory cell, generating a controlled drain current. The current converges on each column bit line, representing the activation input value of the neuron. Subsequently, a transimpedance amplifier in the peripheral circuitry converts the current signal into a voltage signal and transmits it to the next stage of the circuitry. This process performs vector-matrix multiplication within the analog domain, avoiding the data movement bottleneck in the von Neumann architecture.

[0104] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A sensing-memory-computing integrated device based on amorphous oxide semiconductor, characterized in that, It includes the following components: substrate, back gate electrode, amorphous oxide semiconductor active layer, source electrode, drain electrode, passivation layer, and optical window; A back gate electrode is disposed on the substrate; A gate dielectric layer covers the back gate electrode and the substrate; An amorphous oxide semiconductor active layer is disposed on the gate dielectric layer, and the amorphous oxide semiconductor active layer is made of an amorphous oxide semiconductor material; The source electrode and drain electrode are disposed on the amorphous oxide semiconductor active layer and form an ohmic contact with the amorphous oxide semiconductor active layer; In this process, the amorphous oxide semiconductor active layer generates photogenerated carriers in response to an externally input optical signal and triggers charge trapping, causing a shift in the threshold voltage of the transistor. The shift in the threshold voltage is used as stored analog weight information and participates in in-situ simulation calculations based on the transistor transfer characteristics.

2. The integrated sensing, memory, and computing device based on amorphous oxide semiconductor according to claim 1, characterized in that, The amorphous oxide semiconductor material is selected from one or more combinations of indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, C-axis oriented crystalline indium gallium zinc oxide, indium zinc oxide, zinc oxide, or indium tin oxide; the amorphous oxide semiconductor material contains indium, gallium, zinc, tin, or tungsten.

3. The integrated sensing, memory, and computing device based on amorphous oxide semiconductor according to claim 1, characterized in that, The integrated sensing, storage, and computing device includes memory cells arranged in an array. The circuit topology of the memory cells is a 2T0C structure, a 1T1C structure, a 2T1C structure, or a 3T1C structure. When the 2T0C structure is used, the memory cell includes a write transistor and a read transistor. The channel layer of the read transistor is the amorphous oxide semiconductor active layer. The optical signal illuminates the channel region of the read transistor to modulate the threshold voltage of the read transistor.

4. The integrated sensing, memory, and computing device based on amorphous oxide semiconductor according to claim 1, characterized in that, The passivation layer covers the source electrode, the drain electrode, and the amorphous oxide semiconductor active layer. The optical window is formed in the passivation layer and located above the amorphous oxide semiconductor active layer. The optical window is used to define the incident path of the optical signal, so that the optical signal is coupled to the amorphous oxide semiconductor active layer without obstruction.

5. The integrated sensing, memory, and computing device based on amorphous oxide semiconductor according to claim 1, characterized in that, The integrated sensing, storage, and computing device adopts a differential pair structure, which consists of two physical storage units, used to store positive weight components and negative weight components respectively. The integrated sensing, storage, and computing device acquires the output current of the two physical storage units through a differential readout circuit and outputs the current difference to realize four-quadrant analog multiplication operation.

6. The integrated sensing, memory, and computing device based on amorphous oxide semiconductor according to claim 1, characterized in that, The integrated sensing, storage, and computing device is configured as an array structure. The output terminals of multiple memory cells in the same column of the array structure are connected to the same bit line. The bit line converges the drain currents of the multiple memory cells. The total current on the bit line is the algebraic sum of the output currents of each memory cell, thereby physically implementing vector-matrix multiplication.

7. A method for fabricating an integrated sensing, memory, and computing device based on amorphous oxide semiconductor, characterized in that, The device, applied to any one of claims 1 to 6, comprises the following steps: Step S100 Sensing Stage: The externally input light signal irradiates the amorphous oxide semiconductor active layer, exciting photogenerated electron-hole pairs and inducing charge trapping, causing the threshold voltage of the transistor to shift. Step S200 Storage stage: Remove the optical signal and use the binding effect of deep energy level defects on charges to maintain the offset state of the threshold voltage; Step S300 Calculation stage: Apply a bias voltage between the source electrode and the drain electrode, and detect the drain current flowing through the amorphous oxide semiconductor active layer. The drain current is the result of the calculation of the input bias amount and the weight represented by the threshold voltage. Step S400 Reset Phase: Apply a negative voltage pulse or photoelectric combined excitation to the back gate electrode to release the trapped charge and restore the threshold voltage to the initial state.

8. The method for fabricating an integrated sensing, memory, and computing device based on amorphous oxide semiconductor according to claim 7, characterized in that, In the calculation stage of step S300, the control transistor operates in the linear region, the drain current satisfies the linear relationship with the gate-source voltage and the threshold voltage, and the drain current represents the product of the input bias and the weight represented by the threshold voltage. Alternatively, the transistor can be controlled to operate in the saturation region, with the drain current proportional to the square of the overdrive voltage, to perform nonlinear square law calculations.

9. The method for fabricating an integrated sensing, memory, and computing device based on amorphous oxide semiconductor according to claim 7, characterized in that, In the calculation stage of step S300, the threshold decision and comparison function is executed: The gate-source voltage applied to the gate is used as the reference voltage; When the reference voltage is less than the threshold voltage, the transistor is in the off state and the output current is close to zero. When the reference voltage is greater than the threshold voltage, the transistor turns on and outputs current; The integrated sensing, storage, and computing device determines whether the threshold voltage after the optical signal modulation exceeds the reference voltage based on the on / off state of the drain current.

10. The method for fabricating an integrated sensing, memory, and computing device based on amorphous oxide semiconductor according to claim 7, characterized in that, The calculation phase of step S300 includes performing convolution operations: Map the convolution kernel weights to a voltage signal sequence; The voltage signal sequence is applied to the drain electrode or the source electrode of the memory cell; The drain current is generated by multiplying the channel conductivity of the amorphous oxide semiconductor active layer with the voltage signal sequence, and the channel conductivity is determined by the stored image pixel value, i.e., the threshold voltage. The drain currents of multiple memory cells on the same bit line are pooled to complete the multiply-accumulate operation.

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