A method, system, and storage medium for 3D integrated circuit power integrity analysis

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a method, system and storage medium for 3D integrated circuit power integrity analysis. The method solves the problems that the existing fixed spatial resolution image modeling is difficult to uniformly represent the heterogeneous PDN due to the significant difference in the geometric scale of the substrate and the interposer and the complex vertical interconnection structure, and the traditional sparse direct solver is insufficient in calculation efficiency. The technical scheme comprises the following steps: converting the PDN layout into an undirected weighted graph, wherein the nodes include voltage source ports, current sink nodes and internal nodes, and the edge weight is the conductance value; inputting the graph neural network, iteratively learning the equivalent admittance matrix through the physical information message passing mechanism, and updating the node message based on the weighted product of the difference between the adjacent node embedding vectors and the edge conductance; constructing a simplified symmetric positive definite linear equation system according to the equivalent admittance matrix and the port current vector, and solving the port voltage by using a lightweight numerical solver; and the system and the storage medium are used for executing the above method.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and provides a method, system, and storage medium for power integrity analysis of 3D integrated circuits. Background Technology

[0002] Three-dimensional integrated circuits (3D ICs) have densely stacked chips and multi-layered interconnect structures, leading to increasingly complex power delivery networks (PDNs). As design complexity increases, there is an urgent need for left-shift design space exploration (DSE)[1] to ensure early power integrity (PI) convergence[2-4]. This requires fast and scalable DC PI analysis[5,6]. Figure 2 However, achieving fast DC PI analysis for 3DICs remains challenging because PDNs contain a large number of elements, including vias [7-10], metal segments, and irregular power planes

[11] , and exhibit strong cross-scale behavior, with the substrate and interposers differing by several orders of magnitude in geometry

[12] . Typical DC PI analysis involves solving large-scale symmetric positive definite (SPD) systems derived from Kirchhoff's current law (KCL)

[13] . Sparse direct solvers such as Cholesky decomposition

[14] provide robust and accurate results, but become extremely slow on industrial scales [15-18].

[0003] Recent learning-based methods [19-25] have accelerated PI analysis by using convolutional neural networks to encode layout geometry and electrical parameters into multi-channel feature maps, predicting voltage distribution in on-chip scenes. While these methods offer significant runtime advantages, they still face several fundamental limitations.

[0004] First, the complex vertical interconnects and multi-scale PDN structures in 3D ICs pose challenges to image-based modeling. State-of-the-art methods [23,26] employ optimized U-Nets

[27] to process multi-channel images from spatially distributed features such as current density, wire resistance, and power-to-ground distance. However, constructing these feature maps requires a fixed spatial resolution

[26] , which is difficult for 3D ICs: the interposers require fine-grained resolution, which becomes impractical for large substrate areas, while the substrate requires coarse-grained resolution, which may obscure critical interposer details.

[0005] To overcome this limitation, we employ element-based graph PDN modeling, representing the PDN as an electrical graph directly extracted from the layout. Equivalent resistive circuit elements (including wires, vias, and power planes) become graph components annotated with physical parameters. This approach naturally adapts to different geometric scales of the substrate and interposers, enabling unified modeling of heterogeneous PDN structures without relying on a fixed spatial grid. The resulting graph representation supports the use of graph neural networks (GNNs) to learn electrical behavior, enabling fast and scalable DC PI evaluation.

[0006] Secondly, traditional GNN architectures struggle to capture the underlying circuit physics and network topology. Recent neural methods [28,29] attempt to embed circuit behavior into graph-based learning. Circuit-GNN

[28] learns node currents as residual terms to approximate current conservation, while GTN

[29] employs attention-based message passing to capture global voltage dependencies. However, these methods primarily aggregate neighboring features without explicitly modeling the voltage differences that determine current flow between connected nodes.

[0007] To bridge this gap, we devise a physical information messaging scheme tailored to circuit behavior. Our formula introduces a voltage difference-driven message propagation mechanism, where information flows between adjacent nodes according to their voltage difference and are weighted by the corresponding equivalent admittance, thereby directly embedding Kirchhoff-consistent physical behavior into the graph.

[0008] Finally, left-shift designs require fast and robust DC PI evaluation. Traditional numerical solvers cannot meet the turnaround time requirements of iterative left-shift workflows due to computational overhead

[30] . Learning methods that directly predict port voltages [28,29] improve speed, but often lack accuracy and robustness.

[0009] To achieve both high speed and high fidelity, we propose a two-stage voltage prediction method based on the Schur complement neural approximation. The GNN first learns the equivalent admittance matrix (Schur complement) between the VRM (Voltage Regulation Module) and the sink; then, a lightweight numerical solver calculates the port voltage using the simplified SPD system obtained from the solution. This hybrid design combines the efficiency of neural inference with the accuracy of physics-based solutions, making it ideal for fast and reliable DC PI evaluation in left-shift design flows.

[0010] In summary, there is an urgent need for a DC PI analysis method that can uniformly handle multi-scale heterogeneous structures, explicitly incorporate circuit physical mechanisms (especially voltage difference and current conservation), and simultaneously achieve high speed, high fidelity, and good generalization ability. Summary of the Invention

[0011] The purpose of this invention is to address the problems in 3D integrated circuits' power transport networks (PDNs). Due to the significant differences in geometric scale between the substrate and the interposer (cross-scale characteristics) and the complex vertical interconnect structure, existing image modeling methods based on fixed spatial resolution are unable to uniformly represent heterogeneous PDNs (the interposer requires fine-grained resolution while the substrate requires coarse-grained resolution). Traditional sparse direct solvers have low computational efficiency, and existing graph neural network methods lack explicit modeling of circuit physical laws such as voltage difference-driven current flow. As a result, DC power integrity analysis is slow, it is difficult to meet the strict turnaround time requirements of left-shift design space exploration, and there are shortcomings in prediction accuracy, physical consistency, and generalization ability across excitation scenarios.

[0012] To achieve the above objectives, the present invention employs the following technical means:

[0013] This invention provides a method for power integrity analysis of 3D integrated circuits, comprising the following steps:

[0014] Step 1: Obtain the power delivery network (PDN) layout of the 3D integrated circuit, convert the PDN layout into an equivalent resistance network, and represent the equivalent resistance network as an undirected weighted graph; wherein, the nodes of the undirected weighted graph include voltage source port nodes, current sink nodes, and internal nodes, and the weight of the edge is the conductance value of the corresponding resistor connection.

[0015] Step 2: Input the undirected weighted graph into the graph neural network. The graph neural network performs multiple iterations through a physical information message passing mechanism to learn the equivalent admittance matrix between the voltage source port node and the current sink node; where, in each iteration, the message update of the node is based on the weighted product of the difference between the embedding vectors of adjacent nodes and the corresponding edge conductance value.

[0016] Step 3: Construct a simplified symmetric positive definite linear equation system based on the equivalent admittance matrix and port current vector, and solve the simplified symmetric positive definite linear equation system using a lightweight numerical solver to output the port voltages of the voltage source port node and the current sink node.

[0017] In the above scheme, in step 1, the irregular power plane is decomposed into polygons: after Delaunay triangulation, it is subdivided into quadrilateral elements, and nodes are set at the center of the elements. The cross-sectional area of ​​the resistive connection between the centers of adjacent elements is determined by the shared boundary length and the metal thickness.

[0018] In the above scheme, step 1 includes the following steps:

[0019] Step 1.1: Extract the equivalent resistance network from the PDN physical layout of the 3D integrated circuit, and model the conductive features, including metal segments, vias and bumps, as discrete resistors. The resistance value of the discrete resistor is determined according to its geometric parameters and material conductivity. The geometric parameters include length or depth and cross-sectional area.

[0020] Step 1.2: Perform polygon decomposition on the irregular power plane in the PDN layout:

[0021] The irregular power plane is triangulated using Delaunay triangulation, and each triangle is further subdivided into three quadrilateral units by projecting a perpendicular line from the incenter to the edge. An electrical node is set at the center of each quadrilateral unit, and a resistive connection is created between the center nodes of adjacent quadrilateral units. The cross-sectional area of ​​the resistive connection is determined by the length of the shared boundary of the adjacent quadrilateral units and the metal thickness, and the effective length is the distance between the two center nodes.

[0022] Step 1.3: Map the equivalent resistance network as an undirected weighted graph. vertex set Each vertex in the array corresponds to an electrical node, and the edge set... Each edge in the diagram corresponds to a resistor;

[0023] Step 1.4: For each edge of the undirected weighted graph Assign weights, where each weight is the equivalent conductance of the corresponding resistor:

[0024]

[0025] in, Representing an edge The resistance value of the corresponding resistor. Representing an edge The electrical conductivity;

[0026] Step 1.5: Based on the function of nodes in power integrity analysis, classify the nodes in the undirected weighted graph into voltage source port nodes, current sink nodes, and internal nodes, and use the node type as the physical attribute of the node.

[0027] In the above scheme, the physical information message passing mechanism performs a physical normalization operation after each iteration: subtracting the mean of all node embedding features from the node embedding features to force Kirchhoff's current law to be satisfied.

[0028] In the above scheme, step 2 includes the following steps:

[0029] Step 2.1: Input the undirected weighted graph constructed by the PDN physical layout into the graph neural network. The nodes of the undirected weighted graph include voltage source port nodes, current sink nodes and internal nodes, and the weight of the edges is the conductance value.

[0030] Step 2.2: Perform multiple rounds of physical information message passing iterations in the graph neural network. Each iteration includes:

[0031] For each node in the graph Calculate its message :

[0032]

[0033] in, Represents a node The set of neighboring nodes, and Representing nodes respectively With nodes Embedded vector, Representing an edge Learnable conductance, derived from multilayer perceptron based on nodes Embedded vectors, nodes Embedded vectors and edge features Calculated;

[0034] Perform physical normalization on the node embedding vector:

[0035]

[0036] in, This represents the embedding vector of the current node. This represents the total number of nodes in the graph. Representing dimensions and The same vector of all 1s;

[0037] Update node embedding vector:

[0038]

[0039] in, and These are preset scalar coefficients;

[0040] Step 2.3: Based on the node embeddings from the final iterative output of the graph neural network, construct the equivalent admittance matrix between the voltage source port node and the current sink node. The equivalent admittance matrix is ​​expressed in Laplace form as follows:

[0041]

[0042] in, For the port node association matrix, It is a non-negative learnable electrical conduction of the edge between port nodes.

[0043] In the above scheme, step 3 includes the following steps:

[0044] Step 3.1: Based on the equivalent admittance matrix With port current vector Construct a simplified system of symmetric positive definite linear equations:

[0045]

[0046] in, This represents the equivalent admittance matrix between voltage source port nodes and current sink nodes, learned by the graph neural network. This represents the port voltage vector to be solved. Represents the port current vector;

[0047] Step 3.2: Solve the simplified symmetric positive definite linear equation system using a lightweight numerical solver, and output the port voltage vector. .

[0048] In the above scheme, the graph neural network is trained to reduce operator error. Less than 1, where the operator error Defined as:

[0049]

[0050] in, Represents the true admittance matrix. This represents the equivalent admittance matrix predicted by the graph neural network; when When, for any satisfying Port current excitation Predicted port voltage Compared with the actual port voltage The error between them satisfies:

[0051]

[0052] in, Indicates by Defined weighted norm, To correspond to the incentive The actual port voltage.

[0053] In the above scheme, the training process of the graph neural network uses a loss function:

[0054]

[0055] in, This represents the value of the loss function. This indicates the number of ports in the training samples. Indicates the first The predicted voltage for each port is obtained by solving a simplified system of symmetric positive definite linear equations. Indicates the first Numerical simulations of real voltages were obtained for each port using a commercial SPICE solver. This represents the L2 norm.

[0056] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described thereon.

[0057] The present invention also provides a power integrity analysis system, including a processor, a memory, and a GPU acceleration unit. The memory stores instructions, and when the instructions are called by the processor and executed on the GPU acceleration unit, the method is implemented, and the output port voltage is used for PDN design correction or design space exploration processes.

[0058] Because the present invention employs the above-mentioned technical means, it has the following beneficial effects:

[0059] 1. This invention solves the technical problem of existing fixed-spatial-resolution image modeling methods struggling to uniformly represent the cross-scale heterogeneous PDN structure of the substrate (requiring coarse-grained modeling) and interposer (requiring fine-grained modeling) by converting the 3D integrated circuit PDN layout into an element-based equivalent resistance network and mapping it to an undirected weighted graph in step 1 (especially step 1.2, which subdivides the irregular power plane into quadrilateral units using Delaunay triangulation, sets electrical nodes at the center of the units, and determines the cross-sectional area of ​​the resistance connection based on the shared boundary length and metal thickness of adjacent units). This representation allows edge weights to directly reflect electrical conductance rather than geometric distance, naturally adapting to multi-scale physical characteristics and achieving a unified circuit-level abstraction of metal segments, vias, bumps, and irregular power planes, providing a physically meaningful and topologically complete input foundation for subsequent graph learning.

[0060] 2. This invention employs a physical information message passing mechanism in the graph neural network of step 2 (specifically, step 2.2: node message updates are based on the weighted product of the difference in the embedding vectors of adjacent nodes and the edge conductance, and a physical normalization operation is performed after each iteration). This mechanism addresses the technical problem of traditional graph neural networks, which only aggregate neighborhood features while ignoring the fundamental nature of voltage difference-driven current flow and struggle to explicitly satisfy Kirchhoff's current law. It reconstructs message passing into a Laplace difference form, ensuring that the direction and intensity of information flow strictly adhere to the physical laws of the circuit. Physical normalization forces the global node embedding mean to be zero, mathematically guaranteeing the current conservation constraint and significantly improving the model's ability to model the physical consistency of circuit behavior.

[0061] 3. This invention utilizes the technique of constructing and solving a simplified system of symmetric positive definite linear equations in step 3 (step 3.1 based on the equivalent admittance matrix). Equations were constructed using the port current vector b. Step 3.2 employs a lightweight numerical solver, addressing the technical issues of traditional sparse direct solvers' high computational cost on million-node PDNs, difficulty in meeting left-shift design turnaround time requirements, and weak generalization ability of end-to-end voltage prediction methods. This paradigm implicitly eliminates internal nodes, retaining only port-level admittance relationships, significantly reducing the solution scale; simultaneously, because the learning target is the admittance operator rather than a specific voltage value, it incorporates operator errors. The theoretical constraints ensure that for any condition satisfying... The unseen current excitation can produce a physically consistent voltage response, achieving a balance between computational efficiency and cross-scenario robustness.

[0062] This invention achieves significant synergistic effects by organically combining the cross-scale element-based PDN graph representation in step 1, the physical information message passing mechanism in step 2, and the neural Schur complement paradigm in step 3: the element-based graph representation provides accurate topological connections and conductance weights for physical information message passing, enabling the voltage difference-driven message flow to have a real circuit basis; the physical information message passing strictly embeds Kirchhoff's laws and the principle of energy conservation in the iteration, ensuring the learned equivalent admittance matrix. The physical rationality and Laplace structure ( The neural Schur complement paradigm relies on this physically reliable admittance matrix to achieve efficient calculation of port voltage through lightweight solution. These three elements form a closed loop of "accurate modeling—physical constraint learning—efficient solution": if only cross-scale graph representation is used without physical message passing, the learning process is prone to deviating from circuit patterns; if only physical message passing is used without Schur complement simplification, it is impossible to overcome the bottleneck of large-scale solution; if only simplified solution is used without physical constraint learning, the distortion of the admittance matrix will lead to generalization failure. This invention, through deep coupling of these three elements, enables the method to simultaneously achieve unified representation of heterogeneous structures, physical self-consistency in the analysis process, and efficient and generalizable computational flow while maintaining the physical essence of the circuit. Overall, it meets the comprehensive needs of left-shift design space exploration for power integrity analysis in terms of modeling adaptability, physical reliability, and engineering practicality, resulting in a systemic technological advancement that cannot be achieved by a single technical means. Attached Figure Description

[0063] Figure 1 The process flow of this invention is shown in the figure;

[0064] Figure 2 A schematic diagram of a left-shift design in 3D integrated circuit power delivery network planning;

[0065] Figure 3 The diagram shows the structure of a substrate and an interposer, with the following reference numerals: 1-silicon interposer, 2-substrate, 3-μ bump, 4-redistribution layer, 5-through silicon via, 6-C4 bump, 7-TPV, 8-BGA;

[0066] Figure 4 This is a schematic diagram of the PIANO framework;

[0067] Figure 5 A comparison of the sink voltage distribution between PIANO predictions and SPICE simulations in a 3D stacking case.

[0068] Figure 6 A comparison of the training loss and average relative error of the validation set between PIANO and the voltage mapping method;

[0069] Figure 7 To compare the runtime with that of a commercial SPICE simulator

[35] ;

[0070] Figure 8 Evaluation of runtime for PIANO-driven Design Space Exploration (DSE) results. Detailed Implementation

[0071] The embodiments of the present invention will be described in detail below. Although the present invention will be described and illustrated in conjunction with some specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, any modifications or equivalent substitutions made to the present invention should be covered within the scope of the claims of the present invention.

[0072] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the present invention can be practiced without these specific details.

[0073] The method provided in this invention, abbreviated as PIANO, is an admittance neural operator for fast and robust DC PI analysis. First, the equivalent resistive circuit is extracted from the PDN layout and represented as a graph. Then, a GNN equipped with physical information message passing is used to learn the equivalent admittance matrix between the voltage source ports and the sink. Finally, a lightweight numerical solver calculates the port voltages from the predicted admittance matrix. Our main contributions are summarized below.

[0074] 1. Cross-scale element-based PDN representation: This invention proposes a neural modeling method that represents multi-scale, multi-layer PDN as a unified graph, enabling heterogeneous intermediary layer-substrate structures to learn in a consistent manner.

[0075] 2. Physical Information Message Passing: This invention introduces a voltage difference driven message passing scheme. 3. KPEM: Kirchhoff Keeping Energy Message, which enables the model to accurately capture circuit-level physical behavior.

[0076] 4. Neural Schur Complement Paradigm: A neural approximation of Schur complement is constructed to replace explicit matrix elimination, making port voltage calculation efficient and providing physical consistency guarantees.

[0077] 5. High speed and high fidelity: The method of this invention is 12.6 times faster than commercial simulators on industrial PDNs with a port voltage error of only 1.95%, and achieves a speedup of 17.2 times in PI-driven DSE loops.

[0078] To facilitate a better understanding of the technical concept of this invention by those skilled in the art, the relevant technologies involved in this invention will be further described in detail:

[0079] 1.1. Multilayer substrate-intermediate layer structure

[0080] In advanced packaging, the substrate and interposers together form the physical and electrical basis for chip integration and system interconnection. The substrate is typically constructed using organic stacking or high-density interconnect (HDI) techniques, providing mechanical support, power and ground distribution, and electrical interfaces with the printed circuit board (PCB) via solder balls. Above it, the interposers contain fine redistribution layers (RDLs), microbumps, and through-silicon vias (TSVs), enabling dense signal routing and high-bandwidth interconnects between chipsets and memory stacks.

[0081] The substrate features complex polygonal copper regions, including power and ground areas, large copper foils, and irregular shapes, influenced by thermal, mechanical, and manufacturability constraints. These must be explicitly modeled to capture accurate current distribution. This spans from micrometer-level interconnects in the interposer to millimeter-level planes in the substrate. Figure 3 The vastly different geometric scales mean that accurate analysis requires methods that can simultaneously handle polygonal complexity and cross-scale coupling throughout the entire vertical stack.

[0082] 1.2. Problem Formulation

[0083] We formulate the DC PI analysis as an operator learning problem, where PDN represents a multilayer graph. Nodes correspond to discrete points within the metal layers, and edges represent resistive connections between them. Model inputs include:

[0084] a) Multi-layer structure The geometry and topology description of the PDN includes metal traces, vias, and power planes modeled as polygons, as well as their interlayer connections.

[0085] b) Voltage source mapping A group of source nodes with specified voltage values;

[0086] c) Sink current mapping A group of sink nodes with specified current injection.

[0087] The required output is This controls the equivalent admittance matrix of the voltage response at the observation port. Formally, our goal is to construct a model:

[0088] .

[0089] The technical concept of a method for power integrity analysis of 3D integrated circuits provided by this invention is described in detail below:

[0090] 2.1 Overview

[0091] PIANO's overall framework is as follows Figure 4As shown, an element-based PDN representation is first constructed, mapping the physical layout to an undirected resistance graph, where node roles (VRM, sink, internal) and edge conductance encode the underlying electrical structure.

[0092] Next, we design a graph neural operator that learns the admittance matrix directly from the PDN graph, overcoming the limitations of CNN-based agents that require regular grid representations and cannot generalize to arbitrary multi-layer topologies. We further introduce a KPEM module to reconstruct message passing into a Laplacian difference form to explicitly capture circuit physics. Furthermore, we provide an error guarantee, constraining the approximate error of the operator over all right-hand vector constraints, ensuring robust performance outside the training distribution.

[0093] 3.2 Element-based PDN representation

[0094] like Figure 4 As shown on the left, in order to achieve unified modeling of the heterogeneous PDN structure between the substrate and the interposer, an element-based representation was constructed, which maps the physical layout to the equivalent resistance circuit and then to the undirected resistance map.

[0095] First, the equivalent resistance network is extracted from the geometric PDN layout. Conductive features include metal segments, vias, and bumps, each modeled as an individual resistor, the value of which is calculated from its geometry and material properties. Specifically, the equivalent resistance is determined by its length (or the depth of vias and bumps), cross-sectional area, and metallic conductivity.

[0096] Power planes, typically irregular polygons within a substrate or interposer, require special handling. Polygon decomposition is applied, and each region is discretized into quadrilateral cells. The irregular shape is first triangulated using Delaunay triangulation; then, each triangle is subdivided into three quadrilateral cells by projecting perpendicular lines from the incenter to the edge. For each quadrilateral cell, a node is placed at its center, and resistive connections to adjacent cells are created by connecting the centers of adjacent cells. The cross-sectional area of ​​each resistive edge is determined by the shared boundary length and metal thickness, while the effective length corresponds to the distance between the two centers.

[0097] The resulting resistive network is mapped to an undirected weighted graph. Each electrical node becomes a vertex in the graph, and each resistor becomes an undirected edge. For each edge... Assign a scalar weight, which is equal to the equivalent conductance. This formula naturally addresses the cross-scale mismatch between fine-grained interposers and coarse-grained substrate planes because the edge weights reflect electrical conductance, not geometric distance. Therefore, the interaction strength between two nodes reflects actual current flow behavior, rather than spatial resolution.

[0098] Although the graphs are structurally homogeneous, the roles of nodes differ based on their function in PI analysis. We categorize nodes into three types:

[0099] VRM Node Voltage regulation node;

[0100] Sink node : Load terminal;

[0101] Internal nodes A node that has neither voltage constraints nor injected current.

[0102] Finally, we attach physically meaningful properties to each graph element; detailed node and edge embeddings are summarized in Table 1.

[0103] Table 1: Graphic Terminology Used in PIANO

[0104]

[0105] 2.3 Neural Schur Complement Paradigm

[0106] The static IR voltage drop of a PDN can be modeled as a resistive circuit system, where only parasitic resistance is considered, and inductance and capacitance effects are neglected. Therefore, the DC analysis can be formulated as a sparse linear system:

[0107]

[0108] in It is the conductance matrix determined by the network topology and the resistance of the wires. It is the node voltage vector. Including current injection. Reordering equation (2) by node type yields:

[0109]

[0110] The meanings of the symbols are explained as follows:

[0111] Node type definition (meaning of subscripts)

[0112] : Voltage source port node (VRM node, Voltage Regulator Module), where the voltage is set by the power supply to known boundary conditions (e.g., 1.0 V), but the injected current is unknown.

[0113] The current sink node (load terminal) has a known external load current injection value, and the node voltage is the key solution objective (used to evaluate IR voltage drop).

[0114] Internal nodes

[0115] This represents a column vector consisting of the voltages of all voltage source nodes. This represents a column vector consisting of the voltages at all sink nodes. This represents a column vector consisting of all internal node voltages. This represents the column vector of currents injected into the voltage source node. This represents the column vector of currents injected into the sink node. This represents the column vector of currents injected into the internal nodes. Represents the sink node, admittance submatrix meaning:

[0116] The row subscript indicates the node type at the current outflow end, and the column subscript indicates the node type at the voltage application end;

[0117] For example:

[0118] Indicates the voltage at the sink node. The equivalent admittance contribution caused at the voltage source node;

[0119] This represents the coupling admittance of the internal node voltage to the voltage source node current.

[0120] Since the objective is to calculate only the VRM and sink port voltages, internal nodes... This can be analytically eliminated. This simplification yields the equivalent admittance matrix. .

[0121]

[0122] For a PDN with millions of nodes, explicit construction is required. It is not feasible because the calculation The computational cost is too high. This has prompted the adoption of a data-driven approach to directly learn this simplification.

[0123] To perform admittance calculation in neural form, we perform simplification in three stages:

[0124] (1) Encoding: The node and edge features of the multilayer PDN graph are embedded into a latent representation that captures local conductance and topological context;

[0125] (2) Neural elimination: Implicit modeling of message passing between observation nodes and internal nodes corresponds to the current redistribution process of matrix elimination;

[0126] (3) Operator Reconstruction: Combining aggregated messages to form an equivalent admittance operator It maintains symmetry and positive definiteness.

[0127] Given the extracted resistor network, we construct the PDN graph. Each node For each electrical node, each edge This corresponds to one resistor. Table 1 summarizes the components in the diagram and their physical meaning.

[0128] Instead of directly predicting dense matrix entries, GNNs learn the side conductance that reflects the effective coupling between the VRM and the sink port. To ensure symmetry, current conservation, and the SPD structure, we assembled these conductivities into a Laplace form:

[0129]

[0130] in It is the correlation matrix of the port-level graph. This represents the diagonal matrix construction operator.

[0131] Loss function minimizes predicted port voltage Sum of actual values Differences between them:

[0132]

[0133] in It refers to the number of ports. It is obtained by solving the simplified system in formula (4). Indicates the first The predicted voltage (scalar) of each port is obtained by solving a simplified system of equations. Indicates the first The actual voltage obtained by simulation of each port using a commercial SPICE solver;

[0134] Learning Operators Instead of directly regressing the port voltage, this provides a key generalization advantage: once the operator is predicted, the simplified SPD system can be solved for any port excitation. As long as the operator prediction error remains below the stability threshold, there is a theoretical guarantee for the induced voltage error for all unseen right-hand vectors (derivation in 2.5).

[0135] 2.4 Kirchhoff's Energy Preservation Message

[0136] Traditional graph neural networks, such as GCN and GAT, formulate message passing as an averaging or attention-weighted aggregation of neighboring features. While effective for general graph learning, these operations lack a physical basis. Therefore, the learned representations may violate the law of conservation of current and fail to capture the true energy flow characterized by the graph Laplacian operator.

[0137] To address this limitation, we introduced the KPEM (Kirchhoff Preserving Energy Messages) module. Figure 4 KPEM refactors message passing into a Laplace difference form:

[0138]

[0139] in It is a node and Edge features between them It is a learnable conductance, used as an adaptive admittance to regulate the information flow. The entire message operator can be compactly represented as:

[0140]

[0141] in It is a weighted Laplace operator. It is the Dirichlet energy. Therefore, KPEM implements a gradient descent step on the network energy, giving the update physical meaning.

[0142] To enforce the global current conservation required by KCL, we introduce a lightweight physical normalization operator:

[0143]

[0144] in:

[0145] Normalized node embedding vector (output)

[0146] : Current node embedding vector (input, dimension) )

[0147] Total number of nodes in the graph (scalar)

[0148] :and A column vector of all 1s of the same dimension.

[0149] Combining energy-based messaging and KCL normalization, the KPEM update node embedding is as follows:

[0150]

[0151] in and These are trainable scalar coefficients that balance local energy consistency and global current conservation. In practice, we will... Limited to 1.0. The limit is set to 0.1 to ensure stable training. The complete training process for PIANO is summarized in Algorithm 1.

[0152] Algorithm 1: PIANO's Training Process

[0153] Input: Dataset: Output: Optimized PIANO

[0154] 1. foreach do

[0155] 2.

[0156] 3.

[0157] 4. / / Linear projection

[0158] 5. foreach do

[0159] 6.

[0160] 7. Node embedding:

[0161] 8. Edge embedding:

[0162] 9. foreach do:

[0163] 10.

[0164] 11. Message passing:

[0165] 12.

[0166] 13.

[0167] 14. Updated image:

[0168] 15.

[0169] 16.

[0170] 17.

[0171] Dataset, containing multiple samples Each sample includes geometric information. Voltage boundary conditions and current boundary conditions .

[0172] : No. The geometric information of a sample may include metal traces and power planes on the circuit board.

[0173] and : respectively represent the first Voltage and current boundary conditions in each sample.

[0174] and :from The extracted metal traces and power plane polygon regions.

[0175] : Through the Extract and Quadrangulate operations and Convert it into a graph for subsequent processing.

[0176] Linear projection operation to initialize the graph. and These are the weights and bias parameters.

[0177] Attention_Layer: An attention layer used to enhance the model's ability to process graph data, especially suitable for capturing complex relationships between nodes.

[0178] : The method for updating node embedding, where and These are hyperparameters or learned parameters used to control the influence of different parts on the final embedding.

[0179] Physical normalization operations ensure that certain physical constraints are met, such as Kirchhoff's current law.

[0180] : These are the estimated effective admittance matrix and the voltage solution, respectively. The voltage solution is obtained by calculating using MLP_Decoder and then applying it to solve the Dirichlet boundary condition problem. .

[0181] Loss function, used to measure the prediction result. The difference between the actual values ​​and the true values ​​is used to guide the model training process.

[0182] get_traces: Extracts metallic traces (wires, vias, etc.)

[0183] get_polygons: Extracts polygonal regions from the power plane.

[0184] Extract: Convert the traces into an equivalent resistance network.

[0185] Quadrangulate: Discretizes polygons into quadrilateral elements (including Delaunay triangulation and subdivision).

[0186] Multilayer perceptron with edge features (for calculating learnable conductance) )

[0187] The decoder MLP maps the final graph embeddings into learnable electrical conductance.

[0188] Solve_Dirichlet: Solve the simplified SPD system under Dirichlet boundary conditions (i.e., );

[0189] Numerical_Solver: A commercial SPICE solver (such as PowerDC) used to generate real voltages. ;

[0190] 2.5 Error Guarantee for Right-Side Vectors

[0191] As described in Section 2.3, a key advantage of our neural Schur complement paradigm is its ability to generalize solution accuracy to unseen stimuli. Consider a port-level system:

[0192]

[0193] The right-hand vector Encode external current injection.

[0194] Approximate mapping of direct voltage regression training network However, this approximation only applies to a finite training set. This is guaranteed. For those without incentives... Prediction errors can be arbitrarily large; direct regression cannot provide uniform error control.

[0195] In contrast, our operator learns to predict the admittance matrix. Then solve Here, the approximate quality depends on the operator error:

[0196]

[0197] if So for satisfying Any incentive The solution error is bounded:

[0198]

[0199] when hour, It represents a stable perturbation in a real SPD system, where the learned operator produces a physically consistent voltage response to any excitation. If If this condition is no longer met, the system may lose its positive definiteness. Physically, this means that once the operator is learned accurately, the model can produce reliable port voltage predictions for any current injection pattern (not just those seen during training).

[0200] 3. Experiment

[0201] 3.1 Experimental Setup

[0202] All experiments were conducted on a Linux server equipped with an NVIDIA A100 (80GB) GPU and a 48-core Intel Xeon Silver 4130 CPU (running at 3.3 GHz, with 128 GB of memory). PIANO was evaluated on synthetic PDN benchmarks [30,31] and industrial layouts (Section 3.5), covering networks with up to one million nodes and a variety of 2.5D / 3D stack configurations. For 2.5D designs, the TSMC CoWoS-S

[32] architecture was used, in which a high-bandwidth memory (HBM)

[33] stack was placed next to the ASIC chip. For 3D designs, we used the TSMC InFO-PoP

[34] , in which the HBM was stacked vertically on top of the ASIC. A total of 64 design groups were generated for each package category, resulting in 128 layouts. For each layout, 100 voltage maps were created by randomly sampling port stimuli, and detailed DC simulations were performed using a commercial SPICE solver to obtain the corresponding ground-based true port voltage distribution at the sink node. To evaluate generalization capabilities, four additional layouts were synthesized for each category, generating 100 voltage maps each time.

[0203] The geometric parameters following industrial design rules are summarized in Table 2. Bump radii span the BGA, C4, and microbump regions, covering substrate-level and interposer-level interconnects. Via radii range to include through-package vias (TPVs) in the substrate and through-silicon vias (TSVs) in the interposer. Via spacing is set to 2–5 times the via diameter to comply with manufacturability constraints. Power planes use a diagonal length of [missing information]. The grid size is discretized.

[0204] The GNN operator is implemented in PyTorch Geometric. The model uses a graph attention network with four message-passing layers, each containing 64 hidden units. The message update function is parameterized by a two-layer MLP with LeakyReLU activations. The Adam optimizer is used to optimize the GNN. The learning rate was used for 10 rounds of training.

[0205] Table 2: Design rules for packaged PDN datasets in substrate and interposer

[0206]

[0207] 3.2 Comparison with the SOTA method

[0208] PIANO's accuracy was evaluated on the synthetic PDN dataset and compared with state-of-the-art GNN-based DC simulation models, including Circuit-GNN

[28] and GTN

[29] . We reproduced Circuit-GNN by adapting its messaging scheme to accommodate conductance-based connections and reproduced GTN according to its original architecture and training protocol.

[0209] As summarized in Table 3, PIANO consistently outperforms previous methods in both 2.5D and 3D packaging scenarios. Compared to existing GNN-based DC simulations, PIANO reduces the relative error by 7.51%. Specifically, PIANO achieves a relative error of 0.42% in the 2.5D layout and 0.97% (14 mV) in the more challenging 3D case, where the stacked structure introduces a more complex RDL network. These results demonstrate the superior accuracy and generalization ability of our method on heterogeneous PDN topologies. The advantage stems from the fact that the voltage mapping network must directly learn the mapping from excitation to voltage, which is inherently a more difficult task, requiring higher model capacity and typically leading to weaker generalization ability. A detailed comparison between admittance operator learning and voltage mapping is discussed in Section 3.3.

[0210] Table 3: Accuracy comparison between PIANO and the current state-of-the-art (SOTA) method in 2.5D and 3D scenes. Benchmark: SPICE simulator.

[0211]

[0212] 3.3 Accuracy Assessment

[0213] In order to qualitatively assess the prediction fidelity, Figure 5The distribution of sink ports on the top surface of the intermediate layer was visualized. The predicted results match the ground-based true DC solution very well, accurately capturing the spatial pattern and absolute voltage level. As shown in Table 4, the integration of KPEM further reduced the relative error from 2.089% to 0.968%, indicating that KPEM more faithfully models current conservation during message passing.

[0214] Table 4: Ablation Study of KPEM Module

[0215] MP: Message Passing; PN: Physical Normalization; Benchmark: SPICE Simulator

[0216]

[0217] GAT: Graph Attention Network, is the baseline model;

[0218] KPEM MP: KPEM's message passing mechanism (voltage difference driven messages);

[0219] KPEM PN: KPEM's physical normalization module (forces global current conservation).

[0220] “ " indicates that the module is enabled;

[0221] All values ​​were calculated using the SPICE simulator as the actual values.

[0222] The down arrow (↓) indicates that the smaller the value, the better the performance;

[0223] The last line (the complete KPEM) is highlighted in blue to emphasize its optimal performance.

[0224] To isolate the contribution of neural Schur complement, the same GNN architecture is trained to learn an equivalent admittance operator or perform direct voltage regression, such as Figure 6 As shown, the neural Schur formula converges smoothly and achieves a low validation error, while the direct voltage regression saturates early and exhibits a significantly higher error. This confirms that PIANO provides superior numerical stability and generalization ability because it captures circuit-level physical dependencies rather than attempting to directly fit the voltage plot.

[0225] 3.4 Efficiency Evaluation

[0226] We constructed seven test cases for 3D stacked PDNs with 4-16 metal layers, corresponding to the parasitic extraction process containing... arrive The equivalent circuit of the node was determined, and the runtime of each use case was compared with that of a commercial SPICE simulator

[35] .

[0227] like Figure 7 As shown, PIANO consistently outperforms commercial simulators across all circuit sizes. For the smallest use case, our model achieves a 5.7x speedup. The gap widens dramatically as circuit size increases. In cases with… In terms of maximum node design, PIANO achieves a speedup of 114.9x, reducing simulation time from over five hours to four minutes. This significant improvement stems from our method using graph neural networks to obtain a simplified SPD system in a single forward pass, avoiding the repetitive iterations and convergence overhead of directly manipulating full-scale matrices.

[0228] 3.5 Case Study of Industrial Layout

[0229] This invention further evaluates PIANO in an industrial 3D packaging layout with 24 metal layers, including multiple irregular power planes and more than One TSV. Ten representative test samples were extracted from this layout, and the port voltage diagrams of each sample were randomly assigned in the range of 0.8-1.6 V. The predicted voltage distributions were compared with the results of PowerDC

[36] . As shown in Table 5, PIANO achieved an average relative error of 1.95%, demonstrating high fidelity even in complex industrial designs.

[0230] For a fair comparison of runtime, we employ a parallel resistance extraction process for graph construction. As summarized in Table 5, using 32 cores, our method is 12.6 times faster than commercial tools, significantly reducing total runtime while maintaining physical accuracy.

[0231] Table 5: Accuracy and Efficiency Comparison with Cadence PowerDC

[0232]

[0233] 3.6 Discussion on the Exploration of Design Space

[0234] This invention further evaluates the applicability of PIANO in design optimization by constructing a DSE scenario that jointly optimizes TSV geometry and power plane configuration under PI constraints. The goal is to minimize manufacturing costs.

[0235]

[0236]

[0237] in:

[0238] Represents the TSV set. Represents the set of power planes. Indicates the sink voltage. Indicates the target voltage threshold. , and Indicates the radius, spacing, and height of the TSV. It is the power plane The area. Function and These are their respective manufacturing costs. For example... Figure 8 As shown, using Bayesian optimization (BO) and PIANO as a fast surrogate evaluator reduces the total DSE runtime by 17.2 times, from approximately 3 hours to just 10 minutes, while satisfying all PI constraints. This acceleration stems from PIANO replacing each expensive PDN solution with a sub-second evaluation of the learned admittance operator.

[0239] In summary, this invention proposes PIANO, which, by employing an element-based PDN representation, enables unified and scalable PI evaluation across the substrate and interposer structures. The proposed KPEM module introduces voltage difference-driven message passing, allowing GNNs to more faithfully capture circuit-level physical behavior. Furthermore, the neural Schur complement paradigm replaces explicit matrix elimination with learned operators, achieving efficient and physically consistent port voltage calculation. Experimental results show that PIANO is 114.9 times faster than SPICE with a relative error of only 0.96%, and 12.6 times faster on industrial PDNs with a relative error of 1.95%. Integrated into PI-constrained DSE, it provides a 17.2-fold reduction in runtime, demonstrating its practicality and efficiency in iterative design workflows.

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Claims

1. A method for power integrity analysis of 3D integrated circuits, characterized in that, Includes the following steps: Step 1: Obtain the power delivery network (PDN) layout of the 3D integrated circuit, convert the PDN layout into an equivalent resistance network, and represent the equivalent resistance network as an undirected weighted graph; wherein, the nodes of the undirected weighted graph include voltage source port nodes, current sink nodes, and internal nodes, and the weight of the edge is the conductance value of the corresponding resistor connection. Step 2: Input the undirected weighted graph into the graph neural network. The graph neural network performs multiple iterations through a physical information message passing mechanism to learn the equivalent admittance matrix between the voltage source port node and the current sink node. In each iteration, the message update of the node is based on the weighted product of the difference between the embedding vectors of adjacent nodes and the corresponding edge conductance value. Step 3: Construct a simplified symmetric positive definite linear equation system based on the equivalent admittance matrix and port current vector, and solve the simplified symmetric positive definite linear equation system using a lightweight numerical solver to output the port voltages of the voltage source port node and the current sink node.

2. The method according to claim 1, characterized in that, In step 1, the irregular power plane is decomposed into polygons: after Delaunay triangulation, it is subdivided into quadrilateral elements, and nodes are set at the center of the elements. The cross-sectional area of ​​the resistive connection between the centers of adjacent elements is determined by the shared boundary length and the metal thickness.

3. The method according to claim 2, characterized in that, Step 1 includes the following steps: Step 1.1: Extract the equivalent resistance network from the PDN physical layout of the 3D integrated circuit, and model the conductive features, including metal segments, vias and bumps, as discrete resistors. The resistance value of the discrete resistor is determined according to its geometric parameters and material conductivity. The geometric parameters include length or depth and cross-sectional area. Step 1.2: Perform polygon decomposition on the irregular power plane in the PDN layout: The irregular power plane is triangulated using Delaunay triangulation, and each triangle is further subdivided into three quadrilateral units by projecting a perpendicular line from the incenter to the edge. An electrical node is set at the center of each quadrilateral unit, and a resistive connection is created between the center nodes of adjacent quadrilateral units. The cross-sectional area of ​​the resistive connection is determined by the length of the shared boundary of the adjacent quadrilateral units and the metal thickness, and the effective length is the distance between the two center nodes. Step 1.3: Map the equivalent resistance network as an undirected weighted graph. , where vertex set Each vertex in the array corresponds to an electrical node, and the edge set... Each edge in the diagram corresponds to a resistor; Step 1.4: For each edge of the undirected weighted graph Assign weights, where each weight is the equivalent conductance of the corresponding resistor: in, Representing an edge The resistance value of the corresponding resistor. Representing an edge The electrical conductivity; Step 1.5: Based on the function of nodes in power integrity analysis, classify the nodes in the undirected weighted graph into voltage source port nodes, current sink nodes, and internal nodes, and use the node type as the physical attribute of the node.

4. The method according to claim 1, characterized in that, The physical information message passing mechanism performs a physical normalization operation after each iteration: subtracting the mean of all node embedding features from the node embedding features to force Kirchhoff's current law to be satisfied.

5. The method according to claim 1, characterized in that, Step 2 includes the following steps: Step 2.1: Input the undirected weighted graph constructed by the PDN physical layout into the graph neural network. The nodes of the undirected weighted graph include voltage source port nodes, current sink nodes and internal nodes, and the weight of the edges is the conductance value. Step 2.2: Perform multiple rounds of physical information message passing iterations in the graph neural network. Each iteration includes: For each node in the graph Calculate its message : in, Represents a node The set of neighboring nodes, and Representing nodes respectively With nodes Embedded vector, Representing an edge Learnable conductance, derived from multilayer perceptron based on nodes Embedded vectors, nodes Embedded vectors and edge features Calculated; Perform physical normalization on the node embedding vector: in, This represents the embedding vector of the current node. This represents the total number of nodes in the graph. Representing dimensions and The same vector of all 1s; Update node embedding vector: in, and These are preset scalar coefficients; Step 2.3: Based on the node embeddings from the final iterative output of the graph neural network, construct the equivalent admittance matrix between the voltage source port node and the current sink node. The equivalent admittance matrix is ​​expressed in Laplace form as follows: in, For the port node association matrix, It is a non-negative learnable electrical conduction of the edge between port nodes.

6. The method according to claim 1, characterized in that, Step 3 includes the following steps: Step 3.1: Based on the equivalent admittance matrix With port current vector Construct a simplified system of symmetric positive definite linear equations: in, This represents the equivalent admittance matrix between voltage source port nodes and current sink nodes, learned by the graph neural network. This represents the port voltage vector to be solved. Represents the port current vector; Step 3.2: Solve the simplified symmetric positive definite linear equation system using a lightweight numerical solver, and output the port voltage vector. .

7. The method according to claim 1, characterized in that, The graph neural network is trained to minimize operator error. Less than 1, where the operator error Defined as: in, Represents the true admittance matrix. This represents the equivalent admittance matrix predicted by the graph neural network; when When, for any satisfying Port current excitation Predicted port voltage Compared with the actual port voltage The error between them satisfies: in, Indicates by Defined weighted norm, To correspond to the incentive The actual port voltage.

8. The method according to claim 2, characterized in that, The training process of the graph neural network uses a loss function: in, This represents the value of the loss function. This indicates the number of ports in the training samples. Indicates the first The predicted voltage for each port is obtained by solving a simplified system of symmetric positive definite linear equations. Indicates the first Numerical simulations of real voltages were obtained for each port using a commercial SPICE solver. This represents the L2 norm.

9. A computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the method as described in any one of claims 1-8.

10. A power integrity analysis system, comprising a processor, a memory, and a GPU acceleration unit, wherein the memory stores instructions, and when the instructions are invoked by the processor and executed on the GPU acceleration unit, implement the method as described in any one of claims 1-8, and use the output port voltage for PDN design correction or design space exploration processes.

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