Method for manufacturing vias in a multilayer pcb stack and multilayer pcb stack

Abstract

A method for fabricating vias in a multilayer dielectric PCB stack (50) comprising alternating plurality of first dielectric layers (52) and second dielectric layers (54), the first dielectric layers (52) comprising a first dielectric material having a first glass transition temperature (Tg), and the second dielectric layers (54) comprising a second dielectric material having a second glass transition temperature (Tg) higher than the first glass transition temperature (Tg), wherein a plurality of vias (64) are formed (202, 204) into the plurality of first dielectric layers (52) and second dielectric layers (54), the method comprising: at least partially dissolving (206) the first dielectric layers (52) between the vias (64); filling (208, 210) the vias (64) and the spaces formed between the second dielectric layers (54) due to the voids left by the at least partial dissolution of the first dielectric layers (52) with metal (68, 70), thereby obtaining a metal network (72) interconnecting the vias (64) with each other.

Description

Technical Field

[0001] This disclosure relates to a method for fabricating vias in a multilayer PCB stack and to a multilayer PCB stack. Background Technology

[0002] Traditional multilayer PCBs (printed circuit boards) use vias (holes) to interconnect two or more conductive layers. A via is a hole that is mechanically or laser-drilled into a dielectric layer and then covered with a conductive metal layer (such as copper) so that electrical and thermal connections are made in at least the top and bottom conductive layers, respectively, above and below the dielectric layer.

[0003] In the case of power chips embedded in PCBs, connections are made using a high-density via pattern to achieve maximum heat transfer and minimum resistance.

[0004] In fact, in PCBs, heat follows a conduction path due to the better thermal conductivity than in dielectric layers.

[0005] One way to improve the thermal performance of a PCB is to increase the via size and / or via density. This is achieved by using laser drilling to achieve the smallest possible via diameter and covering the connection pads with the maximum number of vias. This known technique involves a series of steps including drilling, chemical copper deposition, and surface polishing.

[0006] Different drilling techniques are known, allowing for vias of varying sizes, shapes, and depths, with varying degrees of speed and / or accuracy in via fabrication. Patent Document 1 discloses a detailed drilling path for a laser head, allowing for holes of different sizes with the same accuracy. Patent Document 2 discloses a technique for drilling cavities in polymer materials. The laser head follows a specific path to create cavities of specific shapes according to the components to be connected. Patent Document 3 discloses sequential drilling and filling steps, allowing for increased metal density in the PCB, thereby improving thermal resistance. While providing better thermal performance, this technique also increases manufacturing time due to multiple sequential steps and production costs. Patent Document 4 discloses specific honeycomb or diagonally arranged via pads, allowing for higher current flow capabilities by increasing metal density in the PCB board.

[0007] All of the solutions described above are thermally limited by via interconnects. While via interconnects do provide a good direct thermal path for heat dissipation locally, the entire surface of the top and bottom conductive layers cannot be contacted (this is known as a "discrete interconnect") because the number of vias that can be created in a PCB stack is limited by drilling techniques. This limits overall heat conduction through the PCB stack and results in higher thermal resistance compared to direct solder for interconnects ("silver sintering" or "metal-based solder").

[0008] Reference List

[0009] Patent documents

[0010] [Patent Document 1] US Patent 5,614,114

[0011] [Patent Document 2] US Patent 4,894,115

[0012] [Patent Document 3] European Patent Application Publication EP4095898 A1

[0013] [Patent Document 4] US Patent 5,764,485 Summary of the Invention

[0014] This disclosure aims to improve the situation. In particular, this disclosure aims to at least partially address some or all of the limitations of the prior art discussed above by proposing solutions that can increase the metal density between the top and bottom conductive layers, allow for better heat extraction from the PCB stack, and reduce the inherent thermal resistance of via interconnects.

[0015] Therefore, this disclosure relates to a method for fabricating vias in a multilayer dielectric PCB stack, the multilayer dielectric PCB stack comprising alternating plurality of first dielectric layers and second dielectric layers, the first dielectric layers comprising a first dielectric material having a first glass transition temperature (Tg), and the second dielectric layers comprising a second dielectric material having a second glass transition temperature (Tg) higher than the first glass transition temperature, wherein a plurality of vias are formed into the plurality of first dielectric layers and second dielectric layers, the method comprising the following steps: At least partially dissolve the first dielectric layer between the vias; The vias and the spaces formed between the second dielectric layers due to the voids left by the at least partial dissolution of the first dielectric layer are filled with metal to obtain a metal network that interconnects the vias with each other.

[0016] In one embodiment, a permanganate desmearing process is performed on the multilayer dielectric PCB stack to at least partially dissolve the first dielectric layer between the vias.

[0017] In one embodiment, in order to fill the vias with metal, electroless metal deposition is performed on the multilayer dielectric PCB stack to deposit a first metal layer on the inner walls of the plurality of vias. The first metal layer also fills the spaces formed between the second dielectric layers due to the voids left by the at least partial dissolution of the first dielectric layer. Metal plating is then performed on the multilayer dielectric PCB stack to fill the plurality of vias with a second metal layer.

[0018] In an embodiment, the first metal layer (68) and the second metal layer (70) comprise copper.

[0019] In one embodiment, the first dielectric layer comprises acrylic acid, and the second dielectric layer comprises FR4.

[0020] In one embodiment, obtaining the plurality of vias includes: A top metal layer is placed above the plurality of first dielectric layers and second dielectric layers; The top metal layer is etched according to a predetermined pattern, thereby leaving multiple mask areas covering the first dielectric layer and the second dielectric layer placed below, and leaving corresponding uncovered areas of the first dielectric layer and the second dielectric layer that are not covered by the top metal layer; Drilling is performed on the first dielectric layer and the second dielectric layer corresponding to the uncovered areas to form the plurality of vias.

[0021] In one embodiment, the bottom metal layer is placed beneath the plurality of first dielectric layers and second dielectric layers.

[0022] In one embodiment, the top metal layer comprises copper.

[0023] In one embodiment, the bottom metal layer comprises copper.

[0024] In this embodiment, drilling the first dielectric layer and the second dielectric layer includes mechanical drilling or laser drilling.

[0025] In one embodiment, the permanganate descaling process includes a first swelling step, a second permanganate etching, and a third manganese oxide reduction.

[0026] This document also provides a multi-layer PCB stack, the multi-layer PCB stack comprising: Alternating first dielectric layers and second dielectric layers, wherein the first dielectric layer comprises a first dielectric material having a first glass transition temperature (Tg), and the second dielectric layer comprises a second dielectric material having a second glass transition temperature (Tg) higher than the first glass transition temperature; A plurality of vias are formed in the plurality of first dielectric layers and second dielectric layers, wherein the first dielectric layer is at least partially dissolved between the vias, wherein the vias and the spaces formed between the second dielectric layers due to the at least partial dissolution of the first dielectric layer are filled with metal, thereby obtaining a metal network that interconnects the vias with each other.

[0027] In one embodiment, the multilayer PCB stack further includes a top metal layer placed above the plurality of first dielectric layers and second dielectric layers, and a bottom metal layer placed below the plurality of first dielectric layers and second dielectric layers.

[0028] In one embodiment, the top and bottom metal layers of the multilayer PCB stack include copper. Attached Figure Description

[0029] Referring to the accompanying drawings, other features and advantages of the invention will become apparent from the following description, which is provided by way of non-limiting example only, wherein: Figure 1 Three different methods for drilling through PCB stacks are shown; Figures 2A to 2C The chemical reactions that occur during the three steps of the permanganate desmear sequence are shown; Figure 3 The steps of a method for manufacturing vias in a multilayer PCB stack according to the present invention are shown; Figure 4 A three-dimensional view of a multilayer PCB stack including a metal network is shown; Figure 5 A three-dimensional view of the PCB stack excluding the metal mesh is shown; Figure 6A A cross-sectional view of a first multilayer PCB stack sample in a first configuration is shown before the application of a desmearing process. Figure 6B This shows the end of the metal plating filling step. Figure 6A The first sample; Figure 7A A cross-sectional view of a second multilayer PCB stack sample in its second configuration is shown before the application of a desmearing process. Figure 7B This shows the end of metal plating filling step 210. Figure 7A The second sample; and Figure 8 A cross-sectional view of the reference stack is shown at the end of the metal plating fill step. Detailed Implementation

[0030] This disclosure relates to a method for fabricating vias in a multilayer PCB stack that improves the thermal behavior of via interconnects.

[0031] A via is a hole that enters the dielectric material layer that forms a PCB stack and isolates two conductive layers (top conductive layer and bottom conductive layer) placed above and below this dielectric material, respectively. The dielectric (epoxy) material can be, for example, acrylic, polyimide or polypropylene.

[0032] Drilling of vias, whether mechanically or by laser, is always followed by a cleaning chemical bath (known as descaling). The chemical bath removes portions of the dielectric material ablated into the via during the drilling step and / or any residue left in the via at the end of the drilling step. Furthermore, the chemical bath promotes the adhesion of subsequent metal deposits in the via by increasing the roughness of the conductive layer, as detailed below, because it cleans the inner walls of the via. Cleaning chemical baths are typically permanganate-based baths that use oxidative chemical reactions to roughen the edges of the via.

[0033] Figure 1 Three different methods for drilling holes in a PCB stack are shown. Specifically, in Figure 1 Part (a) illustrates the UV laser process, in Figure 1 The CO2 laser process is shown in section (b), and... Figure 1 The excimer laser process is shown in part (c).

[0034] Figure 1 Part (a) shows the initial stage 100a, in which a PCB stack 1 is created. The PCB stack 1, shown in the cross-sectional view, includes a dielectric layer 2 placed on a substrate 4 and an RCC (resin-coated copper) layer 8 placed above the dielectric layer 2, with a bottom conductive layer 6 placed between the substrates 4. In the next stage 102a, the RCC layer 8 is etched with a UV laser to create an opening 10. In stage 104a, UV laser ablation is performed to etch the dielectric layer 2 to create a via 12. Then, in stage 106a, a desmearing and metallization process is performed, and a mask 14 is further deposited on top of the PCB stack 1. Then, in stage 108a, metal deposition is performed to cover the PCB stack 1 and the via 12 with a metal layer 16, and finally, in stage 110a, a final etching is performed to remove the mask 14 and the portion of the RCC layer 8 below the mask 14.

[0035] Figure 1 Part (b) shows the initial stage 100b corresponding to the previously disclosed stage 100a. In the next stage 102b, chemical copper reduction is performed to create an opening 10. In stage 104b, CO2 laser ablation is performed to obtain a hole 12. Stages 106b, 108b, and 110b correspond to stages 106a, 108a, and 110a disclosed above.

[0036] Figure 1Part (c) shows the initial stage 100c, in which a dielectric substrate (layer) 20 is provided. In stage 102c, UV laser ablation is performed to etch holes (vias) 22. In stage 104c, a desmearing and metallization process is performed, and a metal layer 24 is deposited in the holes 22 and on top of the substrate 20. In the next stage 106c, an in-line laser process is performed, and then a mask 26 is deposited above and below the substrate 20. In stage 108c, metal deposition is performed to cover the substrate 20 and the holes 22 with a metal layer 28. Finally, in stage 110c, a final etching is performed to remove the mask 26.

[0037] The permanganate used in the descaling process disclosed above exhibits rapid erosion of materials with low Tg (glass transition temperature) (i.e., temperatures below 100°C, such as acrylic acid), thus resulting in deep etching of the material. The dissolution rate is a function of the dielectric material.

[0038] Therefore, the method for fabricating vias in a multilayer PCB stack according to the present invention further discloses in detail the use of materials with different Tg values ​​to create the PCB stack, such that controlled vias (cavities) can be obtained during the desmearing process, and then such cavities are filled with metal (e.g., copper) by a metal deposition process.

[0039] Therefore, the resulting multilayer PCB stack contains a higher density of metal, resulting in better thermal performance.

[0040] Desmearing is a critical process performed before metal deposition (metal plating) to ensure proper adhesion of the metal to the inner walls of the vias. Wet treatment is applied during the desmearing process.

[0041] In wet processing, alkaline permanganate etching, developed during the 1980s, is efficient and inexpensive, and remains the most widely used descaling process. Permanganate etching is more environmentally friendly than chromate etching and is readily applicable to a wide range of polymers and composites.

[0042] The permanganate descaling process (process) consists of three steps: the first swelling step, the second permanganate etching, and the third manganese oxide reduction.

[0043] Figures 2A to 2C The chemical reactions that occur during the three steps of the permanganate descaling process are shown.

[0044] In particular, Figure 2A In the process, the swelling agent molecule 30 diffuses through the epoxy polymer network, in Figure 2B In the middle, permanganate ions MnO4 2-The polymer is eroded from the surface, thereby forming a cavity at the polymer surface (see dashed line 32), and in the reaction formula of Figure 2 C, MnO2 is reactively dissolved by reduction with hydroxyl ammonium (or peroxide), producing water-soluble manganese ions and gaseous nitrogen (or water).

[0045] During the oxidative etching bath, permanganate ions preferentially attack polymer chains in previously formed clusters due to electrostatic interactions.

[0046] In fact, it has been determined that permanganate ions attack the two carbon atoms located at the α-position of alcohol and ether groups; the inductive effect of oxygen atoms leads to the weakening of the adjacent carbon-carbon bond. The oxidation conditions are relatively strong, thus altering the epoxy resin after oxidation or ablation: on the one hand, weakening the adjacent carbon-carbon bond, and on the other hand, removing several micrometers of material from the epoxy resin surface.

[0047] Figure 3 The steps of a method for fabricating vias in a multilayer PCB stack according to the present invention are shown.

[0048] In the first step 200, a multilayer dielectric PCB stack 50 is provided, that is, a PCB stack including multiple alternating first dielectric layers 52 and second dielectric layers 54, and... Figure 3 The top cross-sectional view is shown.

[0049] Advantageously, the first dielectric layer 52 comprises a first dielectric material having a low Tg, such as acrylic acid, and the second dielectric layer 54 comprises a second dielectric material having a high Tg, such as flame retardant type 4 (FR4). In this specification, "low Tg" means a glass transition temperature below or equal to a threshold of 100°C. Similarly, "high Tg" means a glass transition temperature above this 100°C threshold. That is, the glass transition temperature represented by "high Tg" (first Tg) is higher than the glass transition temperature represented by "low Tg" (second Tg). The multilayer PCB stack 50 also includes a top metal layer 56 and a bottom metal layer 58, preferably made of copper, disposed above and below the stack of the first dielectric layer 52 and the second dielectric layer 54, respectively (hereinafter referred to as the dielectric stack).

[0050] In the second step 202, the top metal layer 56 is etched according to a predetermined pattern, thereby leaving multiple mask regions 60 covering the dielectric stack placed below, and leaving corresponding uncovered regions 62 where the dielectric stack is not covered by the top metal layer 56.

[0051] Then, in step 204, mechanical drilling or laser drilling is performed on the dielectric stack corresponding to the uncovered area 62 to obtain a plurality of vias (holes) 64.

[0052] In a further step 206, a permanganate desmearing process (i.e., the process including the three baths mentioned above) is performed on the multilayer PCB stack 50, and then in step 208, electroless metal deposition is performed on the multilayer PCB stack 50 to deposit a first metal layer 68, preferably copper, on the inner walls of the plurality of vias 64.

[0053] During the permanganate descaling process, at least a portion of the first dielectric layer 52 dissolves, and when electroless metal deposition 208 is performed, the first metal layer 68 also fills the spaces formed between the second dielectric layers 54 due to the voids left by the at least partial dissolution of the first dielectric layer 52.

[0054] Optionally, the first dielectric layer 52 is completely dissolved.

[0055] Therefore, a metal ring is formed around the via 64, which at least partially penetrates into the dielectric stack corresponding to the first dielectric layer 52.

[0056] Finally, in step 210, metal plating is performed on the multilayer PCB stack 50 to fill the plurality of vias 64 with a second metal layer 70 (preferably copper).

[0057] Due to the alternation of first dielectric layers 52 and second dielectric layers 54 with different Tg in the multilayer PCB stack 50, the via 64 passes through a metal network 72 formed by a first metal layer 68 replacing the dissolved first dielectric layer 52 (see...). Figure 4 They are interconnected.

[0058] Therefore, the multilayer PCB stack 50 includes a sandwich structure of materials with different Tg (first dielectric layer 52 and second dielectric layer 54) to achieve different etch rates during the desmearing process. This results in the erosion of the first dielectric layer 52 during the desmearing process, followed by the filling of the space between the via 64 and the second dielectric layer 54 with metal during the electroless deposition step 208 and the electroplating fill step 210.

[0059] Figure 4 A three-dimensional view of a multilayer PCB stack 50 including the metal network 72 disclosed above is shown, while Figure 5 A three-dimensional view of a prior art PCB stack 50' excluding this metal mesh 72 is shown. Figure 5 In Figure 5 In the middle, it is marked with Figure 4 Some corresponding figure labels.

[0060] like Figure 4 As shown, with Figure 5Compared to the PCB stack 50', the first metal layer 68, which fills the space between the second dielectric layers 54 and was previously occupied by the first dielectric layer 52, causes the metal network 52 to interconnect multiple vias 64 and is placed between the top metal layer 56 and the bottom metal layer 58.

[0061] Table 1 lists the different dielectric materials that can be used for the first dielectric layer 52 and the second dielectric layer 54 and their corresponding Tg values.

[0062] To achieve optimal performance during the descaling process, materials with a significant difference between their respective Tg values ​​should be selected for use in the first dielectric layer 52 and the second dielectric layer 54, so that the material of the first dielectric layer 52 (with a lower Tg value) dissolves more than the material of the second dielectric layer 54 (with a higher Tg value).

[0063] [Table 1]

[0064] In the context of PCB-embedded power chips, increasing the density of metal on the top and / or bottom sides of the chip helps to achieve a higher overall thermal conductivity of the package and reduce the junction-to-ambient thermal resistance (Rth JA).

[0065] FEM analysis has been performed on the multilayer PCB stack sample (corresponding to the multilayer PCB stack 50 disclosed above) and compared with a reference PCB stack sample in which only one material is used as the dielectric layer (corresponding to the PCB stack 50' shown above).

[0066] Figure 6A A cross-sectional view of a first multilayer PCB stack sample 50a in a first configuration is shown before the desmearing process is applied in step 206, wherein only the first dielectric layer 52 exists in such a first configuration.

[0067] The components corresponding to the multilayer PCB stack 50 disclosed above are indicated by the same reference numerals.

[0068] Figure 6B This shows the end of metal plating filling step 210. Figure 6A The first multilayer PCB stack sample 50a, wherein the first metal layer 68 and the second metal layer 70 have filled the space cleaned from the first dielectric layer 52 during the desmearing process.

[0069] Figure 7A A cross-sectional view of a second multilayer PCB stack sample 50b in a second configuration is shown before the desmearing process is applied in step 206, wherein three first dielectric layers 52 are present in this second configuration.

[0070] Figure 7B This shows the end of the metal plating filling step 210. Figure 7A The second multilayer PCB stack sample 50b, wherein the first metal layer 68 and the second metal layer 70 have filled the space cleaned from the first dielectric layer 52 during the desmearing process.

[0071] Figure 8 A cross-sectional view of a reference PCB stack sample 50c is shown at the end of the metal plating filling step 210. The reference stack 50c includes a top conductive layer 56' and a via 64' made of a single dielectric material.

[0072] In the first multilayer PCB stack sample 50a and the second multilayer PCB stack sample 50b, on the bottom side, the vias 64 that interconnect the multilayer PCB stack samples 50a and 50b to the outer layer are also interconnected with each other by a single fin 74a or three fins 74b.

[0073] In the first multilayer PCB stack sample 50a and the second multilayer PCB stack sample 50b, the thickness of the materials is selected according to the available material specifications. Specifically, the second dielectric layer 54 uses Panasonic R1766 FR4 (with a Tg of 150°C), and the first dielectric layer 52 uses DuPont LF100 acrylic layer (with a Tg of 45°C).

[0074] Tables 2 through 4 show the junction-to-ambient thermal resistance (RthJA) values ​​for reference PCB stack sample 50c and multilayer PCB stack samples 50a and 50b in two configurations, indicating the highest and lowest junction temperatures located within the embedded chip and on the bottom side of the package. The percentage improvement in junction-to-ambient thermal resistance of multilayer PCB stack samples 50a and 50b relative to reference PCB stack sample 50c is shown in the "Rth Gain" column.

[0075] [Table 2]

[0076] [Table 3]

[0077] [Table 4]

[0078] As shown in Tables 2 to 4, the finite element method (FEM) simulation results demonstrate that when this technique is applied to one side of an embedded chip, the RthJA value is significantly improved (25% improvement with three fins). This improvement can be further enhanced when the technique is applied to both sides of the chip. Furthermore, increasing the number of fins to increase metal density improves heat dissipation and thus RthJA.

[0079] The method according to the invention also has the advantage of enabling the fabrication of multilayer PCB stacks by performing standard process steps, as it does not alter the fabrication process of the PCB stack itself. The improved thermal performance of the via interconnects is due to the selection of materials for fabricating the multilayer dielectric stack, which causes the first dielectric layer 52 to be etched during the descaling process and further filled with metal.

[0080] Obviously, while the principles of the invention remain unchanged, the implementation methods and manufacturing details can be made with considerable variation from what has been described and shown above by way of non-limiting example only, without departing from the scope of protection of the invention as defined by the appended claims.

Claims

1. A method for fabricating vias in a multilayer dielectric PCB stack, the multilayer dielectric PCB stack comprising alternating plurality of first dielectric layers and plurality of second dielectric layers, the first dielectric layers comprising a first dielectric material having a first glass transition temperature, and the second dielectric layers comprising a second dielectric material having a second glass transition temperature higher than the first glass transition temperature, wherein a plurality of vias are formed in the plurality of first dielectric layers and the plurality of second dielectric layers. The method includes the following steps: At least partially dissolve the first dielectric layer between the vias; The vias and the spaces formed between the second dielectric layers due to the voids left by the at least partial dissolution of the first dielectric layer are filled with metal to obtain a metal network that interconnects the vias with each other.

2. The method of claim 1, wherein, The step of at least partially dissolving the first dielectric layer between the vias includes performing a permanganate desmearing process on the multilayer dielectric PCB stack.

3. The method of claim 1 or 2, wherein, The steps for filling with metal include: Electroless metal deposition is performed on the multilayer dielectric PCB stack to deposit a first metal layer on the inner walls of the plurality of vias, the first metal layer also filling the space formed between the second dielectric layers due to the voids left by the at least partial dissolution of the first dielectric layer; Metal plating is performed on the multilayer dielectric PCB stack to fill the plurality of vias with a second metal layer.

4. The method of claim 3, wherein, The first metal layer and the second metal layer comprise copper.

5. The method of any one of claims 1 to 4, wherein, The first dielectric layer comprises acrylic acid, and the second dielectric layer comprises FR4.

6. The method according to any one of claims 1 to 5, wherein the method further comprises: A top metal layer is placed above the plurality of first dielectric layers and the plurality of second dielectric layers; The top metal layer is etched according to a predetermined pattern, thereby leaving multiple mask areas covering the first dielectric layer and the second dielectric layer placed below, and leaving corresponding uncovered areas of the first dielectric layer and the second dielectric layer that are not covered by the top metal layer; Drilling is performed on the first dielectric layer and the second dielectric layer corresponding to the uncovered areas to form the plurality of vias.

7. The method of claim 6, further comprising placing a bottom metal layer beneath the plurality of first dielectric layers and the plurality of second dielectric layers.

8. The method according to claim 6, wherein, The top metal layer comprises copper.

9. The method according to claim 7, wherein, The bottom metal layer comprises copper.

10. The method according to claim 6, wherein, Drilling the first dielectric layer and the second dielectric layer includes mechanical drilling or laser drilling.

11. The method according to any one of claims 2 to 10, wherein, The permanganate descaling process includes a first swelling step, a second permanganate etching step, and a third manganese oxide reduction step.

12. A multilayer PCB stack, the multilayer PCB stack comprising: Alternating first dielectric layers and multiple second dielectric layers, wherein the first dielectric layer comprises a first dielectric material having a first glass transition temperature, and the second dielectric layer comprises a second dielectric material having a second glass transition temperature higher than the first glass transition temperature; Multiple vias are formed in the plurality of first dielectric layers and the plurality of second dielectric layers, wherein the first dielectric layer is at least partially dissolved between the vias. The vias and the spaces formed between the second dielectric layers due to the at least partial dissolution of the first dielectric layer are filled with metal to obtain a metal network that interconnects the vias with each other.

13. The multilayer PCB stack of claim 12, further comprising a top metal layer disposed above the plurality of first dielectric layers and the plurality of second dielectric layers, and a bottom metal layer disposed below the plurality of first dielectric layers and the plurality of second dielectric layers.

14. The multilayer PCB stack according to claim 13, wherein, The top metal layer and the bottom metal layer comprise copper.

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