A high linearity sample-and-hold circuit for an electric energy metering chip

Abstract

The application relates to a high-linearity sample-and-hold circuit for an electric energy metering chip, and belongs to the technical field of integrated circuits. The circuit aims to solve the problem of serious deterioration of linearity caused by substrate bias effect and parasitic diode leakage of a traditional sample-and-hold switch under the condition of zero common-mode voltage input. The core of the technical scheme is to introduce a dynamic substrate bias module, so that the substrate potential of a sampling tube and a reset switch can change in real time along with the input signal, and the substrate and the source-drain end are always maintained in reverse bias, and a gate voltage self-boosting circuit is combined to stabilize the gate-source voltage of the sampling tube. The design effectively eliminates threshold voltage drift and substrate leakage current under the premise of almost no increase in circuit complexity, thereby realizing high-linearity signal sampling under the condition of zero common-mode input, and significantly improving the precision and reliability of the electric energy metering chip.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to a high linearity sample-and-hold circuit for electricity meter metering chips, and more particularly to a high linearity sample-and-hold circuit suitable for zero common-mode voltage input. Background Technology

[0002] The accuracy of the electricity meter's internal metering chip is ensured by the analog-to-digital converter (ADC). This ADC requires a sample-and-hold switch with high linearity. The sample-and-hold circuit consists of three parts: a gate voltage bootstrap switch, a sampling capacitor, and a reset switch. Figure 1 As shown. The gate voltage bootstrap switch is crucial for ensuring signal linearity. Since the common-mode voltage of the input signal of the power metering chip is 0V, this poses a significant challenge to traditional sample-and-hold circuits. Because, as... Figure 1 The conventional sample-and-hold circuit shown improves linearity by maintaining a constant gate-source voltage (VGS) of the sampling transistor to suppress changes in on-resistance with the input signal. However, for zero common-mode input signals, the conventional gate-voltage bootstrap switch has the following significant limitations: Limited input range and degraded linearity: Traditional gate-type bootstrap switches experience a significant drop in THD in scenarios with zero common-mode input, such as... Figure 2 As shown, when the input signal common-mode voltage is 0V, the source voltage of the sampling transistor is close to ground potential, which leads to a decrease in its effective gate-source voltage, an increase in on-resistance that varies more sharply with the input signal, and a severe deterioration in linearity.

[0003] Substrate bias effect and leakage current problem: Under zero common-mode input, especially with negative input signals, substrate biasing of the sampling transistor and other MOSFETs in the circuit becomes extremely difficult. If the substrate is fixed to ground, the PN junction between the substrate and the source / drain region will be forward biased when the input voltage is negative, generating severe substrate leakage current and introducing nonlinear distortion. If a source-substrate short-circuit structure is used, the lower plate of the sampling capacitor will reset to zero potential when the input signal is negative, which will also cause parasitic diode forward bias leakage current. These leakage currents vary with the amplitude of the input signal, directly causing distortion of the sampling signal and deterioration of total harmonic distortion.

[0004] In existing technologies, although some studies have attempted to improve linearity by generating negative voltage to power the substrate using a charge pump, the negative voltage generated by this method has poor stability, complex circuit structure, and the introduction of a negative power supply significantly reduces system power efficiency, making it unsuitable for power metering chips with strict power consumption requirements. Therefore, how to design a sample-and-hold circuit that maintains high linearity while also achieving structural simplicity and low power consumption under zero common-mode voltage input conditions has become a pressing technical problem in this field. Summary of the Invention

[0005] In view of this, the object of the present invention is to provide a high linearity sample-and-hold circuit for an energy meter metering chip.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A high-linearity sample-and-hold circuit for an energy meter metering chip includes a sampling module and a dynamic substrate biasing module; The sampling module includes a sampling tube, a sampling capacitor, and a reset switch; The dynamic substrate bias module includes a substrate potential adjustment circuit; The substrate terminals of the sampling tube and the reset switch are both connected to the output terminal of the substrate potential adjustment circuit. The substrate potential adjustment circuit is used to dynamically adjust the substrate potential of the sampling tube according to the input signal, so that the substrate potential of the sampling tube follows the change of the input signal, and when the sampling tube is turned on, the substrate and the source of the sampling tube are kept in reverse bias.

[0007] Furthermore, the sampling module also includes a gate voltage bootstrap circuit, which is used to provide a driving voltage to the gate of the sampling tube during the sampling phase.

[0008] Furthermore, the gate voltage bootstrap circuit includes a first inverter, a first capacitor, a first discharge path, and a gate voltage supply transistor; The input terminal of the first inverter is connected to the first clock signal, and the output terminal of the first inverter is connected to the first plate of the first capacitor. The second plate of the first capacitor is connected to the gate of the sampling tube; The first discharge path is connected between the gate of the sampling tube and the input signal, and is controlled by the first clock signal; The source of the gate voltage supply transistor is connected to the power supply voltage, and its gate and drain are both connected to the second plate of the first capacitor.

[0009] Furthermore, the reset switch is a reset tube, which is used to reset the lower plate of the sampling capacitor to zero potential during the reset phase.

[0010] Furthermore, the sampling module also includes a reset transistor gate voltage control circuit, which includes a second inverter, a second capacitor, and a second discharge path. The input terminal of the second inverter is connected to the second clock signal, and the output terminal of the second inverter is connected to the first plate of the second capacitor; The second plate of the second capacitor is connected to the gate of the reset transistor; The second discharge path is connected between the gate of the reset transistor and ground, and is controlled by the first clock signal.

[0011] Furthermore, the substrate potential adjustment circuit is an operational amplifier. The non-inverting input terminal of the operational amplifier is connected to the drain of the sampling tube to receive the input signal. The inverting input terminal of the operational amplifier is connected to its output terminal. The output terminal of the operational amplifier is simultaneously connected to the substrate terminal of the sampling tube and the reset switch.

[0012] Furthermore, the operational amplifier has a limited output current capability to limit the diode on-current from the substrate end of the sampling tube to its drain-source region.

[0013] Furthermore, the on-resistance of the sampling tube The following relationship must be satisfied:

[0014] in, It's mobility. It is a gate oxide unit capacitance. It is the width of the trench. It is the length of the channel. It is the gate-source voltage of the sampling tube. It is the threshold voltage. It is the body effect coefficient. It is the Fermi potential. It is the source-substrate voltage of the sampling tube.

[0015] Furthermore, the substrate potential adjustment circuit dynamically adjusts the substrate potential of the sampling tube. To control the source substrate voltage So as to affect the on-resistance Change Minimize the amount of change Represented as: .

[0016] Furthermore, the high linearity sample-and-hold circuit is applied to an energy metering analog-to-digital converter system with zero common-mode voltage input. The high linearity sample-and-hold circuit is used to improve the total harmonic distortion (THD) of the analog-to-digital converter under zero common-mode input.

[0017] The beneficial effects of this invention are as follows: (1) By introducing a dynamic substrate bias module, this invention innovatively solves the industry problem of the linearity of traditional gate voltage bootstrap switches deteriorating sharply when the input common-mode voltage is 0V. This solution enables the sample-and-hold circuit to operate stably under the zero common-mode input conditions required by the power metering chip and maintain high linearity, directly meeting the application requirements of high-precision power metering.

[0018] (2) The substrate potential of the sampling transistor and the reset switch is dynamically adjusted by the dynamic substrate bias module (such as an operational amplifier) ​​to make them follow the changes of the input signal in real time. This design ensures that the substrate and source of the sampling transistor are always reverse biased when the input signal is negative, fundamentally eliminating the threshold voltage drift caused by the substrate bias effect. This stabilizes the on-resistance of the sampling transistor, significantly improves the linearity of the circuit in the negative input signal range, and thus improves the total harmonic distortion performance of the entire sampling system.

[0019] (3) Dynamic substrate biasing technology is also applied to the reset switch (reset transistor). By making the substrate potential of the reset transistor dynamically follow the input signal at its drain terminal, the substrate leakage current caused by the reverse bias of the PN junction between the fixed substrate potential (such as ground) and the changing input signal during the reset phase is avoided. This solves the problems of limited input swing and parasitic leakage current that exist when the substrate is fixed to ground or the source and substrate are short-circuited in the traditional structure, and ensures the integrity of the sampled signal.

[0020] (4) On-resistance of the sampling tube Subject to its gate-source voltage and source voltage Combined effects. This invention stabilizes through a gate voltage bootstrap circuit. Simultaneously, precise control is achieved through dynamic substrate bias. This has an impact Key quantities of change ( This is minimized. and The coordinated control ensures the high stability of the sampling switch's on-resistance at the device physical level, which is the core mechanism for achieving high linearity.

[0021] (5) Compared with the complex scheme of generating negative voltage using a charge pump, the present invention only adds a substrate potential adjustment circuit (such as a unity-gain buffer operational amplifier) ​​to the traditional gate voltage bootstrap switch, with almost no increase in circuit complexity. At the same time, the scheme does not require the generation of an unstable negative power supply, avoiding the design complexity and low power efficiency problems caused by negative voltage power supply, making it very suitable for low-power integrated circuits such as power metering chips with strict limitations on area and power consumption.

[0022] (6) For example Figure 6 The test results show that, under conditions of 0V input common-mode voltage and varying input amplitude, the sample-and-hold switch using the circuit of this invention exhibits significantly better linearity (or THD performance) than traditional gate-voltage bootstrap switches. This directly verifies the effectiveness and superiority of this invention in zero common-mode input scenarios.

[0023] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0024] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of a traditional sample-and-hold circuit. Figure 2 It is a traditional gate voltage bootstrap switch; Figure 3 Example of connecting a zero common-mode gate voltage bootstrap switch to a sampling capacitor; Figure 4 It is a timing waveform; Figure 5 It is a traditional gate voltage bootstrap switch; Figure 6 This represents the variation of THD with input amplitude. Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0027] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0028] Please see Figure 3 This diagram illustrates a circuit structure schematic of a high-linearity sample-and-hold circuit for an energy meter metering chip according to an embodiment of the present invention. The circuit mainly includes a sampling module and a dynamic substrate bias module. The sampling module samples the input signal VIN under specific timing control and holds it on the sampling capacitor CS to output a sampled signal VOUT. The dynamic substrate bias module provides a dynamic substrate potential for the key MOS transistor in the sampling module to eliminate substrate bias effects.

[0029] Specifically, the sampling module includes a sampling transistor M1, a gate voltage bootstrap circuit, a reset transistor M7, a sampling capacitor CS, and related control switches. In this embodiment, the dynamic substrate bias module is implemented using an operational amplifier A1.

[0030] The gate voltage bootstrap circuit is used to provide a stable high drive voltage to the gate of the sampling transistor M1 during the sampling phase. It includes a first inverter INV1, a first capacitor C1, a gate voltage supply transistor M2, and a first discharge path composed of M3, M4, M5, and M6. The input of the first inverter INV1 is connected to a first clock signal P1, and its output is connected to the first plate (lower plate) of the first capacitor C1. The second plate (upper plate) of the first capacitor C1 is connected to the gate of the sampling transistor M1. The drain of the gate voltage supply transistor M2 is connected to the upper plate of the first capacitor C1 to the input, and its gate and drain are shorted and connected together to the input signal. The gates of MOSFETs M3 and M4, and M5 and M6 are all shorted to their respective drains. The source of M3 is connected to the drain of M4; the source of M4 is connected to the drain of M5; the source of M5 is connected to the drain of M6; and the source of M6 is connected to the input. M3, M4, M5, and M6 are connected in series to form a controllable discharge path from the gate of M1 to ground under clock control. The source of M1 is connected to the input, and the drain is connected to the lower plate of the sampling capacitor CS.

[0031] The sampling module also includes a reset transistor gate voltage control circuit for controlling the on and off states of the reset transistor M7. This circuit includes a second inverter INV2, a second capacitor C2, and a second discharge path composed of M8 and M9. The input of the second inverter INV2 is connected to the second clock signal P2, and its output is connected to the first plate (lower plate) of the second capacitor C2. The second plate (upper plate) of the second capacitor C2 is connected to the gate of the reset transistor M7. The gate of the MOSFET M8 is connected to the inverted signal of the first clock signal P2, its drain is connected to the upper plate of C2, and its source is connected to the drain of the MOSFET M9. The gate and drain of the MOSFET M9 are shorted.

[0032] The source of sampling transistor M1 serves as the input terminal to receive the input signal VIN, and its drain is connected to the lower plate of sampling capacitor CS. The upper plate of sampling capacitor CS is connected to the output terminal VOUT. The source of reset transistor M7 is grounded, and its drain is connected to the lower plate of sampling capacitor CS (i.e., the drain node of M1).

[0033] The core of the dynamic substrate biasing module is operational amplifier A1. A1 is configured as a unity-gain buffer (voltage follower), with its non-inverting input (+) connected to the common-mode voltage VCM, and its inverting input (-) shorted to its output Vb1. The output Vb1 of operational amplifier A1 is simultaneously connected to the substrates of sampling transistor M1, gate voltage supply transistor M2, switching transistors M3, M4, M5, and M6, reset transistor M7, and switching transistor M8. Operational amplifier A1 is designed to have a limited output current capability.

[0034] The operating timing of the circuit in this invention is controlled by two non-overlapping clocks P1 and P2, and their timing relationship is as follows: Figure 4 As shown below. (Combined with...) Figure 3 and Figure 4 Explain the working principle of the circuit: Sampling phase: This clock phase corresponds to P2 being high and P1 being low.

[0035] Since P2 is high, the second inverter INV2 outputs a low level, causing the lower plate of the second capacitor C2 to be at a low level. Because the voltage across capacitor C2 cannot change abruptly, the voltage of its upper plate (the gate of reset transistor M7) will be pulled down to a negative voltage (approximately 0-VDD), thereby ensuring that reset transistor M7 is reliably turned off.

[0036] During this stage, P1 is low, and the first inverter INV1 outputs a high level, pre-charging the first capacitor C1. At this time, the gate voltage Vg of the sampling transistor M1 is approximately VDD + VX, where VX is the voltage remaining after the gate discharge of M1 in the previous stage. Therefore, the sampling transistor M1 is turned on, and the signal is connected to the lower plate of the sampling capacitor CS through M1.

[0037] With dynamic substrate bias, operational amplifier A1 operates continuously, and the potential of its output terminal Vb1 always follows the potential of its non-inverting input terminal, i.e., the input signal VIN.

[0038] Reset phase: This clock phase corresponds to P1 being high and P2 being low.

[0039] P1 jumps high, P2 jumps low. The output of the first inverter INV1 jumps low. Since the voltage across capacitor C1 cannot change abruptly, the potential of its upper-stage board (i.e., the gate of sampling transistor M1) will be pulled down by VDD from its original low level, becoming a negative voltage. Specifically, assume that at the end of the previous cycle, the potential of the upper-stage board of C1 was... Vg When P1 is high, INV1 output is 0, then the gate potential of M1 becomes Vg- VDD, through proper design, enables M1 to be turned off.

[0040] When P2 is low, the second inverter INV2 outputs a high level, pulling the lower plate of the second capacitor C2 up to VDD. Since the voltage across capacitor C2 cannot change abruptly, the potential of its upper plate (the gate of reset transistor M7) will be raised by VDD, making it much higher than the threshold voltage, thus ensuring that reset transistor M7 is fully turned on and resetting the upper plate of sampling capacitor CS (i.e., the sampling node) to ground potential (0V).

[0041] At the start of the sampling phase, reset transistor M7 first resets the sampling node to 0V. Subsequently, under stable gate voltage drive, sampling transistor M1 turns on, and the input signal VIN charges the sampling capacitor CS through M1, completing signal sampling. After sampling is completed, the clock switches again, the circuit enters hold state, and the voltage on CS is read by subsequent circuits (such as an ADC).

[0042] Whether in the sampling phase or the reset phase, the first leakage circuit formed by MOSFETs M3, M4, M5 and M6 is always working, slowly discharging the voltage of Vg to the off state of M1, while MOSFET M2 ensures that Vg has a suitable voltage.

[0043] During the sampling phase, operational amplifier A1 continues to operate, and the potential of its output terminal Vb1 follows the input signal VIN in real time. This ensures that regardless of whether VIN is a positive or negative voltage, the substrate potential Vb1 of sampling transistor M1 always follows its source potential VIN, thereby guaranteeing its source-substrate voltage. The change is small, thus the change in the on-resistance of M1 is small. For the reset transistor M7, when it is turned off, its source is grounded and its drain is connected to the lower plate of the sampling capacitor CS (at this time, it is VIN). At this time, Vb1 is a fixed voltage higher than VIN because of the forward bias of the substrate of M1 to the source diode. Therefore, it avoids the situation of forward bias leakage of the PN junction of M7 when VIN is negative, which is the case with the traditional grounded substrate method.

[0044] The limiting output current capability of operational amplifier A1 is a critical design consideration. If the output current capability of A1 is too high, when the input VIN is negative, the current flowing from Vb1 to the source / drain region of transistor M1 will be excessive, leading to changes in the on-state voltage drop of the parasitic diode and introducing nonlinearity. By limiting the output current of A1, the on-state current of this diode can be restricted to a fixed small value, thus keeping the voltage drop across the parasitic diode essentially constant. In this way, the Vb1 potential will strictly follow VIN with only a fixed, tiny offset, ensuring high linearity.

[0045] This invention, through the aforementioned dynamic substrate biasing mechanism, reduces the on-resistance of the sampling transistor M1. Highly stable. The calculation formula is:

[0046] in, It's mobility. It is a gate oxide unit capacitance. It is the width of the trench. It is the length of the channel. It is the gate-source voltage of the sampling tube. It is the threshold voltage. It is the body effect coefficient. It is the Fermi potential. It is the source-substrate voltage of the sampling tube.

[0047] In this invention, since Vb1 dynamically follows VIN, the formula is related to... Related nonlinear terms ( ) was greatly suppressed, The variation primarily depends on the VGS provided stably by the gate voltage bootstrap circuit. Key variables of change This minimizes the sampling characteristics, thus achieving high linearity across the entire operating range of zero common-mode voltage input.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A high linearity sample-and-hold circuit for an electric energy metering chip, characterized by: Includes a sampling module and a dynamic substrate biasing module; The sampling module includes a sampling tube, a sampling capacitor, and a reset switch; The dynamic substrate bias module includes a substrate potential adjustment circuit; The substrate terminals of the sampling tube and the reset switch are both connected to the output terminal of the substrate potential adjustment circuit. The substrate potential adjustment circuit is used to dynamically adjust the substrate potential of the sampling tube according to the input signal, so that the substrate potential of the sampling tube follows the change of the input signal, and when the sampling tube is turned on, the substrate and the source of the sampling tube are kept in reverse bias.

2. The high linearity sample-and-hold circuit of claim 1, wherein: The sampling module further includes a gate voltage bootstrap circuit, which is used to provide a driving voltage to the gate of the sampling tube during the sampling phase.

3. The high linearity sample-and-hold circuit according to claim 2, characterized in that: The gate voltage bootstrap circuit includes a first inverter, a first capacitor, a first discharge path, and a gate voltage supply transistor; The input terminal of the first inverter is connected to the first clock signal, and the output terminal of the first inverter is connected to the first plate of the first capacitor. The second plate of the first capacitor is connected to the gate of the sampling tube; The first discharge path is connected between the gate of the sampling tube and ground, and is controlled by the first clock signal; The source of the gate voltage supply transistor is connected to the power supply voltage, and its gate and drain are both connected to the second plate of the first capacitor.

4. The high linearity sample-and-hold circuit according to claim 1, characterized in that: The reset switch is a reset transistor, which is used to reset the lower plate of the sampling capacitor to zero potential during the reset phase.

5. The high linearity sample-and-hold circuit according to claim 4, characterized in that: The sampling module also includes a reset transistor gate voltage control circuit, which includes a second inverter, a second capacitor, and a second discharge path. The input terminal of the second inverter is connected to the second clock signal, and the output terminal of the second inverter is connected to the first plate of the second capacitor; The second plate of the second capacitor is connected to the gate of the reset transistor; The second discharge path is connected between the gate of the reset transistor and ground, and is controlled by the first clock signal.

6. The high linearity sample-and-hold circuit according to claim 1, characterized in that: The substrate potential adjustment circuit is an operational amplifier. The non-inverting input terminal of the operational amplifier is connected to the drain of the sampling tube to receive the input signal. The inverting input terminal of the operational amplifier is connected to its output terminal. The output terminal of the operational amplifier is connected to both the sampling tube and the substrate terminal of the reset switch.

7. The high linearity sample-and-hold circuit according to claim 6, characterized in that: The operational amplifier has a limited output current capability to limit the diode on-current from the substrate end of the sampling tube to its drain-source region.

8. The high linearity sample-and-hold circuit according to claim 1, characterized in that: The on-resistance of the sampling tube The following relationship must be satisfied: in, It's mobility. It is a gate oxide unit capacitance. It is the width of the trench. It is the length of the channel. It is the gate-source voltage of the sampling tube. It is the threshold voltage. It is the body effect coefficient. It is the Fermi potential. It is the source-substrate voltage of the sampling tube.

9. The high linearity sample-and-hold circuit according to claim 8, characterized in that: The substrate potential adjustment circuit dynamically adjusts the substrate potential of the sampling tube. To control the source substrate voltage So as to affect the on-resistance Change Minimize the amount of change Represented as: .

10. The high linearity sample-and-hold circuit according to any one of claims 1 to 9, characterized in that: The high linearity sample-and-hold circuit is applied to an energy metering analog-to-digital converter system with zero common-mode voltage input. The high linearity sample-and-hold circuit is used to improve the total harmonic distortion (THD) of the analog-to-digital converter under zero common-mode input.

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