Semiconductor device and method of manufacturing the same, electronic device
By forming through-holes and channels in semiconductor devices, filling semiconductor pillars and replacing them with gate insulating layers and gates, the problem of difficulty in improving device density and on/off ratio is solved, and the stability and integration of devices are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2024-12-23
- Publication Date
- 2026-06-23
AI Technical Summary
In existing technologies, it is difficult to improve the device density and on/off ratio of semiconductor devices, which presents performance and process challenges.
By fabricating multiple bit lines and dielectric layers on a substrate to form through-holes and channels, filling semiconductor pillars, and replacing the sacrificial layer with a gate insulating layer and a gate, the coverage area of the semiconductor pillars and gate is increased, thereby improving gate control capability.
The gate control area was increased, the on-state current was increased, the device structure was optimized, the device stability and switching ratio were improved, and the device was miniaturized and highly integrated.
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Figure CN122269703A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology
[0002] With the development and progress of semiconductor technology, semiconductor devices are constantly moving towards miniaturization, high density, high integration, and low power consumption. At the same time, they are also facing problems and challenges from performance and process aspects. Summary of the Invention
[0003] This application proposes a semiconductor device and its manufacturing method, as well as an electronic device, to solve the technical problem of difficulty in improving device density and switching ratio in related technologies.
[0004] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising: Multiple bit lines are fabricated on a substrate; the multiple bit lines extend along a first direction and are distributed sequentially along a second direction, the first direction and the second direction intersect and are both parallel to the substrate; Fabricate a first dielectric layer covering multiple bit lines; The sacrificial layer and the second dielectric layer, covering the first dielectric layer, are fabricated sequentially. Multiple first vias are formed, penetrating the second dielectric layer, the sacrificial layer, and the first dielectric layer, and are distributed in an array; the bottom of the first vias exposes the bit line; A portion of the second dielectric layer and a portion of the first dielectric layer surrounding the first through hole are removed to form a first channel; Multiple semiconductor pillars are fabricated; the semiconductor pillars correspond to filling the first through hole and the first channel surrounding the outer periphery of the first through hole; By replacing the sacrificial layer with multiple gate insulating layers and multiple gates surrounding multiple semiconductor pillars, multiple transistors are obtained.
[0005] In some optional embodiments of this application, before fabricating multiple bit lines on the substrate, the method further includes: A first insulating layer is fabricated on the substrate; In addition, multiple bit lines are fabricated on the substrate, including: Fabricate a first conductive layer; cover the first insulating layer with the first conductive layer; The first conductive layer is patterned to form multiple first trenches; the multiple first trenches extend along a first direction and are distributed sequentially at intervals along a second direction, dividing the first conductive layer into multiple bit lines.
[0006] In some optional embodiments of this application, fabricating a first dielectric layer covering multiple bit lines includes: An oxide layer is deposited to obtain a first dielectric layer; the first dielectric layer fills a plurality of first trenches and covers a plurality of bit lines; And, sequentially fabricating a sacrificial layer and a second dielectric layer covering the first dielectric layer, including: Polycrystalline silicon and oxide are deposited sequentially to obtain a sacrificial layer and a second dielectric layer; the sacrificial layer covers the first dielectric layer, and the second dielectric layer covers the sacrificial layer.
[0007] In some optional embodiments of this application, removing a portion of the second dielectric layer and a portion of the first dielectric layer surrounding the first through-hole to form a first channel includes: Through the first through-hole, a portion of the second dielectric layer and a portion of the first dielectric layer surrounding the first through-hole are simultaneously etched laterally to form a first sub-channel and a second sub-channel that are annularly surrounding the first through-hole, thus obtaining the first channel.
[0008] In some optional embodiments of this application, the sacrificial layer is replaced by a plurality of gate insulating layers and a plurality of gates surrounding a plurality of semiconductor pillars, including: Multiple second trenches are formed; the multiple second trenches are alternately distributed with multiple semiconductor pillars along the first direction and each extends along the second direction, the side of the second trench exposes the sacrificial layer and the bottom exposes the first dielectric layer; The sacrificial layer is removed to obtain multiple second channels; the multiple second channels are distributed sequentially along the first direction and each extends along the second direction, exposing multiple semiconductor pillars distributed sequentially along the second direction; Multiple gate insulating layers and multiple word lines are sequentially fabricated to cover and fill multiple second channels; multiple semiconductor pillars distributed sequentially along the second direction share a gate insulating layer and a word line, and the word line includes multiple gates corresponding one-to-one with the multiple semiconductor pillars.
[0009] In some optional embodiments of this application, multiple gate insulating layers and multiple word lines that conformally cover and fill multiple second channels are sequentially fabricated, including: Fabricate an initial gate insulating layer; the initial gate insulating layer conformally covers multiple second trenches and multiple second channels; Fabricate a second conductive layer; the second conductive layer covers the initial gate insulating layer and fills multiple second trenches and multiple second channels; The initial gate insulating layer and the second conductive layer located in the multiple second trenches are removed to expose the first dielectric layer. The remaining initial gate insulating layer and the second conductive layer in the second channel form the gate insulating layer and the word line, respectively.
[0010] In some optional embodiments of this application, after replacing the sacrificial layer with a plurality of gate insulating layers and a plurality of gates surrounding a plurality of semiconductor pillars, the method further includes: Fabricate a second insulating layer; fill multiple second trenches with the second insulating layer; Multiple interconnect structures are fabricated; semiconductor pillars are electrically connected to active devices through the interconnect structures.
[0011] Secondly, embodiments of this application provide a semiconductor device, including: Multiple bit lines are disposed on one side of the substrate, extending along a first direction and distributed sequentially along a second direction; Multiple transistors are arranged in an array; each transistor includes a semiconductor pillar and a gate insulating layer and a gate sequentially wound around the periphery of the semiconductor pillar, and the semiconductor pillar is electrically connected to a bit line. The semiconductor pillar includes a first sublayer, a second sublayer, and a third sublayer arranged sequentially along a direction away from the bit line. In a horizontal cross-section parallel to the substrate, the cross-sectional area of the second sublayer is smaller than the cross-sectional areas of the first and third sublayers.
[0012] In some optional embodiments of this application, the semiconductor device includes at least one of the following: In a vertical section perpendicular to the substrate, the cross-sectional shape of the semiconductor pillar includes a T-shape, a 6-shape, an H-shape with a 90-degree flip, or an I-shape; The gate insulating layer covers the top wall of the first sublayer, the sidewall of the second sublayer, and the bottom wall of the third sublayer, and the gate is filled in the groove formed by the gate insulating layer.
[0013] In some optional embodiments of this application, the semiconductor device includes at least one of the following: Several transistors distributed sequentially along the first direction share a single bit line; The semiconductor device also includes multiple word lines, which are distributed sequentially along a first direction and each extends along a second direction. Several transistors distributed sequentially along the second direction share a single word line. Semiconductor devices also include multiple interconnect structures that are electrically connected to the end of the semiconductor pillar furthest from the bit line.
[0014] Thirdly, embodiments of this application provide an electronic device, including: A semiconductor device manufactured using the semiconductor device manufacturing method described above; or, Semiconductor devices as described above.
[0015] The beneficial technical effects of the technical solutions provided in this application include: In this embodiment, the first via and the first channel define the position and shape of the semiconductor pillar to be formed. The position of the sacrificial layer after forming the first via and the first channel defines the position of the gate insulating layer and the gate to be formed. Since the semiconductor pillar formed in the first via and the first channel covers part of the top wall and part of the bottom wall of the sacrificial layer exposed on the side of the first via and the first channel, by replacing the sacrificial layer with the gate insulating layer and the gate, not only can the semiconductor pillar and the gate have a projection intersection portion corresponding to the first via, but also a projection intersection portion corresponding to the first channel. This ensures that the semiconductor pillar covers the side wall, top wall, and bottom wall of the gate facing the semiconductor pillar, increasing the corresponding area of the semiconductor pillar and the gate. This increases the gate control area of the semiconductor device, effectively improving the gate control capability, effectively increasing the on-state current, improving the switching ratio of the device, optimizing the device structure, and improving the device stability.
[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description
[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application; Figures 2 to 34 This is a schematic diagram of the structure of a semiconductor device manufacturing method provided in this application at different processes.
[0018] Figure label: 10-Substrate; 20 - Bit line; 21 - First conductive layer; 31-First dielectric layer; 32-Sacrificial layer; 321-Sub-sacrificial layer; 33-Second dielectric layer; 41-First through hole; 42-First channel; 421-First sub-channel; 422-Second sub-channel; 43-Second channel; 44-Second through hole; 50 - Transistor; 51 - Semiconductor pillar; 511 - First sublayer; 512 - Second sublayer; 513 - Third sublayer; 52 - Gate insulating layer; 53 - Gate; 54 - Initial gate insulating layer; 61 - First insulating layer; 62 - Second insulating layer; 71 - First trench; 72 - Second trench; 80 - Word line; 81 - Second conductive layer; 90 - Interconnection structure; 91 - First electrode; 92 - Second electrode; 101 - First mask structure; 102 - Second mask structure; 103 - Third mask structure. Detailed Implementation
[0019] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0020] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in the specification of this application means the presence of the stated features, integers, steps, operations, and / or components, but does not exclude implementation as other features, information, data, steps, operations, components, and / or combinations thereof supported by the art. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" can be implemented as "A," or as "B," or as "A and B."
[0021] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0022] The semiconductor devices, manufacturing methods, and electronic devices provided in this application are intended to solve the aforementioned technical problems in related technologies.
[0023] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.
[0024] This application provides a method for manufacturing a semiconductor device, and the flowchart of the method is shown below. Figure 1 As shown, the structural schematic diagrams of the semiconductor device manufacturing method at different processes are as follows: Figures 2 to 34 As shown.
[0025] It should be noted that, as Figure 3 and Figure 17 As shown in the embodiment of this application, the first direction is parallel to the AA direction, and the second direction is parallel to the BB and CC directions.
[0026] In this embodiment of the application, the method for manufacturing the semiconductor device includes: S101. Fabricate multiple bit lines 20 on the substrate 10; such as Figures 3 to 5As shown, multiple bit lines 20 extend along the first direction (AA direction) and are distributed sequentially along the second direction (BB direction). The first direction and the second direction intersect and are both parallel to the substrate 10.
[0027] S102, Fabricate a first dielectric layer 31 covering multiple bit lines 20 (e.g., ... Figure 6 and Figure 7 (As shown).
[0028] S103, sequentially fabricate a sacrificial layer 32 and a second dielectric layer 33 covering the first dielectric layer 31 (e.g., Figure 8 and Figure 9 (As shown).
[0029] S104, Forming a plurality of first vias 41 that penetrate the second dielectric layer 33, the sacrificial layer 32, and the first dielectric layer 31, and are distributed in an array; such as Figures 10 to 12 As shown, the bottom of the first through hole 41 exposes the bit line 20.
[0030] S105. Remove a portion of the second dielectric layer 33 and a portion of the first dielectric layer 31 surrounding the first through hole 41 to form a first channel 42 (e.g., ...). Figure 13 and Figure 14 (As shown).
[0031] S106, Fabricate multiple semiconductor pillars 51; such as Figure 15 and Figure 16 As shown, the semiconductor pillar 51 is filled with the first through hole 41 and the first channel 42 surrounding the outer periphery of the first through hole 41.
[0032] S107. The sacrificial layer 32 is replaced with multiple gate insulating layers 52 and multiple gates 53 surrounding the multiple semiconductor pillars 51, resulting in multiple transistors 50 (e.g., Figures 26 to 28 (As shown).
[0033] In this embodiment, the substrate 10 supports bit lines 20, transistors 50, and first dielectric layer 31, second dielectric layer 33, etc.
[0034] In the embodiments of this application, such as Figures 3 to 5 As shown, a plurality of bit lines 20 are fabricated on the substrate 10. The plurality of bit lines 20 are distributed sequentially at intervals along the second direction and each extends along the first direction.
[0035] Next, as Figure 6 and Figure 7 As shown, a first dielectric layer 31 is fabricated to cover multiple bit lines 20. The first dielectric layer 31 fills a first trench 71 located between any two adjacent bit lines 20 and covers the side of the multiple bit lines 20 away from the substrate 10. Any two adjacent bit lines 20 are electrically isolated through the first dielectric layer 31.
[0036] Next, as Figure 8 and Figure 9 As shown, a sacrificial layer 32 covering the first dielectric layer 31 and a second dielectric layer 33 covering the sacrificial layer 32 are fabricated.
[0037] Next, as Figures 10 to 12 As shown, a plurality of first through holes 41 are formed, the first through holes 41 penetrate the second dielectric layer 33, the sacrificial layer 32 and the first dielectric layer 31, the side of the first through hole 41 exposes the sacrificial layer 32 and the bottom exposes the bit line 20, and the plurality of first through holes 41 are arranged in an array along the first direction and the second direction.
[0038] Next, as Figure 13 and Figure 14 As shown, a plurality of first channels 42 are formed corresponding to a plurality of first through holes 41. Each first channel 42 is arranged around the outer periphery of the corresponding first through hole 41. On a horizontal cross section parallel to the substrate 10, the outer contour dimension of the first channel 42 is larger than the outer contour dimension of the first through hole 41. The first through hole 41 and the first channel 42 define the position and shape of the semiconductor pillar 51 to be formed. The first channel 42 exposes part of the top wall and part of the bottom wall of the sacrificial layer 32.
[0039] Next, as Figure 15 and Figure 16 As shown, a plurality of semiconductor pillars 51 are fabricated corresponding one-to-one with a plurality of first vias 41. Each semiconductor pillar 51 fills the corresponding first via 41 and the corresponding first channel 42, such that the cross-sectional shape of the semiconductor pillar 51 in a vertical section perpendicular to the substrate 10 includes a T-shape, a T-shape, an H-shape flipped by 90 degrees, or an I-shape. The semiconductor pillar 51 covers part of the top wall and part of the bottom wall of the sacrificial layer 32 exposed on the side of the first via 41 and the sacrificial layer 32 exposed on the first channel 42.
[0040] Next, as Figures 26 to 28 As shown, the sacrificial layer 32 is replaced with multiple gate insulating layers 52 and multiple gates 53. The gate insulating layers 52 and gates 53 are sequentially wound around the periphery of the semiconductor pillar 51 to form a transistor 50. The gate insulating layer 52 is located between the semiconductor pillar 51 and the gates 53, thereby electrically isolating the semiconductor pillar 51 and the gates 53.
[0041] In this embodiment, the position of the sacrificial layer 32 after forming the first via 41 and the first channel 42 defines the positions of the gate insulating layer 52 and the gate 53 to be formed. Since the semiconductor pillar 51 formed within the first via 41 and the first channel 42 covers the exposed sidewall of the sacrificial layer 32 of the first via 41 and part of the top and bottom walls of the exposed sidewall of the sacrificial layer 32 of the first channel 42, by replacing the sacrificial layer 32 with the gate insulating layer 52 and the gate 53, not only can the semiconductor pillar 51 and the gate 53 have intersecting projections corresponding to the first via 41, but they also have intersecting projections corresponding to the first channel 42. This ensures that the semiconductor pillar 51 covers the sidewall, top wall, and bottom wall of the gate 53 facing the semiconductor pillar 51, increasing the corresponding area of the semiconductor pillar 51 and the gate 53. This increases the gate control area of the gate 53 relative to the semiconductor device, effectively improving gate control capability, effectively increasing on-state current, improving the switching ratio of the device, optimizing the device structure, and improving device stability.
[0042] In addition, in this embodiment, the axis of the semiconductor pillar 51 is parallel to the axis of the first through hole 41 and perpendicular to the substrate 10. The transistor 50 has a channel region arranged in a direction perpendicular to the substrate 10. The channel region of the transistor 50 occupies a small area in a horizontal plane parallel to the substrate 10. The number of transistors 50 that can be fabricated in a unit area of this horizontal plane is increased, thereby improving the density and integration of the semiconductor device and achieving miniaturization.
[0043] In some optional embodiments of this application, such as Figure 2 As shown, before fabricating multiple bit lines 20 on the substrate 10, the process also includes: A first insulating layer 61 is fabricated on the substrate 10. The first insulating layer 61 can separate the substrate 10 from the conductive components (such as bit lines 20) that are subsequently fabricated, thereby achieving electrical isolation between the substrate 10 and the conductive components and preventing leakage.
[0044] Optionally, in this embodiment, the substrate 10 is made of a semiconductor material, including but not limited to silicon. The first insulating layer 61 is made of an oxide material, including but not limited to oxide.
[0045] In some optional embodiments of this application, such as Figures 2 to 5 As shown, a plurality of bit lines 20 are fabricated on the substrate 10, including: like Figure 2 As shown, a first conductive layer 21 is fabricated; the first conductive layer 21 covers the first insulating layer 61.
[0046] Optionally, in this embodiment, the material of the first conductive layer 21 is a conductive material, including but not limited to TiN (titanium nitride) or W (tungsten). The first conductive layer 21 can be fabricated by a deposition process.
[0047] Next, as Figures 3 to 5 As shown, the pattern is formed to create multiple first trenches 71; the multiple first trenches 71 extend along the first direction (AA direction) and are distributed sequentially at intervals along the second direction (BB direction) to divide the first conductive layer 21 into multiple bit lines 20.
[0048] In this embodiment of the application, each first trench 71 extends along a first direction, and the multiple first trenches 71 are sequentially and spaced along a second direction to divide the first conductive layer 21 into multiple bit lines 20. The multiple bit lines 20 and the multiple first trenches 71 are sequentially and alternately distributed along the second direction, and the resulting bit lines 20 extend along the first direction.
[0049] Optionally, in this embodiment of the application, a plurality of first trenches 71 can be formed by etching process, i.e., etching the first conductive layer 21.
[0050] In some optional embodiments of this application, such as Figure 6 and Figure 7 As shown, fabricating a first dielectric layer 31 covering multiple bit lines 20 includes: An oxide layer 31 is deposited to form a first dielectric layer 31; the first dielectric layer 31 fills a plurality of first trenches 71 and covers a plurality of bit lines 20.
[0051] In this embodiment, the material of the first dielectric layer 31 is an insulating oxide. The first dielectric layer 31 fills the first trench 71 located between any two adjacent bit lines 20 and covers a plurality of bit lines 20. Any two adjacent bit lines 20 are electrically isolated by the first dielectric layer filled in the first trench 71.
[0052] In some optional embodiments of this application, such as Figure 8 and Figure 9 As shown, a sacrificial layer 32 covering the first dielectric layer 31 and a second dielectric layer 33 are sequentially fabricated, including: Polysilicon and oxide are deposited sequentially to obtain a sacrificial layer 32 and a second dielectric layer 33; the sacrificial layer 32 covers the first dielectric layer 31, and the second dielectric layer 33 covers the sacrificial layer 32.
[0053] In this embodiment, the etching selectivity of the sacrificial layer 32 is different from that of the first dielectric layer 31 and the second dielectric layer 33. When etching the first dielectric layer 31 and the second dielectric layer 33, the sacrificial layer 32 will not be etched, and a relatively intact sacrificial layer 32 can be preserved.
[0054] Optionally, in the embodiments of the present application, the material of the second dielectric layer 33 is an insulating oxide. The etching selectivity of the first dielectric layer 31 and the second dielectric layer 33 is the same, so that the sizes of the subsequent formed first sub-channel 421 and second sub-channel 422 are the same, and thus the cross-sectional shape of the subsequent fabricated semiconductor pillar 51 in the vertical cross-section includes a standard H shape rotated 90 degrees. Optionally, the materials of the first dielectric layer 31 and the second dielectric layer 33 are the same.
[0055] Certainly, in other embodiments of the present application, according to actual needs, the etching selectivity of the first dielectric layer 31 and the second dielectric layer 33 can also be made different, so that the sizes of the subsequent formed first sub-channel 421 and second sub-channel 422 are different, and the cross-sectional shape of the subsequent fabricated semiconductor pillar 51 in the vertical cross-section includes two rotated 90-degree H shapes with different side lengths, or a T shape, or an inverted T shape (i.e., a T shape rotated 180 degrees), or a cross shape, or a similar shape, or an I shape, etc.
[0056] In some optional embodiments of the present application, as Figures 10 to 12 shown, forming a plurality of first through-holes 41 that penetrate the second dielectric layer 33, the sacrificial layer 32, and the first dielectric layer 31 and are arranged in an array includes: performing patterning to form a plurality of first through-holes 41.
[0057] Optionally, in the embodiments of the present application, the second dielectric layer 33, the sacrificial layer 32, and the first dielectric layer 31 can be etched in a direction perpendicular to the substrate 10 (such as dry etching) to form a plurality of first through-holes 41 arranged in an array and expose the bit line 20.
[0058] Optionally, as Figures 10 to 12 shown, in the embodiments of the present application, performing patterning to form a plurality of first through-holes 41 includes: Fabricating a first mask structure 101 on the side of the second dielectric layer 33 away from the substrate 10, and patterning the first mask structure 101 to make the first mask structure 101 have a first preset pattern, and using the first preset pattern to define the shapes and positions of a plurality of first through-holes 41 arranged in an array along the first direction and the second direction.
[0059] Then, based on the first mask structure 101 with the first preset pattern, the second dielectric layer 33, the sacrificial layer 32, and the first dielectric layer 31 are etched to form a plurality of first through-holes 41, and the bit line 20 is exposed at the bottom of each first through-hole 41.
[0060] Optionally, the first mask structure 101 can be a hard mask (HM). Optionally, the material of the first mask structure 101 includes but is not limited to SiN (silicon nitride).
[0061] It should be noted that, in the embodiments of this application, the fabrication method of the first mask structure 101 and the first preset pattern can be the same as or similar to conventional mask fabrication techniques in the art, and will not be described in detail here. The setting and fabrication method of the second mask structure 102 and the third mask structure 103 in the following text can adopt the same or similar method as the first mask structure 101, and will not be described in detail here.
[0062] In some optional embodiments of this application, such as Figure 13 and Figure 14 As shown, a portion of the second dielectric layer 33 and a portion of the first dielectric layer 31 surrounding the first through-hole 41 are removed to form a first channel 42, including: Through the first through hole 41, a portion of the second dielectric layer 33 and a portion of the first dielectric layer 31 surrounding the first through hole 41 are simultaneously etched laterally to form a first sub-channel 421 and a second sub-channel 422 that are annularly surrounding the first through hole 41, thus obtaining the first channel 42.
[0063] In this embodiment, the first via 41 penetrates the second dielectric layer 33, the sacrificial layer 32, and the first dielectric layer 31, with the side portion of the first via 41 exposing the second dielectric layer 33, the sacrificial layer 32, and the first dielectric layer 31. Laterally etched portions of the second dielectric layer 33 and the first dielectric layer 31 exposed by the first via 41 are formed, creating a first sub-channel 421 at the laterally etched portion of the second dielectric layer 33. The first sub-channel 421 is annularly arranged around the outer periphery of the first via 41. A second sub-channel 422 is formed at the laterally etched portion of the first dielectric layer 31, also annularly arranged around the outer periphery of the first via 41. The first sub-channel 421 and the second sub-channel 422 form a first channel 42, meaning the first channel 42 includes both the first sub-channel 421 and the second sub-channel 422.
[0064] like Figure 13 and Figure 14 As shown in this embodiment, the side of the first sub-channel 421 exposes the second dielectric layer 33, and the bottom exposes a portion of the top wall of the sacrificial layer 32. The side of the second sub-channel 422 exposes the first dielectric layer 31, the top exposes a portion of the bottom wall of the sacrificial layer 32, and the bottom exposes a portion of the top wall of the bit line 20.
[0065] In this embodiment, the simultaneous lateral etching of the second dielectric layer 33 and the first dielectric layer 31 can simplify the process and improve production efficiency. When the materials of the second dielectric layer 33 and the first dielectric layer 31 are the same, this arrangement can also ensure the dimensional consistency of the fabrication of the first sub-channel 421 and the second sub-channel 422.
[0066] like Figure 13 and Figure 14As shown, in the embodiment of the present application, in the horizontal plane parallel to the substrate 10, the radial dimensions of the first sub-channel 421 and the second sub-channel 422 are greater than the radial dimension of the first through-hole 41. The first sub-channel 421, the first through-hole 41, and the second sub-channel 422 define the position and shape of the semiconductor column 51 to be formed (that is, the cross-sectional shape includes an H shape flipped 90 degrees, or a cross shape, or a character shape similar to "shi", or an I shape).
[0067] Optionally, in the embodiment of the present application, a wet etching method may be used to perform lateral etching on a part of the second dielectric layer 33 and a part of the first dielectric layer 31 wound around the outer periphery of the first through-hole 41. When performing lateral etching on the second dielectric layer 33 and the first dielectric layer 31 made of oxide, the sacrificial layer 32 made of polysilicon and the bit line 20 made of a conductive material will not be etched. The embodiment of the present application uses the WET (wet) etching process to define the position and shape of the channels such as an H shape flipped 90 degrees to be formed.
[0068] In some alternative embodiments of the present application, as Figure 15 and Figure 16 shown, to fabricate a plurality of semiconductor columns 51, the method includes: depositing a semiconductor material in the first channel 42 and the first through-hole 41 to form the semiconductor column 51. The semiconductor column 51 conformally covers and fills the first channel 42 and the first through-hole 41. The plurality of semiconductor columns 51, the plurality of first through-holes 41, and the plurality of first channels 42 are arranged in one-to-one correspondence, that is, one semiconductor column 51 is fabricated in each first through-hole 41 and its corresponding first channel 42.
[0069] As Figure 15 and Figure 16 shown, in the embodiment of the present application, the semiconductor column 51 covers a part of the top wall of the sacrificial layer 32, the side wall facing the semiconductor column 51 (in the direction of the first through-hole 41), and a part of the bottom wall.
[0070] Optionally, in the embodiment of the present application, the material of the semiconductor column 51 includes but is not limited to IGZO (Indium Gallium Zinc Oxide).
[0071] Optionally, as Figure 15 and Figure 16 shown, in the embodiment of the present application, after fabricating a plurality of semiconductor columns 51 and before fabricating a plurality of gate insulating layers 52 and a plurality of gates 53, it further includes: fabricating a second mask structure 102. The second mask structure 102 covers the side of the plurality of semiconductor columns 51 away from the substrate 10. During the subsequent formation of the second trench 72, removal of the sacrificial layer 32, fabrication of the gate insulating layer 52, and word line 80, the second mask structure 102 has a protective effect on the semiconductor column 51.
[0072] In some optional embodiments of this application, such as Figures 17 to 28 As shown, the sacrificial layer 32 is replaced with a plurality of gate insulating layers 52 and a plurality of gates 53 surrounding the plurality of semiconductor pillars 51, including: like Figures 17 to 19 As shown, a plurality of second trenches 72 are formed; the plurality of second trenches 72 are alternately distributed with a plurality of semiconductor pillars 51 along a first direction, and each is along a second direction (e.g., Figure 17 Extending in the middle (CC direction), the second trench 72 exposes the sacrificial layer 32 on its side and the first dielectric layer 31 at its bottom.
[0073] Optionally, such as Figure 17 and Figure 19 As shown in the embodiment of this application, the second trench 72 is along the second direction (e.g., Figure 17 The second trench 72 extends in the middle (CC direction) and is located between two adjacent semiconductor pillars 51. The second trench 72 penetrates the second dielectric layer 33 and the sacrificial layer 32, with the second dielectric layer 33 and the sacrificial layer 32 exposed on the side to facilitate subsequent removal of the sacrificial layer 32, and the first dielectric layer 31 exposed at the bottom.
[0074] Optionally, in this embodiment of the application, a dry etching process can be used to etch the second mask structure 102, the first mask structure 101, the second dielectric layer 33 and the sacrificial layer 32 to form the second trench 72.
[0075] Next, as Figure 20 and Figure 21 As shown, after removing the sacrificial layer 32, multiple second channels 43 are obtained; the multiple second channels 43 are distributed sequentially along the first direction and each extends along the second direction, exposing multiple semiconductor pillars 51 distributed sequentially along the second direction.
[0076] Optionally, such as Figure 18 As shown in the embodiment of this application, a plurality of second trenches 72 divide the sacrificial layer 32 into a plurality of sub-sacrificial layers 321. The plurality of second trenches 72 and the plurality of sub-sacrificial layers 321 are alternately arranged along a first direction, and each sub-sacrificial layer 321 is arranged along a second direction (e.g., ...). Figure 17 Extending in the middle BB direction. Each sub-sacrificial layer 321 is arranged around the second direction (e.g., ...). Figure 17 The periphery of multiple semiconductor pillars 51 arranged sequentially in the middle (BB direction). The sub-sacrificial layer 321 defines the positions of the gate insulating layer 52 and word line 80 to be formed.
[0077] Optionally, such as Figure 20 and Figure 21As shown in this embodiment, removing the sacrificial layer 32 to obtain multiple second channels 43 includes: performing lateral etching on multiple sub-sacrificial layers 321 to completely remove each sub-sacrificial layer 321, forming a second channel 43 at the corresponding position of each removed sub-sacrificial layer 321. The multiple sub-sacrificial layers 321 correspond one-to-one with the multiple second channels 43. The sides, part of the top, and part of the bottom of the second channel 43 expose the semiconductor pillar 51.
[0078] Optionally, in this embodiment, a wet etching process can be used to etch multiple sub-sacrificial layers 321 to form multiple second channels 43. At this point, the entire sacrificial layer 32 is removed.
[0079] Next, as Figures 22 to 28 As shown, multiple gate insulating layers 52 and multiple word lines 80 are sequentially fabricated to cover and fill multiple second channels 43; multiple semiconductor pillars 51 distributed sequentially along the second direction share a gate insulating layer 52 and a word line 80, and the word line 80 includes multiple gates 53 corresponding one-to-one with the multiple semiconductor pillars 51.
[0080] In this embodiment, a plurality of second trenches 72 and a plurality of second channels 43 are alternately distributed along a first direction and each extends along a second direction. The second channel 43 exposes a plurality of semiconductor pillars 51 that are spaced apart along the second direction. The gate insulating layer 52 and word lines 80 fabricated within the second channel 43 extend along the second direction in their entire length, and the gate insulating layer 52 covers the plurality of semiconductor pillars 51 exposed by the second channel 43 and distributed along the second direction. The word lines 80 cover the gate insulating layer 52 and fill the second channel 43.
[0081] The portion of word line 80 corresponding to semiconductor pillar 51 serves as gate 53. Semiconductor pillar 51, gate insulating layer 52, and gate 53 form transistor 50. Multiple transistors 50 distributed sequentially along the second direction share a single gate insulating layer 52 and a word line 80. This reduces the number of traces, which is beneficial for layout design, increases structural density, and improves practicality.
[0082] Two adjacent character lines 80 are separated by the second groove 72.
[0083] In this embodiment, lateral etching is used to define the position and shape of the semiconductor pillar 51 to be formed. Combined with subsequent etching and deposition, such as using ALD (Atomic Layer Deposition) technology, a 90-degree flipped H-shaped, T-shaped, or I-shaped semiconductor pillar is ultimately formed. This increases the area corresponding to the semiconductor pillar and the subsequently fabricated gate, improves gate control capability, and increases the on-state current (I0). on The purpose of ).
[0084] In some optional embodiments of this application, such as Figures 22 to 28 As shown, multiple gate insulating layers 52 and multiple word lines 80 are sequentially fabricated to conformally cover and fill multiple second channels 43, including: like Figure 22 and Figure 23 As shown, an initial gate insulating layer 54 is fabricated; the initial gate insulating layer 54 conformally covers a plurality of second trenches 72 and a plurality of second channels 43. The initial gate insulating layer 54 covers a plurality of semiconductor pillars 51 exposed by the second channels 43.
[0085] Optionally, in this embodiment, the material of the initial gate insulating layer 54 includes, but is not limited to, oxide.
[0086] Next, as Figure 24 and Figure 25 As shown, a second conductive layer 81 is fabricated; the second conductive layer 81 covers the initial gate insulating layer 54 and fills a plurality of second trenches 72 and a plurality of second channels 43.
[0087] Optionally, in the embodiments of this application, the material of the second conductive layer 81 includes, but is not limited to, TiN or W.
[0088] Next, as Figures 26 to 28 As shown, the initial gate insulating layer and the second conductive layer located in the plurality of second trenches 72 are removed to expose the first dielectric layer 31, and the remaining initial gate insulating layer and the second conductive layer in the second channel 43 form the gate insulating layer 52 and the word line 80, respectively.
[0089] In this embodiment, the initial gate insulating layer and the second conductive layer in the plurality of second trenches 72 are removed, thereby disconnecting the plurality of word lines 80 and the plurality of gate insulating layers 52 and avoiding electrical connection between word lines 80.
[0090] In some optional embodiments of this application, such as Figures 29 to 34 As shown, after replacing the sacrificial layer 32 with a plurality of gate insulating layers 52 and a plurality of gates 53 surrounding the plurality of semiconductor pillars 51, the method further includes: like Figure 29 As shown, a second insulating layer 62 is fabricated; the second insulating layer 62 is filled with a plurality of second trenches 72. The word lines 80 are electrically isolated from each other through the second insulating layer 62.
[0091] Optionally, in this embodiment, the material of the second insulating layer 62 includes, but is not limited to, oxide.
[0092] Next, as Figure 29 and Figure 32As shown, a third mask structure 103 is formed on the side of the second insulating layer 62 away from the substrate 10, covering the second insulating layer 62 and the second mask structure 102; and the third mask structure 103 and the second mask structure 102 are patterned to have a plurality of second vias 44 arranged in an array along a first direction and a second direction. The second vias 44 define the position and shape of the interconnect structure 90 to be formed.
[0093] Optionally, in other exemplary embodiments, the second via 44 may also be obtained by partially etching the semiconductor pillar 51 after patterning the third mask structure 103 and the second mask structure 102. For example, in the direction perpendicular to the substrate, the second via 44 may penetrate the third mask structure 103 and the second mask structure 102, exposing the semiconductor pillar 51 at the bottom of the second via 44; or the second via 44 may penetrate the third mask structure 103, the second mask structure 102 and the first mask structure 101, exposing the semiconductor pillar 51 at the bottom of the second via 44, thereby defining the position and shape of the interconnect structure 90 to be formed.
[0094] Furthermore, the position and shape of the interconnect structure 90 defined by the second via 44 further influence the structure and shape of the semiconductor pillar. For example, in the direction perpendicular to the substrate, the second via 44 penetrates the third mask structure 103 and the second mask structure 102, forming a T-shaped or I-shaped semiconductor structure in the vertical cross-section of the substrate. Alternatively, in the direction perpendicular to the substrate, the second via 44 penetrates the third mask structure 103, the second mask structure 102, and the first mask structure 101, forming a 90-degree-flipped H-shaped or I-shaped semiconductor structure in the vertical cross-section of the substrate. That is, the shape of the second via etching defines the shape of the interconnect structure, further influencing the shape of the semiconductor pillar. In other words, the third sublayer of the semiconductor pillar may or may not include the portion located in the first mask structure layer, thereby forming a T-shaped, I-shaped, or 90-degree-flipped H-shaped or I-shaped semiconductor structure.
[0095] Optionally, the material of the third mask structure 103 includes, but is not limited to, SiN. The material of the second mask structure 102 includes, but is not limited to, SiN.
[0096] Next, as Figure 33 and Figure 34 As shown, multiple interconnect structures 90 are fabricated; semiconductor pillars 51 are electrically connected to active devices through the interconnect structures 90. The multiple interconnect structures 90 and the multiple semiconductor pillars 51 are arranged in a one-to-one correspondence.
[0097] Optionally, such as Figure 33 and Figure 34As shown in the embodiment of this application, fabricating multiple interconnect structures 90 includes: fabricating at least one electrode within the second through hole 44, wherein the electrode conformally covers and fills the second through hole 44.
[0098] Optionally, such as Figure 33 and Figure 34 As shown in the embodiment of this application, the interconnect structure 90 includes a first electrode 91 and a second electrode 92 sequentially disposed in the second through hole 44, and the semiconductor pillar 51 is electrically connected to the active device through the first electrode 91 and the second electrode 92.
[0099] Optionally, in the embodiments of this application, the electrode material includes, but is not limited to, TiN or W.
[0100] It should be noted that, in the embodiments of this application, the effective device can be a capacitor or another transistor.
[0101] The semiconductor device manufacturing method provided in this application embodiment can be applied to the field of semiconductor device preparation, and further, to the field of DRAM (Dynamic Random Access Memory).
[0102] The semiconductor device manufacturing method provided in this application embodiment can be used as a 4F gate-all-around channel based method. 2 A fabrication process for semiconductor device structures with 1T1C (1 Transistor 1 Capacitor) devices and 90-degree flipped H-shaped, T-shaped, or I-shaped IGZO channels, used to manufacture novel 4F transistors with vertical and 90-degree flipped H-shaped, T-shaped, or I-shaped channels. 2 Semiconductor device structure.
[0103] It should be noted that, in the embodiments of this application, the structure of each film layer of the semiconductor device can be patterned using a patterning process to fabricate the respective film layers.
[0104] It should be noted that the "patterning process" mentioned in the embodiments of this application includes processes such as depositing film layers, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this application includes processes such as coating film layers, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods; no specific limitations are made here.
[0105] In the description of the embodiments of the present application, it should be understood that a "layer" refers to a thin film made of a certain material on a substrate by using a deposition or coating process. If the thin film does not require patterning during the entire manufacturing process, the thin film can be referred to as a layer. If the thin film also requires patterning during the entire manufacturing process, then at least one "pattern" is included in the "layer" after the patterning process.
[0106] Based on the same inventive concept, the embodiments of the present application provide a semiconductor device, and the structural schematic diagram of the semiconductor device is as shown in Figure 28 、 Figure 33 and Figure 34 The semiconductor device includes: a plurality of bit lines 20 and a plurality of transistors 50.
[0107] The plurality of bit lines 20 are disposed on one side of the substrate 10, extend along the first direction respectively, and are distributed in sequence along the second direction; the plurality of transistors 50 are arrayed; the transistor 50 includes a semiconductor column 51 and a gate insulating layer 52 and a gate 53 sequentially wound around the periphery of the semiconductor column 51, and the semiconductor column 51 is electrically connected to the bit line 20; wherein, the semiconductor column 51 includes a first sub-layer 511, a second sub-layer 512 and a third sub-layer 513 which are sequentially arranged and electrically connected in a direction away from the bit line 20; in a horizontal cross-section parallel to the substrate 10, the cross-sectional area of the second sub-layer 512 is smaller than the cross-sectional areas of the first sub-layer 511 and the third sub-layer 513 respectively.
[0108] In the embodiments of the present application, the side walls of the first sub-layer 511 and the third sub-layer 513 protrude from the side wall of the second sub-layer 512, and the first sub-layer 511, the second sub-layer 512 and the third sub-layer 513 are sequentially connected to form a cross-sectional shape including a "tu" shape, or a "shi" shape, or an H shape rotated 90 degrees, or a "gong" shape, etc. The top wall of the first sub-layer 511, the side wall of the second sub-layer 512 and the bottom wall of the third sub-layer 513 enclose an annular groove, and the gate insulating layer 52 and the gate 53 are sequentially disposed in the annular groove. The gate 53 has parts corresponding to the top wall of the first sub-layer 511, the side wall of the second sub-layer 512 and the bottom wall of the third sub-layer 513 respectively. The gate control area is large, which can effectively improve the gate control ability, effectively increase the on-state current, improve the switching ratio of the device, optimize the device structure, and improve the device stability.
[0109] In some optional embodiments of the present application, as shown in Figure 28 、 Figure 33 and Figure 34 In a vertical cross-section perpendicular to the substrate 10, the cross-sectional shape of the semiconductor column 51 includes an H shape rotated 90 degrees, a "tu" shape, a "shi" shape, or a "gong" shape.
[0110] In this embodiment, the substrate 10 carries a plurality of bit lines 20 and a plurality of transistors 50. The plurality of bit lines 20 are sequentially distributed along a second direction and each extends along a first direction. The plurality of transistors 50 are arrayed along the first and second directions. The end of the semiconductor pillar 51 of the transistor 50 facing the substrate 10 is electrically connected to the bit line 20. Since the cross-sectional shape of the semiconductor pillar 51 in the vertical section includes an H-shape, a T-shape, a 6-shape, or an I-shape with a 90-degree flip, and the gate insulating layer 52 and the gate 53 are sequentially wrapped around the periphery of the semiconductor pillar 51, the portion where the projections of the semiconductor pillar 51 and the gate 53 intersect increases, and the corresponding area increases. This can increase the gate control area of the gate 53 for the semiconductor device, effectively improve the gate control capability, effectively increase the on-state current, improve the switching ratio of the device, optimize the device structure, and improve the device stability.
[0111] In some optional embodiments of this application, such as Figure 33 As shown, several transistors 50 distributed sequentially along the first direction share a single bit line 20. This reduces the number of bit lines 20, which is beneficial for layout design, increases structural density, and improves practicality.
[0112] In some optional embodiments of this application, such as Figure 28 As shown, the gate insulating layer 52 covers the top wall of the first sub-layer 511, the side wall of the second sub-layer 512, and the bottom wall of the third sub-layer 513, and the gate 53 fills the groove formed by the gate insulating layer 52.
[0113] In some optional embodiments of this application, such as Figure 33 and Figure 34 As shown, the semiconductor device also includes multiple word lines 80, which are distributed sequentially along a first direction and each extends along a second direction. Several transistors 50 distributed sequentially along the second direction share a single word line 80. This reduces the number of word lines 80, which is beneficial for layout design, increasing structural density, and improving practicality.
[0114] In some optional embodiments of this application, such as Figure 33 and Figure 34 As shown, the semiconductor device also includes multiple interconnect structures 90, which are electrically connected to the end of the semiconductor pillar 51 away from the bit line 20. The multiple interconnect structures 90 and multiple transistors 50 are arranged in a one-to-one correspondence. The end of the semiconductor pillar 51 of the transistor 50 facing the substrate 10 is electrically connected to the bit line 20, and the end away from the bit line 20 is electrically connected to an active device (such as a capacitor or another transistor) through the corresponding interconnect structure 90.
[0115] It should be noted that the semiconductor devices in the embodiments of this application can be manufactured using the manufacturing method of the semiconductor devices provided in the embodiments of this application. Therefore, the semiconductor devices in the embodiments of this application also have the above-mentioned beneficial effects of the manufacturing method of the semiconductor devices provided in the embodiments of this application, which will not be repeated here.
[0116] In some optional embodiments of this application, the semiconductor device includes, but is not limited to, random access memory, specifically static random access memory or dynamic random access memory, and of course, flash memory, etc.
[0117] Based on the same inventive concept, embodiments of this application provide an electronic device, which includes: a semiconductor device manufactured using the semiconductor device manufacturing method described above; or, a semiconductor device as described above.
[0118] It should be noted that since the electronic devices in the embodiments of this application include semiconductor devices manufactured using the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, the electronic devices in the embodiments of this application also have the above-mentioned beneficial effects of the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, which will not be repeated here.
[0119] In some optional embodiments of this application, the electronic device includes a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include, for example, memory in a computer, and is not limited thereto.
[0120] By applying the embodiments of this application, at least the following beneficial effects can be achieved: In this embodiment of the application, a plurality of bit lines are first fabricated on the substrate. The plurality of bit lines are distributed sequentially at intervals along the second direction and each extends along the first direction.
[0121] Next, a first dielectric layer is fabricated covering multiple bit lines. The first dielectric layer fills a first trench located between any two adjacent bit lines and covers the side of the multiple bit lines away from the substrate. Any two adjacent bit lines are electrically isolated through the first dielectric layer.
[0122] Next, a sacrificial layer covering the first dielectric layer and a second dielectric layer covering the sacrificial layer are fabricated.
[0123] Next, multiple first vias are formed, each through the second dielectric layer, the sacrificial layer, and the first dielectric layer. The side of the first via exposes the sacrificial layer and the bottom exposes the bit line. The multiple first vias are arranged in an array along the first direction and the second direction.
[0124] Next, a plurality of first channels are formed corresponding to the plurality of first vias. Each first channel is arranged around the outer periphery of the corresponding first via. On a horizontal cross section parallel to the substrate, the outer contour dimension of the first channel is larger than the outer contour dimension of the first via. The first vias and the first channels define the position and shape of the semiconductor pillar to be formed. The first channel exposes part of the top wall and part of the bottom wall of the sacrificial layer.
[0125] Next, multiple semiconductor pillars are fabricated that correspond one-to-one with the multiple first vias. Each semiconductor pillar fills the corresponding first via and the corresponding first channel, such that the cross-sectional shape of the semiconductor pillar in a vertical section perpendicular to the substrate includes a T-shape, a T-shape, an H-shape rotated 90 degrees, or an I-shape. The semiconductor pillars cover part of the top wall and part of the bottom wall of the sacrificial layer exposed on the side of the first via and the sacrificial layer exposed on the first channel.
[0126] Next, the sacrificial layer is replaced with multiple gate insulating layers and multiple gates, which are sequentially wound around the periphery of the semiconductor pillar to form a transistor. The gate insulating layer is located between the semiconductor pillar and the gate, thus electrically isolating the semiconductor pillar and the gate.
[0127] In this embodiment, the position of the sacrificial layer after forming the first via and the first channel defines the position of the gate insulating layer and the gate to be formed. Since the semiconductor pillars formed within the first via and the first channel cover part of the top and bottom walls of the sacrificial layer exposed on the side of the first via and the first channel, by replacing the sacrificial layer with the gate insulating layer and the gate, not only can the semiconductor pillars and the gate have projected intersection portions corresponding to the first via, but they also have projected intersection portions corresponding to the first channel. This ensures that the semiconductor pillars cover the sidewalls, top walls, and bottom walls of the gate facing the semiconductor pillars, increasing the corresponding area of the semiconductor pillars and the gate. This increases the gate control area of the semiconductor device, effectively improving gate control capability, effectively increasing on-state current, improving the device's switching ratio, optimizing the device structure, and improving device stability.
[0128] In this embodiment, the axis of the semiconductor pillar is parallel to the axis of the first via and perpendicular to the substrate. The transistor has a channel region arranged in a direction perpendicular to the substrate. The channel region of the transistor occupies a small area in a horizontal plane parallel to the substrate. The number of transistors that can be fabricated per unit area in this horizontal plane is increased, thereby improving the density and integration of the semiconductor device and achieving miniaturization.
[0129] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0130] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: Multiple bit lines are fabricated on the substrate; The plurality of bit lines extend along a first direction and are sequentially distributed along a second direction, wherein the first direction and the second direction intersect and are both parallel to the substrate; Fabricate a first dielectric layer covering multiple of the bit lines; A sacrificial layer and a second dielectric layer covering the first dielectric layer are fabricated sequentially. A plurality of first vias are formed, penetrating the second dielectric layer, the sacrificial layer, and the first dielectric layer, and distributed in an array; the bottom of the first vias exposes the bit line; A portion of the second dielectric layer and a portion of the first dielectric layer surrounding the first through hole are removed to form a first channel; Multiple semiconductor pillars are fabricated; the semiconductor pillars correspondingly fill the first through hole and the first channel surrounding the outer periphery of the first through hole; The sacrificial layer is replaced with a plurality of gate insulating layers and a plurality of gates surrounding the plurality of semiconductor pillars to obtain a plurality of transistors.
2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before fabricating multiple bit lines on the substrate, the following steps are also included: A first insulating layer is formed on the substrate; And, the fabrication of multiple bit lines on the substrate includes: A first conductive layer is fabricated; the first conductive layer covers the first insulating layer; The first conductive layer is patterned to form multiple first trenches; the multiple first trenches extend along the first direction and are distributed at intervals along the second direction, thereby dividing the first conductive layer into multiple bit lines.
3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, Fabricating a first dielectric layer covering the plurality of said bit lines includes: An oxide layer is deposited to obtain the first dielectric layer; the first dielectric layer fills the plurality of the first trenches and covers the plurality of the bit lines; And, sequentially fabricating a sacrificial layer and a second dielectric layer covering the first dielectric layer, including: Polysilicon and oxide are deposited sequentially to obtain the sacrificial layer and the second dielectric layer; the sacrificial layer covers the first dielectric layer, and the second dielectric layer covers the sacrificial layer.
4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that, Removing a portion of the second dielectric layer and a portion of the first dielectric layer surrounding the first through-hole to form a first channel includes: Through the first through hole, a portion of the second dielectric layer and a portion of the first dielectric layer surrounding the first through hole are simultaneously etched laterally to form a first sub-channel and a second sub-channel that are annularly surrounding the first through hole, thus obtaining the first channel.
5. A method for manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that, Replacing the sacrificial layer with a plurality of gate insulating layers and a plurality of gates surrounding the plurality of semiconductor pillars includes: Multiple second trenches are formed; the multiple second trenches are alternately distributed with the multiple semiconductor pillars along the first direction and each extends along the second direction, the side of the second trench exposes the sacrificial layer, and the bottom exposes the first dielectric layer; The sacrificial layer is removed to obtain a plurality of second channels; the plurality of second channels are distributed sequentially along the first direction and each extends along the second direction, and the second channels expose a plurality of semiconductor pillars distributed sequentially along the second direction; Multiple gate insulating layers and multiple word lines are sequentially fabricated to cover and fill multiple second channels in a conformal manner; multiple semiconductor pillars distributed sequentially along the second direction share a gate insulating layer and a word line, and the word line includes multiple gates corresponding one-to-one with the multiple semiconductor pillars.
6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, Multiple gate insulating layers and multiple word lines are sequentially fabricated to conformally cover and fill multiple second channels, including: An initial gate insulating layer is fabricated; the initial gate insulating layer conformally covers a plurality of second trenches and a plurality of second channels; A second conductive layer is fabricated; the second conductive layer covers the initial gate insulating layer and fills a plurality of second trenches and a plurality of second channels; The initial gate insulating layer and the second conductive layer located in the plurality of second trenches are removed to expose the first dielectric layer, and the remaining initial gate insulating layer and the second conductive layer in the second channel form the gate insulating layer and the word line, respectively.
7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, After replacing the sacrificial layer with a plurality of gate insulating layers and a plurality of gates surrounding the plurality of semiconductor pillars, the method further includes: A second insulating layer is fabricated; the second insulating layer fills multiple of the second trenches; Multiple interconnect structures are fabricated; the semiconductor pillars are electrically connected to active devices through the interconnect structures.
8. A semiconductor device, characterized in that, include: Multiple bit lines are disposed on one side of the substrate, extending along a first direction and distributed sequentially along a second direction; Multiple transistors are arranged in an array; each transistor includes a semiconductor pillar and a gate insulating layer and a gate sequentially wound around the periphery of the semiconductor pillar, and the semiconductor pillar is electrically connected to the bit line; The semiconductor pillar includes a first sublayer, a second sublayer, and a third sublayer arranged sequentially along a direction away from the bit line. In a horizontal cross-section parallel to the substrate, the cross-sectional area of the second sublayer is smaller than the cross-sectional areas of the first sublayer and the third sublayer.
9. The semiconductor device according to claim 8, characterized in that, Includes at least one of the following: In a vertical cross-section perpendicular to the substrate, the cross-sectional shape of the semiconductor pillar includes a T-shape, a 6-shape, an H-shape rotated 90 degrees, or an I-shape; The gate insulating layer covers the top wall of the first sub-layer, the side wall of the second sub-layer, and the bottom wall of the third sub-layer, and the gate is filled in the groove formed by the gate insulating layer.
10. The semiconductor device according to claim 8, characterized in that, Includes at least one of the following: A plurality of transistors distributed sequentially along the first direction share a single bit line; The semiconductor device further includes a plurality of word lines, which are distributed sequentially along the first direction and each extends along the second direction. A plurality of transistors distributed sequentially along the second direction share a single word line. The semiconductor device further includes a plurality of interconnect structures electrically connected to the end of the semiconductor pillar away from the bit line.
11. An electronic device, characterized in that, include: A semiconductor device manufactured using the manufacturing method of any one of claims 1 to 7; or, The semiconductor device as described in any one of claims 8 to 10.