Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the structure comprising: a substrate; a channel layer structure suspended above the substrate, the channel layer structure comprising one or more spaced channel layers; a gate structure located on the substrate and across the channel layer structure, the gate structure surrounding the channel layers along a gate structure extending direction, wherein the gate structure located between adjacent channel layers and between the channel layer structure and the substrate is a stacked gate; source-drain doped layers located on the substrate on both sides of the gate structure and in contact with end portions of the channel layer structure; inner side walls located on sidewalls of the stacked gate, the stacked gate being spaced apart from the source-drain doped layers by the inner side walls; and an isolation layer located between the source-drain doped layers and the substrate, the isolation layer being in an integral structure with the inner side walls. The present application is advantageous in improving the working performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has stronger control over the channel and can better suppress short-channel effects. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to ensuring the working performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate; a channel layer structure suspended above the substrate, the channel layer structure including one or more spaced channel layers; a gate structure located on the substrate and spanning the channel layer structure, the gate structure surrounding the channel layer along the extension direction of the gate structure, wherein a gate structure located between adjacent channel layers and between the channel layer structure and the substrate serves as a stacked gate; source / drain doped layers located on the substrate on both sides of the gate structure and in contact with the ends of the channel layer structure; inner sidewalls located on the sidewalls of the stacked gate, the stacked gate and the source / drain doped layers being separated by the inner sidewalls; and an isolation layer located between the source / drain doped layers and the substrate, the isolation layer and the inner sidewalls being an integral structure.

[0006] Optionally, the substrate includes a substrate and a bottom fin protruding from the substrate; a channel layer structure is suspended above the bottom fin; and an insulating layer covers the sidewalls of the bottom fin and the top of the substrate.

[0007] Optionally, the insulating layer extends to the top of the bottom fin and contacts the innermost sidewall.

[0008] Optionally, the thickness of the insulating layer is to

[0009] Optionally, the material of the inner wall includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride; the material of the insulating layer includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride.

[0010] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, on which a stacked structure is formed, the stacked structure including sacrificial layers and channel layers alternately stacked longitudinally from bottom to top, and a dummy gate structure spanning the stacked structure is also formed on the substrate, the dummy gate structure covering the sidewalls and top of the stacked structure; removing a portion of the width of the sacrificial layer from the sidewalls of the stacked structure along the extension direction of the channel layers to form a groove surrounded by longitudinally adjacent channel layers; forming an inner wall located in the groove and an isolation layer covering the top surface of the substrate, the isolation layer being integral with the inner wall. Structure: Source and drain doped layers are formed on the isolation layers on the substrates on both sides of the dummy gate structure, and the source and drain doped layers are in contact with the ends of the stacked structure; the dummy gate structure is removed to form a gate opening; the sacrificial layer in the stacked structure is removed to form a through trench, and the remaining spaced-apart channel layers constitute a channel layer structure, with the through trench exposed on the inner sidewall; a gate structure spanning the channel layer structure is formed in the gate opening and the through trench, and the gate structure surrounds the channel layer along the extension direction of the gate structure, with the gate structures between adjacent channel layers and between the channel layer structure and the substrate as the stacked gate, and the stacked gate and the source and drain doped layers are separated by the inner sidewall.

[0011] Optionally, the steps of forming the inner sidewall located in the groove and the insulating layer covering the top surface of the substrate include: forming a sidewall material layer covering the top and sidewalls of the pseudo-grid structure, covering the sidewalls of the stacked structure, filling the groove, and extending to cover the substrate surfaces on both sides of the pseudo-grid structure; removing the sidewall material layer covering the top and sidewalls of the pseudo-grid structure and the sidewalls of the stacked structure, retaining the sidewall material layer filling the groove as the inner sidewall, and retaining the sidewall material layer extending to cover the substrate surfaces on both sides of the pseudo-grid structure as the insulating layer.

[0012] Optionally, an atomic layer deposition process is used to form a sidewall material layer that covers the top and sidewalls of the pseudo-gate structure, covers the sidewalls of the stacked structure, fills the grooves, and extends to cover the substrate surface on both sides of the pseudo-gate structure.

[0013] Optionally, a dry etching process can be used to remove the sidewall material layer covering the top and sidewalls of the pseudo-gate structure, as well as the sidewalls of the stacked structure.

[0014] Optionally, in the step of forming a sidewall material layer that covers the top and sidewalls of the pseudo-gate structure, covers the sidewalls of the stacked structure, fills the grooves, and extends to cover the substrate surfaces on both sides of the pseudo-gate structure, the thickness of the sidewall material layer is [missing information]. to

[0015] Optionally, in the step of forming a sidewall material layer that covers the top and sidewalls of the pseudo-gate structure, covers the sidewalls of the stacked structure, fills the grooves, and extends to cover the substrate surfaces on both sides of the pseudo-gate structure, the material of the sidewall material layer includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride.

[0016] Optionally, in the step of providing the substrate, the substrate includes a substrate and a bottom fin protruding from the substrate, and the stacked structure is located on the bottom fin; in the step of forming a sidewall material layer that covers the top and sidewalls of the pseudo-gate structure, covers the sidewalls of the stacked structure, fills the groove, and extends to cover the substrate surface on both sides of the pseudo-gate structure, the sidewall material layer covers the sidewalls of the bottom fin and the top of the substrate; in the step of removing the sidewall material layer that covers the top and sidewalls of the pseudo-gate structure and covers the sidewalls of the stacked structure, retaining the sidewall material layer that fills the groove as the inner sidewall, and retaining the sidewall material layer that extends to cover the substrate surface on both sides of the pseudo-gate structure as an isolation layer, the sidewall material layer that covers the bottom fin and the top of the substrate is retained as an isolation layer.

[0017] Optionally, the step of removing the sidewall material layer covering the top and sidewalls of the pseudo-gate structure and the sidewalls of the stacked structure, retaining the sidewall material layer filling the groove as the inner sidewall, and retaining the sidewall material layer extending to cover the substrate surface on both sides of the pseudo-gate structure as the isolation layer includes: forming a protective layer covering the sidewall material layer on the substrate and the sidewall material layer covering the sidewalls of the bottom fin; using the protective layer as an etching mask, removing the sidewalls of the stacked structure exposed by the protective layer, as well as the sidewalls and top of the pseudo-gate structure, retaining the sidewall material layer filling the groove as the inner sidewall, and retaining the sidewall material layer covered by the protective layer as the isolation layer.

[0018] Optionally, the step of forming a protective layer covering the sidewall material layer on the substrate and covering the sidewall of the bottom fin includes: forming a protective material layer covering the sidewall material layer on the substrate; removing a portion of the thickness of the protective material layer, leaving the remaining thickness of the protective material layer covering the sidewall material layer on the substrate and covering the sidewall of the bottom fin as a protective layer.

[0019] Optionally, in the step of forming a protective layer that covers the sidewall material layer on the substrate and the sidewall material layer covering the bottom fin sidewall, the top surface of the protective layer is higher than the top surface of the bottom fin and lower than the bottom surface of the bottommost channel layer.

[0020] Optionally, in the step of forming a protective layer covering the sidewall material layer on the substrate and covering the sidewall of the bottom fin, the material of the protective layer includes spin-coated carbon.

[0021] Optionally, after removing the sidewalls of the stacked structure exposed by the protective layer, as well as the sidewall material layers of the pseudo-gate structure and the top, using the protective layer as an etching mask, the method further includes: removing the protective layer.

[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0023] In the semiconductor structure provided by this invention, the inner sidewall is located on the sidewall of the stacked gate, the stacked gate and the source / drain doped layers are separated by the inner sidewall, and the isolation layer is located between the source / drain doped layers and the substrate. The isolation layer and the inner sidewall are an integral structure. In this invention, the isolation layer and the inner sidewall are an integral structure, that is, the isolation layer can be formed together by the formation step of the inner sidewall, so that the source / drain doped layers are isolated from the substrate. When the semiconductor structure is turned on, it is beneficial to reduce the parasitic capacitance of the substrate below the channel layer structure, thereby reducing the probability of leakage caused by the substrate below the channel layer structure being turned on, and thus helping to ensure the working performance of the semiconductor structure.

[0024] In the formation method provided by the embodiments of the present invention, an inner wall located in the groove and an isolation layer covering the top surface of the substrate are formed. The isolation layer and the inner wall are an integral structure. Source and drain doped layers are formed on the isolation layer on both sides of the substrate of the pseudo-gate structure. The source and drain doped layers are in contact with the ends of the stacked structure. In the embodiments of the present invention, the isolation layer and the inner wall are an integral structure, that is, the isolation layer can be formed together with the formation step of the inner wall, so that the source and drain doped layers are isolated from the substrate. When the semiconductor structure is turned on, it is beneficial to reduce the parasitic capacitance of the substrate below the channel layer structure, thereby reducing the probability of leakage caused by the substrate below the channel layer structure being turned on, and thus helping to ensure the working performance of the semiconductor structure. Attached Figure Description

[0025] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0026] Figure 3 This is a schematic diagram of a corresponding embodiment of the semiconductor structure of the present invention;

[0027] Figures 4 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0028] The performance of current semiconductor structures needs to be guaranteed. This paper analyzes the reasons for this performance guarantee in conjunction with a semiconductor structure formation method.

[0029] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0030] refer to Figure 1 A substrate 10 is provided, on which a laminated structure 20 is formed, the laminated structure 20 including components along the longitudinal direction (e.g., ...). Figure 1 (As shown in the Z direction) Sacrificial layers 21 and channel layers 22 are stacked alternately from bottom to top. A pseudo-gate structure 30 is also formed on the substrate 10, which spans the stacked structure 20. The pseudo-gate structure 30 covers the sidewalls and top of the stacked structure 30. The sidewalls of the sacrificial layers 21 at the ends of the stacked structure 20 are formed with inner sidewalls 50.

[0031] refer to Figure 2 Source and drain doped layers 40 are formed on the substrates 10 on both sides of the pseudo-gate structure 30, which are in contact with the ends of the stacked structure 20.

[0032] Continue to refer to Figure 2 Remove the pseudo-gate structure 30 and the sacrificial layer 21, and retain one or more spaced-apart channel layers 22 as channel layer structure 24; form a gate structure 60 that spans the channel layer structure 24, and the gate structure 60 surrounds the channel layer 22 along the extension direction of the gate structure 60.

[0033] If the source / drain doped layer 40 is in contact with the substrate 10, parasitic capacitance may be generated on the substrate 10 below the channel layer structure 24 when the semiconductor structure is turned on, resulting in leakage and affecting the working performance of the semiconductor structure.

[0034] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, forming a stacked structure on the substrate, the stacked structure including sacrificial layers and channel layers alternately stacked longitudinally from bottom to top, and further forming a dummy gate structure spanning the stacked structure, the dummy gate structure covering the sidewalls and top of the stacked structure; removing a portion of the sacrificial layer from the sidewalls of the stacked structure along the extending direction of the channel layers to form a groove surrounded by longitudinally adjacent channel layers; forming an inner wall located in the groove and an isolation layer covering the top surface of the substrate, the isolation layer and the inner wall being... An integral structure is formed; source and drain doped layers are formed on the isolation layers on the substrates on both sides of the dummy gate structure, and the source and drain doped layers are in contact with the ends of the stacked structure; the dummy gate structure is removed to form a gate opening; the sacrificial layer in the stacked structure is removed to form a through trench, and the remaining multiple channel layers spaced apart form a channel layer structure, with the through trench exposed on the inner sidewall; a gate structure spanning the channel layer structure is formed in the gate opening and the through trench, and the gate structure surrounds the channel layer along the extension direction of the gate structure, with the gate structures between adjacent channel layers and between the channel layer structure and the substrate as the stacked gate, and the stacked gate and the source and drain doped layers are spaced apart by the inner sidewall.

[0035] In this embodiment of the invention, the isolation layer and the inner sidewall are an integral structure, that is, the isolation layer can be formed together with the inner sidewall formation step, so that the source and drain doped layers are isolated from the substrate. When the semiconductor structure is turned on, it is beneficial to reduce the parasitic capacitance of the substrate below the channel layer structure, thereby reducing the probability of leakage caused by the substrate below the channel layer structure being turned on, and thus helping to ensure the working performance of the semiconductor structure.

[0036] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] Figure 3 This is a schematic diagram of a semiconductor structure according to one embodiment of the present invention.

[0038] refer to Figure 3 The semiconductor structure includes: a substrate 100; and a channel layer structure 240, suspended above the substrate 100, in the vertical direction (e.g., ...). Figure 3In the Z-direction shown, the channel layer structure 240 includes one or more spaced channel layers 220; a gate structure 500 located on the substrate 100 and spanning the channel layer structure 240, the gate structure 500 surrounding the channel layer 220 along the extending direction of the gate structure 500, wherein the gate structure 500 located between adjacent channel layers 220 and between the channel layer structure 240 and the substrate 100 serves as a stacked gate 510; source / drain doped layers 400 located on the substrate 100 on both sides of the gate structure 500 and in contact with the ends of the channel layer structure 240; inner sidewalls 310 located on the sidewalls of the stacked gate 510, the stacked gate 510 and the source / drain doped layers 400 being spaced apart by the inner sidewalls 310; and an isolation layer 320 located between the source / drain doped layers 400 and the substrate 100, the isolation layer 320 and the inner sidewalls 310 being an integral structure.

[0039] Substrate 100 provides the basis for the process operations of forming semiconductor structures. These semiconductor structures include gate-all-around (GAA) transistors and forksheet transistors.

[0040] In this embodiment, the substrate 100 includes a substrate 110 and a bottom fin 120 protruding from the substrate 110.

[0041] The substrate 110 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0042] In this embodiment, the bottom fin 120 and the substrate 110 are an integral structure, and the bottom fin 120 protrudes from the substrate 110, increasing the formation space of the source and drain doped layer 400.

[0043] The channel layer structure 240 includes one or more longitudinally spaced channel layers 220, which serve as channels for transistors.

[0044] Accordingly, in this embodiment, the channel layer structure 240 is suspended above the bottom fin 120.

[0045] In this embodiment, the material of the channel layer 220 includes silicon, germanium, silicon germanide, or a group III-V semiconductor material. As an example, the material of the channel layer 220 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0046] The gate structure 500 is used to control the opening and closing of the transistor's channel.

[0047] The gate structure 500 surrounds and covers the channel layer 220. Therefore, the top, bottom and sidewalls of the channel layer 220 can all serve as channels, increasing the area in the channel layer 220 used as channels, thereby increasing the operating current of the semiconductor structure.

[0048] In this embodiment, the gate structure 500 includes a gate dielectric layer surrounding the channel layer 220 along the extending direction of the gate structure 500, and a gate electrode layer located on the gate dielectric layer.

[0049] The gate dielectric layer is used to isolate the gate electrode layer from the channel layer 220, and the gate electrode layer from the substrate 100.

[0050] The gate dielectric layer material includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0051] It should be noted that the gate dielectric layer may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel layer 220. Specifically, the material of the gate oxide layer can be silicon oxide.

[0052] In this embodiment, the gate structure 500 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0053] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0054] In other embodiments, the gate electrode layer may also consist of only the work function layer.

[0055] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0056] The source / drain doped layer 400 is used as the source or drain region of the transistor. Specifically, the doping type of the source / drain doped layer 400 is the same as the channel conductivity type of the corresponding transistor.

[0057] The doping type of the source / drain doped layer 400 is the same as the channel conductivity type of the corresponding transistor. Specifically, when the substrate 100 is used to form an NMOS transistor, the doping ions in the source / drain doped layer 400 are N-type ions, including P ions, As ions, or Sb ions; when the substrate 100 is used to form a PMOS transistor, the doping ions in the source / drain doped layer 400 are P-type ions, including B ions, Ga ions, or In ions.

[0058] The inner wall 310 serves to isolate the gate structure 500 and the source / drain doped layer 400, thereby reducing the parasitic capacitance between the gate structure 500 and the source / drain doped layer 400.

[0059] In this embodiment, the material of the inner wall 310 includes one or more of silicon nitride, silicon oxide, silicon carbon oxynitride, and silicon carbonitride.

[0060] The isolation layer 320 is used to isolate the source / drain doped layer 400 from the substrate 100.

[0061] The isolation layer 320 and the inner wall 310 are an integral structure, meaning that the isolation layer 320 and the inner wall 310 are formed in the same step.

[0062] In this embodiment, the isolation layer 320 and the inner sidewall 310 are an integral structure, that is, the isolation layer can be formed together by the formation step of the inner sidewall 310, so that the source and drain doped layer 400 is isolated from the substrate 100. When the semiconductor structure is turned on, it is beneficial to reduce the parasitic capacitance of the substrate 100 below the channel layer structure 240, thereby reducing the probability of leakage caused by the substrate 100 below the channel layer structure 240 being turned on, and thus helping to ensure the working performance of the semiconductor structure.

[0063] Accordingly, in this embodiment, the isolation layer 320 covers the sidewall of the bottom fin 120 and the top of the substrate 110 to isolate the source / drain doped layer 400 from the bottom fin 120 and from the substrate 110.

[0064] In this embodiment, the stacked grids 510 are spaced apart in the longitudinal direction, and correspondingly, the inner sidewalls 310 are spaced apart in the longitudinal direction. Meanwhile, the insulating layer 320 covers the sidewall of the bottom fin 120. Therefore, the insulating layer 320 extends to the top of the bottom fin 120 and contacts the bottom inner sidewall 310 to form an integral structure.

[0065] In this embodiment, the thickness of the insulating layer 320 is to

[0066] The thickness of the insulating layer 320 is to This ensures the isolation performance between the source / drain doped layer 400 and the substrate 100, and makes it easy to form the isolation layer 320 and the inner sidewall 310 in the same step.

[0067] Accordingly, in this embodiment, the material of the insulating layer 320 includes one or more of silicon nitride, silicon oxide, silicon carbon oxynitride, and silicon carbonitride.

[0068] Using one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride to form the insulating layer 320 is beneficial for obtaining better insulating performance.

[0069] Figures 4 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0070] refer to Figure 4 A substrate 100 is provided, on which a laminated structure 200 is formed, the laminated structure 200 including components along the longitudinal direction (e.g., ...). Figure 4 (As shown in the Z-direction) Sacrificial layers 210 and channel layers 220 are stacked alternately from bottom to top. A pseudo-gate structure 140 is also formed on the substrate 100, which spans the stacked structure 200 and covers the sidewalls and top of the stacked structure 200.

[0071] The substrate 100 provides the basis for the process operation of forming semiconductor structures. These semiconductor structures include fully enclosed gate transistors and fork-type gate transistors.

[0072] In this embodiment, in the step of providing the substrate 100, the substrate 100 includes a substrate 110 and a bottom fin 120 protruding from the substrate 110, and the stacked structure 200 is located on the bottom fin 120.

[0073] The substrate 110 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0074] In this embodiment, the bottom fin 120 and the substrate 110 are an integral structure, and the bottom fin 120 protrudes from the substrate 110, increasing the space for the formation of subsequent source and drain doped layers.

[0075] In the stacked structure 200, the channel layer 220 serves as the channel of the semiconductor structure, and the sacrificial layer 210 provides a process basis for the subsequent floating arrangement of the channel layer 220 and also occupies space for the gate structure to be formed later. In subsequent processes, the sacrificial layer 210 is removed, leaving the channel layer 220 floating, and a gate structure is formed between the channel layer 220 and the substrate 100, and between adjacent channel layers 220.

[0076] The surface covered by the gate structure in the channel layer 220 is used as a channel. In this embodiment, the top, bottom and sidewalls of the channel layer 220 can all be used as channels, which increases the area used as a channel in the channel layer 220, thereby increasing the operating current of the semiconductor structure.

[0077] In this embodiment, during the step of providing the substrate 100, the material of the channel layer 220 includes silicon, germanium, silicon germanide, or a group III-V semiconductor material. As an example, the material of the channel layer 220 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0078] In this embodiment, during the step of providing the substrate 100, the material of the sacrificial layer 210 includes silicon germanide.

[0079] Silicon germanide has a lower etch resistance than silicon, and silicon germanide can form a larger etch selectivity with silicon. Therefore, during the subsequent removal of the sacrificial layer 210, the sacrificial layer 210 is easier to remove, and the damage to the channel layer 220 can be reduced when removing the sacrificial layer 210.

[0080] In other embodiments, the sacrificial layer can be selected from materials that have an etch selectivity ratio suitable for the channel layer, so as to reduce damage to the channel layer when the sacrificial layer is removed subsequently.

[0081] The pseudo-gate structure 140 is used to reserve space for the subsequent formation of the gate structure.

[0082] In this embodiment, the pseudo-gate structure 140 is a stacked structure, including a pseudo-gate oxide layer (not shown) and a pseudo-gate layer (not shown) covering the pseudo-gate oxide layer.

[0083] As an example, in this embodiment, the material of the pseudo-gate oxide layer is silicon oxide, and the material of the pseudo-gate layer is polycrystalline silicon.

[0084] refer to Figure 5 , consisting of a 200-sided wall of a stacked structure, along the extension direction of the channel layer (e.g. Figure 5 (As shown in the X direction), a portion of the sacrificial layer 210 is removed to form a groove 230 surrounded by longitudinally adjacent channel layers 220.

[0085] The groove 230 is used to provide space for the subsequent formation of the inner sidewall.

[0086] Reference Figures 6 to 8 An inner wall 310 is formed in the groove 230, and an isolation layer 320 covers the top surface of the base 100. The isolation layer 320 and the inner wall 310 are an integral structure.

[0087] The inner wall 310 serves to isolate the gate structure 500 and the source / drain doped layer 400, thereby reducing the parasitic capacitance between the gate structure 500 and the source / drain doped layer 400.

[0088] In this embodiment, in the step of forming the inner wall 310 located in the groove 230, the material of the inner wall 310 includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride.

[0089] The isolation layer 320 is used to isolate the subsequently formed source / drain doped layers from the substrate 100.

[0090] The isolation layer 320 and the inner wall 310 are an integral structure, meaning that the isolation layer 320 and the inner wall 310 are formed in the same step.

[0091] In this embodiment, the isolation layer 320 and the inner sidewall 310 are an integral structure, that is, the isolation layer can be formed together with the formation step of the inner sidewall 310, so that the source and drain doped layers formed subsequently are isolated from the substrate 100. When the semiconductor structure is turned on, it is beneficial to reduce the parasitic capacitance of the substrate 100 below the channel layer structure formed subsequently, thereby reducing the probability of leakage caused by the substrate 100 below the channel layer structure being turned on, and thus helping to ensure the working performance of the semiconductor structure.

[0092] Accordingly, in this embodiment, in the step of forming the insulating layer 320 covering the top surface of the substrate 100, the material of the insulating layer 320 includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride.

[0093] Specifically, refer to Figure 6 The steps of forming an inner sidewall 310 located in the groove 230 and an insulating layer 320 covering the top surface of the substrate 100 include: forming a sidewall material layer 300 covering the top and sidewalls of the pseudo-gate structure 140, covering the sidewalls of the laminated structure 200, filling the groove 230, and extending to cover the surfaces of the substrate 100 on both sides of the pseudo-gate structure 140.

[0094] The sidewall material layer 300 is used to form the inner sidewall 310 and also to form the insulation layer 320.

[0095] Specifically, in this embodiment, in the step of forming a sidewall material layer 300 that covers the top and sidewalls of the pseudo-gate structure 140, covers the sidewalls of the stacked structure 200, fills the groove 230, and extends to cover the surface of the substrate 100 on both sides of the pseudo-gate structure 140, the sidewall material layer 300 covers the sidewalls of the bottom fin 120 and the top of the substrate 110.

[0096] In this embodiment, an atomic layer deposition process is used to form a sidewall material layer 300 that covers the top and sidewalls of the pseudo-gate structure 140, covers the sidewalls of the stacked structure 200, fills the groove 230, and extends to cover the surface of the substrate 100 on both sides of the pseudo-gate structure 140.

[0097] The sidewall material layer 300 formed by atomic layer deposition has good thickness uniformity and good step coverage capability, which enables the sidewall material layer 300 to well preserve the top and sidewalls of the conformal pseudo-gate structure 140, cover the sidewalls of the stacked structure 200, extend to cover the surface of the substrate 100 on both sides of the pseudo-gate structure 140, and fill the groove 230 well. This is conducive to the formation of good thickness uniformity of the inner sidewall 310 and the insulating layer 320.

[0098] In this embodiment, in the step of forming a sidewall material layer 300 that covers the top and sidewalls of the pseudo-gate structure 140, covers the sidewalls of the stacked structure 200, fills the groove 230, and extends to cover the surfaces of the substrate 100 on both sides of the pseudo-gate structure 140, the thickness of the sidewall material layer 300 is... to

[0099] The thickness of the sidewall material layer 300 is to This ensures that the thickness of the formed isolation layer 320 is sufficient to guarantee its isolation performance, and also helps to reduce the difficulty of the subsequent process of removing the sidewall material layer 300 covering the top and sidewalls of the pseudo-gate structure 140 and the sidewalls of the stacked structure 200.

[0100] Accordingly, in this embodiment, in the step of forming a sidewall material layer 300 that covers the top and sidewalls of the pseudo-gate structure 140, covers the sidewalls of the stacked structure 200, fills the groove 230, and extends to cover the surface of the substrate 100 on both sides of the pseudo-gate structure 140, the material of the sidewall material layer 300 includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride.

[0101] Accordingly, in this embodiment, the isolation layer 320 covers the sidewall of the bottom fin 120 and the top of the substrate 110 to isolate the source / drain doped layer 400 from the bottom fin 120 and from the substrate 110.

[0102] Reference Figure 7 and Figure 8 Remove the sidewall material layer 300 covering the top and sidewalls of the pseudo-gate structure 140 and the sidewalls of the stacked structure 200, retain the sidewall material layer 300 filling the groove 230 as the inner sidewall 310, and retain the sidewall material layer 300 extending to cover the surface of the base 100 on both sides of the pseudo-gate structure 140 as the insulating layer 320.

[0103] The sidewall material layer 300 covering the top and sidewalls of the pseudo-gate structure 140 and the sidewalls of the stacked structure 200 is removed to form the inner sidewall 310 and the isolation layer 320, and to prepare for the subsequent formation of the source and drain doped layers.

[0104] Specifically, in this embodiment, in the steps of removing the sidewall material layer 300 covering the top and sidewalls of the pseudo-gate structure 140 and the sidewalls of the stacked structure 200, retaining the sidewall material layer 300 filling the groove 230 as the inner sidewall 310, and retaining the sidewall material layer 300 extending to cover the surface of the substrate 100 on both sides of the pseudo-gate structure 140 as the insulating layer 320, the sidewall material layer 300 covering the sidewalls of the bottom fin 120 and the top of the substrate 110 is retained as the insulating layer 320.

[0105] In this embodiment, a dry etching process is used to remove the sidewall material layer 300 that covers the top and sidewalls of the pseudo-gate structure 140 and the sidewalls of the stacked structure 200.

[0106] Dry etching process has the characteristics of anisotropic etching. Therefore, by selecting dry etching process, the etching is more directional, which is beneficial to reduce damage to the trench layer 220 and improve the dimensional accuracy of the inner sidewall 310 and the isolation layer 320.

[0107] Accordingly, in this embodiment, in the step of retaining the sidewall material layer 300 covering the bottom fin 120 and the top of the substrate 110 as the insulating layer 320, the thickness of the insulating layer 320 is... to

[0108] Specifically, refer to Figure 7 The steps of removing the sidewall material layer 300 covering the top and sidewalls of the pseudo-gate structure 140 and the sidewalls of the stacked structure 200, retaining the sidewall material layer 300 filling the groove 230 as the inner sidewall 310, and retaining the sidewall material layer 300 extending to cover the surface of the substrate 100 on both sides of the pseudo-gate structure 140 as the insulating layer 320 include: forming a protective layer 130 covering the sidewall material layer 300 on the substrate 110 and covering the sidewalls of the bottom fin 120.

[0109] The protective layer 130 is used to protect the sidewall material layer 300 covering the substrate 110 and the sidewall of the bottom fin 120 during the removal of the sidewall material layer 300 covering the top and sidewalls of the pseudo gate structure 140 and the sidewalls of the stacked structure 200, so as to retain the sidewall material layer 300 covering the substrate 110 and the sidewall of the bottom fin 120 as the isolation layer 320.

[0110] In this embodiment, in the step of forming a protective layer 130 covering the sidewall material layer 300 on the substrate 110 and covering the sidewall of the bottom fin 120, the top surface of the protective layer 130 is higher than the top surface of the bottom fin 120 and lower than the bottom surface of the bottommost channel layer 220.

[0111] The top surface of the protective layer 130 is higher than the top surface of the bottom fin 120 and lower than the bottom surface of the bottom channel layer 220. This allows the protective layer 130 to cover both the sidewall material layer 300 covering the surface of the substrate 110 and the sidewall of the bottom fin 120, thus retaining it as the isolation layer 320. Furthermore, it also allows the sidewall of the channel layer 220 to be exposed when the sidewall material layer 300 is removed from the protective layer 130, providing a better process basis for the subsequent formation of source / drain doped layers on the sidewall of the channel layer 220.

[0112] In this embodiment, in the step of forming a protective layer 130 covering the sidewall material layer 300 on the substrate 110 and covering the sidewall of the bottom fin 120, the material of the protective layer 130 includes spin-coated carbon (SOC).

[0113] Spin-coated carbon is easy to control in thickness, has a simple forming process, and is easy to remove.

[0114] Specifically, in this embodiment, the step of forming a protective layer 130 covering the sidewall material layer 300 on the substrate 110 and covering the sidewall of the bottom fin 120 includes: forming a protective material layer (not shown) covering the sidewall material layer 300 on the substrate 100.

[0115] A protective material layer is used to form protective layer 130.

[0116] Accordingly, in this embodiment, in the step of forming a protective material layer covering the sidewall material layer 300 on the substrate 100, the material of the protective material layer is spin-coated carbon.

[0117] In this embodiment, a portion of the protective material layer is removed, and the remaining protective material layer covers the sidewall material layer 300 on the substrate 110 and the sidewall of the bottom fin 120, serving as the protective layer 130.

[0118] Remove a portion of the protective material layer so that the remaining protective material layer reaches the thickness required for the process.

[0119] In this embodiment, a protective material layer is formed first, and then the protective material layer is etched back to form the protective layer 130, which is beneficial to obtaining a protective layer 130 with high thickness dimensional accuracy.

[0120] refer to Figure 8Using the protective layer 130 as an etching mask, the sidewalls of the stacked structure 200 exposed by the protective layer 130, as well as the sidewalls and top of the pseudo-gate structure 140, are removed. The sidewall material layer 300 filling the groove 230 is retained as the inner sidewall 310, and the sidewall material layer 300 covered by the protective layer 130 is retained as the isolation layer 320.

[0121] Accordingly, in this embodiment, in the step of retaining the sidewall material layer 300 covered by the protective layer 130 as the insulating layer 320, the insulating layer 320 extends to the top of the bottom fin 120 and contacts the bottom inner sidewall 310 to form an integral structure.

[0122] In this embodiment, the protective layer 130 is used as an etching mask, and a dry etching process is used to remove the sidewalls of the stacked structure 200 exposed by the protective layer 130, as well as the sidewall material layer 300 of the pseudo-gate structure 140 and the top sidewall material layer 300.

[0123] Dry etching process has the characteristics of anisotropic etching. Therefore, by selecting dry etching process, the etching is more directional, which is beneficial to reduce damage to the trench layer 220 and improve the dimensional accuracy of the inner sidewall 310 and the isolation layer 320.

[0124] refer to Figure 9 Using the protective layer 130 as an etching mask, after removing the sidewalls of the stacked structure 200 exposed by the protective layer 130, as well as the sidewalls of the pseudo-gate structure 140 and the top sidewall material layer 300, the process also includes: removing the protective layer 130.

[0125] Remove the protective layer 130 to provide sufficient space for the subsequent formation of source and drain doped layers.

[0126] refer to Figure 10 Source / drain doped layers 400 are formed on the isolation layer 320 on the substrate 100 on both sides of the pseudo-gate structure 140, and the source / drain doped layers 400 are in contact with the ends of the stacked structure 200.

[0127] The source / drain doped layer 400 is used as the source or drain region of the transistor. Specifically, the doping type of the source / drain doped layer 400 is the same as the channel conductivity type of the corresponding transistor.

[0128] Specifically, when the substrate 100 is used to form an NMOS transistor, the dopant ions in the source / drain doped layer 400 are N-type ions, including P ions, As ions, or Sb ions; when the substrate 100 is used to form a PMOS transistor, the dopant ions in the source / drain doped layer 400 are P-type ions, including B ions, Ga ions, or In ions.

[0129] In this embodiment, the source / drain doped layer 400 is formed on the isolation layer 320 on the substrate 100 on both sides of the pseudo-gate structure 140 using an epitaxial growth process, based on the sidewall of the stacked structure 200.

[0130] Epitaxial growth can better control process parameters, has high process controllability, and is easy to obtain a more accurate source / drain doped layer 400 film thickness. In addition, epitaxial growth is easy to form a film with fewer impurities, resulting in a high quality source / drain doped layer 400 film.

[0131] refer to Figure 11 Remove the dummy gate structure 140 to form a gate opening (not shown).

[0132] Gate openings are used to provide space for the subsequent formation of the gate structure.

[0133] Continue to refer to Figure 11 The sacrificial layer 210 in the laminated structure 200 is removed to form a through groove (not shown), and the remaining multiple spaced channel layers 220 constitute a channel layer structure 240, with the through groove exposed on the inner sidewall 310.

[0134] The through slot is used to provide space for the subsequent formation of the gate structure.

[0135] Continue to refer to Figure 11 A gate structure 500 is formed in the gate opening and the through-slot, spanning the channel layer structure 240. The gate structure 500 surrounds the channel layer 220 along the extension direction of the gate structure 500. The gate structures 500 between adjacent channel layers 220 and between the channel layer structure 240 and the substrate 100 serve as a stacked gate 510. The stacked gate 510 and the source / drain doped layer 400 are separated by the inner sidewall 310.

[0136] The gate structure 500 is used to control the opening and closing of the transistor's channel.

[0137] The gate structure 500 surrounds and covers the channel layer 220. Therefore, the top, bottom and sidewalls of the channel layer 220 can all serve as channels, increasing the area in the channel layer 220 used as channels, thereby increasing the operating current of the semiconductor structure.

[0138] In this embodiment, the gate structure 500 includes a gate dielectric layer surrounding the channel layer 220 along the extending direction of the gate structure 500, and a gate electrode layer located on the gate dielectric layer.

[0139] The gate dielectric layer is used to isolate the gate electrode layer from the channel layer 220, and the gate electrode layer from the substrate 100.

[0140] The gate dielectric layer material includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0141] It should be noted that the gate dielectric layer may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel layer 220. Specifically, the material of the gate oxide layer can be silicon oxide.

[0142] In this embodiment, the gate structure 500 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0143] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0144] In other embodiments, the gate electrode layer may also consist of only the work function layer.

[0145] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0146] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A channel layer structure, suspended above the substrate, the channel layer structure comprising one or more spaced channel layers; A gate structure is located on the substrate and spans the channel layer structure, the gate structure surrounding the channel layer along the extension direction of the gate structure, wherein a gate structure located between adjacent channel layers and between the channel layer structure and the substrate is used as a stacked gate. The source and drain doped layers are located on the substrates on both sides of the gate structure and are in contact with the ends of the channel layer structure; The inner sidewall is located on the sidewall of the stacked gate, and the stacked gate and the source / drain doped layers are separated by the inner sidewall; An isolation layer is located between the source / drain doped layer and the substrate, and the isolation layer and the inner sidewall are an integral structure.

2. The semiconductor structure as described in claim 1, characterized in that, The substrate includes a substrate and a bottom fin protruding from the substrate; The channel layer structure is suspended above the bottom fin; The insulating layer covers the sidewalls of the bottom fin and the top of the substrate.

3. The semiconductor structure as described in claim 2, characterized in that, The insulating layer extends to the top of the bottom fin and contacts the innermost wall.

4. The semiconductor structure as described in claim 1, characterized in that, The thickness of the insulating layer is to 5. The semiconductor structure as described in claim 1, characterized in that, The material of the inner wall includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride; The material of the insulating layer includes one or more of silicon nitride, silicon oxide, silicon carbon oxynitride, and silicon carbonitride.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a stacked structure is formed, the stacked structure comprising sacrificial layers and channel layers stacked alternately from bottom to top in a longitudinal direction, and a pseudo-gate structure is also formed on the substrate across the stacked structure, the pseudo-gate structure covering the sidewalls and top of the stacked structure; A portion of the sacrificial layer is removed from the sidewall of the stacked structure along the extending direction of the channel layer to form a groove surrounded by longitudinally adjacent channel layers; An inner wall is formed in the groove, and an insulating layer is formed covering the top surface of the base, wherein the insulating layer and the inner wall are integrally formed. Source and drain doped layers are formed on the isolation layers on the substrates on both sides of the pseudo-gate structure, and the source and drain doped layers are in contact with the ends of the stacked structure; Remove the pseudo-gate structure to form a gate opening; The sacrificial layer in the stacked structure is removed to form a through groove, and the remaining spaced-apart trench layers constitute a trench layer structure, with the through groove exposed on the inner wall. A gate structure is formed in the gate opening and the through-slot, spanning the channel layer structure. The gate structure surrounds the channel layer along the extension direction of the gate structure. The gate structures between adjacent channel layers and between the channel layer structure and the substrate serve as a stacked gate. The stacked gate and the source / drain doped layers are separated by the inner sidewalls.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The steps of forming an inner wall located in the groove and an insulating layer covering the top surface of the substrate include: forming a sidewall material layer that covers the top and sidewalls of the pseudo-grid structure, covers the sidewalls of the stacked structure, fills the groove, and extends to cover the substrate surfaces on both sides of the pseudo-grid structure; Remove the sidewall material layer covering the top and sidewalls of the pseudo-gate structure, as well as the sidewalls of the stacked structure, retain the sidewall material layer filling the groove as the inner sidewall, and retain the sidewall material layer extending to cover the base surface on both sides of the pseudo-gate structure as the isolation layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, An atomic layer deposition process is used to form a sidewall material layer that covers the top and sidewalls of the pseudo-gate structure, covers the sidewalls of the stacked structure, fills the groove, and extends to cover the substrate surfaces on both sides of the pseudo-gate structure.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, A dry etching process is used to remove the sidewall material layer covering the top and sidewalls of the pseudo-gate structure, as well as the sidewalls of the stacked structure.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of forming a sidewall material layer that covers the top and sidewalls of the dummy gate structure, covers the sidewalls of the stacked structure, fills the groove, and extends to cover the base surfaces on both sides of the dummy gate structure, the thickness of the sidewall material layer is: to 11. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of forming a sidewall material layer that covers the top and sidewalls of the pseudo-gate structure, covers the sidewalls of the stacked structure, fills the groove, and extends to cover the substrate surfaces on both sides of the pseudo-gate structure, the material of the sidewall material layer includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride.

12. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of providing the substrate, the substrate includes a substrate and a bottom fin protruding from the substrate, and the stacked structure is located on the bottom fin; In the step of forming a sidewall material layer that covers the top and sidewalls of the pseudo-gate structure, covers the sidewalls of the stacked structure, fills the groove, and extends to cover the substrate surfaces on both sides of the pseudo-gate structure, the sidewall material layer covers the sidewalls of the bottom fin and the top of the substrate; In the steps of removing the sidewall material layer covering the top and sidewalls of the pseudo-gate structure and the sidewalls of the stacked structure, retaining the sidewall material layer filling the groove as the inner sidewall, and retaining the sidewall material layer extending to cover the substrate surface on both sides of the pseudo-gate structure as the isolation layer, the sidewall covering the bottom fin and the sidewall material layer on the top of the substrate are retained as the isolation layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The step of removing the sidewall material layer covering the top and sidewalls of the pseudo-gate structure and the sidewalls of the stacked structure, retaining the sidewall material layer filling the groove as the inner sidewall, and retaining the sidewall material layer extending to cover the substrate surface on both sides of the pseudo-gate structure as the isolation layer includes: forming a protective layer covering the sidewall material layer on the substrate and the sidewall material layer covering the sidewalls of the bottom fin; Using the protective layer as an etching mask, the sidewalls of the stacked structure exposed by the protective layer, as well as the sidewalls and top of the pseudo-gate structure, are removed. The sidewall material layer filling the groove is retained as the inner sidewall, and the sidewall material layer covered by the protective layer is retained as the isolation layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of forming a protective layer covering the sidewall material layer on the substrate and covering the sidewall of the bottom fin includes: forming a protective material layer covering the sidewall material layer on the substrate; A portion of the protective material layer is removed, leaving the remaining protective material layer to cover the sidewall material layer on the substrate and the sidewall of the bottom fin, serving as the protective layer.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming a protective layer that covers the sidewall material layer on the substrate and the sidewall material layer covering the bottom fin sidewall, the top surface of the protective layer is higher than the top surface of the bottom fin and lower than the bottom surface of the bottommost channel layer.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming a protective layer that covers the sidewall material layer on the substrate and the sidewall material layer covering the bottom fin sidewall, the material of the protective layer includes spin-coated carbon.

17. The method for forming a semiconductor structure as described in claim 13, characterized in that, Using the protective layer as an etching mask, after removing the sidewalls of the stacked structure, the sidewalls of the pseudo-gate structure, and the top sidewall material layer exposed by the protective layer, the method further includes: removing the protective layer.

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