Metal gate structure and method of forming the same

Abstract

The application provides a metal gate structure and a forming method thereof. The metal gate structure comprises a substrate, the substrate has a low work function region and a high work function region, a gate dielectric layer is formed on the substrate of the high work function region and the low work function region; a first work function layer and a metal gate, the first work function layer is located on the gate dielectric layer of the high work function region, and the metal gate is located on the first work function layer and the gate dielectric layer of the low work function region. Since the first work function layer is formed between the metal gate and the gate dielectric layer of the high work function region, the diffusion of metal atoms in the metal gate into the gate dielectric layer of the high work function region is blocked, so that the voltage acceleration index is improved, and the time-dependent breakdown performance of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a metal gate structure and a method for forming the same. Background Technology

[0002] Metal-oxide-semiconductor (MOS) transistors are crucial components in integrated circuit manufacturing. MOS transistors are typically formed on a substrate and include a metal gate. Active and drain regions are formed in the substrate on either side of the metal gate through implantation. With continuous advancements in MOS technology, the channel size of the metal gate has become increasingly miniaturized. While this has led to significant performance improvements, it has also drastically shortened device lifetime, particularly when facing reliability issues such as hot carrier injection (HCI) and time-dependent dielectric breakdown (TDDB). Summary of the Invention

[0003] The purpose of this invention is to provide a metal gate structure and a method for forming the same, so as to improve the breakdown performance of the device over time.

[0004] To achieve the above objectives, the present invention provides a metal gate structure, comprising:

[0005] A substrate having a low work function region and a high work function region, wherein a gate dielectric layer is formed on the substrate in the high work function region and the low work function region;

[0006] A first work function layer and a metal gate, wherein the first work function layer is located on the gate dielectric layer in the high work function region, and the metal gate is located on the gate dielectric layer in the first work function layer and the low work function region.

[0007] Optionally, in the metal gate structure, the metal gate structure further includes:

[0008] The lightly doped drain region and the lightly doped source region are located in the substrate on the side of the low work function region away from the high work function region, and the lightly doped source region is located in the substrate on the side of the high work function region away from the low work function region.

[0009] A first halo injection region and a second halo injection region are located in the substrate of the lightly doped drain region near the low work function region and overlap with the substrate portion of the low work function region. The second halo injection region is located in the substrate of the lightly doped source region near the high work function region and overlaps with the substrate portion of the high work function region. The dose of dopant ions in the first halo injection region is greater than the dose of dopant ions in the second halo injection region.

[0010] Optionally, in the metal gate structure, the metal gate structure further includes an interlayer dielectric layer having a gate opening aligned with the high power function region and the low power function region. The first power function layer and the metal gate are both located in the gate opening. The first power function layer covers the gate dielectric layer of the high power function region and extends to cover the sidewall of the gate opening near the high power function region. The metal gate covers the surface of the first power function layer and the gate dielectric layer of the low power function region, and the top surface of the metal gate is flush with the top surface of the interlayer dielectric layer.

[0011] Optionally, in the metal gate structure, the metal gate structure further includes a second work function layer located in the gate opening. The second work function layer covers the gate dielectric layer in the low work function region and extends to cover one sidewall of the gate opening near the low work function region. The thickness of the second work function layer is less than the thickness of the first work function layer, and the metal gate also covers the surface of the second work function layer.

[0012] Based on the same inventive concept, the present invention also provides a method for forming a metal gate structure, comprising:

[0013] A substrate is provided, the substrate having a low work function region and a high work function region, and a gate dielectric layer is formed on the substrate in the high work function region and the low work function region;

[0014] A first work function layer and a metal gate are formed, wherein the first work function layer is located on the gate dielectric layer in the high work function region, and the metal gate is located on the gate dielectric layer in the first work function layer and the low work function region.

[0015] Optionally, in the method for forming the metal gate structure, before forming the first work function layer and the metal gate, the method for forming the metal gate structure further includes:

[0016] A lightly doped drain region and a lightly doped source region are formed sequentially. The lightly doped drain region is located in the substrate on the side of the low work function region away from the high work function region, and the lightly doped source region is located in the substrate on the side of the high work function region away from the low work function region.

[0017] A first halo injection region and a second halo injection region are formed sequentially. The first halo injection region is located in the substrate of the lightly doped drain region near the low work function region and overlaps with the substrate portion of the low work function region. The second halo injection region is located in the substrate of the lightly doped source region near the high work function region and overlaps with the substrate portion of the high work function region. The dose of dopant ions in the first halo injection region is greater than the dose of dopant ions in the second halo injection region.

[0018] Optionally, in the method for forming the metal gate structure, the method for sequentially forming the first halo injection region and the second halo injection region includes:

[0019] A virtual gate, a hard mask layer, and a patterned first photoresist layer are sequentially formed. The virtual gate is located on the gate dielectric layer, the hard mask layer covers the top surface of the virtual gate, and the patterned first photoresist layer covers the hard mask layer of the high work function region and the lightly doped source region.

[0020] Using the patterned first photoresist layer as a mask, the substrate on the side of the lightly doped drain region near the low work function region is ion implanted using a first tilted ion implantation process to form the first halo implantation region.

[0021] Remove the patterned first photoresist layer;

[0022] A patterned second photoresist layer is formed on the substrate, the patterned second photoresist layer covering the hard mask layer of the low work function region and the lightly doped drain region;

[0023] Using the patterned second photoresist layer as a mask, the substrate on the side of the lightly doped source region near the high work function region is ion implanted using the second tilted ion implantation process to form the second halo implantation region;

[0024] Remove the patterned second photoresist layer;

[0025] An annealing process is performed on the substrate.

[0026] Optionally, in the method for forming the metal gate structure, the method for forming the first work function layer and the metal gate includes:

[0027] An interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer being located on the substrate on both sides of the virtual gate;

[0028] Remove the hard mask layer and the dummy gate to form a gate opening that exposes the gate dielectric layer;

[0029] A first work function layer and a metal gate are formed in the gate opening. The first work function layer covers the gate dielectric layer in the high work function region and extends to cover one sidewall of the gate opening near the high work function region. The metal gate covers the surface of the first work function layer and the gate dielectric layer in the low work function region, and the top surface of the metal gate is flush with the top surface of the first work function layer.

[0030] Optionally, in the method for forming the metal gate structure, the method for forming the first work function layer and the metal gate in the gate opening includes:

[0031] A first work function material layer is formed, which covers the bottom and sidewalls of the gate opening;

[0032] Remove the first work function material layer on the low work function region at the bottom of the gate opening, and remove the first work function material layer on the sidewall of the gate opening near the low work function region;

[0033] A metal gate material layer is formed, which covers the first work function material layer and the gate dielectric layer of the low work function region, and the top surface of the metal gate material layer is higher than the top surface of the interlayer dielectric layer.

[0034] A planarization process is performed to remove the metal gate material layer on the interlayer dielectric layer to form a metal gate, while retaining the first work function material layer on the high work function region in the gate opening to form the first work function layer.

[0035] Optionally, in the method for forming the metal gate structure, the method for forming the first work function layer and the metal gate in the gate opening includes:

[0036] A first work function material layer is formed, which covers the bottom and sidewalls of the gate opening;

[0037] Remove the first work function material layer on the low work function region at the bottom of the gate opening, and remove the first work function material layer on the sidewall of the gate opening near the low work function region;

[0038] A second work function material layer is formed, which covers the first work function material layer and the gate dielectric layer of the low work function region, and extends to cover the sidewall of the gate opening near the low work function region;

[0039] A metal gate material layer is formed, which covers the second work function material layer, and the top surface of the metal gate material layer is higher than the top surface of the interlayer dielectric layer;

[0040] A planarization process is performed to remove the metal gate material layer on the interlayer dielectric layer to form a metal gate, and to retain the second work function material layer on the low work function region in the gate opening to form a second work function layer, and to retain the second work function material layer and the first work function material layer on the high work function region in the gate opening to form a first work function layer.

[0041] In the metal gate structure and its formation method provided by the present invention, the metal gate structure includes a substrate having a low work function region and a high work function region, with gate dielectric layers formed on the substrate in both the high and low work function regions; a first work function layer and a metal gate, wherein the first work function layer is located on the gate dielectric layer in the high work function region, and the metal gate is located on both the first work function layer and the gate dielectric layer in the low work function region. Because a first work function layer is formed between the metal gate and the gate dielectric layer in the high work function region, the diffusion of metal atoms from the metal gate into the gate dielectric layer in the high work function region can be prevented, thereby increasing the voltage acceleration index and thus improving the device's breakdown performance over time. Attached Figure Description

[0042] Figure 1 This is a schematic flowchart of the method for forming a metal gate structure provided in an embodiment of the present invention;

[0043] Figures 2-6 This is a schematic diagram of the structure during the step of forming the first halo injection region and the second halo injection region in the method for forming a metal gate structure provided in the embodiment of the present invention;

[0044] Figures 7-12 This is a schematic diagram of the structure during the step of forming a metal gate material layer in a method for forming a metal gate structure according to an embodiment of the present invention;

[0045] Figure 13 This is a schematic diagram of a metal gate structure provided in an embodiment of the present invention;

[0046] Figures 14-15 This is a schematic diagram of the structure during the step of forming a metal gate material layer in a method for forming a metal gate structure according to another embodiment of the present invention;

[0047] Figure 16 This is a schematic diagram of a metal gate structure provided in another embodiment of the present invention;

[0048] The reference numerals in the attached figures are explained as follows:

[0049] 100 - Substrate; 100a - Lightly doped drain region; 100b - Low work function region; 100c - High work function region; 100d - Lightly doped source region;

[0050] 101-Gate dielectric layer; 1011-Silicon oxide layer; 1012-Hafnium oxide layer; 102-Dummy gate; 103-Sidewall; 104-Hard mask layer; 105-Patterned first photoresist layer; 106-Patterned second photoresist layer; 107-Interlayer dielectric layer; 108-Gate opening; 109-Patterned third photoresist layer;

[0051] 110 - First halo injection region; 120 - Second halo injection region; 130 - First work function material layer; 140 - Second work function material layer; 150 - First work function layer; 160 - Second work function layer; 170 - Metal gate material layer; 170a - Metal gate. Detailed Implementation

[0052] The metal gate structure and its formation method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0053] Figure 13 This is a schematic diagram of a metal gate structure provided in an embodiment of the present invention. Figure 13 As shown, the metal gate structure includes a substrate 100, a first work function layer 150, and a metal gate 170a.

[0054] Specifically, the substrate 100 may include materials suitable for semiconductor processes, such as silicon-containing materials. The material of the substrate 100 may include one or a combination of two of the following: silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, and carbon-doped silicon. In this embodiment, the substrate 100 may be a silicon substrate.

[0055] like Figure 13 As shown, the substrate 100 has a low work function region 100b and a high work function region 100c.

[0056] Optional, such as Figure 13As shown, a lightly doped drain region (LDD Drain) 100a and a lightly doped source region (LDD Source) 100d are formed in the substrate 100. The lightly doped drain region 100a is located in the substrate 100 on the side of the low work function region 100b away from the high work function region 100c, and the lightly doped source region 100d is located in the substrate 100 on the side of the high work function region 100c away from the low work function region 100b. The dopant ions in the lightly doped source region 100d and the dopant ions in the lightly doped drain region 100a have the same conductivity type. Specifically, taking NMOS as an example, the conductivity type of both the dopant ions in the lightly doped source region 100d and the dopant ions in the lightly doped drain region 100a can be N-type, such as nitrogen (N) ions, phosphorus (P) ions, or arsenic (As) ions.

[0057] Optional, such as Figure 13 As shown, a first halo implantation region (LDD halo) 110 and a second halo implantation region 120 are also formed in the substrate 100. Specifically, the first halo implantation region 110 is located in the substrate 100 near the low work function region 100b of the lightly doped drain region 100a, and partially overlaps with the substrate 100 of the low work function region 100b. That is, the first halo implantation region 110 partially overlaps with the channel region of the low work function region 100b.

[0058] Specifically, the conductivity type of the doped ions in the first halo injection region 110 is opposite to that of the doped ions in the lightly doped drain region 100a. For example, in an NMOS device, if the doped ions in the lightly doped drain region 100a are N-type, then the doped ions in the first halo injection region 110 are P-type, such as boron (B) ions, gallium (Ga) ions, indium (In) ions, or boron difluoride ions (BF2).

[0059] like Figure 13 As shown, the second halo implantation region 120 is located in the substrate 100 of the lightly doped source region 100d near the high work function region 100c, and partially overlaps with the substrate 100 of the high work function region 100c. In other words, the second halo implantation region 120 partially overlaps with the channel region of the high work function region 100c. The conductivity type of the doped ions in the second halo implantation region 120 is the same as that of the doped ions in the first halo implantation region 110, i.e., the conductivity type of the second halo implantation region 120 is also P-type.

[0060] In this embodiment, both the first halo injection region 110 and the second halo injection region 120 are used to adjust the threshold voltage of the device. The dopant ion dose in the first halo injection region 110 is greater than the dopant ion dose in the second halo injection region 120. This reduces the electric field strength near the lightly doped drain region 100a (i.e., the drain terminal), thereby improving the hot carrier injection (HCI) effect of the device without altering its DC and AC performance. The dopant ion dose in the first halo injection region 110 can be 1E11 ions / cm². 2 ~1E16 ions / cm 2 .

[0061] like Figure 13 As shown, a gate dielectric layer 101 is formed on the substrate 100 of the high work function region 100c and the low work function region 100b, that is, the gate dielectric layer 101 covers the substrate of the high work function region 100c and the low work function region 100b. The gate dielectric layer 101 includes a silicon oxide layer 1011 and a hafnium oxide layer 1012 located on the silicon oxide layer 1011.

[0062] In this embodiment, a first work function layer 150 is formed on the gate dielectric layer 101 of the high work function region 100c, and the first work function layer 150 covers the gate dielectric layer 101 of the high work function region 100c. The first work function layer 150 is used to adjust the work function of the metal gate 170a of the high work function region 100c, and the first work function layer 150 can block the diffusion of metal atoms in the metal gate 170a into the gate dielectric layer 101 of the high work function region 100c, thereby improving the voltage acceleration index, thereby improving the time breakdown performance (TDDB) and reliability of the device, without changing the DC (direct current) performance and AC (alternating current) performance of the device.

[0063] Furthermore, since a first work function layer 150 is formed on the high work function region 100c, the work function of the high work function region 100c is relatively increased compared to the low work function region 100b, thereby increasing the threshold voltage of the high work function region 100c. Simultaneously, the ion doping dose of the first halo implantation region 110 (which partially overlaps with the substrate 100 of the low work function region 100b) is greater than that of the second halo implantation region 120 (which partially overlaps with the substrate of the high work function region 100c), thus causing a corresponding increase in the threshold voltage of the low work function region 100b. Therefore, under the combined action of the first halo injection region 110, the second halo injection region 120, and the first work function layer 150, the threshold voltage of the high work function region 100c is basically the same as or the threshold voltage of the low work function region 100b is small. This reduces the difference in threshold voltage between the low work function region 100b and the high work function region 100c, making the threshold voltage of the low work function region 100b and the threshold voltage of the high work function region 100c closer. It can also reduce charge accumulation at the interface, lower the interface state density, and improve the reliability and stability of the device.

[0064] In this embodiment, the material of the first work function layer 150 includes at least one of titanium nitride, tantalum nitride, and aluminum titanium. The thickness of the first work function layer 150 can be 30 angstroms to 80 angstroms, for example, 40 angstroms, 50 angstroms, or 60 angstroms.

[0065] In this embodiment, the metal gate 170a is located on the gate dielectric layer 101 of the first work function layer 150 and the low work function region 100b.

[0066] In further proposals, such as Figure 13 As shown, the metal gate structure also includes an interlayer dielectric layer 107, which is located on the substrate 100 on both sides of the metal gate 170a.

[0067] Optional, such as Figure 13 As shown, the metal gate structure also includes a sidewall 103, which covers the sidewall of the first work function layer 150 and the sidewall of the metal gate 170a, and the interlayer dielectric layer 107 also covers the sidewall of the sidewall 103.

[0068] refer to Figure 13 and combined Figure 11 As shown, the interlayer dielectric layer 107 has a gate opening 108, which is aligned with the high work function region 100c and the low work function region 100b. The first work function layer 150, the gate dielectric layer 101, and the metal gate 170a are all located in the gate opening 108.

[0069] Specifically, the first work function layer 150 covers the gate dielectric layer 101 of the high work function region 100c and extends to cover the sidewall of the gate opening 108 near the high work function region 100c. That is, the first work function layer 150 includes a vertical portion and a horizontal portion. The vertical portion covers the sidewall of the gate opening 108 near the high work function region 100c, and the horizontal portion covers the gate dielectric layer 101 of the high work function region 100c. The metal gate 170a covers the surface of the first work function layer 150 and the gate dielectric layer of the low work function region 100b, and the top surface of the metal gate 170a is flush with the top surface of the interlayer dielectric layer 107. That is, the metal gate 170a covers the inner wall of the first work function layer 150 (the sidewall of the vertical portion and the top surface of the horizontal portion of the first work function layer 150) and extends to cover the gate dielectric layer 101.

[0070] Figure 16 This is a schematic diagram of a metal gate structure provided in another embodiment of the present invention. Figure 16 As shown, in some embodiments, the metal gate structure further includes a second work function layer 160, which is located in the gate opening 108. Specifically, the second work function layer 160 is located between the metal gate 170a and the gate dielectric layer 101 of the low work function region 100b, and extends to the area between the metal gate 170a and the sidewall of the gate opening 108 near the low work function region 100b. That is, the cross-sectional shape of the second work function layer 160 is L-shaped, meaning that the second work function layer 160 covers the gate dielectric layer 101 of the low work function region 100b and extends to cover the sidewall of the gate opening 108 near the low work function region 100b. The metal gate 170a also covers the inner wall of the second work function layer 160.

[0071] In this embodiment, the material of the second work function layer 160 includes at least one of titanium nitride, tantalum nitride, and aluminum titanium, and the material of the second work function layer 160 can be the same as that of the first work function layer 150.

[0072] In this embodiment, the thickness of the second work function layer 160 is less than the thickness of the first work function layer 150. Since the thickness of the second work function layer 160 located on the low work function region 100b is less than the thickness of the first work function layer 150 located on the high work function region 100c, the work function of the second work function layer 160 located on the low work function region 100b is less than the work function of the first work function layer 150 located on the high work function region 100c, thereby reducing the work function of the low work function region 100b and consequently reducing its threshold voltage. Furthermore, since the first halo injection region 110 partially overlaps with the substrate 100 of the low work function region 100b, and the ion doping dose of the first halo injection region 110 is greater than the ion doping dose of the second halo injection region 120 (which partially overlaps with the substrate 100 of the high work function region 100c), the threshold voltage of the low work function region 100b is increased. In other words, compared to the high work function region 100c, the second work function layer 160 located on the low work function region 100b is thinner, thereby reducing the work function of the low work function region 100b and thus reducing its threshold voltage. The first work function layer 150 located on the high work function region 100c is thicker, thereby increasing the work function of the high work function region 100c and thus increasing its threshold voltage. At the same time, the ion doping dose of the first halo implantation region 110 is greater than that of the second halo implantation region 120, thus resulting in a relatively larger threshold voltage of the low work function region 100b and a relatively smaller threshold voltage of the high work function region 100c.

[0073] Therefore, under the combined action of the first halo injection region 110, the second halo injection region 120, the first work function layer 150, and the second work function layer 160, the threshold voltage of the high work function region 100c is basically the same as or the threshold voltage of the low work function region 100b is small. This reduces the threshold voltage difference between the low work function region 100b and the high work function region 100c, making the threshold voltage of the low work function region 100b and the threshold voltage of the high work function region 100c closer. It also reduces charge accumulation at the interface, lowers the interface state density, and improves the reliability and stability of the device.

[0074] The thickness difference between the second work function layer 160 and the first work function layer 150 can be 10 angstroms to 50 angstroms.

[0075] Figure 1 This is a schematic flowchart of a method for forming a metal gate structure according to an embodiment of the present invention. Figure 1 As shown, this embodiment also provides a method for forming a metal gate structure, including:

[0076] Step S1: Provide a substrate having a low work function region and a high work function region, and a gate dielectric layer is formed on the substrate in the high work function region and the low work function region;

[0077] Step S2: Form a first work function layer and a metal gate, wherein the first work function layer is located on the gate dielectric layer in the high work function region, and the metal gate is located on the gate dielectric layer in the first work function layer and the low work function region.

[0078] Figures 2 to 16 This is a schematic diagram of the steps in the method for forming a metal gate structure provided in an embodiment of the present invention. Next, we will combine... Figures 2 to 16 The method for forming the metal gate structure provided in the embodiments of the present invention will be described in more detail.

[0079] First, execute step S1, as follows: Figure 2 As shown, a substrate 100 is provided, the substrate 100 having a low work function region 100b and a high work function region 100c.

[0080] Specifically, the substrate 100 may include materials suitable for semiconductor processes, such as silicon-containing materials. The material of the substrate 100 may include one or a combination of two of the following: silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, and carbon-doped silicon. In this embodiment, the substrate 100 may be a silicon substrate.

[0081] like Figure 2 As shown, a gate dielectric layer 101 is formed on the substrate 100 of the low work function region 100b and the high work function region 100c. The gate dielectric layer 101 includes a silicon oxide layer 1011 and a hafnium oxide layer 1012 located on the silicon oxide layer 1011.

[0082] Optional, such as Figure 2 As shown, a lightly doped drain region 100a and a lightly doped source region 100d are sequentially formed. The lightly doped drain region 100a is located in the substrate on the side of the low work function region 100b away from the high work function region 100c, and the lightly doped source region 100d is located in the substrate 100 on the side of the high work function region 100c away from the low work function region 100b. The lightly doped drain region 100a and the lightly doped source region 100d can be formed by a lightly doped ion implantation process.

[0083] Optional, such as Figure 6As shown, a first halo injection region 110 and a second halo injection region 120 are formed sequentially. The first halo injection region 110 is located in the substrate 100 of the lightly doped drain region 100a near the low work function region 100b, and partially overlaps with the substrate 100 of the low work function region 100b. The second halo injection region 120 is located in the substrate 100 of the lightly doped source region 100d near the high work function region 100c, and partially overlaps with the substrate 100 of the high work function region 100c. The dose of doped ions in the first halo injection region 110 is greater than the dose of doped ions in the second halo injection region 120. In this way, the electric field strength near the lightly doped drain region 100a (i.e., the drain end) can be reduced, thereby improving the hot carrier injection effect (HCI) of the device, without changing the DC and AC performance of the device.

[0084] Specifically, the method for sequentially forming the first halo injection region 110 and the second halo injection region 120 includes: First, as... Figure 2 As shown, a virtual gate 102, a hard mask layer 104, and a patterned first photoresist layer 105 are sequentially formed. The virtual gate 102 is located on the gate dielectric layer 101, and the hard mask layer 104 covers the top surface of the virtual gate 102. The patterned first photoresist layer 105 covers the hard mask layer 104 of the high work function region 100c and the lightly doped source region 100d, that is, the patterned first photoresist layer 105 exposes the hard mask layer 104 of the low work function region 100b, and exposes the substrate between the lightly doped drain region 100a and the low work function region 100b. The virtual gate 102 may be made of silicon oxide, and the hard mask layer 104 may be made of silicon nitride.

[0085] In addition, such as Figure 2 As shown, after forming the virtual gate 102 and before forming the hard mask layer 104, a sidewall 103 may be formed, which covers the sidewall of the virtual gate 102. The sidewall 103 may be made of silicon nitride.

[0086] After forming the patterned first photoresist layer 105, as Figure 3 As shown, using the patterned first photoresist layer 105 as a mask, a first tilted ion implantation process is used to implant ions into a portion of the substrate 100 in the low work function region 100b to form the first halo implantation region 110.

[0087] It should be noted that, since ions are implanted into the substrate 100 at an angle in the first tilted ion implantation process, and the patterned first photoresist layer 105 only covers the hard mask layer 104 of the high work function region 100c and the lightly doped source region 100d, some doped ions will also be implanted into the substrate 100 of the low work function region 100b during the ion implantation process. As a result, the first halo implantation region 110 formed in the end is located in the substrate 100 of the lightly doped drain region 100a on the side close to the low work function region 100b, and partially overlaps with the substrate 100 of the low work function region 100b.

[0088] Preferably, the implantation angle (the angle between the ion implantation direction and the normal to the substrate) of the first tilted ion implantation process is 0° to 30°, for example, 10° or 20°.

[0089] In this embodiment, the dose of doped ions in the first halo implantation region 110 is greater than the dose of doped ions in the subsequently formed second halo implantation region 120. In other words, the implantation dose of the first tilted ion implantation process is greater than the implantation dose of the subsequent second tilted ion implantation process. This reduces the electric field strength near the lightly doped drain region 100a (i.e., the drain end), thereby improving the hot carrier injection (HCI) effect of the device.

[0090] The implantation dose (i.e., the dose of doped ions in the first halo implantation region 110) of the first tilted ion implantation process can be 1E11 ions / cm 2 ~1E16 ions / cm 2 .

[0091] Furthermore, the conductivity type of the doped ions in the first halo injection region 110 is opposite to that of the doped ions in the lightly doped drain region 100a, in order to adjust the threshold voltage of the device. Specifically, taking NMOS as an example, if the conductivity type of the doped ions in the lightly doped drain region 100a is N-type, then the conductivity type of the doped ions in the first halo injection region 110 is P-type, such as boron (B) ions, gallium (Ga) ions, indium (In) ions, or boron difluoride ions (BF2).

[0092] Next, as Figure 4 As shown, the patterned first photoresist layer 105 is removed. This removal can be achieved using a wet cleaning method.

[0093] Then, as Figure 5As shown, a patterned second photoresist layer 106 is formed on the substrate 100. The patterned second photoresist layer 106 covers the hard mask layer 104 of the low work function region 100b and the lightly doped drain region 100a. That is, the patterned second photoresist layer 106 exposes the hard mask layer 104 of the high work function region 100c and the substrate 100 between the high work function region 100c and the lightly doped source region 100d.

[0094] After that, as Figure 5 As shown, using the patterned second photoresist layer 106 as a mask, a second tilted ion implantation process is employed to implant ions into the substrate 100 on the side of the lightly doped source region 100d near the high work function region 100c, thereby forming the second halo implantation region 120. The dopant ions in the second tilted ion implantation process are the same as those in the first tilted ion implantation process; that is, the conductivity type of the dopant ions in the second tilted ion implantation process is also P-type.

[0095] It should be noted that, since ions are implanted into the substrate 100 at an angle in the second tilted ion implantation process, and the patterned second photoresist layer 106 only covers the hard mask layer 104 of the low work function region 100b and the lightly doped drain region 100a, some doped ions will also be implanted into the substrate of the high work function region 100c during the ion implantation process. As a result, the second halo implantation region 120 formed in the end is located in the substrate 100 of the lightly doped source region 100d on the side close to the high work function region 100c, and partially overlaps with the substrate 100 of the high work function region 100c.

[0096] Preferably, the implantation angle of the second tilted ion implantation process is 0° to 30°, for example, 10° or 20°. The implantation angle of the second tilted ion implantation process can be the same as that of the first tilted ion implantation process.

[0097] Next, as Figure 6 As shown, the patterned second photoresist layer 106 is removed. Then, an annealing process is performed on the substrate 100 to diffuse the doped ions in the lightly doped source region 100d, the lightly doped drain region 100a, the first halo ring implantation region 110, and the second halo ring implantation region 120, thereby further diffusing the doped ions in the first halo ring implantation region 110 and the second halo ring implantation region 120 into the channel region. The annealing temperature can be between 950°C and 1100°C.

[0098] Next, proceed to step S2, as follows: Figure 13As shown, a first work function layer 150 and a metal gate 170a are formed. The first work function layer 150 is located on the gate dielectric layer 101 of the high work function region 100c, and the metal gate 170a is located on the first work function layer 150 and the gate dielectric layer of the low work function region 100b. Because the first work function layer 150 is formed between the high work function region 100c and the metal gate 170a, it can prevent metal atoms in the metal gate 170a from diffusing into the gate dielectric layer 101, thereby increasing the voltage acceleration index and thus improving the time-to-delay breakdown performance (TDDB) and reliability of the device.

[0099] Specifically, the method for forming the first work function layer 150 and the metal gate 170a includes: firstly, as... Figure 6 As shown, an interlayer dielectric layer 107 is formed on the substrate 100. The interlayer dielectric layer 107 is located on the substrate 100 on both sides of the virtual gate 102 and covers the sidewall of the sidewall 103. The material of the interlayer dielectric layer 107 includes silicon oxide, and the interlayer dielectric layer 107 can be formed by chemical vapor deposition.

[0100] Then, as Figure 7 As shown, the hard mask layer 104 and the dummy gate 102 are removed to form a gate opening 108, which exposes the gate dielectric layer 101. The hard mask layer 104 and the dummy gate 102 can be removed using a dry etching process.

[0101] Next, as Figure 13 As shown, a first work function layer 150 and a metal gate 170a are formed in the gate opening 108. The first work function layer 150 covers the gate dielectric layer 101 of the high work function region 100c and extends to cover one sidewall of the gate opening 108 near the high work function region 100c. The metal gate 170a covers the surface of the first work function layer 150 and the gate dielectric layer 101 of the low work function region 100b, and the top surface of the metal gate 170a is flush with the top surface of the interlayer dielectric layer 107.

[0102] In some embodiments, the method of forming the first work function layer 150 and the metal gate 170a in the gate opening 108 includes: firstly, as Figure 8As shown, a first work function material layer 130 is formed, which covers the bottom and sidewalls of the gate opening 108. Furthermore, the first work function material layer 130 may extend to cover the interlayer dielectric layer 107. The material of the first work function material layer 130 includes at least one of titanium nitride (TiN), tantalum nitride (TaN), and aluminum titanium (TiAl). The first work function material layer 130 can be formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0103] Then, as Figure 10 As shown, the first work function material layer 130 on the low work function region 100b at the bottom of the gate opening 108 is removed, as well as the first work function material layer 130 on the sidewall of the gate opening 108 near the low work function region 100b is removed. Specifically, as shown... Figure 9 As shown, a patterned third photoresist layer 109 is formed, which covers the first work function material layer 130 on the high work function region 100c and the interlayer dielectric layer 107, and exposes the first work function material layer 130 on the low work function region 100b. Using the patterned third photoresist layer 109 as a mask, a dry etching process is used to remove the first work function material layer 130 on the low work function region 100b, that is, to remove the first work function material layer 130 at the bottom of the gate opening 108 on the surface of the gate dielectric layer 101 in the low work function region 100b, and to remove the first work function material layer 130 on one sidewall of the gate opening 108 near the low work function region 100b, while retaining the first work function material layer 130 on the high work function region 100c at the bottom of the gate opening 108 and retaining the first work function layer 150 on the sidewall of the gate opening 108 near the high work function region 100c.

[0104] Next, as Figure 11 As shown, the patterned third photoresist layer 109 is removed.

[0105] After that, as Figure 12 As shown, a metal gate material layer 170 is formed, which covers the first work function material layer 130 and the gate dielectric layer 101 of the low work function region 100b. The top surface of the metal gate material layer 170 is higher than the top surface of the interlayer dielectric layer 107, that is, the metal gate material layer 170 fills the gate opening 108 and extends to cover the interlayer dielectric layer 107. The metal gate material layer 170 can be formed by a sputtering process, and its material includes TiAl (titanium aluminum) and / or Al (aluminum).

[0106] After that, as Figure 13As shown, a planarization process is performed to remove the metal gate material layer 170 on the interlayer dielectric layer 107 to form a metal gate 170a, and to remove the first work function material layer 130 on the interlayer dielectric layer 107, while retaining the first work function material layer 130 on the high work function region 100c in the gate opening 108 to form the first work function layer 150. The planarization process can be a chemical mechanical polishing (CMP) process.

[0107] In some embodiments, the method of forming the first work function layer 150 and the metal gate 170a in the gate opening 108 includes: firstly, as Figure 8 As shown, a first work function material layer 130 is formed, which covers the bottom and sidewalls of the gate opening 108. Furthermore, the first work function material layer 130 may extend to cover the interlayer dielectric layer. The material of the first work function material layer 130 includes at least one of titanium nitride (TiN), tantalum nitride (TaN), and aluminum titanium (TiAl). The first work function material layer 130 can be formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0108] Then, as Figure 11 As shown, the first work function material layer 130 on the low work function region 100b at the bottom of the gate opening 108 is removed, and the first work function material layer 130 on the sidewall of the gate opening 108 near the low work function region 100b is also removed.

[0109] Next, as Figure 14 As shown, a second work function material layer 140 is formed, which covers the first work function material layer 130 and the gate dielectric layer 101 of the low work function region 100b, and extends to cover the sidewall of the gate opening 108 near the low work function region 100b. The second work function material layer 140 can, together with the first work function material layer 130, constitute the first work function layer 150 of the high work function region 100c, thereby increasing the thickness of the first work function layer 150, and thus increasing the blocking ability of the first work function layer 150 to metal atoms in the metal gate 170a.

[0110] like Figure 14 As shown, the material of the second work function material layer 140 is the same as that of the first work function material layer 130. The thickness t2 of the second work function material layer 140 can be less than or equal to the thickness t1 of the first work function material layer 130. For example, the thickness of the second work function material layer 140 can be 1 angstrom to 20 angstroms.

[0111] Then, as Figure 15As shown, a metal gate material layer 170 is formed, which covers the second work function material layer 140, and the top surface of the metal gate material layer 170 is higher than the top surface of the interlayer dielectric layer 107, that is, the metal gate material layer 170 fills the gate opening 108 and extends to cover the interlayer dielectric layer 107.

[0112] After that, as Figure 16 As shown, a planarization process is performed to remove the metal gate material layer 170 on the interlayer dielectric layer 107 to form a metal gate 170a, and to remove the second work function material 140 and the first work function material layer 130 on the interlayer dielectric layer, retaining the second work function material layer 140 and the first work function material layer 130 on the high work function region 100c in the gate opening 108 to form the first work function layer 150, and retaining the second work function material layer 140 on the low work function region 100b in the gate opening 108 to form the second work function layer 160. That is, the first work function layer 150 covers the gate dielectric layer of the high work function region 100c and extends to cover the side wall of the gate opening 108 near the high work function region 100c, and the second work function layer 160 covers the gate dielectric layer of the low work function region and extends to cover the side wall of the gate opening 108 near the low work function region 100b. In other words, the cross-sectional shape of the second work function layer 160 is L-shaped, and the second work function layer 160 is continued on one side of the first work function layer 150.

[0113] Furthermore, the thickness of the second work function layer 160 in the low work function region 100b is less than the thickness of the first work function layer 150 in the high work function region 100c. Therefore, the second work function layer 160 in the low work function region 100b is thinner than that in the high work function region 100c, thereby reducing the work function of the low work function region 100b and thus reducing its threshold voltage. Conversely, it relatively increases the work function of the high work function region 100c, thereby relatively increasing its threshold voltage. At the same time, the ion doping dose of the first halo implantation region 110 is greater than that of the second halo implantation region 120. Therefore, the threshold voltage of the low work function region 100b is relatively increased, while the threshold voltage of the high work function region 100c is relatively decreased. Therefore, under the combined action of the first halo injection region 110, the second halo injection region 120, the first work function layer 150, and the second work function layer 160, the threshold voltage of the high work function region 100c is basically the same as or the threshold voltage of the low work function region 100b is small. This reduces the threshold voltage difference between the low work function region 100b and the high work function region 100c, thereby making the threshold voltage of the low work function region 100b and the threshold voltage of the high work function region 100c closer. It also reduces charge accumulation at the interface, lowers the interface state density, and improves the reliability and stability of the device.

[0114] In summary, in the metal gate structure and its formation method provided by the present invention, the metal gate structure includes a substrate having a low work function region and a high work function region, and a gate dielectric layer is formed on the substrate in the high work function region and the low work function region; a first work function layer is formed between the metal gate and the gate dielectric layer in the high work function region. In this way, the diffusion of metal atoms in the metal gate into the gate dielectric layer in the high work function region can be blocked, thereby increasing the voltage acceleration index and thus improving the breakdown performance of the device over time.

[0115] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

[0116] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A metal gate structure, characterized in that, include: A substrate having a low work function region and a high work function region, wherein a gate dielectric layer is formed on the substrate in the high work function region and the low work function region; A first work function layer and a metal gate, wherein the first work function layer is located on the gate dielectric layer in the high work function region, and the metal gate is located on the gate dielectric layer in the first work function layer and the low work function region.

2. The metal gate structure as described in claim 1, characterized in that, The metal gate structure further includes: The lightly doped drain region and the lightly doped source region are located in the substrate on the side of the low work function region away from the high work function region, and the lightly doped source region is located in the substrate on the side of the high work function region away from the low work function region. A first halo injection region and a second halo injection region are located in the substrate of the lightly doped drain region near the low work function region and overlap with the substrate portion of the low work function region. The second halo injection region is located in the substrate of the lightly doped source region near the high work function region and overlaps with the substrate portion of the high work function region. The dose of dopant ions in the first halo injection region is greater than the dose of dopant ions in the second halo injection region.

3. The metal gate structure as described in claim 1, characterized in that, The metal gate structure further includes an interlayer dielectric layer having a gate opening aligned with the high power function region and the low power function region. The first power function layer and the metal gate are both located within the gate opening. The first power function layer covers the gate dielectric layer of the high power function region and extends to cover one sidewall of the gate opening near the high power function region. The metal gate covers the surface of the first power function layer and the gate dielectric layer of the low power function region, and the top surface of the metal gate is flush with the top surface of the interlayer dielectric layer.

4. The metal gate structure as described in claim 3, characterized in that, The metal gate structure further includes a second work function layer located in the gate opening. The second work function layer covers the gate dielectric layer in the low work function region and extends to cover one sidewall of the gate opening near the low work function region. The thickness of the second work function layer is less than the thickness of the first work function layer, and the metal gate also covers the surface of the second work function layer.

5. A method for forming a metal gate structure, characterized in that, include: A substrate is provided, the substrate having a low work function region and a high work function region, and a gate dielectric layer is formed on the substrate in the high work function region and the low work function region; A first work function layer and a metal gate are formed, wherein the first work function layer is located on the gate dielectric layer in the high work function region, and the metal gate is located on the gate dielectric layer in the first work function layer and the low work function region.

6. The method for forming a metal gate structure as described in claim 5, characterized in that, Before forming the first work function layer and the metal gate, the method for forming the metal gate structure further includes: A lightly doped drain region and a lightly doped source region are formed sequentially. The lightly doped drain region is located in the substrate on the side of the low work function region away from the high work function region, and the lightly doped source region is located in the substrate on the side of the high work function region away from the low work function region. A first halo injection region and a second halo injection region are formed sequentially. The first halo injection region is located in the substrate of the lightly doped drain region near the low work function region and overlaps with the substrate portion of the low work function region. The second halo injection region is located in the substrate of the lightly doped source region near the high work function region and overlaps with the substrate portion of the high work function region. The dose of dopant ions in the first halo injection region is greater than the dose of dopant ions in the second halo injection region.

7. The method for forming a metal gate structure as described in claim 6, characterized in that, The method for sequentially forming the first halo injection region and the second halo injection region includes: A virtual gate, a hard mask layer, and a patterned first photoresist layer are sequentially formed. The virtual gate is located on the gate dielectric layer, the hard mask layer covers the top surface of the virtual gate, and the patterned first photoresist layer covers the hard mask layer of the high work function region and the lightly doped source region. Using the patterned first photoresist layer as a mask, the substrate on the side of the lightly doped drain region near the low work function region is ion implanted using a first tilted ion implantation process to form the first halo implantation region. Remove the patterned first photoresist layer; A patterned second photoresist layer is formed on the substrate, the patterned second photoresist layer covering the hard mask layer of the low work function region and the lightly doped drain region; Using the patterned second photoresist layer as a mask, the substrate on the side of the lightly doped source region near the high work function region is ion implanted using the second tilted ion implantation process to form the second halo implantation region; Remove the patterned second photoresist layer; An annealing process is performed on the substrate.

8. The method for forming a metal gate structure as described in claim 5, characterized in that, The method of forming the first work function layer and the metal gate includes: An interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer being located on the substrate on both sides of the virtual gate; Remove the hard mask layer and the dummy gate to form a gate opening that exposes the gate dielectric layer; A first work function layer and a metal gate are formed in the gate opening. The first work function layer covers the gate dielectric layer in the high work function region and extends to cover one sidewall of the gate opening near the high work function region. The metal gate covers the surface of the first work function layer and the gate dielectric layer in the low work function region, and the top surface of the metal gate is flush with the top surface of the first work function layer.

9. The method for forming a metal gate structure as described in claim 8, characterized in that, The method of forming the first work function layer and the metal gate in the gate opening includes: A first work function material layer is formed, which covers the bottom and sidewalls of the gate opening; Remove the first work function material layer on the low work function region at the bottom of the gate opening, and remove the first work function material layer on the sidewall of the gate opening near the low work function region; A metal gate material layer is formed, which covers the first work function material layer and the gate dielectric layer of the low work function region, and the top surface of the metal gate material layer is higher than the top surface of the interlayer dielectric layer. A planarization process is performed to remove the metal gate material layer on the interlayer dielectric layer to form a metal gate, while retaining the first work function material layer on the high work function region in the gate opening to form the first work function layer.

10. The method for forming a metal gate structure as described in claim 8, characterized in that, The method of forming the first work function layer and the metal gate in the gate opening includes: A first work function material layer is formed, which covers the bottom and sidewalls of the gate opening; Remove the first work function material layer on the low work function region at the bottom of the gate opening, and remove the first work function material layer on the sidewall of the gate opening near the low work function region; A second work function material layer is formed, which covers the first work function material layer and the gate dielectric layer of the low work function region, and extends to cover the sidewall of the gate opening near the low work function region; A metal gate material layer is formed, which covers the second work function material layer, and the top surface of the metal gate material layer is higher than the top surface of the interlayer dielectric layer; A planarization process is performed to remove the metal gate material layer on the interlayer dielectric layer to form a metal gate, and to retain the second work function material layer on the low work function region in the gate opening to form a second work function layer, and to retain the second work function material layer and the first work function material layer on the high work function region in the gate opening to form a first work function layer.

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