An efficient ac power line zero-crossing detection chip

Abstract

This invention relates to the field of pulse circuit technology and discloses a high-efficiency AC power line zero-crossing detection chip, including a path selection module, a signal processing module, and a driving module. The path selection module switches the charging circuit according to the potential of the internal power supply capacitor. The signal processing module uses a feedback loop to adjust the switching level of the sampling branch and generate a zero-crossing trigger pulse signal. The driving module responds to the zero-crossing trigger pulse signal by segmentally turning on the internal power supply capacitor and the external energy supply capacitor in the initial and subsequent stages of the zero-crossing point. This invention solves the contradiction between the ultra-high input impedance sampling environment and the driving strength through a controlled hysteresis window and a segmented current injection mechanism, suppresses signal jitter, improves the timing accuracy of zero-crossing detection, and effectively reduces the static power consumption of the system.

Description

Technical Field

[0001] This invention belongs to the field of pulse circuit technology, and in particular relates to a high-efficiency AC power line zero-crossing detection chip. Background Technology

[0002] Current AC power line zero-crossing detection is a digital information synchronization transmission technology used to extract the time reference for AC voltage crossing a reference ground level, providing a synchronization carrier for carrier communication and phase control. In engineering designs that prioritize low standby power consumption, megaohm-level current-limiting resistors are typically selected at the sampling front end to limit the available charge in the sampling circuit to the microampere level. Mainstream solutions use Zener diodes for clamping protection, causing redundant charge after the energy storage terminal voltage crosses the threshold to dissipate as heat through parallel branches, limiting the system's energy conversion efficiency. For example, a prior art bidirectional AC power line zero-crossing detection chip, circuit, and method uses a Zener diode at the input to clamp and prevent device damage. However, when the energy storage capacitor voltage exceeds the Zener diode clamping voltage, the Zener diode conducts, consuming excess energy, causing the zero-crossing detection chip to fail. The chip's actual efficiency is low (<50%). If a large capacitor is used to collect energy, the charging power will be insufficient in one cycle, and the voltage will be insufficient to discharge at a large current, thus failing to drive the external optocoupler and affecting the normal functioning of the chip. Due to the cutoff characteristics of the rectifier branch near zero, the sampling point potential is in a floating state in the AC zero-crossing interval, making the synchronization signal susceptible to random power line noise interference. The conventional approach is to use a high-speed comparator to improve detection accuracy, but its internally integrated bias current source generates a continuous static current demand. For example, in order to improve the accuracy of the judgment point, a comparator is needed to compare the input signal, which consumes 5uA to 10uA of static power consumption, further reducing the chip efficiency. Under weak energy supply conditions, the voltage of the energy storage capacitor will drop below the logic flip threshold, causing the zero-crossing pulse signal to be lost.

[0003] In complex power grid operating conditions, in addition to the physical constraints imposed by the limitations of conventional current limiting architectures and packaging structures, existing technologies also have shortcomings in software-level control methods. For example, Chinese invention patent CN223870735U discloses a zero-crossing detection circuit with dual-channel zero-crossing output. The aforementioned solution mainly relies on a static hardware path composed of a fixed RC network and a comparator to capture zero crossings. It lacks software control methods based on the dynamic characteristics of the power grid and adaptive feedback adjustment logic. When the power grid exhibits strong harmonic interference or drastic fluctuations in source impedance, the control logic based solely on an ideal sine wave and a constant threshold preset suffers from logic oscillation and severe time base drift due to a fundamental mismatch between the underlying preset premise and the actual harsh operating conditions. It is impossible to dynamically reconstruct the switching level through internal logic. Under the objective conditions of weak charge constraints and high-noise environments, it is difficult to maintain the accuracy of pulse edge timing.

[0004] Therefore, the technical problem to be solved by this invention is how to achieve signal discrimination with ultra-low static power consumption while maintaining high input impedance, and how to generate synchronous pulses with controlled pulse width and high driving capability. Summary of the Invention

[0005] This invention provides a high-efficiency AC power line zero-crossing detection chip, comprising: The path selection module is used to monitor the terminal voltage of the internal power supply capacitor, and when the terminal voltage is lower than the internally fixed preset start-up threshold, it conducts the current-limiting path from the AC signal input terminal to the internal power supply capacitor, and when the terminal voltage is higher than the preset start-up threshold, it selects the storage path from the AC signal input terminal to the external energy supply capacitor. The signal processing module, connected to the path selection module, is used to adjust the switching level of the sampling branch according to the feedback loop in order to establish a hysteresis comparison window and output a zero-crossing trigger pulse signal. The driving module is connected to the internal power supply capacitor, the external energy supply capacitor, and the signal processing module, respectively, and is used to enable the segmented discharge timing based on the logic edge of the zero-crossing trigger pulse signal. The segmented discharge timing includes: at the rising edge of the zero-crossing trigger pulse signal, opening the first current path from the internal power supply capacitor to the optocoupler, and opening the second current path from the external energy supply capacitor to the optocoupler after a preset delay time, so as to maintain the conduction current of the optocoupler through charge superposition.

[0006] Preferably, the path selection module includes a level comparator and a path switching transistor; the sampling terminal of the level comparator is connected to the CC port, and is used to perform amplitude determination on the sampled voltage of the internal power supply capacitor at the CC port and the preset start-up threshold, and output a switching control level; the path switching transistor is connected to the level comparator, and is used to cut off the charging circuit of the external energy supply capacitor during the chip start-up stage according to the switching control level, so that the energy of the AC signal input terminal is concentrated to the internal power supply capacitor until the terminal voltage of the internal power supply capacitor crosses the reference switching voltage of the level comparator.

[0007] Preferably, the signal processing module includes a feedback adjustment unit and a pulse shaping unit; the feedback adjustment unit is used to extract the discharge state characteristics of the drive module and generate a feedback bias current to change the switching threshold of the sampling branch; the pulse shaping unit is connected to the feedback adjustment unit and is used to perform slope compensation on the detection level of the AC signal input terminal according to the feedback bias current, so that the logic edge of the zero-crossing trigger pulse signal is anchored in the AC voltage zero-position region.

[0008] Preferably, the pulse shaping unit includes a first control transistor, a second control transistor, and a logic gate circuit; the logic gate circuit is used to acquire the AC sampling voltage and control the gate potentials of the first and second control transistors to change the current sinking amount of the sampling branch when the sampling voltage crosses a preset start-up threshold.

[0009] Preferably, the driving module includes a timing logic circuit, a first discharge switch, and a second discharge switch; the timing logic circuit is connected to the signal processing module and is used to trigger the internal RC delay circuit when the zero-crossing trigger pulse signal changes, and output a supplementary driving signal after a preset delay time is reached; the first discharge switch is used to respond to the zero-crossing trigger pulse signal and conduct the discharge circuit from the internal power supply capacitor to the optocoupler; the second discharge switch is used to respond to the supplementary driving signal and conduct the parallel path from the external energy supply capacitor to the optocoupler.

[0010] Preferably, the internal power supply capacitor is connected to the CC port through the chip pin, and its capacity is 30nF; the external energy supply capacitor is connected through the chip pin, and its capacity is not less than 220nF.

[0011] Preferably, the path selection module includes two sets of enhanced switching transistors. The enhanced switching transistors are connected between the AC signal input terminal and the external energy supply capacitor. The on-resistance of the enhanced switching transistors is configured to a low-resistance state to improve charging efficiency. The static charging current entering the chip is limited to within 50μA by a current-limiting resistor group connected to the front end of the AC signal input terminal.

[0012] Preferably, the drive module further includes an active clamping unit connected to the drive output terminal. During the non-pulse period of the zero-crossing trigger pulse signal, the drive output terminal is in a normal charging state. The active clamping unit locks the potential of the drive output terminal at the power supply voltage potential, so that the positive and negative ends of the optocoupler remain at the same potential to discharge the junction charge of the optocoupler. During the pulse period, the internal power supply capacitor draws current through the optocoupler.

[0013] Preferably, the high-efficiency AC power line zero-crossing detection chip signal processing module includes a Schmitt trigger. The signal processing module uses the inherent detection voltage threshold of the Schmitt trigger as a reference for adjusting the switching level. The Schmitt trigger independently performs level comparison to avoid the independent bandgap reference power node that generates continuous standby current, thereby achieving extremely low static power consumption.

[0014] Compared with existing technologies, the high-efficiency AC power line zero-crossing detection chip of this invention has the following advantages: 1. In AC power line zero-crossing detection, the path selection module dynamically switches the charging circuit by monitoring the power supply voltage status, prioritizing ensuring that the power supply voltage crosses the digital logic start threshold. It utilizes the remaining time of the AC cycle to replenish energy to the backup energy storage terminal, achieving on-demand charge distribution under weak current constraints. This fundamentally resolves the contradiction between ultra-high input impedance and drive pulse establishment speed. The chip charging path control of this invention first uses a small capacitor to store energy, rapidly charging the VDD voltage to the required value, then uses a large capacitor to receive excess power. During discharge, the high voltage of the small capacitor is discharged first, followed by a brief high current output to initiate the discharge. After the optocoupler is activated, switching to a large capacitor at a low voltage and outputting a small current to maintain the optocoupler's conduction state significantly improves the circuit's efficiency and perfectly matches the optocoupler's driving requirements. It can fully utilize the charging current of the entire AC cycle. Under the same application conditions (220Vac, 3M input resistance, 56nF main energy storage capacitor), this solution can achieve an efficiency of 70%, which is 100% higher than the 35% efficiency of existing chips. Under the same input resistance conditions, the amount of energy stored in the capacitor can increase by 100%, and the output pulse width is widened by two times. It has lower requirements for the performance of the subsequent microprocessor and is more applicable.

[0015] 2. The signal processing module utilizes a feedback adjustment mechanism to establish a controlled resistor-capacitor delay path in the sampling branch. By alternately guiding the input terminal to ground, the sampling potential is locked, making the input voltage flipping characteristics match the detection threshold of the internal trigger logic. This effectively suppresses logic oscillation and signal jitter in high-impedance sampling environments, ensuring the timing accuracy of zero-crossing pulse edges. Furthermore, through a cleverly designed circuit structure, all comparison operations are implemented by Schmitt triggers, achieving a chip static power consumption of <1uA (far less than the 5uA~10uA of existing solutions), further improving efficiency.

[0016] 3. The drive module, in conjunction with the path selection module, establishes a segmented discharge timing sequence. In the initial stage of the zero crossing, the main energy storage terminal provides a high-intensity instantaneous drive current to cross the conduction dead zone of the optocoupled load, triggering the parallel output mode of the main and backup energy storage terminals to extend the charge release time, achieving controlled widening of the output pulse width, and reducing the performance requirements of the subsequent information processing unit on the pulse capture frequency. Attached Figure Description

[0017] Figure 1 This is the overall logical architecture and segmented injection control flowchart of the system of the present invention; Figure 2 This is a logic block diagram of the adaptive feedback adjustment and hysteresis window establishment of the present invention; Figure 3 This is a topology diagram showing the internal functional module distribution and external pin connections of the chip in this invention; Figure 4 This is a diagram of the timing logic and pulse conversion structure of the signal processing core of this invention; Figure 5 This is a controlled charging switching logic circuit diagram of the path selection module of the present invention; Figure 6 This is the peripheral circuit diagram of the power line zero-crossing detection system of the present invention in a typical application scenario. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0019] It should be noted that all directional and positional terms used in this invention, such as: up, down, left, right, front, back, vertical, horizontal, inner, outer, top, bottom, transverse, longitudinal, center, etc., are only used to explain the relative positional relationship and connection between components in a specific state (as shown in the accompanying drawings). They are only for the convenience of describing this invention and do not require that this invention be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention. In addition, the descriptions of "first," "second," etc., in this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated.

[0020] In the description of this invention, unless otherwise explicitly specified and limited, the terms installation, connection, and linking should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood in conjunction with the specific circumstances.

[0021] In the description of this specification, references to the terms "an embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example, and the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0022] A high-efficiency AC power line zero-crossing detection chip, comprising: The path selection module is used to monitor the terminal voltage of the internal power supply capacitor, and when the terminal voltage is lower than the internally fixed preset start-up threshold, it conducts the current-limiting path from the AC signal input terminal to the internal power supply capacitor, and when the terminal voltage is higher than the preset start-up threshold, it selects the storage path from the AC signal input terminal to the external energy supply capacitor. The signal processing module, connected to the path selection module, is used to adjust the switching level of the sampling branch according to the feedback loop in order to establish a hysteresis comparison window and output a zero-crossing trigger pulse signal. The driving module is connected to the internal power supply capacitor, the external energy supply capacitor, and the signal processing module, respectively, and is used to enable the segmented discharge timing based on the logic edge of the zero-crossing trigger pulse signal. The segmented discharge timing includes: at the rising edge of the zero-crossing trigger pulse signal, opening the first current path from the internal power supply capacitor to the optocoupler, and opening the second current path from the external energy supply capacitor to the optocoupler after a preset delay time, so as to maintain the conduction current of the optocoupler through charge superposition.

[0023] Preferably, the path selection module includes a level comparator and a path switching transistor; the sampling terminal of the level comparator is connected to the CC port, and is used to perform amplitude determination on the sampled voltage of the internal power supply capacitor at the CC port and the preset start-up threshold, and output a switching control level; the path switching transistor is connected to the level comparator, and is used to cut off the charging circuit of the external energy supply capacitor during the chip start-up stage according to the switching control level, so that the energy of the AC signal input terminal is concentrated to the internal power supply capacitor until the terminal voltage of the internal power supply capacitor crosses the reference switching voltage of the level comparator.

[0024] Preferably, the signal processing module includes a feedback adjustment unit and a pulse shaping unit; the feedback adjustment unit is used to extract the discharge state characteristics of the drive module and generate a feedback bias current to change the switching threshold of the sampling branch; the pulse shaping unit is connected to the feedback adjustment unit and is used to perform slope compensation on the detection level of the AC signal input terminal according to the feedback bias current, so that the logic edge of the zero-crossing trigger pulse signal is anchored in the AC voltage zero-position region.

[0025] Preferably, the pulse shaping unit includes a first control transistor, a second control transistor, and a logic gate circuit; the logic gate circuit is used to acquire the AC sampling voltage and control the gate potentials of the first and second control transistors to change the current sinking amount of the sampling branch when the sampling voltage crosses a preset start-up threshold.

[0026] Preferably, the driving module includes a timing logic circuit, a first discharge switch, and a second discharge switch; the timing logic circuit is connected to the signal processing module and is used to trigger the internal RC delay circuit when the zero-crossing trigger pulse signal changes, and output a supplementary driving signal after a preset delay time is reached; the first discharge switch is used to respond to the zero-crossing trigger pulse signal and conduct the discharge circuit from the internal power supply capacitor to the optocoupler; the second discharge switch is used to respond to the supplementary driving signal and conduct the parallel path from the external energy supply capacitor to the optocoupler.

[0027] Preferably, the internal power supply capacitor is connected to the CC port through the chip pin, and its capacity is 30nF; the external energy supply capacitor is connected through the chip pin, and its capacity is not less than 220nF.

[0028] Preferably, the path selection module includes two sets of enhanced switching transistors. The enhanced switching transistors are connected between the AC signal input terminal and the external energy supply capacitor. The on-resistance of the enhanced switching transistors is configured to a low-resistance state to improve charging efficiency. The static charging current entering the chip is limited to within 50μA by a current-limiting resistor group connected to the front end of the AC signal input terminal.

[0029] Preferably, the drive module further includes an active clamping unit connected to the drive output terminal. The active clamping unit is used to drive the output terminal to be in a normal charging state during the non-pulse period of the zero-crossing trigger pulse signal. The active clamping unit locks the potential of the drive output terminal at the power supply voltage potential, so that the positive and negative ends of the optocoupler remain at the same potential to discharge the junction charge of the optocoupler. During the pulse period, the internal power supply capacitor draws current through the optocoupler.

[0030] Preferably, the high-efficiency AC power line zero-crossing detection chip signal processing module includes a Schmitt trigger. The signal processing module uses the inherent detection voltage threshold of the Schmitt trigger as a reference for adjusting the switching level. The Schmitt trigger independently performs level comparison to avoid the independent bandgap reference power node that generates continuous standby current, thereby achieving extremely low static power consumption.

[0031] Preferably, the high-efficiency AC power line zero-crossing detection chip includes six ports: VDD, VSS, L, N, VDD2, and CC. Internally, it includes: a charging and rectification module, which rectifies and limits the AC input sine wave and charges the chip power supply; a signal processing module, which processes the rectified signal to generate AC power line zero-crossing edge pulses; a driving module, which generates zero-crossing pulses based on AC power line zero-crossing edge pulses; and a path selection module, which adjusts different charging paths based on the VDD voltage to ensure the chip fully utilizes the charging current throughout the entire cycle.

[0032] Preferably, the signal processing module includes an edge-pulse converter, an RS flip-flop, a timer, a driver, an LVDT (low voltage detection module), and a NAND gate; the path selection module includes a NOR gate, a Schmitt trigger, and a path switch. Through the above structure, the drawing features are converted into text descriptions, thereby establishing a clear correspondence between detailed port labels, component symbols, and Chinese functional modules.

[0033] Preferably, all comparison operations are implemented by a Schmitt trigger, so that the input signal is matched to the detection voltage of the Schmitt trigger (approximately 1V).

[0034] Preferably, the high-efficiency AC power line zero-crossing detection chip is connected to an external application circuit through six ports. The application circuit includes a current-limiting resistor, an external main energy storage capacitor, an external backup energy storage capacitor, and an optocoupler (OC).

[0035] It should be noted that, in order to balance the diverse application requirements of extremely high integration and high-power external drive, the internal power supply capacitor and the external energy supply capacitor of this invention have flexible configuration in physical topology. In the low-power fully integrated architecture, the internal power supply capacitor is connected to the CC port through the chip pin, and its capacity is not less than 30nF, in conjunction with the external energy supply capacitor with a capacity of approximately 220nF. In the preferred application scenario of high-capacity charge throughput, the internal power supply capacitor is actually an independent main energy storage capacitor physically connected to the VDD and CC pins, while the external energy supply capacitor is a backup energy storage capacitor physically connected to the VDD2 pin. The capacity base of the two can be flexibly adapted to the nanofarad level (such as the range of 30nF to 220nF) according to the driving requirements of the external load. This flexible energy storage medium configuration mechanism decouples the strict binding of specific capacitance value and package form in theory, enabling the energy conversion efficiency of the whole machine to jump to 70%.

[0036] Example 1: In an industrial power line carrier communication scenario relying on a megaohm-level high-impedance front-end to extract the phase synchronization reference, the system faces the contradiction of limited available charge in the sampling loop at the microampere level and the need for milliampere-level drive current at the moment of startup of the external isolation optocoupler. A high-efficiency AC power line zero-crossing detection chip is connected between the AC signal input terminal and the optocoupler. The chip's path selection module monitors the terminal voltage of an internal power supply capacitor connected to the CC port with a capacitance of not less than 30nF. When the chip is powered on and the terminal voltage of the internal power supply capacitor is lower than a preset startup threshold, the path selection... The path selection module opens the current-limiting path from the AC signal input terminal to the internal power supply capacitor. Through the current-limiting resistor group R1, R2, R3, and R4 connected to the front end of the AC signal input terminal, the static charging current entering the chip is limited to within 50μA, causing the energy from the AC signal input terminal to be concentrated in the internal power supply capacitor. This continues until the voltage at the internal power supply capacitor crosses the reference switching voltage of the level comparator. The path selection module then cuts off the charging branch of the internal power supply capacitor and opens the storage path from the AC signal input terminal to an external energy replenishment capacitor with a capacity of approximately 220nF. The remaining time of the AC cycle is then utilized. The system supplies energy to an external energy supply capacitor, decoupling the rapid voltage establishment requirement during system startup from the energy reserve requirement during signal maintenance in a single-input architecture. In the specific hardware wiring, the path selection module includes enhanced switching transistors NM2 and NM3, which are connected between the AC signal input and the external energy supply capacitor. Furthermore, enhanced switching transistors NM2 and NM3 exhibit extremely low on-resistance when in the conducting state to improve charging efficiency. When the terminal voltage monitoring circuit determines that the internal power supply capacitor potential at the CC port has reached the preset startup value... At the threshold, the output control signal drives the enhancement switching transistor to switch the charging current from the internal power supply circuit to the external storage path. By using the enhancement switching transistor to switch between different charging paths, it is ensured that there will be no drastic fluctuations in the AC input voltage at the moment of switching. The system uses the physical current limiting characteristics of the front-end current limiting resistor group R1, R2, R3 and R4 to keep the static charging current entering the chip constant within the limit value of 50μA. This hardware current limiting method uses the resistor network to set the static operating point, without the need for additional active bias circuits, thereby eliminating the introduction of additional standby power consumption.

[0037] As the AC signal approaches the zero-voltage region, the rectifier branch enters a cutoff state, causing the sampling point potential to float. At this time, the signal processing module extracts the discharge state characteristics of the drive module and generates a feedback bias current. Based on the slope of the detection level compensation at the AC signal input terminal according to this feedback bias current, the signal processing module adjusts the switching level of the sampling branch by changing the current intake of the sampling branch, establishing a controlled hysteresis comparison window and outputting a zero-crossing trigger pulse signal with its logic edge anchored in the AC voltage zero-voltage region. This zero-crossing trigger pulse signal is input to the drive module. Based on the rising edge of this zero-crossing trigger pulse signal, the drive module triggers the first discharge switch, conducting the first current path from the internal power supply capacitor (which is in a high-potential state) to the optocoupler, providing instantaneous current across the optocoupler's conduction dead zone. Simultaneously, the timing logic circuit inside the drive module triggers the internal RC delay circuit to start timing when the zero-crossing trigger pulse signal transitions. When the preset delay time is reached... The output supply drive signal triggers the second discharge switch, which opens the second injection path by connecting the external energy supply capacitor to the parallel path of the optocoupler.

[0038] The zero-crossing trigger pulse signal output by the aforementioned signal processing module provides the basis for determining the timing of the drive module. The ladder-like charge distribution of the main and backup capacitors constructed by the path selection module during the non-pulse period provides charge support for the segmented current injection mechanism of the drive module. The drive module uses the high-voltage discharge of the internal power supply capacitor to cross the dead zone of the optocoupler load and uses the large-capacity energy storage of the external energy replenishment capacitor to maintain the conduction current through charge superposition, so that the output terminal generates a pull-down level pulse with controlled pulse width expansion. During the non-pulse period of the zero-crossing trigger pulse signal, the drive output terminal is in a normal charging state. The active clamping unit locks the potential of the drive output terminal at the power supply voltage VDD. At this time, the potentials of the positive and negative terminals of the optocoupler are both the power supply voltage VDD, thereby discharging the charge of the optocoupler junction. During the pulse period, the power supply voltage VDD begins to draw current from the internal power supply capacitor C1 through the optocoupler, so that the optocoupler maintains a longer conduction time under the same AC cycle charging power and stabilizes the overall static current consumption of the chip below 1μA during the non-pulse period.

[0039] Example 2: The industrial inverter main control board test platform is connected to a power frequency AC signal with a peak voltage of 311V. This power frequency AC signal is superimposed with Gaussian white noise with a signal-to-noise ratio of 20dB and power frequency harmonic interference with an amplitude of 15% of the input fundamental frequency. The load end of the test platform is connected to an optocoupler with a turn-on dead zone voltage of 1.15V. The chip path selection module and the drive module work together. Based on the increase in the forward voltage drop of the optocoupler's light-emitting diode with the increase of ambient temperature, the amount of transient impulse charge required for the initial conduction of the optocoupler is calculated, and the coordinated configuration of the chip's internal segmented delay and external energy storage is established. The internal delay time td of the drive module is determined by the charging of the internal integrated capacitor of less than 0.1pF by the nanoampere-level microcurrent generated by the internal bias source, so that the internal delay time td reaches 2μs. At the same time, considering that driving the optocoupler requires a transient current of 10mA within these 2μs, the picofarad-level capacitor under low voltage conditions cannot physically provide enough energy. Therefore, the system configures the internal power supply capacitor C1 connected to the CC port with a capacity of 30nF to meet the initial high-intensity drive requirements.

[0040] A comparative system of physical samples with different architecture configurations was established. The control group used a pure on-chip picofarad-level energy storage architecture without external picofarad capacitors to drive the load. When the AC signal crossed the zero-point region, due to the extremely low energy storage of the picofarad capacitors, the discharge current was far below the 10mA level required for the optocoupler to turn on, and the optocoupler could not conduct normally, resulting in severe loss of the zero-crossing trigger pulse signal at the output end. The experimental group adopted the collaborative architecture of this invention, with the internal power supply capacitor C1 set to 30nF and the external energy supply capacitor C2 set to 220nF. At the moment of zero-crossing trigger, the drive module turned on the first discharge switch, and the 30nF internal power supply capacitor C1 injected an initial high-intensity current of 10mA into the optocoupler, significantly shortening the optocoupler turn-on delay time to 2.1μs. After the internal bias source charged the less than 0.1pF integrated capacitor on the chip for a preset delay time of 2μs, the drive module turned on the 220nF external energy supply capacitor C2 to release charge and perform parallel power supply, and the optocoupler pulse width stably broadened to 2.8ms.

[0041] Test results confirm that the design approach of using a nanoampere-level microcurrent generated by an internal bias source combined with an on-chip microcapacitor to achieve precise 2μs delay control, and combining it with an external 30nF large-capacity capacitor to solve the physical bottleneck of transient high current, is entirely correct. This segmented discharge sequence successfully overcomes the optocoupler conduction dead zone while maintaining extremely low static charge consumption. Under the input condition of superimposed Gaussian white noise, the zero-crossing trigger pulse signal suppresses the jitter voltage to within 3.1mV. The signal processing module extracts the discharge state characteristics and outputs the feedback bias current compensation detection level slope. The chip outputs a milliampere-level transient drive pulse while maintaining a static charging current of less than 1μA.

[0042] Example 3: This example combines Figures 1 to 6 This paper describes the logic and circuit implementation of a high-efficiency AC power line zero-crossing detection chip, such as... Figure 1 As shown, the logic flow of the high-efficiency AC power line zero-crossing detection chip includes: introducing AC signal and energy at the AC signal input terminal; monitoring the terminal voltage by the path selection module and switching the charging circuit accordingly; conducting the current-limiting path when the terminal voltage is lower than the preset start-up threshold to enable the internal power supply capacitor to perform current-limiting aggregation during the start-up phase; and selecting the storage path from the AC signal input terminal to the external energy supply capacitor when the terminal voltage is higher than the preset start-up threshold. Simultaneously, the path selection module is connected to the signal processing module, which adjusts the switching level of the sampling branch based on the feedback loop to establish a controlled hysteresis comparison window and output a zero-crossing trigger pulse signal. The drive module responds to the logic edge of the zero-crossing trigger pulse signal to enable the segmented discharge sequence. At the rising edge, it opens the first current path from the internal power supply capacitor to the optocoupler, and after a preset delay time, it opens the second current path from the external energy supply capacitor to the optocoupler. By executing the segmented discharge sequence, it provides the conduction current, ultimately using the charge superposition effect to maintain the conduction state of the optocoupler.

[0043] like Figure 2 As shown, the feedback regulation logic of the signal processing module captures the transient voltage of the AC signal through the sampling branch and injects transient charge into the feedback loop. The feedback loop senses the drain-source voltage drop of the power transistor in the drive module and outputs a current proportional to the voltage difference through the transconductance amplifier. This adjusts the tail current source bias and, in conjunction with the digital-to-analog conversion network, changes the input resistance value using the trimming control word. The phase and level deviation are compensated by fixing the trimming control word. The flip threshold determined by the feedback loop is used to establish a hysteresis comparison window to suppress signal jitter caused by random power line noise, thereby generating a precise logic edge trigger signal and forming a zero-crossing trigger pulse signal. The logic edge of this signal further guides the drive module to start the subsequent segmented discharge sequence.

[0044] like Figure 3 As shown, the overall circuit topology of the chip includes AC input terminals L and N, followed by a rectifier bridge composed of diodes D1, D2, D3, and D4, and a clamping protection branch composed of Zener diodes DZ1 and DZ2 connected in parallel. The circuit integrates... Path switching module and The signal processing module has chip pin ports covering CC, VDD2, VDD, and the reference ground level VSS; among them, power transistors NM1, NM2, and NM3 are controlled by The module enables dynamic switching of charge storage paths. The sampling signal at the input end is extracted by Schmitt triggers I1 and I2, and then sent to the signal processing core for logic conversion through inverters I3 and I4. The drive output end is connected to the external load branch through power transistor NM6 and resistor R1.

[0045] like Figure 4 As shown, the internal circuit structure of the signal processing module is that Schmitt triggers I1 and I2 receive signals input through the L and N ports and reference the ground level VSS. Their output terminals are connected to two symmetrically distributed edge-pulse converters I3 and I4. The generated pulse signals are summarized by NOR gate I5 and input to the set terminal S of RS trigger I7. The reset terminal R of RS trigger I7 is connected to the low voltage detection module LVDTI6 to monitor the power supply status. Its output terminal Q drives the driver I9 and the timer I8 respectively, and then controls the conduction of the driver transistor NM6 and the operation of the current injection switching transistor NM1 according to the logic timing, realizing the segmented driving logic based on the superposition of charges of VDD, VDD2 and CC ports.

[0046] like Figure 5 As shown, the path switching module The internal logic includes a Schmitt trigger I10 connected to the internal power supply VDD by a voltage divider resistor network. Its output signal is connected to one input of AND gates I11 and I12 via inverter I13. The other input of the AND gates receives the synchronization pulse signal processed by the preceding inverters I3 and I4. The control level generated by this logic combination drives the gates of power transistors NM2 and NM3, thereby controlling the conduction of the charging circuit from the AC input terminal L or N to the external energy supply port VDD2 according to the internal potential state. The entire logic judgment process refers to the VDD power supply level inside the chip.

[0047] like Figure 6As shown, in the specific application circuit wiring of the chip, the AC input terminal L is connected to the input pin of chip I1 via current-limiting resistors R1, R2, R3, and R4 in sequence. The chip pin is externally connected to an external energy supply capacitor C2 with a capacity of 220nF and an internal power supply capacitor C1 with a capacity of 30nF. The path selection module monitors the potential of the CC pin in real time. Before the potential of the CC pin reaches the set threshold, the charging path from the AC signal input terminal to the internal power supply capacitor C1 is selected so that energy is preferentially concentrated in the internal power supply capacitor C1. After the potential of the CC pin reaches the set threshold, the storage path from the AC signal input terminal to the external energy supply capacitor C2 is selected, and the energy of the external energy supply capacitor C2 is replenished by the remaining time of the AC cycle. The drive output pin CC of the chip is connected to the light-emitting side input terminal of the optocoupler OC via an external resistor R5. The light-receiving side output terminal of the optocoupler OC is connected to the logic power supply VCC through a pull-up resistor R6, and the final signal output terminal OUT is led out with the help of a filter capacitor, thereby forming a power line zero-crossing detection system with high-efficiency charge management function.

[0048] Example 4: Industrial power line carrier communication network nodes are exposed to a wide temperature range and strong harmonic interference environment. Ambient temperature drift and line impedance fluctuations cause phase shifts in the zero-crossing detection of the fixed threshold. The chip's signal processing module extracts the discharge state characteristics of the drive module and compensates for the detection level slope through a feedback adjustment unit. This feedback adjustment unit monitors the drain-source potential of the first discharge switch in the drive module, captures the drain-source voltage drop during the conduction of the first discharge switch, and uses a built-in transconductance amplifier to convert the drain-source voltage drop into a proportional feedback bias current. According to the formula Determine the feedback bias current The value of, among which, This is the fixed transconductance value of the transconductance amplifier. The measured drain-source voltage drop of the first discharge switch.

[0049] The pulse shaping unit inside the signal processing module receives the feedback bias current. The current is injected into the sampling branch node where the AC signal input is located, changing the total current flowing through the input resistor of the sampling branch. This causes a shift in the equivalent flip level of the sampling branch when the AC signal approaches zero potential on the falling edge, offsetting the input offset voltage of the level comparator caused by temperature drift and the signal phase delay introduced by the high impedance at the front end. The pulse shaping unit adjusts the pulse based on the injected feedback bias current. The comparison result between the combined node potential and the reference zero potential outputs a zero-crossing trigger pulse signal for state reversal, and the feedback bias current generated by the discharge state is obtained. A controlled hysteresis comparison window is established. The chip anchors the logic edge of the zero-crossing trigger pulse signal to the zero-position region of the AC voltage, eliminating phase errors introduced by environmental factors. The signal processing module uses the feedback bias current to establish the hysteresis comparison window based on the specific node potential superposition rule. The pulse shaping unit contains a current injection node connected in parallel with the sampling branch. After the feedback adjustment unit outputs the feedback bias current injection node, a compensation voltage drop is generated on the equivalent input resistance of the sampling branch. Within half a working cycle when the AC signal crosses the zero position interval, the compensation voltage drop is superimposed in the opposite direction with the original AC sampling voltage, causing the equivalent flip level at the input of the level comparator to physically shift in the first polarity direction. Within half a working cycle, a physical shift in the opposite direction is generated. The sum of the absolute values ​​of the two reverse potential shifts directly constitutes the physical voltage width of the hysteresis comparison window. The upper limit of the value is uniquely limited by the product of the fixed transconductance value of the transconductance amplifier and the input resistance value.

[0050] Example 5: In a scenario of mass deployment of industrial power line carrier communication network nodes, considering the physical dispersion of the forward voltage drop of the LEDs in different batches of optocouplers, the system initiates a fixed transconductance value for the transconductance amplifier within the signal processing module before installation. The offline calibration procedure involves the calibration platform injecting a standard sinusoidal excitation voltage into the AC signal input terminal and simultaneously acquiring the initial drain-source voltage drop across the drain-source terminals of the first discharge switch in the drive module. The test probe captures the reference conduction delay time of the optocoupler corresponding to the standard sinusoidal excitation voltage. The calibration platform compares this reference conduction delay time with the preset target communication synchronization timing and generates a time deviation compensation. The algorithm control unit adjusts the tuning control word of the internal digital-to-analog converter network based on this time deviation compensation, changing the resistance value connected to the bias resistor array of the transconductance amplifier's tail current source. This makes the actual output current of the transconductance amplifier reach the theoretical bias current required to eliminate the time deviation compensation. The calibration platform uses the communication interface to solidify the final tuning control word that brings the deviation to zero into the chip's one-time programmable read-only memory, completing the fixation of the transconductance value. Hardware structure lock-in to the physical characteristics of a specific batch of optocouplers.

[0051] The calibration platform initiates a pre-calibration procedure on-site based on the preset start threshold of the path selection module. A precision source meter injects a constant stepped test current of 50μA into the AC signal input terminal of the chip. The high-speed voltage acquisition card simultaneously monitors the voltage rise slope of the internal power supply capacitor. When the measured voltage rise slope drops below 5% of the reference slope within three consecutive sampling cycles, the calibration platform determines that the internal parasitic branch of the chip has entered a critical state of leakage current balance and records the peak voltage at this time. The control platform is based on the formula Calculate the toggling threshold of the level comparator, where, The preset start threshold after calibration. A 50mV safety redundancy voltage difference is pre-written into the storage matrix. This 50mV redundancy value is determined based on the typical input offset voltage of the chip's internal level comparator and the power supply ripple coefficient. Specifically, the startup consistency of multiple sample chips is tested in a laboratory environment, and three times the standard deviation is selected as the redundancy limit to prevent frequent logic switching of the path selection module at the startup critical point due to small voltage fluctuations. The calibration platform adjusts this preset startup threshold by fusing the fuse network inside the chip. In the reference voltage generation circuit of the path selection module, the chip identifies the charge accumulation state based on the preset start threshold during operation and switches the storage path from the AC signal input terminal to the external energy supply capacitor, thereby eliminating the interference of component manufacturing tolerances on the zero-crossing detection phase accuracy.

[0052] Example 6: In an industrial power line carrier communication network node deployment scenario, random high-frequency noise superimposed on the AC input signal causes logic oscillation of the level comparator when the AC fundamental wave crosses near zero potential. Before installation, the test platform initiates the boundary parameter calibration procedure for the hysteresis comparison window within the signal processing module. A low-frequency triangular wave sweep signal approaching zero potential is injected into the AC signal input terminal, and a broadband random noise sequence with a preset signal-to-noise ratio is simultaneously superimposed. The peak-to-peak amplitude parameter of the broadband random noise sequence is continuously captured by the chip's internal peak detection circuit within a set sampling time window. The control unit reads the peak-to-peak amplitude parameter and calculates the hysteresis voltage width. According to the formula Determine the value of the hysteresis voltage width, where λ is the immunity coefficient stored in the read-only register. This is the peak-to-peak voltage of the broadband random noise sequence output by the peak detection circuit.

[0053] The control unit will hysteresis voltage width The signal is converted into a corresponding digital trimming word. The control bus then sends the digital trimming word to the feedback adjustment unit inside the signal processing module. The feedback adjustment unit changes the equivalent resistance value of the weighted resistor array connected in parallel to the feedback bias current path according to the digital trimming word. By adjusting the current sink of the branch, the absolute voltage difference between the positive and negative flip levels of the sampling branch is anchored to the hysteresis voltage width. The calibration test bench uses the fuse programming port to solidify the digital trim word into the chip's non-volatile memory cell. During the chip's operation, a hysteresis comparison window is established based on the digital trim word. The physical threshold envelope of the zero-crossing trigger pulse signal output by the signal processing module covers the noise level boundary of the input signal. The logical flip action of the system output pulse coincides with the zero-crossing moment of the AC fundamental voltage.

[0054] The embodiments of this application have been described above with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. This application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit of this application and the scope of protection of this invention, and all of these forms are within the protection scope of this application.

Claims

1. A high-efficiency AC power line zero-crossing detection chip, characterized in that, include: The path selection module is used to monitor the terminal voltage of the internal power supply capacitor, and when the terminal voltage is lower than the internally fixed preset start-up threshold, it conducts the current-limiting path from the AC signal input terminal to the internal power supply capacitor, and when the terminal voltage is higher than the preset start-up threshold, it selects the storage path from the AC signal input terminal to the external energy supply capacitor. The signal processing module, connected to the path selection module, is used to adjust the switching level of the sampling branch according to the feedback loop in order to establish a hysteresis comparison window and output a zero-crossing trigger pulse signal. The driving module is connected to the internal power supply capacitor, the external energy supply capacitor, and the signal processing module, respectively, and is used to enable the segmented discharge timing based on the logic edge of the zero-crossing trigger pulse signal. The segmented discharge timing includes: at the rising edge of the zero-crossing trigger pulse signal, opening the first current path from the internal power supply capacitor to the optocoupler, and opening the second current path from the external energy supply capacitor to the optocoupler after a preset delay time, so as to maintain the conduction current of the optocoupler through charge superposition.

2. The high-efficiency AC power line zero-crossing detection chip according to claim 1, characterized in that, The path selection module includes a level comparator and a path switching transistor; the sampling terminal of the level comparator is connected to the CC port, which is used to perform amplitude determination on the sampled voltage of the internal power supply capacitor at the CC port and the preset start threshold, and output the switching control level; The path switching transistor is connected to the level comparator and is used to cut off the charging circuit of the external energy supply capacitor during the chip startup phase according to the switching control level, so that the energy of the AC signal input terminal is concentrated to the internal power supply capacitor until the terminal voltage of the internal power supply capacitor crosses the reference switching voltage of the level comparator.

3. The high-efficiency AC power line zero-crossing detection chip according to claim 1, characterized in that, The signal processing module includes a feedback adjustment unit and a pulse shaping unit; the feedback adjustment unit is used to extract the discharge state characteristics of the drive module and generate a feedback bias current to change the switching threshold of the sampling branch. The pulse shaping unit is connected to the feedback adjustment unit and is used to perform slope compensation on the detection level of the AC signal input terminal according to the feedback bias current, so that the logic edge of the zero-crossing trigger pulse signal is anchored in the AC voltage zero-position region.

4. The high-efficiency AC power line zero-crossing detection chip according to claim 3, characterized in that, The pulse shaping unit includes a first control transistor, a second control transistor, and a logic gate circuit. The logic gate circuit is used to acquire the AC sampling voltage and control the gate potentials of the first and second control transistors to change the current sinking amount of the sampling branch when the sampling voltage crosses a preset start-up threshold.

5. The high-efficiency AC power line zero-crossing detection chip according to claim 1, characterized in that, The driving module includes a timing logic circuit, a first discharge switch, and a second discharge switch. The timing logic circuit is connected to the signal processing module and is used to trigger the internal RC delay circuit when the zero-crossing trigger pulse signal changes, and output a supplementary driving signal after the preset delay time is reached. The first discharge switch is used to respond to the zero-crossing trigger pulse signal and conduct the discharge circuit from the internal power supply capacitor to the optocoupler. The second discharge switch is used to respond to the supplementary driving signal and conduct the parallel path from the external energy supply capacitor to the optocoupler.

6. The high-efficiency AC power line zero-crossing detection chip according to claim 1, characterized in that, The internal power supply capacitor is connected to the CC port through the chip pin, and its capacity is 30nF; the external energy supply capacitor is connected through the chip pin, and its capacity is not less than 220nF.

7. The high-efficiency AC power line zero-crossing detection chip according to claim 1, characterized in that, The path selection module includes two sets of enhanced switching transistors. The enhanced switching transistors are connected between the AC signal input terminal and the external energy supply capacitor. The on-resistance of the enhanced switching transistors is configured to a low-resistance state to improve charging efficiency. The static charging current entering the chip is limited to within 50μA by a current-limiting resistor group connected to the front end of the AC signal input terminal.

8. The high-efficiency AC power line zero-crossing detection chip according to claim 1, characterized in that, The drive module also includes an active clamping unit, which is connected to the drive output terminal. During the non-pulse period of the zero-crossing trigger pulse signal, the drive output terminal is in a normal charging state. The active clamping unit locks the potential of the drive output terminal at the power supply voltage potential, so that the positive and negative ends of the optocoupler remain at the same potential to discharge the junction charge of the optocoupler. During the pulse period, the internal power supply capacitor draws current through the optocoupler.

9. A high-efficiency AC power line zero-crossing detection chip according to claim 1, characterized in that, The high-efficiency AC power line zero-crossing detection chip signal processing module includes a Schmitt trigger. The signal processing module uses the inherent detection voltage threshold of the Schmitt trigger as a reference for adjusting the switching level. The Schmitt trigger independently performs level comparison to avoid the independent bandgap reference power node that generates continuous standby current, thus achieving extremely low static power consumption.

Images