Multi-chip addressing control method, electronic device, storage medium, and program product

Abstract

This invention relates to the field of peripheral control technology, specifically to a multi-chip addressing control method, electronic devices, storage media, and program products. The method includes: receiving a control request and generating a command packet containing a source address, a target address, and command data; splitting the command packet and sending it to different target chips under a synchronous control request, and sending the command packet according to the target address under an asynchronous control request; forwarding the command to the master control chip when the slave chip lacks execution capability; executing the command packet when both the master and slave chips receive the same command data; receiving a response packet and determining the responding chip based on the source address, and outputting the control result. This invention enables directional control, collaborative execution, and response differentiation in multi-chip peripherals.

Description

Technical Field

[0001] This invention relates to the field of peripheral control technology, specifically to multi-chip addressing control methods, electronic devices, storage media, and program products. Background Technology

[0002] As computer peripherals evolve towards higher performance, more complex functions, and more precise control, the use of multiple control chips working in tandem has become increasingly common. For example, in peripherals like keyboards and mice, different chips can handle tasks such as main communication, overall system status control, local function processing, lighting effects driving, key scanning, or auxiliary input processing. This distributes the processing burden across individual chips and supports the parallel operation of more functional modules. While this multi-chip architecture enhances the functional capabilities and responsiveness of peripherals, current control methods typically still distribute commands uniformly across the entire system, lacking clear control paths at the chip level. This results in unclear boundaries of responsibility, command destinations, and response attributions between different chips.

[0003] In practical applications, when a host computer issues commands for lighting effect switching, mode switching, parameter configuration, or combined control, problems often arise such as commands arriving first at chips lacking execution capabilities, multiple chips repeatedly executing the same command, a lack of smooth transition paths when a local chip cannot process the command, and repeated reporting of response results or difficulty in distinguishing their sources. Especially in scenarios where synchronous and local control coexist, the lack of a stable command addressing and response identification mechanism can lead to longer control chains, inconsistent execution results, and chaotic peripheral status updates. Therefore, establishing a target-chip-oriented control mechanism in multi-chip peripherals to achieve targeted command distribution, collaborative execution, and differentiated response results has become a technical problem that needs to be solved in this field. Summary of the Invention

[0004] This invention provides a multi-chip addressing control method, electronic device, storage medium, and program product, which at least solves the problems of unclear command distribution paths, repeated execution or repeated responses, and difficulty in identifying the source of responses in multi-chip peripherals.

[0005] In a first aspect, the present invention provides a multi-chip addressing control method, which is applied to a multi-chip peripheral including a master control chip and a slave control chip, the method comprising: Receive control requests; A command packet is generated based on the control request. The command packet includes a source address, a destination address, and command data. The destination address is used to indicate the target chip. In response to a control request that is a synchronous control request, the command packet is split into multiple command packets corresponding to different target chips, and sent to the corresponding target chips respectively; In response to an asynchronous control request, a command packet is sent to the target chip based on the target address; In response to the fact that the target chip is a slave chip and the slave chip does not have the ability to execute command data, the command packet is forwarded to the master chip; When the master control chip and the slave control chip receive command packets with the same command data, the master control chip executes the command packet, while the slave control chip does not execute the command packet and does not return a response packet. Receive the response packet, determine the response chip based on the source address in the response packet, and output the control result.

[0006] In one possible implementation, the target chip is either the master control chip or the slave control chip, and the target address is the chip identifier that corresponds one-to-one with the master control chip and the slave control chip.

[0007] In one possible implementation, the command packet is split into multiple command packets corresponding to different target chips, and each packet is sent to its corresponding target chip. This includes: determining multiple target chips corresponding to the synchronization control request; determining multiple target addresses based on the chip identifiers of each target chip; generating multiple command packets based on each target address; and sending each command packet to its corresponding target chip.

[0008] In one possible implementation, sending a command packet to a target chip based on a target address includes: determining the target chip based on the target address; and sending the command packet to the target chip.

[0009] In one possible implementation, forwarding the command packet to the master control chip includes: determining the command type based on the command data; matching the command type with the command types supported by the slave control chip; and forwarding the command packet to the master control chip if the matching fails.

[0010] In one possible implementation, the master control chip executes the command packet, while the slave control chip does not execute the command packet and does not return a response packet. This includes: determining the master control chip as the priority execution chip according to a preset priority; having the master control chip execute the command packet; and causing the slave control chip to not execute the command packet and not return a response packet.

[0011] In one possible implementation, the source address in the response packet is the chip identifier corresponding to the chip that sent the response packet. Determining the response chip based on the source address in the response packet includes: obtaining the source address in the response packet; matching the corresponding chip identifier based on the source address; and determining whether the response chip is a master control chip or a slave control chip based on the chip identifier.

[0012] In a second aspect, the present invention provides an electronic device, including a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, it implements a multi-chip addressing control method.

[0013] Thirdly, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements a multi-chip addressing control method.

[0014] Fourthly, the present invention provides a computer program product, including a computer program, which, when executed by a processor, implements a multi-chip addressing control method.

[0015] Compared with the prior art, the advantages and beneficial effects of the present invention are as follows: By setting the target address in the command packet and indicating the target chip with the target address, the control request is distributed to different chips in a targeted manner; by splitting the synchronous control request and sending it to different target chips separately, multi-chip collaborative processing is achieved; by forwarding the command packet to the master control chip when the slave control chip lacks execution capability, the control link is continuously maintained; by prioritizing the execution of command packets with identical command data received by both the master and slave control chips, duplicate execution and duplicate responses are avoided; and by identifying the responding chip based on the source address in the response packet, the source of the control result is distinguishable and the result feedback relationship is clear. Therefore, this invention simultaneously achieves command directionality, collaboration, and result traceability. Attached Figure Description

[0016] Figure 1 This is a schematic flowchart of the method of the present invention; Figure 2 This is a flowchart illustrating the synchronization control request distribution process of the method of the present invention; Figure 3 This is a flowchart of the asynchronous control forwarding process of the method of the present invention; Figure 4 This is a flowchart of the response recognition and control process of the method of the present invention. Detailed Implementation

[0017] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0019] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0020] Addressing control is a fundamental processing mechanism in control systems used to establish a correspondence between "control request - execution object - feedback result". Its core lies in accurately allocating control requests to the corresponding execution units based on preset identifiers, address rules, or object mapping relationships, and identifying and merging the feedback sources after execution. In multi-control unit collaborative scenarios, addressing control not only affects the accuracy of command allocation but also determines the boundaries of responsibility, collaborative order, and result feedback paths between different execution units. Therefore, when the controlled object expands from a single control unit to multiple control chips, it is necessary to establish a finer-grained addressing control mechanism around chip-level objects to enable control requests to be directed, collaboratively processed, and their results identified according to the target chip. This invention is proposed based on this principle.

[0021] like Figure 1 As shown, a multi-chip addressing control method is applied to a multi-chip peripheral including a master control chip and slave control chips. The method includes: Receive control requests; In one embodiment, the multi-chip peripheral can be a keyboard, mouse, or a composite peripheral that integrates button control and lighting effect control. The driver or control program in the host computer sends control requests to the multi-chip peripheral via a wired or wireless interface. Upon receiving a control request, the multi-chip peripheral first parses the control category, target scope, and command content in the request, and then performs validity checks on field integrity, data length, and request source. If the checks pass, the control request is written to the receive buffer and a pending control record is generated. The control category distinguishes between synchronous and asynchronous control requests, and the target scope indicates whether the current control request is directed to a single chip or multiple chips. If the checks fail, the current control request is discarded and an error record is generated.

[0022] A command packet is generated based on the control request. The command packet includes a source address, a destination address, and command data. The destination address is used to indicate the target chip. In one embodiment, after receiving a control request, the multi-chip peripheral first parses the control category, function item, device type, and target range in the control request, and then generates a command packet based on the control request. The command packet includes at least a source address, a target address, and command data. The source address identifies the sender of the control request, the target address identifies the target chip corresponding to the current command packet, and the command data carries the command identifier and parameter content corresponding to the current control action. After the command packet is generated, it is written to a transmission buffer as input for subsequent synchronous distribution or targeted transmission. The target address maintains a correspondence with the target chip, enabling the multi-chip peripheral to distinguish the processing objects of different chips within the same peripheral.

[0023] The target chip is either the master control chip or the slave control chip, and the target address is the chip identifier that corresponds one-to-one with the master control chip and the slave control chip.

[0024] In one embodiment, the added limitation is that the target chip is limited to either the master control chip or the slave control chip, the target address is limited to a chip identifier that corresponds one-to-one with the master control chip and the slave control chip, and the command packet generation process revolves around this correspondence. The reason for introducing this limitation is that different chips in a multi-chip peripheral device perform different functions. If only the peripheral-level command description is retained without establishing a chip-level identifier relationship, although command packets can be sent in the subsequent transmission stage, they cannot accurately reach the specific chip within the peripheral device. This can easily lead to situations where the master control chip and the slave control chip simultaneously parse the same command or neither parses it at all.

[0025] Based on this, in computer peripheral scenarios such as keyboards and mice, fixed chip identifiers can be pre-configured for the master control chip and slave control chips, and a chip identifier mapping table can be established on the firmware side. Taking a multi-chip keyboard as an example, the master control chip can be responsible for power supply status control, global lighting effect scheduling, and main communication link management, while the slave control chip can be responsible for local key matrix scanning, local lighting zone driving, or auxiliary function processing. Taking a multi-chip mouse as an example, the master control chip can be responsible for main communication, mode switching, and core control, while the slave control chip can be responsible for side button area scanning, auxiliary lighting effect control, or local function expansion. Upon receiving a control request, the system first determines whether the current command is directed to the master control chip, slave control chip, or a chip object to be further determined based on the target scope in the control request. When the control request already carries target information, the target information is directly read and matched with the corresponding chip identifier. When the control request does not directly provide target information, the target attribution is determined based on the command content. For example, commands related to the overall system status, communication control, and global configuration are preferentially mapped to the master control chip, while commands related to local functions, local lighting zones, or auxiliary input are mapped to the slave control chip.

[0026] After determining the target attribution, the matched chip identifier is written to the target address field, the sender identifier is written to the source address field, and the command type, command parameters, and command length are organized and written to the command data field to form a complete command packet. Once generated, the command packet is written to the transmission buffer. Each command packet in the transmission buffer maintains a relationship where one target address corresponds to only one target chip, so that subsequent transmission phases can directly target and send commands based on the target address.

[0027] like Figure 2 As shown, in response to a control request that is a synchronous control request, the command packet is split into multiple command packets corresponding to different target chips, and sent to the corresponding target chips respectively; In one embodiment, after receiving a synchronization control request, the multi-chip peripheral first extracts the control category, synchronization object, and command data from the control request, and then determines the multiple target chips participating in this synchronization control based on the synchronization object. Subsequently, a command packet is generated for each target chip, and the target address corresponding to the target chip is written into each command packet, so that each command packet corresponds one-to-one with each target chip. After the command packets are generated, they are written into a sending queue and sent sequentially to the corresponding target chips, so that multiple target chips execute their respective control actions around the same synchronization control request. Through this processing method, the same control request can be split into multiple execution units targeting different chips within the same peripheral, which facilitates the synchronous control of multi-chip peripherals such as keyboards and mice.

[0028] The command packet is split into multiple command packets corresponding to different target chips, and each packet is sent to the corresponding target chip. This includes: determining multiple target chips corresponding to the synchronization control request; determining multiple target addresses based on the chip identifier of each target chip; generating multiple command packets based on each target address; and sending each command packet to the corresponding target chip.

[0029] In one embodiment, a new limiting point is added: the synchronization control request is not directly broadcast as a single command packet to all chips. Instead, multiple target chips corresponding to the synchronization control request are first identified, and then multiple target addresses are determined based on the chip identifiers of each target chip. Subsequently, multiple command packets are generated based on each target address, and each command packet is sent to its corresponding target chip. This limiting point is introduced because although different chips in a multi-chip peripheral system participate in the same synchronization control, the functional boundaries of each chip are not entirely the same. If the same command packet is directly and indiscriminately sent to all chips, it is easy to cause duplicate processing, invalid processing, or inconsistent processing results.

[0030] Based on this, in the keyboard peripheral scenario, the function items in the synchronization control request can be used to determine whether the current synchronization object is lighting effect control, key configuration update, or state switching. If the synchronization object is lighting effect control, the main control chip and the slave control chip responsible for driving the zone lighting effect can be identified as the target chips. If the synchronization object is key configuration update, the main control chip and the slave control chip responsible for scanning the local key matrix can be identified as the target chips. In the mouse peripheral scenario, the function items in the synchronization control request can be used to determine whether the current synchronization object is mode switching, lighting effect linkage, or side button configuration update. If the synchronization object is mode switching, the main control chip and the slave control chip responsible for the auxiliary function area can be identified as the target chips. After the target chips are identified, the chip identifier corresponding to each target chip is read, and each chip identifier is written into the target address field of the corresponding command packet. At this time, the command data in each command packet can maintain the same control category, or different parameters can be written according to the functional boundaries of the target chip while maintaining the same control purpose. For example, in a keyboard lighting synchronization scenario, the command packet corresponding to the main control chip can write the overall lighting effect mode and global brightness parameters, while the command packet corresponding to the slave control chip can write the zone light position number and local lighting effect parameters. In a mouse mode synchronization scenario, the command packet corresponding to the main control chip can write the main working mode switching parameters, while the command packet corresponding to the slave control chip can write the side button area linkage parameters. After each command packet is generated, it is written to the sending queue according to the target address. The sending queue can be sent in the order of chip identifiers or in a pre-set synchronization order.

[0031] During transmission, each command packet is delivered by the communication interface to the target chip corresponding to the target address, causing each target chip to execute its corresponding control action around the same synchronization control request. If it is found before transmission that there are fewer than two target chips corresponding to the synchronization control request, the current control request will no longer be processed as a synchronization control request, but will instead be transferred to the single-chip transmission path to avoid invalid splitting.

[0032] like Figure 3 As shown, in response to an asynchronous control request, a command packet is sent to the target chip based on the target address; In one embodiment, after receiving an asynchronous control request, the multi-chip peripheral first parses the target range in the control request. If the target range points to only one processing object, the current control request is determined to be an asynchronous control request. Subsequently, the target address is read from the command packet, and the corresponding target chip is located based on the target address. The command packet is then sent to the target chip for execution. After receiving the command packet, the target chip only parses and processes the command data in the current command packet, without triggering synchronous execution of other chips. Through this processing method, multi-chip peripherals such as keyboards and mice can drive only one target chip to execute the corresponding function in a single control process, avoiding duplicate execution and invalid responses caused by multiple chips participating in processing simultaneously.

[0033] Sending command packets to the target chip based on the target address includes: determining the target chip based on the target address; and sending command packets to the target chip.

[0034] In one embodiment, a new limiting point is added: the asynchronous control request transmission process follows the path of "determining the target chip based on the target address, and then sending the command packet to the target chip," to ensure that the single-chip control path remains clear, stable, and facilitates subsequent forwarding and response identification. This limiting point is introduced because multi-chip peripherals typically include at least a master control chip and slave control chips, which perform different processing tasks. If the asynchronous control request is broadcast directly to the peripheral without first determining the target chip during the transmission phase, it can easily lead to multiple chips receiving the command packet simultaneously, resulting in duplicate judgments during subsequent parsing and increasing the internal processing burden.

[0035] Based on this, in the keyboard peripheral scenario, single-chip control actions such as overall connection state switching, main communication link maintenance, and global configuration updates can be mapped to the main control chip, while local button area control, local lighting area control, or auxiliary function switching can be mapped to the slave control chip. In the mouse peripheral scenario, main mode switching, main sensor control, and main communication maintenance can be mapped to the main control chip, while side button area control, local lighting effect switching, or auxiliary function processing can be mapped to the slave control chip. In practice, the target address is first extracted from the command packet, and then the target chip corresponding to the target address is queried in the chip mapping table. The chip mapping table can be pre-established during the peripheral initialization phase, maintaining a fixed correspondence between the target address and the main and slave control chips.

[0036] Once the target chip is determined, the command packet is written to the corresponding transmission channel or forwarding buffer of the target chip, and then delivered to the target chip via the communication interface. If the target address corresponds to the master control chip, the command packet enters the master control chip's execution path; if the target address corresponds to the slave control chip, the command packet enters the slave control chip's execution path. If no target chip corresponding to the target address is found in the chip mapping table, the current command packet does not enter the transmission stage, but is recorded as an invalid command packet and the current processing ends. To ensure the distinction between asynchronous and synchronous control paths, a target quantity judgment rule can be set during the control request parsing stage. When the target quantity is one, it enters the current transmission path; when the target quantity is greater than one, it switches to the synchronous control path. Through the above method, asynchronous control requests always maintain a single target, single path, and single chip processing relationship, thus providing a stable input basis for subsequent command forwarding, priority execution, and response identification.

[0037] In response to the fact that the target chip is a slave chip and the slave chip does not have the ability to execute command data, the command packet is forwarded to the master chip; In one embodiment, after receiving a command packet, the slave chip in a multi-chip peripheral device first parses the command data to determine whether the control content corresponding to the current command data falls within the executable range of the slave chip. If the determination result indicates that the slave chip does not have the ability to execute the current command data, it forwards the current command packet to the master chip for processing. After receiving the forwarded command packet, the master chip re-parses the command data and executes the corresponding control action. Through this processing method, even if a command packet from a multi-chip peripheral device such as a keyboard or mouse arrives at the slave chip first but the slave chip cannot complete the processing, the current control request can still be completed through the master chip, avoiding the command packet terminating at the slave chip.

[0038] Forwarding the command packet to the master control chip includes: determining the command type based on the command data; matching the command type with the command types supported by the slave control chip; and forwarding the command packet to the master control chip if the matching fails.

[0039] In one embodiment, a new limiting point is added: command packet forwarding does not occur immediately after the slave chip receives any command packet. Instead, the command type is first determined based on the command data, and then matched against the command types supported by the slave chip. Only if the match fails is the command packet forwarded to the master chip. This limiting point is introduced because slave chips in multi-chip peripherals are typically not entirely devoid of processing capabilities, but rather possess only partial local control capabilities. If command type matching is not performed first, and all packets are forwarded to the master chip, local control tasks that the slave chip could have completed independently would also be routed back to the master chip for processing, increasing the burden on the master chip and weakening the significance of the multi-chip division of labor structure.

[0040] Based on this, in the keyboard peripheral scenario, overall connection status switching, global lighting effect mode switching, global parameter configuration updates, and main communication link control can be categorized as command types prioritized by the main control chip, while local key area scanning configuration, local lighting area adjustment, and auxiliary function area control can be categorized as command types supported by the slave control chip. In the mouse peripheral scenario, main mode switching, main sensor control, and main connection management can be categorized as command types prioritized by the main control chip, while side button area configuration, local lighting effect control, and auxiliary input processing can be categorized as command types supported by the slave control chip. In specific implementation, after receiving a command packet, the slave control chip first reads the command identifier and parameter content in the command data, and then queries the command type mapping table to find the command type corresponding to the current command data. The command type mapping table can be pre-established during the firmware initialization phase and records the execution correspondence between various commands and the main and slave control chips according to functional boundaries.

[0041] After command type identification, the slave chip capability table is read to determine if the current command type is within the set of command types supported by the slave chip. If the command type exists in the set, the slave chip continues to execute the current command packet. If the command type does not exist in the set, the match fails, and the current command packet is written to the master chip forwarding channel. During forwarding, the source address, destination address, and command data can remain unchanged, or a forwarding flag can be written once in the forwarding flag area to distinguish whether the current command packet originates from an external direct transmission or is forwarded internally by the slave chip. After receiving the forwarded command packet, the master chip enters its execution path, parses the command data, and completes the control action. If the master chip also cannot process the current command type, the current command packet is no longer forwarded but enters the error handling path. Through this method, the command packet is only transferred to the master chip for processing when the slave chip cannot execute it, thus clearly defining the division of labor between the local processing capabilities of the slave chip and the global processing capabilities of the master chip, and ensuring that control requests have a continuous and executable processing path within the multi-chip peripherals.

[0042] When the master control chip and the slave control chip receive command packets with the same command data, the master control chip executes the command packet, while the slave control chip does not execute the command packet and does not return a response packet. In one embodiment, when the master control chip and the slave control chip receive command packets with identical command data, the multi-chip peripherals first enter a same command determination process, comparing the command identifiers and command parameters in the two command packets. If the comparison result indicates that the two command packets correspond to the same control action, the current processing scenario is determined to be a concurrent same command scenario. After determining the concurrent same command scenario, the master control chip executes the current command packet, and the slave control chip stops the execution process of the current command packet and cancels the sending of the response packet. Through this processing method, when multiple chips simultaneously receive the same control command, the master control chip can uniformly complete the command processing for multi-chip peripherals such as keyboards and mice, avoiding the repeated execution of the same control action or the repeated return of response results by multiple chips.

[0043] The master control chip executes the command packet, while the slave control chip does not execute the command packet and does not return a response packet. This includes: determining the master control chip as the priority execution chip according to a preset priority; the master control chip executes the command packet; and the slave control chip does not execute the command packet and does not return a response packet.

[0044] In one embodiment, a new limiting point is added: in scenarios with concurrent commands, processing is not directly and fixedly executed by the master control chip after detecting identical command data. Instead, a priority chip is first determined based on a preset priority, and then the priority chip executes the command packet, while the other chip stops executing and stops returning response packets. The preset priority specifies that the master control chip is higher than the slave control chip. The reason for introducing this limiting point is that in actual operation, multiple chip peripherals may simultaneously experience external sending, internal forwarding, or cached retransmission, and the same control action may reach the master control chip and the slave control chip separately. If a unified priority rule is not established, and each chip independently determines whether to execute, it is easy for the overall device status to be repeatedly modified, lighting effects to be repeatedly refreshed, mode switching to be continuously triggered, or the host computer to receive multiple response packets with the same content.

[0045] Based on this, in the keyboard peripheral scenario, when the master control chip and the slave control chip receive the same lighting effect switching command, the same overall configuration switching command, or the same function mode switching command, the master control chip can execute the command first, while the slave control chip only retains the received record and does not enter the actual execution process. In the mouse peripheral scenario, when the master control chip and the slave control chip receive the same mode switching command, the same connection status switching command, or the same lighting effect linkage command, they are handled in the same way. In specific implementation, a priority table is first established within the multi-chip peripheral, and the priority table at least records the rule that the master control chip takes precedence over the slave control chip. After any chip receives a command packet, in addition to performing regular command parsing, it also writes the command identifier and command parameters into the command comparison area; when the comparison area detects that another chip already has a command packet with the same command data, priority determination is triggered.

[0046] After priority determination, if the current chip is the master control chip, the current command packet continues to be executed, and a response packet is generated upon completion. If the current chip is a slave control chip, the execution path is immediately terminated, the pending execution flag corresponding to the current command packet is cleared, and the response packet generation process is stopped. To prevent the slave control chip from entering a partial processing stage before termination, a priority confirmation point can be set before the command execution entry point, preventing the slave control chip from entering the hardware register writing, status update, or peripheral driver stage before passing the priority confirmation. If the slave control chip has already entered the command preprocessing stage, only the parsing result is retained, and no further execution action is submitted. In this way, the same control action is always actually executed by only one chip within a multi-chip peripheral system, and only one response result is generated, thus ensuring a clear execution boundary between the master and slave control chips.

[0047] like Figure 4 As shown, the system receives the response packet, determines the response chip based on the source address in the response packet, and outputs the control result.

[0048] In one embodiment, after completing command execution, the multi-chip peripheral receives a response packet, extracts the source address from the response packet, determines the responding chip that sent the current response packet based on the source address, and finally outputs the control result corresponding to the current response packet. The source address is used to characterize the source of the response packet, and the responding chip is used to distinguish whether the current control result comes from the master control chip or the slave control chip. After completing the responding chip identification, the control result can be returned to the host computer control program or written to the local result buffer for subsequent status updates, interface display, or log recording. Through this processing method, multi-chip peripherals such as keyboards and mice can accurately distinguish the response results returned by different chips after multiple chips participate in the control execution.

[0049] The source address in the response packet is the chip identifier corresponding to the chip that sent the response packet. Determining the response chip based on the source address in the response packet includes: obtaining the source address in the response packet; matching the corresponding chip identifier based on the source address; and determining whether the response chip is a master control chip or a slave control chip based on the chip identifier.

[0050] In one embodiment, a new limiting point is added: the source address in the response packet is not a random identifier in the general sense, but rather the chip identifier corresponding to the chip that sent the response packet; the process of determining the responding chip follows the path of "obtaining the source address, matching the chip identifier, and determining the responding chip". This limiting point is introduced because, in scenarios involving synchronous control, forwarding execution, and priority execution of multiple peripheral chips, response packets may be returned by different chips. If the response packet does not carry a clear source identifier, or if there is no fixed correspondence between the source identifier and the chip object, the host computer, although able to receive the response result, cannot determine whether the current response result comes from the master control chip or the slave control chip, which can easily lead to incorrect status attribution in subsequent result processing.

[0051] Based on this, a chip identifier mapping table can be pre-established during the peripheral initialization phase, so that the master control chip and slave control chip correspond to different chip identifiers. Each chip is required to write its own chip identifier into the source address field when generating a response packet. Taking a multi-chip keyboard as an example, when the master control chip executes the overall lighting effect switching command, it can write the corresponding chip identifier of the master control chip into the response packet; when the slave control chip executes the local lighting zone control command, it can write the corresponding chip identifier of the slave control chip into the response packet. Taking a multi-chip mouse as an example, when the master control chip completes mode switching, it can write the corresponding chip identifier of the master control chip into the response packet; when the slave control chip completes side button area configuration update, it can write the corresponding chip identifier of the slave control chip into the response packet.

[0052] In practice, the current response packet is first read from the receive buffer, and then the source address field is extracted. Next, a chip identifier matching the source address is queried in the chip identifier mapping table. If the query result corresponds to the master control chip, the source of the current response packet is determined to be the master control chip; if the query result corresponds to the slave control chip, the source of the current response packet is determined to be the slave control chip. After determining the response chip, the control result is generated by combining the status field, result field, or returned data in the current response packet, and then sent to the host computer control program. If the source address does not have a corresponding entry in the chip identifier mapping table, the current response packet is marked as invalid and does not enter the control result output path. Through this method, a stable correspondence is formed between the source identification of the response packet and the control result output, ensuring that multiple peripheral chips can accurately distinguish their respective returned response results when the master and slave control chips execute different control actions.

[0053] On the other hand, the present invention provides an electronic device including a processor and a memory. The memory stores at least one computer program, which is loaded and executed by the processor to implement all or part of the steps in the above-described multi-chip addressing control method. Specifically, during the execution of the computer program, the processor can perform processing steps such as receiving control requests, generating command packets, splitting and distributing command packets under synchronous control requests, sending commands to target chips under asynchronous control requests, forwarding commands from slave chips to master chips, prioritizing execution by the master chip, and identifying and outputting control results to response chips. In some embodiments, the electronic device can be a personal computer, a laptop computer, a tablet computer, or other terminal devices capable of running peripheral control programs, or it can be a control circuit board or control unit disposed inside a multi-chip peripheral. The specific structure of the electronic device does not constitute a limitation of the present invention; as long as the processor can execute the computer program to implement the above-described multi-chip addressing control method, it is applicable to the technical solution of the present invention.

[0054] In one exemplary embodiment, a computer-readable storage medium is also provided, which stores at least one computer program. This computer program is loaded and executed by a processor to implement all or part of the steps in the aforementioned multi-chip addressing control method. Specifically, the computer program stored in the computer-readable storage medium can be used to implement processing procedures such as control request parsing, target address generation, target chip location, command packet splitting and sending, command packet forwarding, priority execution control, and response result identification. For example, the computer-readable storage medium can be a read-only memory, random access memory, read-only optical disk, magnetic tape, floppy disk, and optical data storage device. It should be noted that the specific type of computer-readable storage medium is not a limiting condition for the validity of the technical solution of this invention. As long as the stored computer program can implement the aforementioned multi-chip addressing control method when executed by the processor, it should fall within the protection scope of this invention.

[0055] In one exemplary embodiment, a computer program product is also provided. The computer program product includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, which, when executed by a computer, cause the computer to perform all or part of the steps in the multi-chip addressing control method provided in the above embodiments. Specifically, the program instructions can drive the processor to complete processes such as receiving control requests, encapsulating command packets, splitting synchronous and asynchronous control requests, determining the execution capability of slave chips, controlling command packet forwarding, controlling the priority execution of master chips, and identifying the source of response packets, according to a preset execution order. By setting up the computer program product, the multi-chip addressing control scheme of the present invention can be deployed programmatically in peripheral management software, driver software, or embedded control software, thereby enabling the corresponding device to implement the above-described multi-chip addressing control method after loading and executing the program instructions.

[0056] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects.

[0057] The above are merely embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A multi-chip addressing control method, characterized in that, The method is applied to a multi-chip peripheral device including a master control chip and a slave control chip, and the method includes: Receive control requests; A command packet is generated based on the control request. The command packet includes a source address, a target address, and command data. The target address is used to indicate the target chip. In response to the control request being a synchronous control request, the command packet is split into multiple command packets corresponding to different target chips, and each packet is sent to its corresponding target chip. In response to the control request being an asynchronous control request, the command packet is sent to the target chip according to the target address; In response to the fact that the target chip is the slave chip and the slave chip does not have the ability to execute the command data, the command packet is forwarded to the master chip; In response to the master control chip and the slave control chip receiving command packets with the same command data, the master control chip executes the command packet, while the slave control chip does not execute the command packet and does not return a response packet; Receive the response packet, determine the response chip based on the source address in the response packet, and output the control result.

2. The method according to claim 1, characterized in that, The target chip is either the master control chip or the slave control chip, and the target address is a chip identifier that corresponds one-to-one with the master control chip and the slave control chip.

3. The method according to claim 2, characterized in that, The step of splitting the command packet into multiple command packets corresponding to different target chips and sending them to the corresponding target chips includes: Identify the multiple target chips corresponding to the synchronization control request; Multiple target addresses are determined based on the chip identifier corresponding to each target chip; Multiple command packets are generated based on each of the target addresses; Each of the command packets is sent to the corresponding target chip.

4. The method according to claim 2, characterized in that, Sending the command packet to the target chip according to the target address includes: The target chip is determined based on the target address; The command packet is sent to the target chip.

5. The method according to claim 1, characterized in that, The step of forwarding the command packet to the main control chip includes: The command type is determined based on the command data; Match the command type with the command types supported by the slave control chip; If a match fails, the command packet is forwarded to the main control chip.

6. The method according to claim 1, characterized in that, The process of the master control chip executing the command packet, while the slave control chip neither executes the command packet nor returns a response packet, includes: The main control chip is determined to be the priority execution chip according to a preset priority. The command package is executed by the main control chip; The slave control chip is prevented from executing the command packet and from returning the response packet.

7. The method according to claim 1, characterized in that, The source address in the response packet is the chip identifier corresponding to the chip that sent the response packet. Determining the response chip based on the source address in the response packet includes: Obtain the source address from the response packet; Match the corresponding chip identifier based on the source address; The responding chip is determined to be either the master control chip or the slave control chip based on the chip identifier.

8. An electronic device, characterized in that, It includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, it implements the multi-chip addressing control method as described in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the multi-chip addressing control method as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, It includes a computer program, which, when executed by a processor, implements the multi-chip addressing control method as described in any one of claims 1 to 7.

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