A boost multi-phase interleaved silicon carbide single tube parallel current sharing design method
By building a dual-pulse simulation platform and designing a symmetrical PCB layout, and by controlling parasitic parameters through copper foil stacking, the problem of poor current sharing in parallel SiC single tubes was solved, and a high-efficiency, low-cost parallel SiC single tube design was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG MECHANICAL & ELECTRICAL COLLEGE
- Filing Date
- 2026-03-26
- Publication Date
- 2026-06-26
AI Technical Summary
Existing SiC single-tube parallel connection has poor current sharing performance, requires amplification device margin, resulting in design redundancy, and the system efficiency and cost cannot be optimized.
A dual-pulse simulation platform was built to identify key factors in parallel current sharing, and a symmetrical PCB layout design was carried out. Copper foil stacking was used to control the consistency of parasitic parameters, and a design closed loop was formed through dual-pulse and steady-state thermal testing.
It achieves good current sharing of silicon carbide single tubes in parallel, reduces design redundancy, improves system efficiency and reduces costs, and adapts to the flexibility of the overall machine structure.
Smart Images
Figure CN122287533A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of circuit design technology, and in particular to a design method for parallel current sharing of BOOST multiphase interleaved silicon carbide single transistors. Background Technology
[0002] Current high-power fuel cell DC-DC controllers generally adopt a multiphase boost interleaved parallel architecture. Due to the high-frequency operation requirements of fuel cell systems for converters, the demand for third-generation semiconductor silicon carbide (SiC) devices in this field continues to increase. However, the switching speed of SiC devices is much higher than that of traditional IGBTs, which significantly increases the technical difficulty of their parallel application. Currently, the industry mainly adopts two technical solutions: parallel connection of SiC modules and parallel connection of single SiC tubes. However, both solutions have insurmountable technical defects.
[0003] For the SiC module parallel solution, the packaging manufacturer completes the wafer-level parallel packaging. It can draw on the mature IGBT module design experience to achieve good current sharing performance and meet the needs of high-power and high-current applications. However, this solution has significant limitations. The module packaging structure is standardized and customized by the manufacturer, which cannot adapt to the different structural and system requirements of end customers. The flexibility of application-side design is strictly limited. At the same time, the module solution does not have advantages in system efficiency and cost control.
[0004] In contrast, the SiC single-tube parallel solution uses a universal single-tube package for on-demand combination, which can solve the structural adaptation problem of the module solution. However, due to the difficulty of parallel current sharing design, the industry generally ensures operational reliability by amplifying device margins, which leads to design redundancy and resource waste. Even so, this solution fails to fundamentally optimize system efficiency and cost control. Summary of the Invention
[0005] To address the aforementioned problems, this invention proposes a BOOST multiphase interleaved silicon carbide single-tube parallel current sharing design method, which mainly solves the problems of difficulty in ensuring current sharing of existing SiC single-tube parallel connections, design redundancy caused by the need for amplification device margin, and inability to optimize system efficiency and cost.
[0006] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows:
[0007] A design method for parallel current sharing of multiphase interleaved silicon carbide single tubes for BOOST circuits includes the following steps:
[0008] A dual-pulse simulation platform based on parallel silicon carbide single transistors was built. Then, the simulation models of silicon carbide power devices and driver chips were connected to the dual-pulse simulation platform. The electrical parameters of the main power circuit and the drive circuit of the dual-pulse simulation platform were configured. The switching transient and conduction steady-state conditions of the devices were simulated and reproduced. The key factors affecting the parallel current sharing were identified and determined.
[0009] Based on the overall structural requirements of the target device, the silicon carbide single-tube packaging form was selected and the layout planning of parallel devices was completed.
[0010] Based on the aforementioned key factors, a symmetrical PCB layout design was implemented for the main power circuit and drive circuit of the parallel branches, and a copper foil stacking method was used to control the consistency of parasitic parameters of each branch.
[0011] The PCB prototype was subjected to dual-pulse current sharing test and steady-state thermal equilibrium test to verify the current sharing performance of the parallel silicon carbide single tube until the target values of the key factors reached the preset range.
[0012] In some implementations, the dual-pulse simulation platform is built using LTspice software, and the dual-pulse simulation platform integrates the DC bus, inductor, freewheeling circuit, drive power supply, gate resistor, snubber network, clamping network, and parasitic parameters of the main power circuit and drive circuit.
[0013] In some implementations, the parasitic parameters include gate circuit parasitic inductance, commutation circuit parasitic inductance, and common source parasitic inductance.
[0014] In some embodiments, the silicon carbide single tube is packaged in a TO-247-4 package.
[0015] In some implementations, the parallel devices are selected from silicon carbide single tubes of the same model, package, and with consistent heat dissipation conditions, and arranged close to each other during layout planning.
[0016] In some implementations, the PCB symmetrical layout design includes maintaining consistency in the geometric length, copper width, number of vias, and inter-layer switching method of each parallel branch main current path.
[0017] In some embodiments, the copper stacking method includes a copper layer stacking structure in which the drain circuits and source circuits of each parallel silicon carbide single tube are arranged adjacent to each other with reverse current.
[0018] In some implementations, the evaluation metrics for the dual-pulse current sharing test include branch peak current differences, current slope differences, switching voltage overshoot differences, and switching energy differences.
[0019] In some implementations, the evaluation metrics for the steady-state thermal equilibrium test include differences in conduction current distribution, differences in device voltage drop, and consistency of case temperature / junction temperature.
[0020] The beneficial effects of this invention are as follows: by building a dual-pulse simulation platform to identify key parasitic parameters, completing the device layout in conjunction with the overall structure, using PCB symmetry and copper foil stacking to control the consistency of parasitic parameters, and forming a design closed loop through dual-pulse and steady-state thermal testing, the problem of poor current sharing in parallel silicon carbide single tubes is effectively solved. Furthermore, this method can ensure balanced current distribution in switching transients and conduction steady states, eliminate current sharing failures caused by parasitic parameter mismatch, fully utilize the performance of silicon carbide single tubes without amplifying device margin, flexibly adapt to the overall structure layout, improve space utilization, optimize system efficiency, reduce design costs and redundancy, and achieve a reliable, efficient, and highly adaptable BOOST multiphase interleaved silicon carbide single tube parallel current sharing design. Attached Figure Description
[0021] Figure 1 This is a flowchart of the BOOST multiphase interleaved silicon carbide single-tube parallel current sharing design method disclosed in an embodiment of the present invention;
[0022] Figure 2 This is a schematic diagram of the main power circuit in an application example of the present invention;
[0023] Figure 3 This is a schematic diagram of the current sharing state during dual-pulse testing of SiC in an application example of the present invention;
[0024] Figure 4 This is a schematic diagram illustrating the temperature rise state of SiC shell temperature during temperature rise testing in an application example of the present invention. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of this invention clearer and more explicit, the content of this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to this invention are shown in the accompanying drawings, not all of them.
[0026] Example
[0027] This embodiment proposes a BOOST multiphase interleaved silicon carbide single-tube parallel current sharing design method, including the following steps 1-4:
[0028] Step 1: Build a dual-pulse simulation platform based on parallel silicon carbide single transistors. Then, connect the silicon carbide power device simulation model and the driver chip simulation model to the dual-pulse simulation platform, configure the electrical parameters of the main power circuit and the drive circuit of the dual-pulse simulation platform, simulate and reproduce the switching transient and conduction steady-state conditions of the device, and identify and determine the key factors affecting the parallel current sharing.
[0029] In step 1 of this solution, the dual-pulse simulation platform is used to reproduce the entire process of turn-on, turn-off, and freewheeling of a silicon carbide (SiC) single transistor under actual operating conditions, accurately evaluating the dynamic current sharing and steady-state conduction characteristics of parallel devices. Specifically, the aforementioned SiC power device simulation model and driver chip simulation model are the SPICE sub-circuit model provided by the SiC power device manufacturer and the SPICE macro model provided by the driver chip manufacturer, respectively. In one example, the dual-pulse simulation platform is built using LTspice software. During the construction process, it includes not only the SiC single transistor (SiC single transistor) and driver chip (driver IC) models, but also integrates the DC bus, inductor, freewheeling circuit, drive power supply, gate resistor, snubber network, clamping network, and parasitic parameters of the main power circuit and drive circuit. In the above example, by completely restoring the electrical connection relationship and parasitic parameter environment of the main power circuit and drive circuit, the simulation results are highly matched with the actual hardware operating conditions, avoiding excessive deviation between simulation and actual measurement.
[0030] During the simulation, the simulation model of the silicon carbide power device and the simulation model of the driver chip are connected in the LTspice schematic through the gate drive terminal, the source / Kelvin source terminal and the power supply circuit. A dual-pulse drive signal is generated by the pulse excitation source to reproduce the turn-on, turn-off and freewheeling process of the device under actual operating conditions. The transient switching behavior, steady-state conduction behavior and dynamic current sharing characteristics between parallel branches of the silicon carbide single transistor can be evaluated through the dual-pulse simulation platform.
[0031] During the simulation process, in addition to the simulation models of silicon carbide power devices and driver chips, at least the device model and package, the number of parallel connections, drive parameters, bus voltage, test current points, test temperature points, and key parasitic parameters of each parallel branch should be defined. In this step, parasitic parameters include gate circuit parasitic inductance, commutation circuit parasitic inductance, and common-source parasitic inductance. Among these, the common-source parasitic inductance directly affects the rate of change of the device's gate drive voltage and current through negative feedback, and is most sensitive to the impact on parallel current sharing. By identifying these three types of key parameters through simulation, the key factors (core causes) leading to current sharing imbalance can be accurately located, and the target value range of the key factors (drain and source stray parameters) can be determined, providing a clear basis for subsequent PCB layout design.
[0032] Step 2: Based on the overall structural requirements of the target device, select the silicon carbide single-tube package and complete the layout planning of parallel devices.
[0033] In step 2 of this solution, the device layout planning is used to adapt to the overall structural space and lay the hardware foundation for parallel current sharing. In one example, the silicon carbide single tube adopts a TO-247-4 package. This package has an independent Kelvin source pin, which can completely isolate the drive circuit from the main power return path, effectively reduce the disturbance of the main circuit to the gate drive signal, and improve the switching synchronization of parallel devices.
[0034] Optionally, when planning the layout of parallel devices, silicon carbide single tubes of the same model, package, and with consistent heat dissipation conditions should be selected and arranged close to each other. In the above optional scheme, by unifying device parameters, reducing the placement spacing, and balancing heat dissipation conditions, the steady-state current shunt deviation caused by the dispersion of the device body and thermal unevenness can be reduced.
[0035] Step 3: Based on key factors, perform PCB symmetrical layout design for the main power circuit and drive circuit of the parallel branches, and use copper foil stacking to control the consistency of parasitic parameters of each branch.
[0036] In step 3 of this solution, the symmetrical PCB layout design focuses on the consistency of parasitic parameters in parallel branches. In one example, the symmetrical PCB layout design includes maintaining consistency in the geometric length, copper width, via quantity, and inter-layer switching method of the main current path for each parallel branch. In the example above, by ensuring complete matching of the physical parameters of the main current path for each branch, the parasitic parameter mismatch between parallel branches is minimized, thereby improving the uniformity of dynamic current distribution in the devices.
[0037] In this embodiment, the copper stacking method includes: arranging the drain and source circuits of each parallel silicon carbide single transistor adjacent to each other using reverse current configurations. This copper stacking layout utilizes the principle of electromagnetic induction to cancel out the magnetic fields generated by the reverse current circuits. Without altering the structural space, it precisely controls the stray inductance of each branch, ensuring that parasitic parameter deviations remain within acceptable limits. The overall design process is as follows: Figure 1 As shown.
[0038] Step 4: Perform dual-pulse current sharing test and steady-state thermal equilibrium test on the PCB prototype to verify the current sharing performance of the parallel silicon carbide single tube until the target values of the key factors reach the preset range, thus forming a closed loop for current sharing design.
[0039] In step 4 of this scheme, the dual-pulse current sharing test is used to verify the dynamic current sharing effect of the device during switching transients. In one example, the evaluation metrics for the dual-pulse current sharing test include branch peak current difference, current slope difference, switching voltage overshoot difference, and switching energy difference. These metrics are used to quantitatively evaluate the accuracy of switching transient current sharing and ensure that the current synchronization of each branch meets the design requirements.
[0040] Steady-state thermal equalization testing is used to verify the consistency of current distribution and heat distribution during steady-state conduction of a device. In one example, the evaluation metrics for steady-state thermal equalization testing include differences in conduction current distribution, differences in device voltage drop, and case temperature / junction temperature consistency.
[0041] The above scheme verifies the effectiveness of the parallel circuit design through dual-dimensional testing of double-pulse current sharing and steady-state thermal equilibrium, thereby forming a complete current sharing design closed loop of simulation, layout, testing and optimization, ensuring the reliability and repeatability of the scheme.
[0042] Application Examples
[0043] In a specific application example, the present invention designs a single-phase power unit for a BOOST multiphase interleaved topology as follows:
[0044] In this example, as Figure 2 As shown, a certain phase BOOST power unit uses two TO-247-4 packaged silicon carbide single transistors connected in parallel. The two parallel devices are arranged in a completely symmetrical power loop layout on the PCB, ensuring that the main current paths of the two parallel branches, from the positive terminal of the DC bus, through the power devices to the output node, and then back to the negative terminal of the bus, are consistent in terms of geometric length, copper width, number of vias, and inter-layer switching method. This minimizes the inconsistency of parasitic parameters between the parallel branches. In the application scenario of discrete power devices in parallel, the parasitic parameter mismatch introduced by the PCB layout is the core factor causing the imbalance of parallel current. The above-mentioned symmetrical layout can effectively improve the uniformity of dynamic current distribution of parallel devices. This design principle is applicable to both discrete IGBT devices and discrete SiC MOSFET devices.
[0045] In this example's layout design, the present invention focuses on controlling the parasitic inductance of the commutation loops of each parallel branch, specifically including the gate loop parasitic inductance, the current commutation loop parasitic inductance, and the common source path parasitic inductance. These parasitic parameters are summarized as gate inductance LG, commutation loop inductance LC, and common source inductance LE. Among these, the mismatch of the common source inductance LE between parallel branches has a more sensitive impact on current sharing performance than the commutation loop inductance LC. This is because LE directly affects the effective gate drive voltage and current change rate during device turn-on and turn-off through negative feedback. Therefore, this example not only requires the main power loop to meet the design requirements of wide copper foil and short path, but also requires the source loops of the parallel branches to maintain a high degree of consistency.
[0046] In practical implementation, if the design conditions of "sufficiently wide copper foil" and "sufficiently short path" cannot be simultaneously met due to space constraints in the overall structure, this example employs copper layer stacking and adjacent return path optimization to collaboratively adjust the stray inductance of the drain and source circuits, controlling the parasitic parameter deviations of each parallel branch within the design tolerance range. Parasitic parameter extraction and parallel testing verification show that even if the device body parameters remain consistent, differences in parasitic parameters between the inner and outer sides of different branches due to layout will still cause uneven current distribution during the turn-on process and generate additional loss differences. Therefore, the core purpose of the stacked and symmetrical return design in this example is not simply to reduce the total stray inductance, but to reduce the parasitic parameter mismatch between parallel branches.
[0047] This example preferably uses a single silicon carbide transistor in a TO-247-4 package. The device's built-in Kelvin source pins are used to separate the drive circuit from the main power circuit, reducing the disturbance of the drive signal by parasitic parameters of the common source. The four-pin Kelvin connection structure effectively improves the parallel current distribution accuracy, reduces the additional voltage drop and drive error caused by parasitic parameters, reduces the dependence on additional current sharing measures, and improves the synchronization and operational reliability of parallel devices under high-frequency switching conditions.
[0048] In summary, the PCB power module design scheme adopted in this example takes the consistency of parasitic parameters in parallel branches as its core design goal. Through device package selection, drive circuit layout, symmetrical design of the main power circuit, and PCB stack-up optimization, it comprehensively improves the switching transient current sharing capability and steady-state thermal equilibrium capability of SiC single-tube parallel operation. The results of dual-pulse current sharing tests and case temperature tests verify that the design method of this invention can effectively improve the consistency of current distribution and thermal distribution among parallel branches. In scenarios using two or three discrete devices in parallel, a symmetrical layout should be prioritized, and the cooling conditions of each device should be kept consistent to avoid further deterioration of parallel operation reliability due to uneven temperature distribution.
[0049] See Figure 3 and Figure 4 Actual testing fully demonstrates the effectiveness of the present invention.
[0050] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made based on the essence of the content of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A design method for parallel current sharing of BOOST multiphase interleaved silicon carbide single tubes, characterized in that, Includes the following steps: A dual-pulse simulation platform based on parallel silicon carbide single transistors was built. Then, the simulation models of silicon carbide power devices and driver chips were connected to the dual-pulse simulation platform. The electrical parameters of the main power circuit and the drive circuit of the dual-pulse simulation platform were configured. The switching transient and conduction steady-state conditions of the devices were simulated and reproduced. The key factors affecting the parallel current sharing were identified and determined. Based on the overall structural requirements of the target device, the silicon carbide single-tube packaging form was selected and the layout planning of parallel devices was completed. Based on the aforementioned key factors, a symmetrical PCB layout design was implemented for the main power circuit and drive circuit of the parallel branches, and a copper foil stacking method was used to control the consistency of parasitic parameters of each branch. The PCB prototype was subjected to dual-pulse current sharing test and steady-state thermal equilibrium test to verify the current sharing performance of the parallel silicon carbide single tube until the target values of the key factors reached the preset range.
2. The BOOST multiphase interleaved silicon carbide single-tube parallel current sharing design method as described in claim 1, characterized in that, The dual-pulse simulation platform is built using LTspice software and integrates the parasitic parameters of the DC bus, inductor, freewheeling circuit, drive power supply, gate resistor, snubber network, clamping network, and main power circuit and drive circuit.
3. The BOOST multiphase interleaved silicon carbide single-tube parallel current sharing design method as described in claim 2, characterized in that, The parasitic parameters include gate circuit parasitic inductance, commutation circuit parasitic inductance, and common source parasitic inductance.
4. The BOOST multiphase interleaved silicon carbide single-tube parallel current sharing design method as described in claim 1, characterized in that, The silicon carbide single tube is packaged in TO-247-4.
5. The BOOST multiphase interlaced silicon carbide single-tube parallel current sharing design method as described in claim 1, characterized in that, When planning the layout of the parallel devices, silicon carbide single tubes of the same model, package and heat dissipation conditions are selected and arranged close to each other.
6. The BOOST multiphase interleaved silicon carbide single-tube parallel current sharing design method as described in claim 1, characterized in that, The symmetrical PCB layout design includes maintaining consistency in the geometric length, copper width, number of vias, and inter-layer switching method of the main current path of each parallel branch.
7. The BOOST multiphase interleaved silicon carbide single-tube parallel current sharing design method as described in claim 1, characterized in that, The copper foil stacking method includes: a copper layer stacking structure in which the drain circuit and source circuit of each parallel silicon carbide single tube are arranged adjacently with reverse current.
8. The BOOST multiphase interleaved silicon carbide single-tube parallel current sharing design method as described in claim 1, characterized in that, The evaluation indicators for the dual-pulse current sharing test include branch peak current difference, current slope difference, switching voltage overshoot difference, and switching energy difference.
9. The BOOST multiphase interleaved silicon carbide single-tube parallel current sharing design method as described in claim 1, characterized in that, The evaluation metrics for the steady-state thermal equilibrium test include differences in conduction current distribution, differences in device voltage drop, and consistency of case temperature / junction temperature.