Display panel and display device

Abstract

This invention provides a display panel and a display device. The display panel includes a display area and a non-display area at least partially surrounding the display area; the display area includes a plurality of pixels arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; the non-display area includes at least one scan driving circuit; the scan driving circuit includes a plurality of shift registers, each shift register including a first end and a second end; the scan driving circuit includes a first driving column and a second driving column arranged along the first direction; the plurality of shift registers includes first shift registers and second shift registers; the first driving column includes a plurality of first shift registers arranged along the second direction, and the second driving column includes a plurality of second shift registers arranged along the second direction; the plurality of first shift registers and the plurality of second shift registers correspond one-to-one, and the first end of each of the first and second shift registers is located between the second ends of the first and second shift registers. This invention reduces the resistance difference and parasitic capacitance difference between different cascaded lines, improving the display uniformity of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] With the continuous development of display technology, near-eye display devices such as virtual reality (VR) and augmented reality (AR) are placing increasingly higher demands on the resolution of display panels. In ultra-high resolution (PPI) display panels, pixel sizes are compressed to tens of micrometers or even smaller. To meet the requirements of narrow bezel designs, the gate drive circuit is typically integrated directly into the non-display area of ​​the display panel. Gate drive circuits can be symmetrically arranged on the left and right sides of the display panel to achieve bilateral driving, thereby improving the uniformity of the scanning signal and the driving capability.

[0003] However, with the further increase in PPI and the continuous shrinking of pixel size, how to design the gate drive circuit in a limited space and ensure the stable transmission of the scanning signal has become an important research direction in the design of ultra-high PPI display panels. Summary of the Invention

[0004] The purpose of this invention is to provide a display panel and display device to solve the problem of large differences in resistance and parasitic capacitance between different cascaded lines.

[0005] To achieve the above objectives, the present invention provides a display panel, the display panel comprising:

[0006] The display area includes a plurality of pixels arranged in an array along a first direction and a second direction; the first direction intersects the second direction; A non-display area, at least partially surrounding the display area; the non-display area includes at least one scan driving circuit, the scan driving circuit includes a plurality of shift registers, the shift registers include a first end and a second end, and the scan driving circuit includes a first driving column and a second driving column arranged along the first direction. The plurality of shift registers includes a first shift register and a second shift register. The first drive column includes a plurality of first shift registers arranged along the second direction, and the second drive column includes a plurality of second shift registers arranged along the second direction. The plurality of first shift registers and the plurality of second shift registers correspond one-to-one, and the first end of the first shift register and the first end of the second shift register are both located between the second end of the first shift register and the second end of the second shift register.

[0007] In one embodiment, in the second direction, the height of both the first shift register and the second shift register is equal to the height of the two rows of pixels.

[0008] In one embodiment, the display panel further includes: Multiple first signal lines, each corresponding to a plurality of first shift registers; each first signal line includes a first concatenation line, one end of which is connected to the first end of the corresponding first shift register, and the other end of which is connected to the second end of the second shift register located in the same row. Multiple second signal lines, each corresponding to a plurality of second shift registers; each second signal line includes a second concatenation line, one end of which is connected to the first end of the corresponding second shift register, and the other end of which is connected to the second end of the first shift register located in the next row; Wherein, the length of the first cascade is equal to the length of the second cascade; In one embodiment, the first end of the shift register is the output end of the shift register, and the second end of the shift register is the input end of the shift register.

[0009] In one embodiment, the first signal line further includes: The first scan line, one end of which is connected to the first end of the corresponding first shift register, and the other end of which is connected to the first row of pixels in the corresponding two rows of pixels; The first compensation line has one end connected to the first end of the corresponding first shift register, and the other end of the first compensation line extends in the opposite direction to the first scan line and is flush with the second signal line. The second signal line also includes: The second scan line has one end connected to the first end of the corresponding second shift register, and the other end connected to the second row of pixels in the corresponding two rows of pixels; Wherein, the length of the first scan line is greater than the length of the second scan line, and the length of the first signal line is equal to the length of the second signal line.

[0010] In one embodiment, the display panel further includes: Multiple first signal lines, each corresponding to a plurality of first shift registers; each first signal line includes a first concatenation line, one end of which is connected to the second end of the corresponding first shift register, and the other end of which is connected to the first end of the second shift register located in the same row. Multiple second signal lines, each corresponding one-to-one with a plurality of second shift registers; each second signal line includes a second concatenation line, one end of which is connected to the second end of the corresponding second shift register, and the other end of which is connected to the first end of the first shift register located in the next row; wherein, the length of the first concatenation line is equal to the length of the second concatenation line; In one embodiment, the first signal line further includes: The first scan line has one end connected to the second end of the corresponding first shift register, and the other end connected to the first row of pixels in the corresponding two rows of pixels. In one embodiment, the second signal line further includes: The second scan line, one end of which is connected to the second end of the corresponding second shift register, and the other end of which is connected to the second row of pixels in the corresponding two rows of pixels; The second compensation line; one end of the second compensation line is connected to the second end of the corresponding second shift register, and the other end of the second compensation line extends in the opposite direction to the second scan line and is flush with the first signal line; wherein, the length of the first scan line is greater than the length of the second scan line, and the length of the first signal line is equal to the length of the second signal line; In one embodiment, the first end of the shift register is the input end of the shift register, and the second end of the shift register is the output end of the shift register.

[0011] In one embodiment, the shift register further includes a third terminal and a fourth terminal; The display panel also includes: Multiple third-level concatenation lines are provided, each corresponding to one of the multiple first shift registers. One end of each third-level concatenation line is connected to the third end of the corresponding first shift register, and the other end of each third-level concatenation line is connected to the first or second end of the second shift register located in the same row. Multiple fourth-level concatenation lines are provided, each corresponding to one of the multiple second shift registers. One end of each fourth-level concatenation line is connected to the fourth end of the corresponding second shift register, and the other end of each fourth-level concatenation line is connected to the first or second end of the first shift register located in the next row. Wherein, the length of the third-level connector is equal to the length of the fourth-level connector; In one embodiment, one of the first end and the second end of the shift register is the input end of the shift register, and the other is the output end of the shift register.

[0012] In one embodiment, the display panel further includes: Multiple third signal lines are provided, each corresponding to one of the multiple first shift registers. Each third signal line includes a third scan line, one end of which is connected to the first or second end of the corresponding first shift register, and the other end of which is connected to the first row of pixels in the corresponding two rows of pixels. Multiple fourth signal lines are provided, each corresponding to one of the multiple second shift registers. Each fourth signal line includes a fourth scan line, one end of which is connected to the first or second end of the corresponding second shift register, and the other end of which is connected to the second row of pixels in the corresponding two rows of pixels. The length of the third scan line is greater than the length of the fourth scan line.

[0013] In one embodiment, the fourth signal line further includes a third compensation line; one end of the third compensation line is connected to the first or second end of the corresponding second shift register, and the other end of the third compensation line extends in the opposite direction to the fourth scan line and is flush with the third scan line; The length of the third signal line is equal to the length of the fourth signal line.

[0014] In one embodiment, the display panel further includes: An input signal line is connected to a first or second end of the first shift register in the first row of the first drive column; The first clock signal line is connected to the first or second terminal of each of the first shift registers, and the first clock signal line is connected to the first or second terminal of each of the second shift registers. The second clock signal line is connected to either the first or second end of each of the first shift registers, and the second clock signal line is also connected to either the first or second end of each of the second shift registers.

[0015] The present invention also provides a display device comprising the above-described display panel.

[0016] The present invention proposes a display panel that reduces the length difference of different cascaded lines between the first and second shift registers by mirroring and symmetrically setting the first shift register and the second shift register in the scanning drive circuit. This reduces the resistance difference and parasitic capacitance difference between different cascaded lines, thereby improving the display uniformity of the display panel. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a display panel in the prior art; Figure 2 This is a schematic diagram of the structure of another display panel in the prior art; Figure 3 This is a schematic diagram of another display panel structure in the prior art; Figure 4 A schematic diagram of the structure of a display panel provided by the present invention; Figure 5 This is a schematic diagram of the structure of a display panel in one embodiment of the present invention; Figure 6 for Figure 5 A partial structural diagram of the display panel in the embodiment; Figure 7 This is a schematic diagram of the structure of another display panel provided by the present invention; Figure 8 for Figure 7 A partial structural diagram of the display panel in the embodiment; Figure 9 This is a schematic diagram of the structure of another display panel provided by the present invention; Figure 10 for Figure 9 A partial structural diagram of the display panel in the embodiment; Figure 11 This is a schematic diagram of another display panel structure provided by the present invention; Figure 12 for Figure 11 A partial structural diagram of the display panel in the embodiment; Figure 13 This is a schematic diagram of the structure of a display device in one embodiment of the present invention. Detailed Implementation

[0019] The following description, with reference to the accompanying drawings, illustrates preferred embodiments of the present invention, demonstrating its implementability. These embodiments provide a complete overview of the invention for those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein.

[0020] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. The dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component. To make the illustrations clearer, the thickness of components is appropriately exaggerated in some places in the drawings.

[0021] Furthermore, the following descriptions of the embodiments of the invention are made with reference to the accompanying illustrations, illustrating specific embodiments in which the invention can be implemented. Directional terms used in this invention, such as "upper," "lower," "front," "rear," "left," "right," "inner," "outer," and "side," are merely directional references to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of the invention, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] When a component is described as being "on" another component, the component may be placed directly on the other component; alternatively, there may be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "installed to" or "connected to" another component, both can be understood as being directly "installed" or "connected" to, or as being indirectly "installed to" or "connected to" another component via an intermediate component.

[0023] With the continuous improvement of display panel resolution, especially for ultra-high PPI (pixel density) OLED display panels designed for near-eye display applications such as virtual reality (VR) and augmented reality (AR), pixel size has shrunk to tens of micrometers or even smaller. Please refer to [reference needed]. Figure 1 In a display panel with a pixel density of 1500 PPI, for example, the size of a single pixel is approximately 16.92 μm. In such display panels, the size of each shift register in the gate drive circuit can be close to the pixel size. This ensures that during bilateral driving, the shift registers in both gate drive circuits are horizontally aligned with the corresponding connected pixel rows. That is, the Nth-level shift register is approximately aligned with the Nth row of pixels in the first direction X, thus guaranteeing synchronous output of the scan signal. Please refer to [reference needed]. Figure 2In display panels with higher resolutions (e.g., 2000 PPI), the size of a single pixel is further reduced to approximately 12.7µm. In such panels, due to limitations in transistor physical size and driving capability requirements, the shift registers in the gate drive circuit cannot be scaled down synchronously with the pixel size, resulting in a single shift register being taller than a row of pixels in the second direction Y. In this case, the shift registers and pixels cannot maintain a rough correspondence in the first direction X, but rather exhibit positional misalignment. For example, a second pixel row electrically connected to a second-stage shift register may be located at the same horizontal position as the first-stage shift register. This misalignment requires the connection lines between the shift registers and the pixel rows they drive to span longer distances, increasing the complexity of the wiring layout and potentially causing differences in signal transmission delay. Simultaneously, to achieve proper connection, the bezel size of non-display areas may also be forced to increase, which is detrimental to narrow bezel designs.

[0024] To address the issue of insufficient wiring space at ultra-high PPI, existing technologies employ a dual-sided, dual-row drive structure. Please refer to [reference needed]. Figure 3 The structure includes scan drive circuits located on the left and right sides of the display panel. These circuits work together to drive the same row of pixels, improving driving capability and display uniformity. To meet the requirements of progressive scanning, each scan drive circuit employs a two-column side-by-side layout: the first and second drive columns are arranged side-by-side along the first direction X. Each drive column contains multiple shift registers. The height of each shift register is designed to be the height of two rows of pixels, thus providing sufficient space for the shift registers and connecting lines. Specifically, the shift registers in the first drive column drive pixels in odd-numbered rows, and the shift registers in the second drive column drive pixels in even-numbered rows, thereby achieving progressive scanning. Specifically, the first-level shift register of the first column in the left scanning drive circuit and the first-level shift register of the first column in the right scanning drive circuit output simultaneously to drive the first row of pixels; the first-level shift register of the second column in the left scanning drive circuit and the first-level shift register of the second column in the right scanning drive circuit output simultaneously to drive the second row of pixels; the second-level shift register of the first column in the left scanning drive circuit and the second-level shift register of the first column in the right scanning drive circuit output simultaneously to drive the third row of pixels; and so on, to complete the row-by-row scanning.

[0025] In the existing scheme described above, each shift register has an input terminal and an output terminal, and the input and output terminals are arranged sequentially along the first direction X. For details, please refer to [link / reference]. Figure 3In this structure, the first shift register in the first driving column and the second shift register in the second driving column are arranged side-by-side in the same row. The input and output terminals of the first shift register are located at its left and right ends, respectively, and similarly, the input and output terminals of the second shift register are also located at its left and right ends, respectively. In this configuration, the cascading lines between different shift registers mainly fall into two categories. The first type is cascading line A formed between the first and second shift registers in the same row. For example, the output terminal of the first shift register in the first row is connected to the input terminal of the second shift register in the same row. Since the first and second shift registers are arranged side-by-side and the positions of the output and input terminals match, cascading line A connects directly along the first direction X, resulting in a shorter trace length. The second type is cascading line B formed between the first and second shift registers in adjacent rows. For example, the output terminal of the second shift register in the first row needs to be connected to the input terminal of the first shift register in the second row. Therefore, cascading line B needs to extend at least two columns along the first direction X, significantly increasing the trace length. Therefore, in the existing scheme described above, there is a significant difference in the trace lengths of cascaded line A and cascaded line B. Since the resistance of a metal trace is proportional to its length, the longer the trace, the greater the resistance. The resistance of cascaded line B is higher than that of cascaded line A. In the scanning drive circuit, this resistance difference leads to different voltage drops during signal transmission, thus affecting the amplitude consistency of the drive signal. Furthermore, parasitic capacitance forms between the metal trace and surrounding conductors (such as adjacent traces). The magnitude of parasitic capacitance is related to factors such as trace length, trace spacing, and dielectric constant. The longer the trace, the larger the parasitic capacitance. Therefore, the parasitic capacitance of cascaded line B is also greater than that of cascaded line A. In integrated circuits, signal transmission delay is typically determined by the product of resistance (R) and parasitic capacitance (C) (RC time constant). Since both the resistance and parasitic capacitance of cascaded line B are greater than those of cascaded line A, its signal transmission delay is also greater, which can lead to problems such as uneven display on the display panel. In ultra-high PPI display panels, the pixel size is extremely small and the driving frequency is high, making the aforementioned problems even more pronounced and severely impacting display quality. Therefore, a design solution that can reduce the difference in cascade line length is needed.

[0026] To address the aforementioned technical problems, this invention provides a display panel, please refer to [reference needed]. Figure 4The display panel 200 includes a display area AA and a non-display area NAA that at least partially surrounds the display area. The display area AA includes a plurality of pixels arranged in an array along a first direction X and a second direction Y. In high PPI displays, the size of these pixels is extremely small (e.g., approximately 12.7 μm at 2000 PPI). The non-display area NAA is located on either side of the display area AA and includes at least one scan driving circuit (i.e., GIP circuit) 10, which provides line-by-line scan signals to each row of pixels within the display area. The scan driving circuit 10 includes a plurality of shift registers 100, each shift register 100 including a first terminal 100a and a second terminal 100b. Each shift register 100 further includes a first shift register 110 and a second shift register 120.

[0027] Please continue to refer to this. Figure 4The scan driving circuit 10 includes a first driving column 11 and a second driving column 12, which are arranged side-by-side along a first direction X (horizontal direction). The first driving column 11 contains a plurality of first shift registers 110, which are distributed in multiple rows along a second direction Y (vertical direction). For example, a first-level first shift register 110 is located in the first row, a second-level first shift register 110 is located in the second row, and so on. Each first shift register 110 includes a first terminal 100a and a second terminal 100b. Similarly, the second driving column 12 contains a plurality of second shift registers 120, which are distributed in multiple rows along the second direction Y, and each second shift register 120 corresponds one-to-one with a first shift register 110. For example, a first-level second shift register 120 and a first-level first shift register 110 are both located in the first row, a second-level second shift register 120 and a second-level first shift register 110 are both located in the second row, and so on. Each second shift register 120 includes a first terminal 100a and a second terminal 100b. In this embodiment, the first terminal 100a of the first shift register 110 and the first terminal 100a of the second shift register 120 are both located between the second terminal 100b of the first shift register 110 and the second terminal 100b of the second shift register 120. In some embodiments, the first terminal 100a can be an input terminal and the second terminal 100b can be an output terminal, or the first terminal 100a can be an output terminal and the second terminal 100b can be an input terminal. Taking the scan drive circuit 10 on the left as an example, the input terminal of the first shift register 110 is located on the side of the first shift register 110 away from the second shift register 120 (i.e., the left side), and the input terminal of the second shift register 120 is located on the side of the second shift register 120 away from the first shift register 110 (i.e., the right side). As another mirror symmetry method, the input terminal of the first shift register 110 can also be located on the side of the first shift register 110 closer to the second shift register 120 (i.e., the right side), and the input terminal of the second shift register 120 can be located on the side of the second shift register 120 closer to the first shift register 110 (i.e., the left side).

[0028] In this embodiment of the invention, by mirror-symmetrically arranging the first shift register 110 and the second shift register 120, the trace length of cascade line B (i.e., the output terminal of the second shift register 120 in a certain row's second drive column 12 connects to the input terminal of the first shift register 110 in the first drive column 11 of the next row) is shortened. In fact, the lengths of cascade line B and cascade line A (i.e., the output terminal of the first shift register 110 in a certain row's first drive column 11 connects to the input terminal of the first shift register 110 in the second drive column 12 of the same row) are close to or equal, thereby reducing the resistance and parasitic capacitance differences between different cascaded traces. Ultimately, this improves the timing consistency of the output signal of the scan drive circuit, enhances the display uniformity of the display panel, and facilitates the implementation of a narrow bezel design.

[0029] Please continue to refer to this. Figure 4 In one embodiment of the present invention, in the second direction Y, the heights of the first shift register 110 and the second shift register 120 are both equal to the height of two rows of pixels. With the increase in display panel resolution (e.g., 2000 PPI), the size of a single pixel in the second direction Y can be reduced to approximately 12.7 μm. However, the shift register 100 in the scan driving circuit 10 is limited by the physical size of the transistors and the requirements of its driving capability, making it difficult to proportionally reduce its minimum height to the height of a single row of pixels. Forcibly compressing the height of the shift register 100 to the height of one row of pixels would result in insufficient transistor layout space, ineffective wiring, and even a decrease in signal driving capability. Therefore, setting the heights of the first shift register 110 and the second shift register 120 to the height of two rows of pixels ensures that the shift register 100 structure has sufficient dimensional margin, guaranteeing the driving strength and waveform integrity of the scan signal. Secondly, since each shift register 100 covers the vertical height of two rows of pixels, and the two columns of shift registers 100 are responsible for driving the odd and even rows respectively, alternating odd and even scanning can still achieve bilateral driving of each row of pixels without losing row resolution due to the increase in the height of the shift registers 100. At the same time, this design avoids excessively increasing the bezel width of the non-display area to accommodate the large-sized shift registers 100, which is beneficial for realizing narrow bezel display panels.

[0030] Please refer to Figures 4-6 , Figure 4 This invention provides a display panel. Figure 5 This is a schematic diagram of the display panel structure in this embodiment. Figure 6 for Figure 5A partial structural diagram is shown. In this embodiment, the first terminal 100a of the shift register 100 serves as the output terminal of the shift register 100, and the second terminal 100b of the shift register 100 serves as the input terminal of the shift register 100. Furthermore, the display panel also includes multiple first signal lines 20 and multiple second signal lines 30. The multiple first signal lines 20 correspond one-to-one with multiple first shift registers 110, and the multiple second signal lines 30 correspond one-to-one with multiple second shift registers 120. The first signal line 20 includes a first concatenation line 21, one end of which is connected to the first terminal 100a of the corresponding first shift register 110, and the other end of which is connected to the second terminal 100b of the second shift register 120 located in the same row. The second signal line 30 includes a second cascade line 31. One end of the second cascade line 31 is connected to the first end 100a of the corresponding second shift register 120, and the other end of the second cascade line 31 is connected to the second end 100b of the first shift register 110 located in the next row. The length of the first cascade line 21 is equal to the length of the second cascade line 31.

[0031] In this embodiment, the cascading line serves to enable signal transmission between different shift registers. Through the aforementioned connection, horizontal cascading (first cascading line 21) is achieved between the first shift register 110 and the second shift register 120 within the same row, and cross-row cascading (second cascading line 31) is achieved between the second shift register 120 and the first shift register 110 in the next row. Since the first shift register 110 and the second shift register 120 are arranged in a mirror-symmetric layout, the path of the first cascading line 21 is: extending from the output terminal (first terminal 100a) of the first shift register 110 to the input terminal (second terminal 100b) of the second shift register 120 in the same row. Its length is mainly determined by the width of the first shift register 110 (i.e., the size of the shift register 100 in the first direction X), approximately equal to the width of a single shift register 100. The path of the second cascading line 31 is: starting from the output terminal of the second shift register 120, first vertically downwards across the height of one row, and then horizontally to the left to the input terminal of the first shift register 110 in the next row. The horizontal extension to the left is approximately the width of a single shift register 100. Since the horizontal distance is much greater than the vertical distance, the length of the second cascade line 31 is primarily determined by the horizontal distance, making it roughly equal to the length of the first cascade line 21. By making the lengths of the first cascade line 21 and the second cascade line 31 close to or equal, the resistance and parasitic capacitance differences between different cascaded traces can be reduced, ensuring consistent signal transmission delay between each shift register 100. Ultimately, the timing of the scan signal output by the scan drive circuit is more precise, improving the brightness uniformity of the display panel.

[0032] Please continue to refer to this. Figure 4-6In one embodiment of the present invention, the first signal line 20 further includes a first scan line 22 and a first compensation line 23. One end of the first scan line 22 is connected to the first terminal 100a (output terminal) of the corresponding first shift register 110, and the other end of the first scan line 22 is connected to the first row of pixels in the corresponding two rows of pixels. One end of the first compensation line 23 is connected to the first terminal 100a of the corresponding first shift register 110, and the other end of the first compensation line 23 extends in the opposite direction to the first scan line 22 and is flush with the second signal line 30. In this embodiment, the second signal line 30 further includes a second scan line 32. One end of the second scan line 32 is connected to the first terminal 100a (output terminal) of the corresponding second shift register 120, and the other end of the second scan line 32 is connected to the second row of pixels in the corresponding two rows of pixels; wherein, the length of the first scan line 22 is greater than the length of the second scan line 32, and the length of the first signal line 20 is equal to the length of the second signal line 30.

[0033] In this embodiment, the first scan line 22 and the second scan line 32 are respectively used to transmit scan signals to their respective corresponding pixel rows. For example, the first scan line 22 transmits scan signals to odd-numbered pixel rows, and the second scan line 32 transmits scan signals to even-numbered pixel rows. Since the first scan line 22 and the first concatenation line 21 share the output of the first shift register 110, and both the first scan line 22 and the first concatenation line 21 extend in the same direction from the non-display area NAA to the display area AA; while the second scan line 32 and the second concatenation line 31 share the output of the second shift register 120, the second scan line 32 extends in the direction from the non-display area NAA to the display area AA, while the second concatenation line 31 extends in the opposite direction, their extension directions are different. Therefore, the length of the first signal line 20 composed of the first scan line 22 and the first concatenation line 21 is less than the length of the second signal line 30 composed of the second scan line 32 and the second concatenation line 31. When scanning signal output nodes and cascaded signal output nodes are shared, differences in the length of different signal lines will lead to inconsistencies in line resistance and parasitic capacitance: shorter signal lines have lower resistance and parasitic capacitance, resulting in faster signal transmission; longer signal lines have higher resistance and parasitic capacitance, resulting in slower signal transmission. This difference will cause timing mismatch and waveform changes in the scanning signal, affecting display uniformity.

[0034] To address the aforementioned issues, one embodiment of the present invention adds a first compensation line 23 to the first signal line 20. One end of the first compensation line 23 is connected to the first terminal 100a (output terminal) of the first shift register 110, and the other end extends in the opposite direction to the first cascade line 21 and the first scan line 22. The extension length of the first compensation line 23 is configured such that the length of the first signal line 20 (including the first cascade line 21, the first scan line 22, and the first compensation line 23) is substantially equal to the length of the second signal line 30 (including the second cascade line 31 and the second scan line 32). In this way, the resistance and parasitic capacitance of the first signal line 20 and the second signal line 30 tend to be consistent, thereby eliminating signal transmission deviation caused by differences in trace length. In some embodiments, the first compensation line 23 may be a dummy metal line that is not connected to any functional module and is only used for load balancing, without participating in actual signal transmission.

[0035] Please refer to Figure 7-8 , Figure 7 This is yet another display panel proposed in this invention. Figure 8 for Figure 7 A partial structural diagram is shown. In this embodiment, the first terminal 100a of the shift register 100 serves as the input terminal of the shift register 100, and the second terminal 100b of the shift register 100 serves as the output terminal of the shift register 100. Furthermore, the display panel also includes multiple first signal lines 20 and multiple second signal lines 30. The multiple first signal lines 20 correspond one-to-one with multiple first shift registers 110, and the multiple second signal lines 30 correspond one-to-one with multiple second shift registers 120. In this embodiment, the first signal line 20 includes a first concatenation line 21. One end of the first concatenation line 21 is connected to the second terminal 100b of the corresponding first shift register 110, and the other end of the first concatenation line 21 is connected to the first terminal 100a of the second shift register 120 located in the same row. The second signal line 30 includes a second cascade line 31. One end of the second cascade line 31 is connected to the second end 100b of the corresponding second shift register 120, and the other end of the second cascade line 31 is connected to the first end 100a of the first shift register 110 located in the next row.

[0036] In this embodiment, the above connection relationship enables horizontal cascading (first cascading line 21) between the first shift register 110 and the second shift register 120 within the same row, and cross-row cascading (second cascading line 31) between the second shift register 120 and the first shift register 110 in the next row. Since the first shift register 110 and the second shift register 120 are arranged in a mirror-symmetric layout, the path of the first cascading line 21 is: extending from the output terminal (second terminal 100b) of the first shift register 110 to the input terminal (first terminal 100a) of the second shift register 120 in the same row, with a length approximately equal to the width of a single shift register 100. The path of the second cascading line 31 is: starting from the output terminal of the second shift register 120, first vertically downwards across one row's height, and then horizontally to the left to the input terminal of the first shift register 110 in the next row. The horizontal leftward extension distance is also approximately the width of a single shift register 100. Since the horizontal distance is much greater than the vertical distance, the length of the second cascade line 31 is mainly determined by the horizontal distance and is approximately equal to the length of the first cascade line 21. By making the lengths of the first cascade line 21 and the second cascade line 31 close to or equal, the resistance and parasitic capacitance differences between different cascaded traces can be reduced, ensuring that the signal transmission delay remains consistent across the shift registers 100. Ultimately, the timing of the scan signal output by the scan drive circuit is more precise, improving the brightness uniformity of the display panel.

[0037] Please continue to refer to this. Figure 7-8 In one embodiment of the present invention, the first signal line 20 further includes a first scan line 22. One end of the first scan line 22 is connected to the second end 100b of the corresponding first shift register 110, and the other end of the first scan line 22 is connected to the first row of pixels in the corresponding two rows of pixels. The second signal line 30 further includes a second scan line 32 and a second compensation line 33. One end of the second scan line 32 is connected to the second end 100b of the corresponding second shift register 120, and the other end of the second scan line 32 is connected to the second row of pixels in the corresponding two rows of pixels. One end of the second compensation line 33 is connected to the second end 100b of the corresponding second shift register 120, and the other end of the second compensation line 33 extends in the opposite direction to the second scan line 32 and is flush with the first signal line 20. The length of the first scan line 22 is greater than the length of the second scan line 32, and the length of the first signal line 20 is equal to the length of the second signal line 30.

[0038] In this embodiment, the first scan line 22 and the second scan line 32 are respectively used to transmit scan signals to their respective corresponding pixel rows. For example, the first scan line 22 transmits scan signals to odd-numbered rows of pixels, and the second scan line 32 transmits scan signals to even-numbered rows of pixels. Since the first scan line 22 and the first concatenation line 21 share the second terminal 100b (output terminal) of the first shift register 110, and the first scan line 22 extends from the leftmost side of the non-display area NAA to the right to connect to the pixel row, while the first concatenation line 21 extends in the same direction to connect to the input terminal of the second shift register 120 in the same row, the length of the first signal line 20 composed of the first scan line 22 and the first concatenation line 21 is approximately equal to the length of the first scan line 22 extending from the leftmost side to the pixel row. Similarly, the second scan line 32 and the second concatenation line 31 share the second terminal 100b (output terminal) of the second shift register 120, and the second scan line 32 extends from the non-display area NAA to the right side of the display area AA to connect to the pixel row, while the second concatenation line 31 extends in the opposite direction to the input terminal of the first shift register 110 in the next row. Therefore, the length of the second signal line 30 composed of the second scan line 32 and the second concatenation line 31 is approximately equal to the sum of the lengths of the second scan line 32 and the second concatenation line 31. Thus, the length of the second signal line 30 is less than the length of the first signal line 20. When scanning signal output nodes and cascaded signal output nodes are shared, differences in the length of different signal lines will lead to inconsistencies in line resistance and parasitic capacitance: shorter signal lines have lower resistance and parasitic capacitance, resulting in faster signal transmission; longer signal lines have higher resistance and parasitic capacitance, resulting in slower signal transmission. This difference will cause timing mismatch and waveform changes in the scanning signal, affecting display uniformity.

[0039] To address the aforementioned issues, one embodiment of the present invention also adds a second compensation line 33 to the second signal line 30. One end of the second compensation line 33 is connected to the second terminal 100b of the second shift register 120, and the other end extends in the same direction as the second cascade line 31. The extension length of the second compensation line 33 is configured such that the length of the first signal line 20 is substantially equal to the length of the second signal line 30. In this way, the resistance and parasitic capacitance of the first signal line 20 and the second signal line 30 tend to be consistent, thereby eliminating signal transmission deviation caused by differences in trace length. In some embodiments, the second compensation line 33 may be a dummy metal line that is not connected to any functional module and is only used for load balancing, without participating in actual signal transmission.

[0040] In previous embodiments, the scan lines and cascade lines shared the output of the shift register. While this simplifies node design, the pixel load connected to the scan lines can couple to the cascade lines, potentially interfering with the transmission stability of the cascaded signals. Therefore, in some embodiments, the output nodes of the scan lines and cascade lines can be separated to achieve load isolation.

[0041] Please refer to Figure 9-10 , Figure 9 This is yet another display panel proposed in this invention. Figure 10 for Figure 9 A partial structural diagram is shown. In this embodiment, the shift register 100 further includes a third terminal 100c and a fourth terminal 100d. In this embodiment, the third terminal 100c can be used as a cascade node for the first shift register 110, and the fourth terminal 100d can be used as a cascade node for the second shift register 120. Meanwhile, the first terminal 100a and the second terminal 100b of the shift register 100 still serve as input and output nodes, thereby achieving physical separation of the cascaded signal path and the scan signal path. Specifically, the display panel includes multiple third cascade lines 40 and multiple fourth cascade lines 50. The multiple third cascade lines 40 correspond one-to-one with multiple first shift registers 110, and the multiple fourth cascade lines 50 correspond one-to-one with multiple second shift registers 120. One end of the third cascade line 40 is connected to the third terminal 100c of the corresponding first shift register 110, and the other end of the third cascade line 40 is connected to the first terminal 100a or the second terminal 100b of the second shift register 120 located in the same row. One end of the fourth concatenation line 50 is connected to the fourth terminal 100d of the corresponding second shift register 120, and the other end of the fourth concatenation line 50 is connected to either the first terminal 100a or the second terminal 100b of the first shift register 110 located in the next row; wherein, the length of the third concatenation line 40 is equal to the length of the fourth concatenation line 50. In this embodiment, one of the first terminal 100a and the second terminal 100b of the shift register 100 is the input terminal of the shift register 100, and the other is the output terminal of the shift register 100.

[0042] In this embodiment, the third concatenation line 40 enables horizontal concatenation between the first shift register 110 and the second shift register 120 within the same row, while the fourth concatenation line 50 enables cross-row concatenation between the second shift register 120 and the first shift register 110 in the next row. Since the concatenation nodes (third terminal 100c, fourth terminal 100d) and the scan output nodes (first terminal 100a, second terminal 100b) are independent, the pixel load carried by the scan lines will not affect the concatenation lines, thus avoiding interference from the scan load on the concatenation signal transmission. Simultaneously, the concatenation lines can independently optimize parameters such as line width and line spacing to further reduce resistance and parasitic capacitance, improving the transmission speed and integrity of the concatenated signals. Furthermore, with separate settings, even if the scan lines experience waveform distortion due to a large load, it will not affect the timing accuracy of the concatenated signals, thereby ensuring the concatenation stability between each level of shift register and improving the reliability and display uniformity of the entire scan drive circuit.

[0043] Please continue to refer to this. Figure 9-10In one embodiment of the present invention, the display panel further includes multiple third signal lines 60 and multiple fourth signal lines 70. The multiple third signal lines 60 correspond one-to-one with multiple first shift registers 110, and the multiple fourth signal lines 70 correspond one-to-one with multiple second shift registers 120. Each third signal line 60 includes a third scan line 61, one end of which is connected to either the first terminal 100a or the second terminal 100b of the corresponding first shift register 110, and the other end of which is connected to the first row of pixels in the corresponding two rows of pixels. Each fourth signal line 70 includes a fourth scan line 71, one end of which is connected to either the first terminal 100a or the second terminal 100b of the corresponding second shift register 120, and the other end of which is connected to the second row of pixels in the corresponding two rows of pixels. The length of the third scan line 61 is greater than the length of the fourth scan line 71. The fourth signal line 70 also includes a third compensation line 72. One end of the third compensation line 72 is connected to the first end 100a or the second end 100b of the corresponding second shift register 120, and the other end of the third compensation line 72 extends in the opposite direction to the fourth scan line 71 and is flush with the third scan line 61; wherein, the length of the third signal line 60 is equal to the length of the fourth signal line 70.

[0044] In this embodiment, since the cascade node and the scan output node are set separately, the third scan line 61 and the fourth scan line 71 no longer share nodes with the cascade line. In this case, the third scan line 61 extends to the right from the output terminal of the first shift register 110 (e.g., the second terminal 100b) to the odd-numbered rows of pixels in the display area AA, and the fourth scan line 71 extends to the right from the output terminal of the second shift register 120 to the even-numbered rows of pixels in the display area AA. Therefore, the length of the third scan line 61 is greater than the length of the fourth scan line 71. This length difference will cause the resistance and parasitic capacitance of the two scan lines to be different, resulting in timing deviations and waveform distortions in the scan signals received by the odd-numbered and even-numbered rows of pixels, affecting the uniformity of the display.

[0045] To address the aforementioned issues, this embodiment adds a third compensation line 72 to the fourth signal line 70. This third compensation line 72 shares an output terminal with the fourth scan line 71 and extends in the opposite direction to the fourth scan line 71. Its extension length is configured such that the length of the fourth signal line 70 (length of the fourth scan line 71 + length of the third compensation line 72) is substantially equal to the length of the third signal line 60 (length of the third scan line 61). In this way, the resistance and parasitic capacitance of the third signal line 60 and the fourth signal line 70 tend to be consistent, thereby eliminating the imbalance of odd and even row scanning signals caused by the difference in scan line lengths. In some embodiments, the third compensation line 72 may be a dummy metal line that is not connected to any functional module and is only used to adjust the total length, without participating in the actual scan signal transmission.

[0046] Please refer to Figure 11-12 , Figure 11 This is yet another display panel proposed in this invention. Figure 12 for Figure 11 A partial structural diagram is shown. This display panel also uses separately configured cascading nodes and scan output nodes to achieve cascading and scan output. The settings of each port, cascading line, and scan line are as described above and will not be repeated here.

[0047] By separating the cascade nodes from the scan output nodes and using a compensation line design, this embodiment of the invention achieves both cascade line length balance and scan line load balance, thereby comprehensively improving the scan driving performance of ultra-high PPI display panels.

[0048] Please continue to refer to this. Figure 4-11 The scan drive circuit also includes an input signal line, a first clock signal line, and a second clock signal line. The input signal line is connected to either a first terminal 100a or a second terminal 100b of the first shift register 110 in the first row of the first drive column. The first clock signal line is connected to either a first terminal 100a or a second terminal 100b of each first shift register 110, and is also connected to either a first terminal 100a or a second terminal 100b of each second shift register 120. The second clock signal line is connected to either a first terminal 100a or a second terminal 100b of each first shift register 110, and is also connected to either a first terminal 100a or a second terminal 100b of each second shift register 120.

[0049] In this embodiment, the input signal line is only connected to the first shift register 110 in the first row of the first driving column, and is used to provide the start signal SIN to the scan driving circuit 10 to start the line-by-line scanning process. The first clock signal line and the second clock signal line are respectively connected to the input terminals of all first shift registers 110 and all second shift registers 120, that is, the input terminal of each shift register 100 can receive two clock signals SCK1 and SCK2. This connection method enables the scan driving circuit 10 to generate alternating scan outputs according to different clock phases, thereby realizing the line-by-line scanning control of odd and even rows of pixels. Since the first shift registers 110 and the second shift registers 120 adopt a mirror symmetrical layout, by reasonably planning the routing path of the clock signal line and using the mirror symmetrical design to make the positions of the input terminals on both sides relatively centered, the length of the clock signal line can be effectively shortened, the load capacitance and resistance of the clock signal can be reduced, thereby ensuring the consistency of the clock signal among the shift registers. Furthermore, using alternating inputs of dual clock signals (SCK1 and SCK2) can avoid waveform distortion caused by a single clock signal during long-distance transmission, thereby improving the reliability and high-frequency performance of the scan drive. In this embodiment, one of the first terminal 100a and the second terminal 100b of the shift register 100 serves as the input terminal of the shift register 100, and the other serves as the output terminal of the shift register 100.

[0050] by Figure 4 Taking the display panel structure shown as an example, the specific process of the scan drive circuit 10 implementing line-by-line scanning is as follows: First, the input signal line transmits the start signal SIN (e.g., a strobe start pulse) to the input terminal (second terminal 100b) of the first shift register 110 (i.e., the first-stage first shift register 110) in the first row of the first driving column 11. Upon receiving the start signal SIN and the clock signals SCK1 / SCK2 provided by the first or second clock signal line, the first shift register 110 generates a corresponding first scan signal and a first concatenated signal. The first scan signal is output to the corresponding first row of pixels (odd rows) via the first scan line 22 connected to the output terminal (first terminal 100a), completing the scan driving of the first row of pixels. Simultaneously, the first concatenated signal is transmitted to the input terminal of the second shift register 120 in the same row (first row) via the first concatenated line 21 connected to the output terminal. After receiving the first concatenated signal, the second shift register 120 combines it with the clock signals SCK1 / SCK2 to generate a second scan signal and a second concatenated signal. The second scan signal is output to the corresponding second row of pixels (even-numbered rows) via the second scan line 32 connected to the first terminal 100a, completing the scanning drive of the second row of pixels. Simultaneously, the second concatenation signal is transmitted to the input of the first shift register 110 of the next row (second row) via the second concatenation line 31 connected to the first terminal 100a. This first shift register 110 is triggered by the second concatenation signal, generating the corresponding first scan signal and first concatenation signal, and completing pixel scanning and the activation of the next shift register 100 via the scan line and concatenation line, respectively. Similarly, each first shift register 110 in the first driving column 11 sequentially generates scan signals for odd-numbered rows, and each second shift register 120 in the second driving column 12 sequentially generates scan signals for even-numbered rows. Thus, by using the alternating output of the two columns of shift registers 100, line-by-line scanning of all pixel rows within the display area AA is achieved.

[0051] Based on the same inventive concept, the present invention also provides a display device. Please refer to... Figure 13 The display device 300 includes the display panel 200 as described above. The display device can be any device with display function, such as a mobile phone, tablet computer, laptop computer, handheld computer, in-vehicle electronic device, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a non-mobile device such as a personal computer (PC), television (TV), ATM, or self-service machine.

[0052] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A display panel, characterized in that, include: The display area includes a plurality of pixels arranged in an array along a first direction and a second direction; the first direction intersects the second direction; A non-display area, at least partially surrounding the display area; the non-display area includes at least one scan driving circuit, the scan driving circuit includes a plurality of shift registers, the shift registers include a first end and a second end, and the scan driving circuit includes a first driving column and a second driving column arranged along the first direction. The plurality of shift registers includes a first shift register and a second shift register. The first drive column includes a plurality of first shift registers arranged along the second direction, and the second drive column includes a plurality of second shift registers arranged along the second direction. The plurality of first shift registers and the plurality of second shift registers correspond one-to-one, and the first end of the first shift register and the first end of the second shift register are both located between the second end of the first shift register and the second end of the second shift register.

2. The display panel according to claim 1, characterized in that: In the second direction, the height of both the first shift register and the second shift register is equal to the height of the two rows of pixels.

3. The display panel according to claim 2, characterized in that, Also includes: Multiple first signal lines, each corresponding to a plurality of first shift registers; each first signal line includes a first concatenation line, one end of which is connected to the first end of the corresponding first shift register, and the other end of which is connected to the second end of the second shift register located in the same row. Multiple second signal lines, each corresponding to a plurality of second shift registers; each second signal line includes a second concatenation line, one end of which is connected to the first end of the corresponding second shift register, and the other end of which is connected to the second end of the first shift register located in the next row; Wherein, the length of the first cascade is equal to the length of the second cascade; Preferably, the first end of the shift register is the output end of the shift register, and the second end of the shift register is the input end of the shift register.

4. The display panel according to claim 3, characterized in that, The first signal line also includes: The first scan line, one end of which is connected to the first end of the corresponding first shift register, and the other end of which is connected to the first row of pixels in the corresponding two rows of pixels; The first compensation line has one end connected to the first end of the corresponding first shift register, and the other end of the first compensation line extends in the opposite direction to the first scan line and is flush with the second signal line. The second signal line also includes: The second scan line has one end connected to the first end of the corresponding second shift register, and the other end connected to the second row of pixels in the corresponding two rows of pixels; Wherein, the length of the first scan line is greater than the length of the second scan line, and the length of the first signal line is equal to the length of the second signal line.

5. The display panel of claim 2, wherein, Also includes: Multiple first signal lines, each corresponding to a plurality of first shift registers; each first signal line includes a first concatenation line, one end of which is connected to the second end of the corresponding first shift register, and the other end of which is connected to the first end of the second shift register located in the same row. Multiple second signal lines, each corresponding one-to-one with a plurality of second shift registers; each second signal line includes a second concatenation line, one end of which is connected to the second end of the corresponding second shift register, and the other end of which is connected to the first end of the first shift register located in the next row; wherein, the length of the first concatenation line is equal to the length of the second concatenation line; Preferably, the first signal line further includes: The first scan line has one end connected to the second end of the corresponding first shift register, and the other end connected to the first row of pixels in the corresponding two rows of pixels. Preferably, the second signal line further includes: The second scan line, one end of which is connected to the second end of the corresponding second shift register, and the other end of which is connected to the second row of pixels in the corresponding two rows of pixels; The second compensation line; one end of the second compensation line is connected to the second end of the corresponding second shift register, and the other end of the second compensation line extends in the opposite direction to the second scan line and is flush with the first signal line; wherein, the length of the first scan line is greater than the length of the second scan line, and the length of the first signal line is equal to the length of the second signal line; Preferably, the first end of the shift register is the input end of the shift register, and the second end of the shift register is the output end of the shift register.

6. The display panel according to claim 2, characterized in that: The shift register also includes a third terminal and a fourth terminal; The display panel also includes: Multiple third-level concatenation lines are provided, each corresponding to one of the multiple first shift registers. One end of each third-level concatenation line is connected to the third end of the corresponding first shift register, and the other end of each third-level concatenation line is connected to the first or second end of the second shift register located in the same row. Multiple fourth-level concatenation lines are provided, each corresponding to one of the multiple second shift registers. One end of each fourth-level concatenation line is connected to the fourth end of the corresponding second shift register, and the other end of each fourth-level concatenation line is connected to the first or second end of the first shift register located in the next row. Wherein, the length of the third-level connector is equal to the length of the fourth-level connector; Preferably, one of the first end and the second end of the shift register is the input end of the shift register, and the other is the output end of the shift register.

7. The display panel of claim 6, wherein, Also includes: Multiple third signal lines are provided, each corresponding to one of the multiple first shift registers. Each third signal line includes a third scan line, one end of which is connected to the first or second end of the corresponding first shift register, and the other end of which is connected to the first row of pixels in the corresponding two rows of pixels. Multiple fourth signal lines are provided, each corresponding to one of the multiple second shift registers. Each fourth signal line includes a fourth scan line, one end of which is connected to the first or second end of the corresponding second shift register, and the other end of which is connected to the second row of pixels in the corresponding two rows of pixels. The length of the third scan line is greater than the length of the fourth scan line.

8. The display panel of claim 7, wherein: The fourth signal line also includes a third compensation line; one end of the third compensation line is connected to the first or second end of the corresponding second shift register, and the other end of the third compensation line extends in the opposite direction to the fourth scan line and is flush with the third scan line. The length of the third signal line is equal to the length of the fourth signal line.

9. The display panel of claim 1, wherein, Also includes: An input signal line is connected to either the first or second end of the first shift register in the first row of the first drive column. The first clock signal line is connected to the first or second terminal of each of the first shift registers, and the first clock signal line is connected to the first or second terminal of each of the second shift registers. The second clock signal line is connected to either the first or second end of each of the first shift registers, and the second clock signal line is also connected to either the first or second end of each of the second shift registers.

10. A display device, characterized by comprising: Includes the display panel as described in any one of claims 1-9.

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