Phase-locked loop, control method and frequency source

Abstract

This application provides a phase-locked loop (PLL), a control method, and a frequency source. It includes a controller, a time-to-digital converter (TD-to-digital converter), an arithmetic logic unit (ALU), a digitally controlled oscillator (DCO), and a frequency divider. The DCO outputs a linearly swept frequency signal based on a frequency control signal from the ALU. The frequency divider generates a divided frequency signal based on the output frequency of the DCO. The TD-to-digital converter outputs the phase difference between the divided frequency signal and a reference signal. The ALU outputs a frequency control signal based on the phase difference and a control code to adjust the output frequency of the DCO. The controller acquires the output signal of the TD-to-digital converter after a step point in the division ratio, and adjusts the control code until the output signal of the TD-to-digital converter after the step point is zero when the output signal is not zero. This method improves the linearity of the sawtooth waveform generated by the PLL at the step point.

Description

TECHNICAL FIELD

[0001] The present application relates to the control technology of phase-locked loop, and in particular to a phase-locked loop, a control method and a frequency source. BACKGROUND

[0002] Linear sweep frequency source is a key element of linear sweep radar. Linear sweep radar transmits frequency signals of sawtooth waveform which linearly changes with time to the target to be measured through the transmitter, and the receiver receives the echo signal. The frequency difference between the echo signal and the transmitted signal is used to calculate the distance of the target to be measured. The linearity of the frequency source directly affects the accuracy of the measurement result.

[0003] At present, the linear sweep frequency signal of sawtooth waveform is usually generated based on the phase-locked loop structure. When the output frequency of the phase-locked loop jumps from the highest point to the lowest point at the step point, the output waveform of the phase-locked loop is prone to nonlinearity. SUMMARY

[0004] Embodiments of the present application provide a phase-locked loop, a control method and a frequency source to improve the linearity of the sawtooth waveform generated by the phase-locked loop at the step point.

[0005] In a first aspect, embodiments of the present application provide a phase-locked loop, comprising: a controller, a time-to-digital converter, an operator, a digitally controlled oscillator and a frequency divider;

[0006] The digitally controlled oscillator is connected with the operator, and the digitally controlled oscillator is configured to output a linear sweep frequency signal according to a frequency control signal output by the operator;

[0007] The input end of the frequency divider is connected with the output end of the digitally controlled oscillator, and the output end of the frequency divider is connected with the input end of the time-to-digital converter. The frequency divider is configured to generate a frequency division signal according to the output frequency of the digitally controlled oscillator; and the time-to-digital converter is configured to output a phase difference between the frequency division signal and a reference signal;

[0008] The input end of the operator is connected with the output end of the time-to-digital converter and receives a control code. The operator is configured to output the frequency control signal according to the phase difference and the control code, so as to adjust the output frequency of the digitally controlled oscillator;

[0009] The controller is connected with the time-to-digital converter and the operator. The controller is configured to acquire the output signal of the time-to-digital converter after the step point of the frequency division ratio, and adjust the control code when the value of the output signal of the time-to-digital converter is not zero, until the value of the output signal of the time-to-digital converter after the step point is zero.

[0010] Optionally, the controller comprises:

[0011] Adder, first multiplier, second multiplier, accumulator;

[0012] The adder is connected to the accumulator via the first multiplier and the second multiplier;

[0013] The adder is used to sum the n consecutive output signals of the time-to-digital converter after the step point;

[0014] The first multiplier is used to output the result of the adder to the second multiplier after the step point;

[0015] The second multiplier is used to multiply the output of the first multiplier by a scaling factor and output the result to the accumulator;

[0016] The accumulator is used to sum the result of the multiplication with the difference between the highest and lowest points of the current control code to obtain a first result; wherein the difference between the highest and lowest points of the adjusted control code is the first result.

[0017] Optionally, the phase-locked loop further includes: a digital filter;

[0018] The time-to-digital converter is connected to the arithmetic unit via the digital filter;

[0019] The digital filter is used to filter the signal output by the time-to-digital converter.

[0020] Secondly, embodiments of this application provide a control method for a phase-locked loop (PLL), applied to a controller of the PLL as described in any one of the first aspects, the method comprising:

[0021] Obtain the output signal of the time-to-digital converter after the frequency division ratio reaches the step point;

[0022] If the output signal of the time-to-digital converter is not zero, the lowest point of the control code of the digital control oscillator is adjusted until the output signal of the time-to-digital converter is zero after the step point.

[0023] Optionally, adjusting the lowest point of the control code of the digitally controlled oscillator specifically includes:

[0024] If the output signal value of the time-to-digital converter is greater than zero, then the lowest point of the control code of the digitally controlled oscillator is increased to increase the output frequency of the phase-locked loop.

[0025] If the output signal value of the time-to-digital converter is less than zero, the lowest point of the control code of the digitally controlled oscillator is reduced to decrease the output frequency of the phase-locked loop.

[0026] Optionally, adjusting the lowest point of the control code of the digitally controlled oscillator specifically includes:

[0027] Acquire n consecutive output signals of the time-to-digital converter after the step point; where n is a positive integer;

[0028] Add n consecutive output signals, multiply by a scaling factor, and sum the result of the multiplication with the difference between the highest and lowest points of the current control code to obtain the first result;

[0029] The lowest point of the control code of the digitally controlled oscillator is adjusted, wherein the difference between the highest and lowest points of the adjusted control code is the first result.

[0030] Optionally, adjusting the lowest point of the control code of the digitally controlled oscillator includes:

[0031] Obtain the magnitude of the highest point of the control code of the digitally controlled oscillator;

[0032] Calculate the difference between the size of the highest point and the first result;

[0033] The value of the lowest point of the control code is adjusted to the difference result.

[0034] Optionally, the value of n is 3.

[0035] Optionally, the method further includes:

[0036] If the output signal of the time-to-digital converter is zero, then the lowest point of the control code of the digitally controlled oscillator remains unchanged.

[0037] Thirdly, embodiments of this application provide a frequency source, including a phase-locked loop as described in any of the first aspects.

[0038] The phase-locked loop, control method, and frequency source provided in this application embodiment allow the phase-locked loop controller to adjust the lowest point of the control code of the digital control oscillator at the step point, thereby achieving a zero output value of the time-to-digital converter (TDC). This ensures that the phase-locked loop remains locked at the step point, improving the linearity of the sawtooth waveform generated by the phase-locked loop at the step point. Attached Figure Description

[0039] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0040] Figure 1 This is a schematic diagram illustrating the application scenarios involved in the embodiments of this application;

[0041] Figure 2 A schematic diagram of a linear sweep frequency signal provided in an embodiment of this application;

[0042] Figure 3 This is a schematic diagram of a phase-locked loop provided in an embodiment of this application;

[0043] Figure 4 This is a schematic diagram of a nonlinear waveform at a step point;

[0044] Figure 5 This is a schematic diagram of another phase-locked loop provided in an embodiment of this application;

[0045] Figure 6 A schematic diagram illustrating the adjustment of a control code provided in an embodiment of this application;

[0046] Figure 7 A schematic flowchart illustrating a phase-locked loop control method provided in an embodiment of this application;

[0047] Figure 8 A schematic flowchart illustrating the second phase-locked loop control method provided in this application embodiment;

[0048] Figure 9 This is a flowchart illustrating the third phase-locked loop control method provided in this application embodiment.

[0049] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0050] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0051] Figure 1 This is a schematic diagram illustrating an application scenario involved in an embodiment of this application. For example... Figure 1As shown, the specific application scenario of this application is ranging using a linear sweep frequency radar. The linear sweep frequency source is a key component of a linear sweep frequency radar. The transmitter of the linear sweep frequency radar uses the linear sweep frequency source to transmit a linear sweep frequency signal to the target. This waveform can be a sine wave whose frequency increases proportionally with time, and the receiver receives the echo signal. There is a certain time difference between the transmitted signal and the echo signal; at the moment the echo signal is received, the frequency of the transmitted signal has changed to a new frequency. Dividing the frequency difference between the transmitted and echo signals at the same moment by the rate of change of frequency with time yields the propagation time of the transmitted and echo signals between the radar and the target. The larger the frequency difference between the echo and transmitted signals at the same moment, the longer the propagation time of the transmitted and echo signals, and the farther the target is. Therefore, the frequency difference between the echo and transmitted signals at the same moment can be used to calculate the distance to the target. If the frequency of the linear waveform generated by the frequency source does not change proportionally with time, the calculated distance to the target will deviate from the actual distance to the object. Therefore, the linearity of the frequency source directly affects the accuracy of the measurement results.

[0052] Figure 2 This is a schematic diagram of a linear sweep frequency signal provided in an embodiment of this application. The waveforms of commonly used linear sweep frequency sources generally have two shapes: sawtooth waves and triangular waves. For example... Figure 2 As shown in (a), the signal is a linear sweep frequency signal of a triangular wave waveform, also known as a continuously modulated triangular wave. Figure 2 (a) Solid lines represent transmitted wave signals, and dashed lines represent echo signals. The radar transmitter sends a linearly swept frequency signal with a triangular wave waveform, and the receiver receives the echo signal. The frequency difference between the transmitted wave signal and the echo signal at the same moment is proportional to the distance to the target.

[0053] like Figure 2 As shown in (b), the signal is a linear sweep frequency signal of a sawtooth wave waveform, also known as a continuously modulated sawtooth wave. Figure 2 (b) The dashed line represents the transmitted wave signal, and the dashed line represents the echo signal. The radar transmitter sends a linearly swept frequency signal of a sawtooth wave waveform, and the receiver receives the echo signal. The frequency difference between the transmitted wave signal and the echo signal at the same moment is proportional to the distance to the target.

[0054] The linear sweep frequency signal of a sawtooth waveform is widely used in linear sweep frequency radar due to its simplicity of implementation and its fast fallback characteristic, which allows for faster ranging update rates and improved ranging resolution. This linear sweep frequency signal of the sawtooth waveform is typically generated based on a phase-locked loop (PLL) structure.

[0055] Figure 3 This is a schematic diagram of a phase-locked loop provided in an embodiment of this application.Figure 3 As shown, the phase-locked loop includes a time-to-digital converter, a digitally controlled oscillator, and a frequency divider. The phase-locked loop can be any device that synchronizes the frequency and phase of the output signal with the frequency and phase of the input signal, such as an all-digital phase-locked loop (ADPLL), an analog phase-locked loop, or any other type. This application uses an all-digital phase-locked loop (ADPLL) as an example for illustrative purposes.

[0056] A time-to-digital converter (TDC) can be any device that can convert a time interval or phase difference into a digital signal.

[0057] A digitally controlled oscillator (DCO) can be any oscillator that can generate a frequency-adjustable output signal by being controlled by a digital signal, such as a control code.

[0058] A frequency divider (DIV) can be any device that divides the input frequency according to the input division ratio.

[0059] The Digital Controlled Oscillator (DCO) outputs signals of different frequencies depending on the value of the input control code; a larger control code value results in a higher output frequency, and a smaller control code value results in a lower output frequency. The frequency divider (DIV) divides the frequency signal output by the DCO to generate a divided frequency signal, which is fed back to the Time-to-Digital Converter (TDC). The TDC measures the phase difference between the divided frequency signal and a reference signal and converts this phase difference into a digital phase difference signal. The reference signal can be, for example, a signal generated by a local oscillator, an external clock signal, or a GPS signal. The digital phase difference signal output by the TDC is used to adjust the value of the control code in the DCO, thereby achieving phase locking.

[0060] Furthermore, the phase-locked loop (PLL) also includes a digital filter. The digital loop filter (DLF) can be any filter that allows certain frequency signals to pass while suppressing others; for example, it can be a low-pass filter, or any type such as a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter. The digital phase difference signal output from the time-to-digital converter (TDC) is filtered by the DLF to remove high-frequency noise, and then used to adjust the control code of the digitally controlled oscillator (DCO), further improving the stability of the PLL.

[0061] In one example, when the frequency of the divided signal is lower than the frequency of the reference signal, the digital phase difference signal output by the time-to-digital converter (TDC) is greater than zero. After high-frequency noise is removed by the digital filter (DLF), this digital phase difference signal is summed with the control code, thereby increasing the value of the control code. As the value of the control code increases, the frequency of the digitally controlled oscillator (DCO) increases, so that the phase-locked loop can output an output signal that is synchronized with the frequency and phase of the reference signal.

[0062] In one example, when the frequency of the divided signal is higher than the frequency of the reference signal, the digital phase difference signal output by the time-to-digital converter (TDC) is less than zero. After high-frequency noise is removed by the digital filter (DLF), this digital phase difference signal is summed with the control code, thereby reducing the value of the control code. As the value of the control code decreases, the frequency output by the digitally controlled oscillator (DCO) decreases, so that the phase-locked loop can output an output signal that is synchronized with the frequency and phase of the reference signal.

[0063] When generating a linear sweep frequency signal with a sawtooth waveform based on a fully digital phase-locked loop (ADPLL), the ADPLL employs a two-point modulation mode, simultaneously modulating the inputs of the frequency divider (DIV) and the digitally controlled oscillator (DCO). For example, if the frequency of the sawtooth wave output by the ADPLL is required to gradually increase, the division ratio at the DIV input needs to gradually increase, and simultaneously, the control code at the DCO input also needs to gradually increase. Changes in the DCO control code directly affect the oscillator's output frequency; by precisely controlling the change in the control code value, linear frequency growth can be achieved. In practical applications, due to the nonlinear characteristics of the DCO, directly changing the control code may lead to nonlinear changes in the output frequency. As mentioned earlier, the ADPLL has a feedback mechanism that can effectively compensate for these nonlinear effects. The time-to-digital converter (TDC) and the digital filter (DLF) can adjust the input of the DCO, ensuring that the output frequency maintains a linear change. Because both the frequency division ratio and the control code are gradually changing signals, the nonlinearity generated by the DCO control code can be eliminated by the all-digital phase-locked loop (ADPLL). Through these adjustments, the ADPLL can output a signal with a gradually increasing frequency. To obtain a sawtooth waveform, the output frequency can be reset to its initial value at the end of each time period, thus forming a periodic sawtooth wave.

[0064] However, when the output frequency is reset to its initial value at the end of each time cycle, the output frequency of the all-digital phase-locked loop (ADPLL) changes from its highest frequency to its lowest frequency, which is the step point of the sawtooth waveform. At this time, the division ratio of the frequency divider (DIV) is reset from its maximum value to its minimum value, and the control code of the digitally controlled oscillator (DCO) is also reset from its maximum value to its minimum value. In practical applications, the output frequency and control code of the DCO are positively correlated, but they cannot be perfectly matched one-to-one. This may result in the DCO's control code resetting from its peak to its lowest point, where the value at the lowest point is either too large or too small. The lowest point of the DCO's control code may not match the minimum value of the division ratio well. In this case, the ADPLL needs to relock, requiring both frequency sweeping and locking, which may lead to poor linearity of the output sawtooth waveform at the lowest frequency point. For ease of explanation, the peak can also be referred to as the highest point.

[0065] Figure 4 This is a schematic diagram of a nonlinear waveform at a step point. For example... Figure 4 As shown, at the step point, when the output frequency of the digitally controlled oscillator (DCO) is too low, the output of the time-to-digital converter (TDC) is positive, and the output frequency needs to be increased.

[0066] At the step point, when the output frequency of the digitally controlled oscillator (DCO) is too high, the output of the time-to-digital converter (TDC) becomes negative, and the output frequency needs to be reduced.

[0067] In view of this, this application proposes a phase-locked loop (PLL) with a newly added PLL controller. The controller is used to adjust the lowest point of the control code of the digital control oscillator (DCO) to make the output value of the time-to-digital converter (TDC) zero when the output frequency needs to be reset to the minimum value at the end of each time period of the sawtooth waveform. This means that the phase difference between the frequency division signal generated by the frequency divider (DIV) and the reference signal is the same, indicating that the sawtooth waveform is at the step point. The all-digital PLL (ADPLL) remains locked, improving the linearity of the sawtooth waveform at the frequency step point.

[0068] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0069] Figure 5 This is a schematic diagram of another phase-locked loop provided in an embodiment of this application. Figure 5 As shown, it includes: a controller, a time-to-digital converter, an arithmetic unit, a digitally controlled oscillator, and a frequency divider.

[0070] The arithmetic unit can be any arithmetic unit capable of performing addition or subtraction operations.

[0071] The controller can be any device capable of performing addition and multiplication operations, such as a microcontroller, embedded processor, programmable logic device, or any other processing unit. Optionally, in addition to the processing unit, it may also include peripheral circuit units for the processing unit. The controller may also be an arithmetic circuit including adders and multipliers.

[0072] The digitally controlled oscillator (DCO) is connected to the arithmetic logic unit (ALU). The DCO is used to output a linear sweep frequency signal based on the frequency control signal output by the ALU.

[0073] The input of the frequency divider DIV is connected to the output of the digitally controlled oscillator, and the output of the frequency divider is connected to the input of the time-to-digital converter. The frequency divider is used to generate a frequency-divided signal based on the output frequency of the digitally controlled oscillator. The time-to-digital converter is used to output the phase difference between the frequency-divided signal and the reference signal.

[0074] The input terminal of the arithmetic unit is connected to the output terminal of the time-to-digital converter (TDC) and receives control codes. The arithmetic unit is used to output a frequency control signal based on the phase difference and the control code to adjust the output frequency of the digitally controlled oscillator (DCO).

[0075] The choice between an adder and a subtractor in the arithmetic unit depends on the output signal of the phase-locked loop time-to-digital converter (TDC).

[0076] For example, when the frequency of the divided signal is lower than the frequency of the reference signal, the output digital phase difference signal is greater than zero; when the frequency of the divided signal is higher than the frequency of the reference signal, the output digital phase difference signal is less than zero. In this mode, the arithmetic unit can select an adder. Alternatively, when the frequency of the divided signal is lower than the frequency of the reference signal, the output digital phase difference signal is less than zero; when the frequency of the divided signal is higher than the frequency of the reference signal, the output digital phase difference signal is greater than zero. In this mode, the arithmetic unit can select a subtractor. This embodiment illustrates the situation where the time-to-digital converter (TDC) outputs a digital phase difference signal greater than zero when the frequency of the divided signal is lower than the frequency of the reference signal, and a digital phase difference signal less than zero when the frequency of the divided signal is higher than the frequency of the reference signal, using an adder as the arithmetic unit.

[0077] In one example, when the frequency of the divided signal is lower than the frequency of the reference signal, the digital phase difference signal output by the time-to-digital converter (TDC) is greater than zero. The arithmetic logic unit (ALU) can sum the control code with this digital phase difference signal and output an increased frequency control signal, thereby increasing the value of the control code. The increased control code value leads to an increased frequency output by the digital controlled oscillator (DCO), allowing the phase-locked loop (PLL) to output a signal synchronized with the reference signal in both frequency and phase. Conversely, when the frequency of the divided signal is higher than the frequency of the reference signal, the digital phase difference signal output by the time-to-digital converter (TDC) is less than zero. The ALU can sum the control code with this digital phase difference signal and output a decreased frequency control signal, thereby decreasing the value of the control code. The decreased control code value leads to a decreased frequency output by the DCO, allowing the PLL to output a signal synchronized with the reference signal in both frequency and phase. In this case, the ALU can select an adder.

[0078] The controller connects the time-to-digital converter (TDC) and the arithmetic unit. The controller is used to acquire the output signal of the TDC after the step point of the frequency division ratio, and adjust the control code when the value of the output signal of the TDC is not zero, until the value of the output signal of the TDC after the step point is zero.

[0079] The output frequency of the digitally controlled oscillator (DCO) can be adjusted by regulating the lowest point of the control code; the frequency signal after the phase-locked loop (PLL) output frequency is divided by the frequency divider (DIV) will also change. This alters the input signal of the time-to-digital converter (TDC). When the frequency and phase of the TDC input signal are synchronized with the reference signal, the output signal of the TDC at the step point can be zero. This ensures that the output frequency of the PLL output signal at the step point is synchronized with the frequency and phase of the reference signal.

[0080] In summary, the phase-locked loop provided in this application embodiment, by adding a controller, can adjust the lowest point of the control code of the digital control oscillator at the step point, thereby achieving a zero output value of the time-to-digital converter (TDC). This ensures that the phase-locked loop remains locked at the step point, improving the linearity of the sawtooth waveform generated by the phase-locked loop at the step point.

[0081] Furthermore, the controller may include: an adder, a first multiplier, a second multiplier, and an accumulator;

[0082] An adder can be any arithmetic unit capable of performing addition. Both the first and second multipliers can be any arithmetic unit capable of performing multiplication. An accumulator can be any arithmetic unit that performs addition and accumulates values. For example, an accumulator can sum the first and second addends to obtain a first sum, update the first sum to the first addend, and then perform the next summation operation with the next second addend.

[0083] The adder is connected to the accumulator via a first multiplier and a second multiplier. The adder is used to sum the n consecutive output signals of the time-to-digital converter after the step point.

[0084] The first multiplier outputs the result of the adder to the second multiplier after the step point. For example, the sawtooth reset signal can be positive 1 or negative 1 after the step point, and 0 at other times. This ensures that the result of the adder is output to the second multiplier after the step point. The second multiplier multiplies the output of the first multiplier by a scaling factor and outputs it to the accumulator.

[0085] The accumulator is used to sum the result of the multiplication with the difference between the highest and lowest points of the current control code to obtain the first result; wherein, the difference between the highest and lowest points of the adjusted control code is the first result.

[0086] In one example, after a step point, n consecutive time-to-digital converter (TDC) output signals are summed by an adder and then input into a first multiplier. The first multiplier then multiplies this signal by a sawtooth reset signal, which is input into a second multiplier. The second multiplier then multiplies this signal by a scaling factor k, which is input into an accumulator. The accumulator sums the result of the multiplication with the difference between the highest and lowest points of the current control code to obtain the adjusted difference between the highest and lowest points of the control code. Subtracting the adjusted difference between the highest and lowest points of the control code from the highest point of the control code yields the lowest point of the control code.

[0087] After the next step point, n consecutive time-to-digital converter (TDC) output signals are added together by an adder and then input into the first multiplier. The first multiplier then multiplies this signal by a sawtooth wave reset signal and inputs it into the second multiplier. The second multiplier then multiplies this signal by a scaling factor k and inputs it into an accumulator. The accumulator sums the result of the multiplication with the difference between the highest and lowest points of the control code at the next step point to obtain the adjusted difference between the highest and lowest points of the control code. This process is equivalent to continuously accumulating the difference between the highest and lowest points of the control code multiplied by the result at each step point.

[0088] The following example, using three signals output by n consecutive time-to-digital converters (TDCs), illustrates how to adjust the difference between the peak and trough of the control code.

[0089] If the output value of the time-to-digital converter (TDC) is greater than zero after the control code input to the digitally controlled oscillator (DCO) is reset from its peak to its lowest point, it indicates that the DCO output frequency is too low and needs to be increased. Therefore, the difference between the peak and lowest points of the control code needs to be reduced, and the reduction can be k*(TDC). <0> +TDC <1> +TDC <2> The absolute value of ), where k is the proportionality constant. TDC <0> TDC <1> TDC <2> These are the first three values ​​output by the Time-to-Digital Converter (TDC) after the control code is reset from the vertices. Figure 5 In the structure shown, if the value of the sawtooth wave reset signal is negative, the value of the proportional coefficient k can be positive; or, if the value of the sawtooth wave reset signal is positive, the value of the proportional coefficient k can be negative.

[0090] If the output value of the time-to-digital converter (TDC) is less than zero after the control code input to the digitally controlled oscillator (DCO) resets from its peak to its lowest point, it indicates that the DCO output frequency is too high and needs to be reduced. Therefore, the difference between the peak and lowest points of the control code needs to be increased, and the increase can be k*(TDC). <0> +TDC <1> +TDC <2> The absolute value of ), where k is the proportionality constant. TDC <0> TDC <1> TDC <2> These are the first three values ​​output by the Time-to-Digital Converter (TDC) after the control code is reset from the vertices. Figure 5 In the structure shown, if the value of the sawtooth wave reset signal is negative, the value of the proportional coefficient k can be positive; or, if the value of the sawtooth wave reset signal is positive, the value of the proportional coefficient k can be negative.

[0091] After several clock cycles of adjustment, the output value of the time-to-digital converter (TDC) is zero after the control code input to the digital control oscillator (DCO) is reset from the peak to the lowest point. This indicates that the phase-locked loop (PLL) remains locked after the reset, thus solving the problem of poor frequency sweep linearity caused by the unlocked state.

[0092] Figure 6 This is a schematic diagram illustrating the adjustment of a control code provided in an embodiment of this application. For example... Figure 6As shown, the accumulated output value represents the difference between the highest and lowest points of the control code. For example, at the first step point, the difference between the highest and lowest points of the control code is 30; at this time, the value output by the time-to-digital converter (TDC) is greater than 0, k*(TDC) <0> +TDC <1> +TDC <2> If the absolute value of k*(TDC) is 5, then the difference between the highest and lowest points of the control code is 30-5=25. At the second step point, the difference between the highest and lowest points of the control code is 25; at this time, the value output by the time-to-digital converter (TDC) is greater than 0, k*(TDC) <0> +TDC <1> +TDC <2> If the absolute value of k*(TDC) is 4, then the difference between the highest and lowest points of the control code is 25-4=21. At the third step point, the difference between the highest and lowest points of the control code is 21; at this time, the output value of the time-to-digital converter (TDC) is greater than 0, k*(TDC) <0> +TDC <1> +TDC <2> If the absolute value of k*(TDC) is 3, then the difference between the highest and lowest points of the control code is 21-3=18. At the fourth step point, the difference between the highest and lowest points of the control code is 18; at this time, the output value of the time-to-digital converter (TDC) is less than 0, k*(TDC) <0> +TDC <1> +TDC <2> If the absolute value of k*(TDC) is 2, then the difference between the highest and lowest points of the control code is 18 + 2 = 20. At the fifth step point, the difference between the highest and lowest points of the control code is 20; at this time, the output value of the time-to-digital converter (TDC) is greater than 0, k*(TDC) <0> +TDC <1> +TDC <2> If the absolute value of ) is equal to 1, then the difference between the highest and lowest points of the control code is 20-1=19. At the sixth step point, the difference between the highest and lowest points of the control code is 19; at this time, the output value of the time-to-digital converter (TDC) is equal to 0, indicating that the phase-locked loop remains locked after the reset, and at subsequent step points, the difference between the highest and lowest points of the control code can be maintained at 19.

[0093] If the initial value of the highest point of the control code is 40, then at the first step point, the value of the lowest point of the control code is 40-30=10; at the second step point, it is 40-25=15; at the third step point, it is 40-21=19; at the fourth step point, it is 40-18=22; at the fifth step point, it is 40-20=20; and at the sixth step point, it is 40-19=21. At subsequent step points, the output frequency corresponding to control code 21 of the digital controlled oscillator (DCO) maintains frequency and phase synchronization with the reference signal of the time-to-digital converter (TDC), thus solving the problem of poor frequency sweep linearity caused by the phase-locked loop (PLL) not being locked at step points.

[0094] Furthermore, the phase-locked loop also includes: a digital filter; a time-to-digital converter (TDC) connected to an arithmetic unit via the digital filter; and the digital filter used to filter the signal output by the TDC. The digital phase difference signal output by the TDC, after having high-frequency noise removed by the digital filter (DLF), is used to adjust the control code of the digitally controlled oscillator (DCO), further improving the stability of the phase-locked loop.

[0095] This application provides a control method for a phase-locked loop (PLL), applied to a PLL controller.

[0096] Figure 7 This is a flowchart illustrating a phase-locked loop control method provided in an embodiment of this application. Figure 7 As shown, the method includes:

[0097] S701, the controller acquires the output signal of the time-to-digital converter after the division ratio reaches the step point; wherein, the frequency divider is used to input the frequency signal after dividing the output frequency of the phase-locked loop to the time-to-digital converter according to the division ratio.

[0098] At the end of each time cycle of the sawtooth waveform, the output frequency needs to be reset to its minimum value; this point can be called a step point. For example, when the frequency division ratio is reset from its maximum value to its minimum value, it can be determined that the current point is a step point. When the frequency division ratio is at a step point, the control code of the digital controlled oscillator (DCO) and the output frequency of the phase-locked loop will also jump downwards from their highest points.

[0099] The controller can obtain the division ratio value in each clock cycle and compare it with the minimum value to detect whether it is currently at a step point. Alternatively, the controller can detect the decrease in the division ratio and determine that it is currently at a step point when the decrease is greater than a first preset value.

[0100] Alternatively, the controller can detect the decrease in the output frequency of the phase-locked loop, and determine that it is currently at a step point when the decrease is greater than a second preset value.

[0101] Alternatively, the controller can detect the drop in the control code of the digitally controlled oscillator (DCO), and determine that it is currently at a step point when the drop exceeds a third preset value.

[0102] The frequency divider DIV inputs the frequency signal obtained by dividing the output frequency of the phase-locked loop into the time-to-digital converter TDC based on the current division ratio. The time-to-digital converter TDC measures the phase difference between the divided frequency signal and the reference signal and converts the phase difference into a digital phase difference signal.

[0103] One implementation involves sampling the output of the time-to-digital converter (TDC) starting at the first rising or falling edge of the clock after the step point, to obtain the output signal of the TDC with the division ratio after the step point.

[0104] One implementation involves sampling the output of the time-to-digital converter (TDC) at a preset rising or falling edge of the clock after the step point, to obtain the output signal of the TDC with the frequency division ratio after the step point.

[0105] S702, the controller determines whether the value of the output signal of the time-to-digital converter is zero.

[0106] By acquiring the output signal of the time-to-digital converter (TD-SCDMA) after the step point in the frequency division ratio, it can be determined whether the output signal of the phase-locked loop (PLL) is synchronized with the reference signal. For example, when the output signal of the TD-SCDMA is zero, it can be assumed that the PLL's output signal is synchronized with the reference signal in both frequency and phase, and the PLL is in a locked state. When the output signal of the TD-SCDMA is not zero, it can be assumed that the PLL may have lost lock at the step point and needs to be re-locked.

[0107] If the output signal of the time-to-digital converter (TDC) is not zero, then step S703 is executed.

[0108] S703: The controller adjusts the lowest point of the control code of the digital control oscillator until the output signal value of the time-to-digital converter after the step point is zero.

[0109] In one example, the lowest point of the control code can be adjusted by feeding the output of the time-to-digital converter (TDC) back to the control code of the digitally controlled oscillator (DCO).

[0110] In another example, the controller can preset the adjustment step size, which can adjust the value of the control code by adjusting the preset adjustment step size to adjust the lowest point of the control code.

[0111] The output frequency of the digitally controlled oscillator (DCO) can be adjusted by regulating the lowest point of the control code; the frequency signal after the phase-locked loop (PLL) output frequency is divided by the frequency divider (DIV) will also change. This alters the input signal of the time-to-digital converter (TDC). When the frequency and phase of the TDC input signal are synchronized with the reference signal, the output signal of the TDC at the step point can be zero. This ensures that the output frequency of the PLL output signal at the step point is synchronized with the frequency and phase of the reference signal.

[0112] The phase-locked loop control method provided in this application can achieve a zero output value of the time-to-digital converter (TDC) by adjusting the lowest point of the control code of the digital control oscillator at the step point. This ensures that the phase-locked loop remains locked at the step point, thereby improving the linearity of the sawtooth waveform generated by the phase-locked loop at the step point.

[0113] Figure 8This is a flowchart illustrating a second phase-locked loop control method provided in an embodiment of this application. Figure 8 As shown, in this embodiment... Figure 7 Based on the embodiments, the control method of the phase-locked loop is described in detail, which includes:

[0114] S801, the controller acquires the output signal of the time-to-digital converter after the step point of the frequency division ratio.

[0115] S802, the controller determines whether the value of the output signal of the time-to-digital converter is zero.

[0116] In one example, when the frequency of the divided signal is lower than the frequency of the reference signal, the value of the digital phase difference signal output by the time-to-digital converter (TDC) is greater than zero.

[0117] When the frequency of the divided signal is higher than the frequency of the reference signal, the value of the digital phase difference signal output by the time-to-digital converter (TDC) is less than zero.

[0118] When the frequency of the divided signal is equal to the frequency of the reference signal, the digital phase difference signal output by the time-to-digital converter (TDC) is zero.

[0119] If the output signal value of the time-to-digital converter (TDC) is greater than zero, then step S803 is executed.

[0120] If the output signal value of the time-to-digital converter (TDC) is less than zero, then step S804 is executed.

[0121] If the output signal of the time-to-digital converter (TDC) is zero, then step S805 is executed.

[0122] S803: The controller increases the lowest point of the control code of the digitally controlled oscillator to increase the output frequency of the phase-locked loop.

[0123] By increasing the lowest point of the control code, the output frequency of the digitally controlled oscillator (DCO) can be increased; the frequency signal after the frequency divider (DIV) divides the output frequency of the phase-locked loop (PLL) will also increase accordingly. This increases the input signal of the time-to-digital converter (TDC). When the input signal of the TDC is synchronized with the frequency and phase of the reference signal, the output signal of the TDC at the step point can be zero. This ensures that the output frequency of the PLL at the step point is synchronized with the frequency and phase of the reference signal.

[0124] S804 The controller reduces the lowest point of the control code of the digitally controlled oscillator to reduce the output frequency of the phase-locked loop.

[0125] By reducing the lowest point of the control code, the output frequency of the digitally controlled oscillator (DCO) can be reduced; the frequency signal after the frequency divider (DIV) divides the output frequency of the phase-locked loop (PLL) will also decrease accordingly. This reduces the input signal of the time-to-digital converter (TDC). When the input signal of the TDC is synchronized with the frequency and phase of the reference signal, the output signal of the TDC at the step point can be zero. This ensures that the output frequency of the PLL at the step point is synchronized with the frequency and phase of the reference signal.

[0126] S805, the controller keeps the lowest point of the control code of the digitally controlled oscillator unchanged.

[0127] By keeping the lowest point of the control code of the digitally controlled oscillator (TDC) unchanged, the output frequency of the DCO remains constant; the frequency signal after the frequency divider (DIV) divides the output frequency of the phase-locked loop (PLL) also remains constant. This keeps the input signal of the time-to-digital converter (TDC) constant. When the input signal of the TDC is synchronized with the frequency and phase of the reference signal, the output signal of the TDC at the step point is zero. This ensures that the output frequency of the PLL at the step point is synchronized with the frequency and phase of the reference signal.

[0128] The phase-locked loop control method provided in this application increases the lowest point of the control code of the digital control oscillator when the output signal value of the time-to-digital converter (TDC) is greater than zero at the step point; and decreases the lowest point of the control code of the digital control oscillator when the output signal value of the time-to-digital converter (TDC) is less than zero. This can achieve a zero output value of the time-to-digital converter (TDC), so that the phase-locked loop remains locked at the step point, thereby improving the linearity of the sawtooth wave at the step point.

[0129] Figure 9 This is a flowchart illustrating the third phase-locked loop control method provided in this application embodiment. Figure 9 As shown, in this embodiment... Figure 7 Based on the embodiments, the control method of the phase-locked loop is described in detail, which includes:

[0130] S901, the controller acquires the output signal of the time-to-digital converter after the step point of the frequency division ratio.

[0131] The controller acquires the output signal of the time-to-digital converter (TDC) at the first rising edge of the clock after the step point of the frequency division ratio.

[0132] S902, The controller determines whether the value of the output signal of the time-to-digital converter is zero.

[0133] If the output signal of the time-to-digital converter (TDC) is not zero, then step S903 is executed.

[0134] S903: The controller acquires n consecutive output signals of the time-to-digital converter after the step point; where n is a positive integer.

[0135] For example, a time-to-digital converter (TDC) measures the phase difference between an input signal and a reference signal, outputting a phase difference signal on each rising / falling edge of the clock. The controller acquires n output signals consecutively, starting from the first rising edge of the clock after the step point.

[0136] Acquiring the n consecutive output signals of the time-to-digital converter after the step point can improve the sampling accuracy.

[0137] S904. The controller adds up n consecutive output signals, multiplies them by a proportional coefficient, and sums the result of the multiplication with the difference between the highest and lowest points of the current control code to obtain the first result.

[0138] The sum of n consecutive output signals, multiplied by a scaling factor, yields a result that can be used to adjust the amount by which the lowest point of the control code is increased or decreased. The scaling factor can be a value less than zero.

[0139] The sum of the result of multiplication and the difference between the highest and lowest points of the current control code can be used to obtain the difference between the highest and lowest points of the new control code.

[0140] By setting a scaling factor, the output signal of the Time-to-Digital Converter (TDC) can form negative feedback on the difference between the highest and lowest points of the control code. When the result of the multiplication is greater than zero (i.e., when the output signal of the TDC is less than zero), the difference between the highest and lowest points of the current control code can be increased; conversely, when the result of the multiplication is less than zero (i.e., when the output signal of the TDC is greater than zero), the difference between the highest and lowest points of the current control code can be decreased.

[0141] S905. The controller adjusts the lowest point of the control code of the digital control oscillator, wherein the difference between the highest and lowest points of the adjusted control code is the first result.

[0142] For example, when the result of multiplication is greater than zero, the difference between the highest and lowest points of the adjusted control code can be increased, and the lowest point of the control code can be decreased if the highest point of the control code remains unchanged; when the result of multiplication is less than zero, the difference between the highest and lowest points of the adjusted control code can be decreased, and the lowest point of the control code can be increased if the highest point of the control code remains unchanged.

[0143] As an example, step S905 may include the following steps:

[0144] (1) Obtain the magnitude of the highest point of the control code of the digitally controlled oscillator.

[0145] (2) Calculate the difference between the size of the highest point and the first result.

[0146] (3) Adjust the value of the lowest point of the control code as the difference result.

[0147] Repeat steps S902-S905 until the output signal of the time-to-digital converter (TDC) is zero after the step point. After repeating the above steps, the output of the time-to-digital converter (TDC) is finally zero after the control code of the digitally controlled oscillator (DCO) is reset from the peak to the lowest point. At this time, it indicates that the phase-locked loop (PLL) remains locked after the reset, thus solving the problem of poor frequency sweep linearity caused by the PLL being unlocked at the step point.

[0148] The phase-locked loop control method provided in this application obtains n consecutive output signals of the time-to-digital converter (TDC) after the step point, and uses these output signals as negative feedback to adjust the lowest point of the control code of the digital control oscillator. This can achieve a zero output value of the time-to-digital converter (TDC), so that the phase-locked loop remains locked at the step point of the sawtooth wave waveform, thereby improving the linearity of the sawtooth wave waveform at the step point.

[0149] This application also provides a frequency source, including a phase-locked loop.

[0150] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A phase-locked loop, characterized in that, include: Controller, time-to-digital converter, arithmetic unit, digitally controlled oscillator, and frequency divider; The digitally controlled oscillator is connected to the arithmetic unit, and the digitally controlled oscillator is used to output a linear sweep frequency signal according to the frequency control signal output by the arithmetic unit; The input terminal of the frequency divider is connected to the output terminal of the digitally controlled oscillator, and the output terminal of the frequency divider is connected to the input terminal of the time-to-digital converter. The frequency divider is used to generate a frequency-divided signal based on the output frequency of the digitally controlled oscillator. The time-to-digital converter is used to output the phase difference between the frequency-divided signal and the reference signal. The input terminal of the arithmetic unit is connected to the output terminal of the time-to-digital converter, and receives control codes; The arithmetic unit is used to output the frequency control signal according to the phase difference and the control code, so as to adjust the output frequency of the digitally controlled oscillator; The controller connects the time-to-digital converter and the arithmetic unit. The controller is used to acquire the output signal of the time-to-digital converter after the step point of the frequency division ratio, and adjust the control code when the value of the output signal of the time-to-digital converter is not zero, until the value of the output signal of the time-to-digital converter after the step point is zero.

2. The phase-locked loop according to claim 1, characterized in that, The controller includes: Adder, first multiplier, second multiplier, accumulator; The adder is connected to the accumulator via the first multiplier and the second multiplier; The adder is used to sum the n consecutive output signals of the time-to-digital converter after the step point; The first multiplier is used to output the result of the adder to the second multiplier after the step point; The second multiplier is used to multiply the output of the first multiplier by a scaling factor and output the result to the accumulator; The accumulator is used to sum the result of the multiplication with the difference between the highest and lowest points of the current control code to obtain a first result; wherein the difference between the highest and lowest points of the adjusted control code is the first result.

3. The phase-locked loop according to any one of claims 1 to 2, characterized in that, The phase-locked loop further includes: a digital filter; The time-to-digital converter is connected to the arithmetic unit via the digital filter; The digital filter is used to filter the signal output by the time-to-digital converter.

4. A control method for a phase-locked loop, characterized in that, The method, applied to a controller of a phase-locked loop as described in any one of claims 1 to 3, comprises: Obtain the output signal of the time-to-digital converter after the frequency division ratio reaches the step point; If the output signal of the time-to-digital converter is not zero, the lowest point of the control code of the digital control oscillator is adjusted until the output signal of the time-to-digital converter is zero after the step point.

5. The method according to claim 4, characterized in that, The adjustment of the lowest point of the control code of the digitally controlled oscillator specifically includes: If the output signal value of the time-to-digital converter is greater than zero, then the lowest point of the control code of the digitally controlled oscillator is increased to increase the output frequency of the phase-locked loop. If the output signal value of the time-to-digital converter is less than zero, the lowest point of the control code of the digitally controlled oscillator is reduced to decrease the output frequency of the phase-locked loop.

6. The method according to claim 4, characterized in that, The adjustment of the lowest point of the control code of the digitally controlled oscillator specifically includes: Acquire n consecutive output signals of the time-to-digital converter after the step point; where n is a positive integer; Add n consecutive output signals, multiply by a scaling factor, and sum the result of the multiplication with the difference between the highest and lowest points of the current control code to obtain the first result; The lowest point of the control code of the digitally controlled oscillator is adjusted, wherein the difference between the highest and lowest points of the adjusted control code is the first result.

7. The method according to claim 6, characterized in that, The adjustment of the lowest point of the control code of the digitally controlled oscillator includes: Obtain the magnitude of the highest point of the control code of the digitally controlled oscillator; Calculate the difference between the size of the highest point and the first result; The value of the lowest point of the control code is adjusted to the difference result.

8. The method according to claim 6, characterized in that, The value of n is 3.

9. The method according to any one of claims 5 to 8, characterized in that, The method further includes: If the output signal of the time-to-digital converter is zero, then the lowest point of the control code of the digitally controlled oscillator remains unchanged.

10. A frequency source, characterized in that, include: The phase-locked loop as described in any one of claims 1 to 3.

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