Hardware cooperation-based wake-up signal detection method and device, equipment and medium

Abstract

This invention belongs to the field of sensors and discloses a hardware-coordinated wake-up signal detection method, apparatus, device, and medium. It is applied to a sensor system including a main control chip and an IO-Link chip. The method includes: associating a DMA channel with capture events of input capture channels; when a capture event occurs, recording the level state of the communication pin of the IO-Link chip controlled by the main control chip through the DMA channel; calculating the pulse width of the signal on the receiving pin of the IO-Link chip and the time difference between the first edge of the wake-up pin and the signal edge on the receiving pin of the IO-Link chip based on the time information recorded by each input capture channel; combining this with the level state of the communication pin of the IO-Link chip controlled by the main control chip to determine whether the first edge of the wake-up pin corresponds to a real wake-up signal; if so, performing a wake-up operation. This improves the accuracy of identifying the real wake-up signal of the IO-Link chip.

Description

Technical Field

[0001] This invention belongs to the field of sensors, specifically relating to a method, device, equipment, and medium for detecting wake-up signals based on hardware collaboration. Background Technology

[0002] IO-Link, a point-to-point industrial communication protocol, is widely used in sensors and actuators. In existing IO-Link sensor systems, the typical connection between the master control chip and the IO-Link slave chip is as follows: the general-purpose input / output pins of the master control chip are connected to the chip's communication line pins, receive pins, and wake-up pins; the receive pin signal and the communication line pin signal are inverted. Its wake-up detection mechanism relies on the chip's internal short-circuit detection circuit. Specifically, the logic is as follows: when the communication line pin outputs a high level, an 80µs low level is detected with a current greater than 500mA; or when the communication line pin outputs a low level or a high impedance state, an 80µs high level is detected with a current greater than 500mA. This is considered a valid wake-up event, and the master control chip is notified by outputting a rising or falling edge through the wake-up pin. The master control chip captures the response through an external interrupt or timer and releases control of the communication line pin. However, industrial environments are rife with electromagnetic interference, such as motor start-stop and inverter noise. This interference can easily couple to communication lines, generating transient pulses of nearly 80µs, accompanied by instantaneous large current spikes. This can trigger the chip's internal short-circuit detection logic, leading to false triggering of the wake-up pin. Once the wake-up pin is falsely triggered, the main control chip will prematurely release control of the communication line pin. If the sensor detects a real target at this time, the main control chip will be unable to output a switching signal through the communication line pin, resulting in system malfunction or communication failure.

[0003] To suppress false triggering of the wake-up pin, existing technologies typically add software filtering at the main control chip level, such as repeatedly reading the level or capturing the communication line waveform during the wake-up interrupt. However, the frequent changes in the communication line pin and the receiving pin during normal operation can lead to a large number of edge interrupts on the receiving pin, causing a sharp increase in CPU load and even triggering task scheduling delays or system crashes. If a polling method is used, it will consume a large amount of CPU resources and reduce the system's response speed. In addition, while adding an independent auxiliary microcontroller or complex programmable logic device can reduce the burden on the main control chip, it significantly increases material costs and board area, which is not conducive to the widespread adoption of cost-sensitive industrial sensors.

[0004] Therefore, how to more accurately identify the real wake-up signal of the IO-Link chip in an electromagnetic interference environment is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] To address the technical problem of IO-Link chips erroneously triggering wake-up signals in electromagnetic interference environments, this invention provides a hardware-coordinated wake-up signal detection method, apparatus, device, and medium.

[0006] In a first aspect, the present invention provides a hardware-coordinated wake-up signal detection method, applied to a sensor system including a main control chip and an IO-Link chip, the method comprising: Configure multiple input capture channels for the main control chip's timer, and configure the main control chip's direct memory access (DMA) channel; The DMA channel is associated with at least a portion of the input capture channels of the main control chip's timer, and when the capture event occurs, the DMA channel is used to automatically record the level state of the communication pin of the IO-Link chip controlled by the main control chip. Polling to detect whether a capture event has occurred in the capture channel associated with the wake-up pin of the IO-Link chip in the input capture channel; When a capture event is detected in the capture channel associated with the wake-up pin of the IO-Link chip, the time information recorded by each input capture channel of the timer is read. Based on the time information recorded by each input capture channel, calculate the pulse width of the signal on the receiving pin of the IO-Link chip and the time difference between the first edge of the wake-up pin and the signal edge on the receiving pin of the IO-Link chip, and combine the recorded level state of the communication pin of the IO-Link chip controlled by the main control chip to determine whether the first edge of the wake-up pin corresponds to the real wake-up signal; If the first edge of the wake-up pin corresponds to a real wake-up signal, the main control chip performs a wake-up operation.

[0007] Preferably, configuring multiple input capture channels of the main control chip's timer and configuring the main control chip's direct memory access (DMA) channel includes: Configure the first input capture channel of the first timer of the main control chip to capture the second edge of the receiving pin of the IO-Link chip, and configure the second input capture channel of the first timer of the main control chip to capture the third edge of the receiving pin; Configure the third input capture channel of the first timer of the main control chip to capture the second edge of the receiving pin of the IO-Link chip, and configure the fourth input capture channel of the first timer of the main control chip to capture the third edge of the receiving pin; Configure the first input capture channel of the second timer of the main control chip to capture the first edge of the wake-up pin of the IO-Link chip.

[0008] Preferably, associating the DMA channel with at least a portion of the input capture events of the main control chip's timer, and automatically recording the level state of the communication pins of the IO-Link chip controlled by the main control chip via the DMA channel when the capture event occurs, includes: The first DMA channel is configured to be associated with the capture event of the first input capture channel of the first timer, and when the second edge of the receive pin is captured, the level state of the communication pin output of the IO-Link chip currently controlled by the main control chip is stored in the first memory address; Configure the second DMA channel to be associated with the capture event of the third input capture channel of the first timer, and when the second edge of the receive pin is captured, store the constant value representing the second edge to the edge type flag variable address; The third DMA channel is configured to be associated with the capture event of the second input capture channel of the first timer, and when the third edge of the receive pin is captured, the level state of the communication pin output of the IO-Link chip currently controlled by the main control chip is stored in the second memory address. Configure the fourth DMA channel to be associated with the capture event of the fourth input capture channel of the first timer, and when the third edge of the receive pin is captured, store the constant value representing the third edge to the edge type flag variable address.

[0009] Preferably, polling to detect whether a capture event has occurred in the capture channel associated with the wake-up pin of the IO-Link chip in the input capture channel includes: In the main loop or low-priority background task of the main control chip, read the capture update flag bit of the first input capture channel of the second timer of the main control chip; When the capture update flag is valid, it is determined that a capture event has occurred on the capture channel associated with the wake-up pin.

[0010] Preferably, when a capture event is detected in the capture channel associated with the wake-up pin of the IO-Link chip, reading the time information recorded by each input capture channel of the timer includes: Read the second edge time of the receive pin recorded by the first input capture channel of the first timer, and read the third edge time of the receive pin recorded by the second input capture channel of the first timer; Read the first edge moment of the wake-up pin recorded by the first input capture channel of the second timer, and read the edge type flag variable to determine the edge type of the receive pin; Based on the value of the edge type flag variable, select to read the level state of the communication pin stored in the first memory address or the second memory address.

[0011] Preferably, the step of calculating the pulse width of the signal on the IO-Link chip receiving pin and the time difference between the first edge of the wake-up pin and the signal edge on the IO-Link chip receiving pin based on the time information recorded by each input capture channel, and combining this with the recorded level state of the communication pin of the IO-Link chip controlled by the main control chip, to determine whether the first edge of the wake-up pin corresponds to a real wake-up signal includes: Obtain the value of the edge type flag variable. When the edge type flag variable represents a positive pulse, use the difference between the third edge time of the receiving pin and the second edge time of the receiving pin as the pulse width. The time difference is the difference between the first edge time of the wake-up pin and the second edge time of the receive pin. Determine whether the original level state of the communication pin is a first preset level state, whether the pulse width is within a first preset threshold range, and whether the time difference is less than a second preset threshold. If all conditions are met, it is confirmed as a real wake-up signal.

[0012] Preferably, the step of calculating the pulse width of the signal on the IO-Link chip receiving pin and the time difference between the first edge of the wake-up pin and the signal edge on the IO-Link chip receiving pin based on the time information recorded by each input capture channel, and combining this with the recorded level state of the communication pin of the IO-Link chip controlled by the main control chip, to determine whether the first edge of the wake-up pin corresponds to a real wake-up signal, further includes: Obtain the value of the edge type flag variable. When the edge type flag variable represents a negative pulse, use the difference between the second edge time and the third edge time of the receiving pin as the pulse width. The time difference is the difference between the first edge time of the wake-up pin and the third edge time of the receive pin. Determine whether the original level state of the communication pin is the second preset level state, whether the pulse width is within the first preset threshold range, and whether the time difference is less than the second preset threshold. If all conditions are met, it is confirmed as a real wake-up signal.

[0013] Secondly, the present invention also provides a hardware-coordinated wake-up signal detection device, applied to a sensor system including a main control chip and an IO-Link chip, the device comprising: The configuration module is used to configure multiple input capture channels of the main control chip's timer and to configure the main control chip's direct memory access (DMA) channel. The association module is used to associate the DMA channel with at least a portion of the input capture channels of the main control chip's timer, and when the capture event occurs, automatically record the level state of the communication pin of the IO-Link chip controlled by the main control chip through the DMA channel; The detection module is used to poll and detect whether a capture event has occurred in the capture channel associated with the wake-up pin of the IO-Link chip in the input capture channel; The reading module is used to read the time information recorded by each input capture channel of the timer when a capture event is detected in the capture channel associated with the wake-up pin of the IO-Link chip; The judgment module is used to calculate the pulse width of the signal on the receiving pin of the IO-Link chip and the time difference between the first edge of the wake-up pin and the signal edge on the receiving pin of the IO-Link chip based on the time information recorded by each input capture channel, and combine the recorded level state of the communication pin of the IO-Link chip controlled by the main control chip to determine whether the first edge of the wake-up pin corresponds to the real wake-up signal. The wake-up module performs a wake-up operation if the first edge of the wake-up pin corresponds to a real wake-up signal.

[0014] Thirdly, the present invention also provides a hardware-coordinated wake-up signal detection device, including a memory and a processor, wherein: The memory is used to store computer programs; The processor is used to read the computer program in the memory and execute the steps of the hardware-coordinated wake-up signal detection method as described in any of the first aspects above.

[0015] Fourthly, the present invention also provides a computer-readable storage medium having a readable computer program stored thereon, which, when executed by a processor, implements the steps of the hardware-coordinated wake-up signal detection method as described in any of the first aspects above.

[0016] Compared with existing technologies, this invention provides a hardware-coordinated wake-up signal detection method, apparatus, device, and medium. It automatically records the level states of the communication pins of the IO-Link chip controlled by the main control chip via a DMA channel. The entire process requires no CPU intervention, effectively avoiding CPU interruptions caused by frequent changes in the IO-Link chip's communication and receiving pins, significantly reducing the load on the main control chip, and ensuring the system's real-time performance and stability under high-frequency signal changes. Furthermore, it calculates the pulse width and delay based on the read time information and combines this with the recorded communication pin level states to determine whether the first edge of the wake-up pin corresponds to a genuine wake-up signal. This determination process introduces triple verification logic of polarity matching, pulse width matching, and delay matching, effectively filtering out false triggers caused by industrial noise and significantly improving the accuracy of identifying the genuine wake-up signal of the IO-Link chip. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and not all embodiments. For those skilled in the art, other drawings obtained from these drawings without creative effort are all within the scope of protection of the present invention.

[0018] Figure 1 This is a flowchart illustrating a hardware-coordinated wake-up signal detection method provided in an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of a process for associating a DMA channel with a capture event, provided as an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of a process for reading time information recorded by each input capture channel of a timer, provided as an embodiment of the present invention.

[0021] Figure 4 This is a flowchart illustrating a process for determining whether the first edge of the wake-up pin corresponds to a real wake-up signal, as provided in an embodiment of the present invention.

[0022] Figure 5 This invention provides a hardware-coordinated wake-up signal detection device.

[0023] Figure 6 This is a schematic diagram of a hardware-coordinated wake-up signal detection device provided in an embodiment of the present invention.

[0024] Figure 7This is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0026] To provide a more detailed and complete description of the present invention, illustrative descriptions of its implementation methods and specific embodiments are provided below; however, these are not the only forms of implementing or utilizing the specific embodiments of the present invention. The implementation methods cover features of multiple specific embodiments, as well as the methods, steps, and their order for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equivalent functions and sequence of steps. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0028] In the description of the embodiments of the present invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The word "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present invention, "multiple" means two or more. Other quantifiers should be understood similarly. The preferred embodiments described herein are only for illustrating and explaining the present invention and are not intended to limit the present invention. Furthermore, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0029] To address the technical problem of IO-Link chips falsely triggering wake-up signals in electromagnetic interference environments, this invention provides a hardware-coordinated wake-up signal detection method. Please refer to... Figure 1 , Figure 1 This is a flowchart illustrating a hardware-coordinated wake-up signal detection method provided in an embodiment of the present invention. The method is applied to a sensor system including a main control chip and an IO-Link chip, and includes: S10: Configure multiple input capture channels for the main control chip's timer and configure the main control chip's Direct Memory Access (DMA) channel. Specifically, in this embodiment of the invention, configuring multiple input capture channels and a DMA channel for the main control chip's timer provides a foundation for subsequent automatic hardware data acquisition and transfer. This configuration only requires standard peripherals available in mainstream MCUs, without the need for additional dedicated chips or complex logic circuits, resulting in low hardware cost and high versatility. Simultaneously, the timer capture accuracy can reach the clock cycle level, providing a high-precision time reference for subsequent accurate measurement of pulse width and delay.

[0030] S20: Associate the DMA channel with capture events of at least a portion of the input capture channels of the main control chip's timer, and automatically record the level state of the communication pins of the IO-Link chip controlled by the main control chip through the DMA channel when the capture event occurs. Specifically, in this embodiment of the invention, the DMA channel is associated with capture events of a portion of the timer's input capture channels, and the DMA automatically records the level state of the communication pins when a capture event occurs, without CPU intervention. This effectively avoids CPU interruptions caused by frequent changes in the IO-Link chip's communication pins and chip receive pins, significantly reduces the load on the main control chip, and ensures the real-time performance and stability of the system under high-frequency signal changes.

[0031] S30: Polling to detect whether a capture event has occurred in the capture channel associated with the wake-up pin of the IO-Link chip. Specifically, in this embodiment of the invention, a polling method is used to detect whether a capture event has occurred in the capture channel associated with the wake-up pin, instead of using an external interrupt. Polling is executed in the main loop or a low-priority background task, requiring only the reading of hardware flag bits, resulting in minimal overhead. Since wake-up events are low-frequency events in industrial applications, polling will not significantly burden the CPU, and at the same time avoids interrupts caused by frequent false triggering of the wake-up pin signal due to noise, further reducing the response pressure on the main control chip.

[0032] S40: When a capture event is detected on the capture channel associated with the wake-up pin of the IO-Link chip, the time information recorded by each input capture channel of the timer is read. Specifically, in this embodiment of the invention, when a capture event is detected on the capture channel associated with the wake-up pin, the time information recorded by each input capture channel of the timer is read. This time information is automatically captured and stored by hardware. The CPU only needs to read it once to obtain the rising edge time, falling edge time, and the first edge time of the wake-up pin of the IO-Link chip, without the need for on-site measurement or software filtering calculation. This method ensures the accuracy of the timestamp and avoids the real-time performance degradation caused by multiple software reads. It should be noted that the first edge of the wake-up pin of the IO-Link chip can be either a rising edge or a falling edge, depending on the actual situation of the chip.

[0033] S50: Calculate the pulse width of the signal on the receiving pin of the IO-Link chip and the time difference between the first edge of the wake-up pin and the signal edge on the receiving pin of the IO-Link chip based on the time information recorded by each input capture channel. Combined with the recorded level state of the communication pin of the IO-Link chip controlled by the main control chip, determine whether the first edge of the wake-up pin corresponds to the real wake-up signal. Specifically, in this embodiment of the invention, the pulse width and delay are calculated based on the read time information, and combined with the recorded level state of the communication pin, it is determined whether the first edge of the wake-up pin corresponds to the real wake-up signal. This step introduces a triple verification logic of polarity matching, pulse width matching, and delay matching. Polarity matching utilizes the inverse relationship between the IO-Link chip communication pin and the chip receiving pin. Pulse width matching strictly follows the 80μs protocol requirement, such as 75~85μs. Delay matching is based on the upper limit of the chip's internal processing time; for example, the delay can be less than 300μs. Even in a strong interference environment, the real wake-up signal can be accurately identified, and the sensor can still maintain normal switching output under extreme interference, improving system security.

[0034] S60: If the first edge of the wake-up pin corresponds to a real wake-up signal, the main control chip performs a wake-up operation. Specifically, in this embodiment of the invention, the main control chip only performs a wake-up operation and releases the control of the IO-Link chip communication pin to the IO-Link protocol stack when it is determined to be a real wake-up signal. This mechanism avoids prematurely releasing the control of the IO-Link chip communication pin due to noise-induced false triggering, thereby preventing the sensor from failing to output a switch signal when it detects a real target. Simultaneously, since the judgment logic is based on precise data recorded by the hardware and only requires simple arithmetic comparison, the wake-up operation is fast and reliable, ensuring a smooth switch of the sensor from sleep mode to digital communication mode.

[0035] As one implementation, in step S10, configuring multiple input capture channels of the main control chip's timer and configuring the main control chip's direct memory access (DMA) channel includes: S11: Configure the first input capture channel of the first timer of the main control chip to capture the second edge of the receiving pin of the IO-Link chip, and configure the second input capture channel of the first timer of the main control chip to capture the third edge of the receiving pin. Specifically, in this embodiment of the invention, configuring the first channel of the first timer to capture the second edge of the receiving pin and the second channel to capture the third edge of the receiving pin can accurately record the start and end times of a complete pulse on the receiving pin of the IO-Link chip. Both timestamps are automatically captured by hardware with an accuracy at the timer clock cycle level, providing a high-precision time reference for subsequent calculation of the pulse width, i.e., the low-level duration of the wake-up signal. Simultaneously, this configuration requires no CPU intervention, avoiding the latency and load caused by software sampling or interrupt handling. In this embodiment of the invention, the second edge of the receiving pin of the IO-Link chip can be either a rising edge or a falling edge. The third edge of the receiving pin of the IO-Link chip can be either a rising edge or a falling edge. When the second edge of the IO-Link chip's receive pin is a rising edge, the third edge of the IO-Link chip's receive pin is a falling edge; when the second edge of the IO-Link chip's receive pin is a falling edge, the third edge of the IO-Link chip's receive pin is a rising edge.

[0036] S12: Configure the third input capture channel of the first timer of the main control chip to capture the second edge of the receiving pin of the IO-Link chip, and configure the fourth input capture channel of the first timer of the main control chip to capture the third edge of the receiving pin. Specifically, in this embodiment of the invention, the third channel of the first timer is configured to capture the second edge of the receiving pin, and the fourth channel is configured to capture the third edge of the receiving pin, but its main purpose is not to record timestamps, but to provide an independent trigger source for the DMA channel. By configuring two capture channels for the second edge and the third edge respectively, the time recording and DMA triggering functions can be separated. This design avoids resource conflicts or timing problems that may occur when a single channel needs to record time and trigger multiple DMAs, thereby improving the hardware parallel processing capability and system reliability.

[0037] S13: Configure the first input capture channel of the second timer of the main control chip to capture the first edge of the wake-up pin of the IO-Link chip. Specifically, in this embodiment of the invention, the first channel of the second timer is configured to capture the first edge of the wake-up pin, and an independent timer is used to monitor the wake-up pin event. Since the first edge of the wake-up pin is a low-frequency event, while the edge change of the IO-Link chip's receiving pin is very frequent, assigning them to different timers can avoid the complexity of overflow handling caused by sharing the same counter, and also prevent the potential impact of frequent capture of the IO-Link chip's receiving pin on the capture accuracy of the wake-up pin. At the same time, the independent timer capture is still automatically completed by hardware without CPU interrupt, ensuring accurate recording of the first edge moment of the wake-up pin, and providing an accurate timestamp for subsequent delay matching.

[0038] As one implementation method, please refer to Figure 2 , Figure 2 This invention provides a flowchart illustrating the association of a DMA channel with a capture event. In step S20, associating the DMA channel with a capture event of at least a portion of the input capture channel of the main control chip's timer, and automatically recording the level state of the communication pin of the IO-Link chip controlled by the main control chip through the DMA channel when the capture event occurs, includes: S21: Configure the first DMA channel to be associated with the capture event of the first input capture channel of the first timer, and when the second edge of the receive pin is captured, store the current level state of the IO-Link chip communication pin output controlled by the main control chip to the first memory address. Specifically, in this embodiment of the invention, when the second edge of the receive pin is captured, the current level state of the IO-Link chip communication pin output controlled by the main control chip is stored to the first memory address. The entire data transfer process is completed entirely by hardware without CPU intervention, thereby avoiding software interruption overhead and response delay caused by frequent reading of pin states. At the same time, since the state of the IO-Link chip communication pin level just before the wake-up pulse occurs is the key basis for polarity matching judgment, this step ensures that the state is accurately and without delay, providing reliable historical data for subsequent differentiation between real wake-up and noise interference, while avoiding interruption overhead and timing errors caused by software reading.

[0039] S22: Configure the second DMA channel to be associated with the capture event of the third input capture channel of the first timer, and when the second edge of the receive pin is captured, store the constant value representing the second edge to the edge type flag variable address. Specifically, in this embodiment of the invention, the second DMA channel is associated with the third input capture channel of the first timer, and when the second edge is captured, the constant value representing the second edge is automatically stored to the edge type flag variable address. By automatically updating the edge type flag variable through DMA, the CPU can know the edge type of the chip's receive pin in real time without any intervention.

[0040] S23: Configure the third DMA channel to be associated with the capture event of the second input capture channel of the first timer, and when the third edge of the receive pin is captured, store the current level state of the IO-Link chip communication pin output controlled by the main control chip to the second memory address. Specifically, in this embodiment of the invention, the current level state of the IO-Link chip communication pin output controlled by the main control chip is stored to the second memory address. The state of the communication pin recorded at this time, combined with the state of the communication pin recorded at the second edge, can completely reflect the change of the communication pin level during the entire pulse. This provides symmetrical historical information for polarity matching verification, ensuring that the correct original state of the communication pin can be obtained regardless of whether the wake-up pulse is a positive or negative pulse, thereby enhancing the comprehensiveness and accuracy of anti-interference judgment.

[0041] S24: Configure the fourth DMA channel to be associated with the capture event of the fourth input capture channel of the first timer, and when the third edge of the receive pin is captured, store the constant value representing the third edge to the edge type flag variable address. Specifically, in this embodiment of the invention, the fourth DMA channel is associated with the fourth input capture channel of the first timer, and when the third edge of the receive pin is captured, the constant value representing the third edge is automatically stored to the edge type flag variable address. When the third edge of the receive pin occurs, the flag variable is updated to the third edge identifier of the receive pin. This four-channel parallel automatic recording mechanism not only ensures high data synchronization and consistency, but also completely solves the problems of excessive CPU load and decreased real-time performance caused by frequent interruptions in traditional software filtering.

[0042] As one implementation, in step S30, polling and detecting whether a capture event has occurred in the capture channel associated with the wake-up pin of the IO-Link chip in the input capture channel includes: S31: In the main loop or low-priority background task of the main control chip, read the capture update flag bit of the first input capture channel of the second timer of the main control chip. Specifically, in this embodiment of the invention, reading the capture update flag bit of the first input capture channel of the second timer of the main control chip in the main loop or low-priority background task of the main control chip realizes low-overhead polling detection of the first edge event of the wake-up pin. Since the wake-up event is a low-frequency event in industrial applications, placing the polling in the main loop or low-priority task will not occupy the execution time of the high-priority task, nor will it interrupt the real-time requirements of the system. Compared with the traditional external interrupt method, this design avoids interruptions caused by frequent false triggering of the wake-up pin by noise. At the same time, the polling operation itself only needs to read a hardware flag bit, with minimal CPU overhead. Thus, while ensuring timely response to the real wake-up signal, it significantly reduces the load on the main control chip, which is especially suitable for complex sensors running embedded operating systems.

[0043] S32: When the capture update flag is valid, it is determined that a capture event has occurred on the capture channel associated with the wake-up pin. Specifically, in this embodiment of the invention, when the capture update flag is valid, it is determined that a capture event has occurred on the capture channel associated with the wake-up pin, so that the CPU can confirm the occurrence of the first edge of the wake-up pin without entering a complex interrupt service routine. Since polling detection does not involve context saving, interrupt nesting, or other operations, the event confirmation speed is extremely fast, and interrupt loss will not occur due to high-priority task blocking. Once the event is confirmed, the CPU can immediately switch to subsequent data reading and judgment steps, realizing a smooth transition from hardware events to software processing. This mechanism ensures reliable capture of wake-up pin events while maintaining a low interrupt burden on the system.

[0044] As one implementation method, please refer to Figure 3 , Figure 3 This invention provides a flowchart illustrating the process of reading time information recorded by each input capture channel of a timer. In step S40, when a capture event is detected in the capture channel associated with the wake-up pin of the IO-Link chip, reading the time information recorded by each input capture channel of the timer includes: S41: Read the second edge time of the receive pin recorded by the first input capture channel of the first timer, and read the third edge time of the receive pin recorded by the second input capture channel of the first timer. Specifically, in this embodiment of the invention, reading the second edge time of the receive pin recorded by the first input capture channel of the first timer and the third edge time of the receive pin recorded by the second input capture channel of the first timer allows for the simultaneous acquisition of the start and end times of the most recent complete pulse on the chip's receive pin. Both timestamps are automatically captured and stored by hardware when the edge occurs, with an accuracy up to the timer clock cycle level, eliminating the need for on-site CPU measurement or software filtering calculations. By reading the time data prepared by the hardware, the CPU can quickly calculate the pulse width, providing an accurate basis for subsequent pulse width matching, while avoiding the real-time performance degradation and resource consumption caused by multiple software sampling.

[0045] S42: Read the first edge time of the wake-up pin recorded by the first capture channel of the second timer, and read the edge type flag variable to determine the edge type of the receiving pin. Specifically, in this embodiment of the invention, reading the first edge time of the wake-up pin recorded by the first capture channel of the second timer and the edge type flag variable can accurately obtain the specific time of the wake-up pin event and the edge type of the chip's most recent receiving pin. The first edge time of the wake-up pin is a key parameter for calculating the delay and the time difference between the wake-up pin and the pulse start, while the edge type flag variable directly indicates whether the last completed pulse on the chip's receiving pin is a positive or negative pulse. Both of these data are automatically maintained and updated by the hardware, and the CPU only needs to read them without interrupt processing or status query, thus obtaining the core information required for subsequent polarity matching and delay matching with extremely low overhead.

[0046] S43: Based on the value of the edge type flag variable, select the communication pin level state stored in the first memory address or the second memory address to read. Specifically, in this embodiment of the invention, by selecting the communication pin level state stored in the first memory address or the second memory address based on the value of the edge type flag variable, automatic matching of the original output state of the IO-Link chip communication pin with the pulse polarity is achieved. For example, when the edge type represents a falling edge, the original output state of the communication pin at the rising edge is read; when the edge type represents a rising edge, the original output state of the communication pin at the falling edge is read. This selective reading mechanism ensures that the acquired original output state of the communication pin completely corresponds to the actual state at the pulse start time, providing correct historical data for polarity matching verification and further improving the accuracy of the anti-interference logic.

[0047] As one implementation method, please refer to Figure 4 , Figure 4This invention provides a flowchart illustrating a method for determining whether the first edge of a wake-up pin corresponds to a real wake-up signal. In step S50, the step of calculating the pulse width of the signal on the receiving pin of the IO-Link chip and the time difference between the first edge of the wake-up pin and the signal edge on the receiving pin of the IO-Link chip based on the time information recorded by each input capture channel, and combining this with the recorded level state of the communication pin of the IO-Link chip controlled by the main control chip, to determine whether the first edge of the wake-up pin corresponds to a real wake-up signal, includes: S51: Obtain the value of the edge type flag variable. When the edge type flag variable represents a positive pulse, use the difference between the third edge time and the second edge time of the receiving pin as the pulse width. Specifically, in this embodiment of the invention, since the third edge time and the second edge time of the receiving pin of the IO-Link chip are automatically recorded by the hardware timer capture channel, the time difference calculation is accurate and reliable, avoiding measurement errors caused by response delays under software polling or interrupt methods. This pulse width directly reflects the duration of the wake-up pulse, providing a high-precision basis for subsequent judgment on whether it meets the 80μs requirement specified by the IO-Link protocol, such as an allowable error range of 75-85μs, thereby effectively filtering out noise pulses whose width does not conform to the wake-up specification.

[0048] S52: The difference between the first edge time of the wake-up pin and the second edge time of the receiving pin is used as the time difference. Specifically, in this embodiment of the invention, the difference between the first edge time of the wake-up pin and the second edge time of the receiving pin is used as the time difference. This time difference characterizes the internal processing time required for the IO-Link chip to actually output the first edge of the wake-up pin from detecting the wake-up pulse. By subtracting the second edge, the third edge, and the first edge of the wake-up pin from three timestamps automatically recorded by the hardware, this delay can be accurately obtained. Since the chip processing time corresponding to the actual wake-up pulse usually has an upper limit, this step utilizes this physical characteristic to determine events with excessively large or small delays as interference, further improving the accuracy of wake-up verification, while avoiding misjudgment of false wake-up pin signals caused by noise.

[0049] S53: Determine whether the communication pin's level is a first preset level, whether the pulse width is within a first preset threshold range, and whether the time difference is less than a second preset threshold. If all three conditions are met, it is confirmed as a genuine wake-up signal. Specifically, in this embodiment of the invention, it simultaneously determines whether the communication pin's level is a first preset level, whether the pulse width is within a first preset threshold range, and whether the time difference is less than a second preset threshold. Only when all three conditions are met is it confirmed as a genuine wake-up signal. This triple verification mechanism comprehensively determines the signal based on three dimensions: polarity, pulse width, and timing. Polarity matching utilizes the positive or negative phase relationship between the IO-Link chip's communication pin and receiving pin to ensure the correct start state of the wake-up pulse. For example, when the IO-Link chip's communication pin and receiving pin are in negative phase, and the edge type flag variable represents a positive pulse, the first preset level is high, and the polarity matching logic is correct. Pulse width matching strictly follows the protocol standard; delay matching utilizes the inherent characteristics of the chip's internal processing timing. Even if the IO-Link chip pulls down the wake-up pin due to noise misjudgment, the main control chip can filter it out through this logic, thereby ensuring that the sensor can maintain the correct output state in a strong interference environment.

[0050] The step of calculating the pulse width of the signal on the receiving pin of the IO-Link chip and the time difference between the first edge of the wake-up pin and the signal edge on the receiving pin of the IO-Link chip based on the time information recorded by each input capture channel, and combining this with the recorded level state of the communication pin of the IO-Link chip controlled by the main control chip, to determine whether the first edge of the wake-up pin corresponds to a real wake-up signal, further includes: S54: Obtain the value of the edge type flag variable. When the edge type flag variable represents a negative pulse, the difference between the second edge time and the third edge time of the receiving pin is used as the pulse width. Specifically, in this embodiment of the invention, when the edge type flag variable represents a negative pulse, the difference between the second edge time and the third edge time of the receiving pin is used as the pulse width. By calculating using the second and third edge times automatically recorded by hardware, the width of the negative pulse can be accurately obtained. This measurement method is also directly calculated by hardware timestamps, unaffected by software response delays, ensuring high-precision matching of the 80μs wake-up pulse specified in the protocol, for example, 75~85μs, thereby effectively identifying legitimate high-level wake-up requests while eliminating noise with mismatched widths.

[0051] S55: The difference between the first edge time of the wake-up pin and the third edge time of the receiving pin is used as the time difference. Specifically, in this embodiment of the invention, the difference between the first edge time of the wake-up pin and the third edge time of the receiving pin is used as the time difference, i.e., the wake-up pin delay. For example, in a negative pulse scenario, the pulse starts at the third edge of the receiving pin, so the third edge is used as the benchmark for delay calculation. The difference between the first edge time of the wake-up pin and the third edge time of the receiving pin, recorded by hardware, accurately reflects the internal processing time of the chip. Since the chip processing time corresponding to the actual wake-up pulse has an inherent upper limit, such as less than 300μs, this step utilizes this timing characteristic to determine wake-up pin events exceeding a reasonable range as interference, further enhancing the rigor of verification and avoiding misjudgment of false wake-up pin signals caused by noise.

[0052] S56: Determine whether the communication pin's level state is a second preset level state, whether the pulse width is within a first preset threshold range, and whether the time difference is less than a second preset threshold. If all three conditions are met, it is confirmed as a genuine wake-up signal. Specifically, in this embodiment of the invention, it simultaneously determines whether the communication pin's level state is a second preset level state, whether the pulse width is within a first preset threshold range, and whether the time difference is less than a second preset threshold. Only when all three conditions are met is it confirmed as a genuine wake-up signal. For example, when the IO-Link chip's communication pin and receiving pin are inverted, and when the edge type flag variable represents a negative pulse, the second preset level state is low or high impedance, and the polarity matching logic is correct.

[0053] In another embodiment of the present invention, the first edge detection of the wake-up pin of the IO-Link chip can be implemented without relying on a separate second timer, but rather using a main loop polling method. Instead of configuring a second timer to capture the first edge of the wake-up pin, the main loop of the main control chip continuously reads the level state of the first edge of the wake-up pin. When a change in the wake-up pin level is detected, the current count value of the first timer is immediately read as the moment when the rising or falling edge of the wake-up pin occurs. It should be noted that this scheme requires the single execution time of the main loop to be strictly controlled within 10µs, and there should be no hard delays in the program to ensure the real-time performance of the polling. Alternatively, an external trigger interrupt scheme can be used, configuring the wake-up pin as an external interrupt input and setting it to be triggered by a rising or falling edge. When the rising or falling edge of the wake-up pin occurs, the CPU responds to the external interrupt and immediately reads the current count value of the first timer in the interrupt service routine as the moment when the wake-up pin rises or falls. This scheme also does not require a second timer, but it is important to note that when the interrupt service routine is used, resource contention with other high-priority interrupts or main tasks should be avoided.

[0054] Example 2 Based on the above-described hardware-coordinated wake-up signal detection method, this invention provides a hardware-coordinated wake-up signal detection device, please refer to... Figure 5 , Figure 5 A hardware-coordinated wake-up signal detection device 50 is provided as an embodiment of the present invention, comprising: Configuration module 51 is used to configure multiple input capture channels of the main control chip's timer and configure the main control chip's direct memory access (DMA) channel. The association module 52 is used to associate the DMA channel with the capture event of at least a portion of the input capture channel of the main control chip timer, and automatically record the level state of the communication pin of the IO-Link chip controlled by the main control chip through the DMA channel when the capture event occurs; The detection module 53 is used to poll and detect whether a capture event has occurred in the capture channel associated with the wake-up pin of the IO-Link chip in the input capture channel; The reading module 54 is used to read the time information recorded by each input capture channel of the timer when a capture event is detected in the capture channel associated with the wake-up pin of the IO-Link chip; The judgment module 55 is used to calculate the pulse width of the signal on the receiving pin of the IO-Link chip and the time difference between the first edge of the wake-up pin and the signal edge on the receiving pin of the IO-Link chip based on the time information recorded by each input capture channel, and combine the recorded level state of the communication pin of the IO-Link chip controlled by the main control chip to determine whether the first edge of the wake-up pin corresponds to the real wake-up signal. The wake-up module 56, if the first edge of the wake-up pin corresponds to a real wake-up signal, then the main control chip performs a wake-up operation.

[0055] For further details regarding the implementation of the above-mentioned technical solution by each module in the hardware-coordinated wake-up signal detection device, please refer to the description of the hardware-coordinated wake-up signal detection method provided in the above-mentioned embodiments of the invention, which will not be repeated here.

[0056] Example 3 Based on the above hardware-coordinated wake-up signal detection method, such as Figure 6 As shown in the diagram, an embodiment of the present invention provides a hardware-coordinated wake-up signal detection device. The device includes a processor 61 and a memory 62 coupled to the processor 61. The memory 62 stores a computer program. When the computer program is executed by the processor 61, the processor 61 performs the steps of the hardware-coordinated wake-up signal detection method described in the above embodiment.

[0057] For further details regarding the implementation of the above-mentioned technical solution by the processor 61 in the hardware-coordinated wake-up signal detection device, please refer to the description in the hardware-coordinated wake-up signal detection method provided in the above-mentioned embodiments of the invention, which will not be repeated here.

[0058] The processor 61 can also be called a CPU (Central Processing Unit). The processor 61 may be an integrated circuit chip with signal processing capabilities. The processor 61 can also be a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor, or the processor 61 can be any conventional processor.

[0059] Example 4 like Figure 7 The diagram illustrates the structure of a computer-readable storage medium provided in this embodiment of the invention. The storage medium stores a readable computer program 71. This computer program 71 can be stored in the storage medium as a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in various embodiments of the invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, magnetic disks or optical disks, ROM (Read-Only Memory), RAM (Random Access Memory), or terminal devices such as computers, servers, mobile phones, and tablets.

[0060] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, apparatuses, or modules, and may be electrical, mechanical, or other forms.

[0061] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0062] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium.

[0063] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0064] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0065] The technical solutions provided in this application have been described in detail above. Specific examples have been used in this application to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0066] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0067] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0068] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0069] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0070] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A hardware-cooperative based wake-up signal detection method, characterized in that, The method, applied to a sensor system comprising a main control chip and an IO-Link chip, includes: Configure multiple input capture channels for the main control chip's timer, and configure the main control chip's direct memory access (DMA) channel; The DMA channel is associated with at least a portion of the input capture channels of the main control chip's timer, and when the capture event occurs, the DMA channel is used to automatically record the level state of the communication pin of the IO-Link chip controlled by the main control chip. Polling to detect whether a capture event has occurred in the capture channel associated with the wake-up pin of the IO-Link chip in the input capture channel; When a capture event is detected in the capture channel associated with the wake-up pin of the IO-Link chip, the time information recorded by each input capture channel of the timer is read. Based on the time information recorded by each input capture channel, calculate the pulse width of the signal on the receiving pin of the IO-Link chip and the time difference between the first edge of the wake-up pin and the signal edge on the receiving pin of the IO-Link chip, and combine the recorded level state of the communication pin of the IO-Link chip controlled by the main control chip to determine whether the first edge of the wake-up pin corresponds to the real wake-up signal; If the first edge of the wake-up pin corresponds to a real wake-up signal, the main control chip performs a wake-up operation.

2. The hardware-cooperative based wake-up signal detection method of claim 1, wherein, The configuration of multiple input capture channels for the main control chip's timer and the configuration of the main control chip's direct memory access (DMA) channel include: Configure the first input capture channel of the first timer of the main control chip to capture the second edge of the receiving pin of the IO-Link chip, and configure the second input capture channel of the first timer of the main control chip to capture the third edge of the receiving pin; Configure the third input capture channel of the first timer of the main control chip to capture the second edge of the receiving pin of the IO-Link chip, and configure the fourth input capture channel of the first timer of the main control chip to capture the third edge of the receiving pin; Configure the first input capture channel of the second timer of the main control chip to capture the first edge of the wake-up pin of the IO-Link chip.

3. The hardware-cooperative based wake-up signal detection method of claim 2, wherein, The step of associating the DMA channel with at least a portion of the input capture channels of the main control chip's timer, and automatically recording the level state of the communication pins of the IO-Link chip controlled by the main control chip through the DMA channel when the capture event occurs, includes: The first DMA channel is configured to be associated with the capture event of the first input capture channel of the first timer, and when the second edge of the receive pin is captured, the level state of the communication pin output of the IO-Link chip currently controlled by the main control chip is stored in the first memory address; Configure the second DMA channel to be associated with the capture event of the third input capture channel of the first timer, and when the second edge of the receive pin is captured, store the constant value representing the second edge to the edge type flag variable address; The third DMA channel is configured to be associated with the capture event of the second input capture channel of the first timer, and when the third edge of the receive pin is captured, the level state of the communication pin output of the IO-Link chip currently controlled by the main control chip is stored in the second memory address. Configure the fourth DMA channel to be associated with the capture event of the fourth input capture channel of the first timer, and when the third edge of the receive pin is captured, store the constant value representing the third edge to the edge type flag variable address.

4. The hardware-cooperative based wake-up signal detection method of claim 2, wherein, Polling to detect whether a capture event has occurred in the capture channel associated with the wake-up pin of the IO-Link chip in the input capture channel, including: In the main loop or low-priority background task of the main control chip, read the capture update flag bit of the first input capture channel of the second timer of the main control chip; When the capture update flag is valid, it is determined that a capture event has occurred on the capture channel associated with the wake-up pin.

5. The hardware-cooperative wake-up signal detection method according to claim 3, wherein When a capture event is detected in the capture channel associated with the wake-up pin of the IO-Link chip, the time information recorded by each input capture channel of the timer is read, including: Read the second edge time of the receive pin recorded by the first input capture channel of the first timer, and read the third edge time of the receive pin recorded by the second input capture channel of the first timer; Read the first edge moment of the wake-up pin recorded by the first input capture channel of the second timer, and read the edge type flag variable to determine the edge type of the receive pin; Based on the value of the edge type flag variable, select to read the level state of the communication pin stored in the first memory address or the second memory address.

6. The wake-up signal detection method based on hardware collaboration according to claim 5, characterized in that, The step of calculating the pulse width of the signal on the receiving pin of the IO-Link chip and the time difference between the first edge of the wake-up pin and the signal edge on the receiving pin of the IO-Link chip based on the time information recorded by each input capture channel, and combining this with the recorded level state of the communication pin of the IO-Link chip controlled by the main control chip, to determine whether the first edge of the wake-up pin corresponds to a real wake-up signal, includes: Obtain the value of the edge type flag variable. When the edge type flag variable represents a positive pulse, use the difference between the third edge time of the receiving pin and the second edge time of the receiving pin as the pulse width. The time difference is the difference between the first edge time of the wake-up pin and the second edge time of the receive pin. Determine whether the original level state of the communication pin is a first preset level state, whether the pulse width is within a first preset threshold range, and whether the time difference is less than a second preset threshold. If all conditions are met, it is confirmed as a real wake-up signal.

7. The wake-up signal detection method based on hardware collaboration according to claim 5, characterized in that, The step of calculating the pulse width of the signal on the receiving pin of the IO-Link chip and the time difference between the first edge of the wake-up pin and the signal edge on the receiving pin of the IO-Link chip based on the time information recorded by each input capture channel, and combining this with the recorded level state of the communication pin of the IO-Link chip controlled by the main control chip, to determine whether the first edge of the wake-up pin corresponds to a real wake-up signal, further includes: Obtain the value of the edge type flag variable. When the edge type flag variable represents a negative pulse, use the difference between the second edge time and the third edge time of the receiving pin as the pulse width. The time difference is the difference between the first edge time of the wake-up pin and the third edge time of the receive pin. Determine whether the original level state of the communication pin is the second preset level state, whether the pulse width is within the first preset threshold range, and whether the time difference is less than the second preset threshold. If all conditions are met, it is confirmed as a real wake-up signal.

8. A wake-up signal detection device based on hardware collaboration, characterized in that, The device is used in a sensor system that includes a main control chip and an IO-Link chip, and includes: The configuration module is used to configure multiple input capture channels of the main control chip's timer and to configure the main control chip's direct memory access (DMA) channel. The association module is used to associate the DMA channel with at least a portion of the input capture channels of the main control chip's timer, and when the capture event occurs, automatically record the level state of the communication pin of the IO-Link chip controlled by the main control chip through the DMA channel; The detection module is used to poll and detect whether a capture event has occurred in the capture channel associated with the wake-up pin of the IO-Link chip in the input capture channel; The reading module is used to read the time information recorded by each input capture channel of the timer when a capture event is detected in the capture channel associated with the wake-up pin of the IO-Link chip; The judgment module is used to calculate the pulse width of the signal on the receiving pin of the IO-Link chip and the time difference between the first edge of the wake-up pin and the signal edge on the receiving pin of the IO-Link chip based on the time information recorded by each input capture channel, and combine the recorded level state of the communication pin of the IO-Link chip controlled by the main control chip to determine whether the first edge of the wake-up pin corresponds to the real wake-up signal. The wake-up module performs a wake-up operation if the first edge of the wake-up pin corresponds to a real wake-up signal.

9. A wake-up signal detection device based on hardware collaboration, characterized in that, Includes memory and processor, wherein: The memory is used to store computer programs; The processor is used to read the computer program in the memory and execute the steps of the hardware-coordinated wake-up signal detection method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores a readable computer program that, when executed by a processor, implements the steps of the hardware-coordinated wake-up signal detection method as described in any one of claims 1 to 7.

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