Vertically stacked uled pixel structure, monolithic integrated full-color uled micro-display chip suitable for flip-chip packaging and preparation method thereof

Abstract

This invention discloses a vertically stacked uLED pixel structure, a monolithically integrated full-color uLED microdisplay chip suitable for flip-chip packaging, and its fabrication method. By vertically stacking blue, green, and red light-emitting units, full-color display is achieved through monolithic integration. The blue, green, and red light-emitting units share the same light-emitting surface, reducing the planar area occupied by the pixel units and improving display resolution. Simultaneously, shallow trenches filled with insulating dielectric are used to isolate adjacent pixel structures, further reducing pixel spacing and increasing pixel density. By placing the insulating dielectric layer on the surface of the red light-emitting unit, metal interconnect rewiring is implemented within the insulating dielectric layer, and the interconnects are led out from the insulating dielectric layer through lead-out structures electrically connected to the metal interconnects. This avoids the use of through-silicon vias (TSVs), simplifying the fabrication process, streamlining the pixel wiring structure, and optimizing the circuit layout.

Description

Technical Field

[0001] This invention relates to the field of third-generation semiconductor technology, and in particular to a vertically stacked uLED pixel structure, a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging, and a method for fabricating the same. Background Technology

[0002] μLED technology, based on the third-generation semiconductor material GaN and derived from Mini-LED, is a newly emerging display technology in recent years. Compared to existing mainstream technologies, it has advantages such as low power consumption, wide color gamut, high brightness, and ease of implementation in AR / VR applications. It has already begun to be deployed in consumer sectors such as smart glasses, smartwatches, automotive electronics, and home appliances.

[0003] Existing commercially available full-color μLED microdisplay chips primarily consist of three independent μLED chips (blue, green, and red) mounted on the surface of a driver chip in a flat manner to form a colored pixel unit. Numerous pixel units are arranged in a two-dimensional array to form a display unit. There are also methods that use miniature optical modules to combine the monochrome images displayed by blue, green, and red microdisplays to form a color image. Recently, literature reports a method using hBN two-dimensional thin film material as a stress buffer layer, growing GaN-based blue and green LED epitaxial layers on a sapphire substrate, and growing an AlInP / GaInP-based red epitaxial layer on a GaAs substrate. Red, green, and blue μLEDs are vertically stacked on a silicon substrate using organic bonding adhesive and mechanical peeling to construct the luminescent pixel unit. Nature vol.614, pp.81–87, 2023 Another approach involves first vertically growing blue and green epitaxial layers on a sapphire substrate to fabricate blue-green dual-color vertically stacked μLED chips, and then using flip-chip packaging technology to horizontally combine them with red μLEDs to form a tiny full-color pixel unit. (Light:Science&Applications(2023)12:258) In recent years, publicly available patent literature has reported... (CN1160312778B, WO2024012274A1) There are also examples of vertically stacked or horizontally integrated red, green and blue μLEDs to construct full-color pixel units. How to simplify the wiring structure and process of full-color pixel units with vertically stacked three-color epitaxial wafers has become an urgent problem to be solved. Summary of the Invention

[0004] This invention provides a vertically stacked uLED pixel structure, a monolithically integrated full-color uLED microdisplay chip suitable for flip-chip packaging, and its fabrication method. It achieves vertical stacking of the three primary colors (red, green, and blue) in the pixel unit in a monolithic integration manner, and realizes metal interconnect rewiring in the insulating dielectric layer on the surface of the pixel unit, simplifying the wiring structure and process and optimizing the line layout.

[0005] According to one aspect of the present invention, a vertically stacked uLED pixel structure is provided, comprising: a stress buffer layer; a pixel unit, the structure of which includes: a blue light-emitting unit, a green light-emitting unit, and a red light-emitting unit stacked vertically on the stress buffer layer, wherein spacer layers are respectively disposed between the blue light-emitting unit and the green light-emitting unit, and between the green light-emitting unit and the red light-emitting unit; an insulating dielectric layer disposed on the surface of the red light-emitting unit; a metal interconnect redistribution line embedded in the insulating dielectric layer, the metal interconnect redistribution line being electrically connected to the blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit; and a lead-out structure electrically connected to the metal interconnect redistribution line and led out from the side of the insulating dielectric layer away from the red light-emitting unit.

[0006] Optionally, the blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit all include a first semiconductor layer, a light-emitting layer, and a second semiconductor layer that are stacked vertically; The pixel structure also includes three first ohmic contact structures and three second ohmic contact structures, which are vertically disposed on the blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit. The three first ohmic contact structures are electrically connected to the first semiconductor layer of the blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit, respectively. The three second ohmic contact structures are electrically connected to the first semiconductor layer of the blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit, respectively. The three first ohmic contact structures and the three second ohmic contact structures all extend into the insulating dielectric layer.

[0007] Optionally, the metal interconnect rewiring includes three first interconnect lines and three second interconnect lines; the three first interconnect lines are electrically connected to three first ohmic contact structures one-to-one, and the three second interconnect lines are electrically connected to three second ohmic contact structures one-to-one.

[0008] Optionally, the lead-out structure includes a first lead-out structure and three second lead-out structures; the first lead-out structure is electrically connected to all three first interconnecting lines, and the three second lead-out structures are electrically connected to the three second interconnecting lines one-to-one.

[0009] Optionally, the insulating dielectric layer includes a first insulating dielectric layer and a second insulating dielectric layer, with the first insulating dielectric layer located between the red light-emitting unit and the second insulating dielectric layer; a first interconnecting line, a second interconnecting line, a first lead-out structure, and three second lead-out structures are disposed on the first insulating dielectric layer; the second insulating dielectric layer covers the first interconnecting line, the second interconnecting line, the first lead-out structure, the three second lead-out structures, and the first insulating dielectric layer, and the free ends of the first lead-out structure and the three second lead-out structures are exposed from the surface of the second insulating dielectric layer away from the first insulating dielectric layer.

[0010] Optionally, the vertically stacked uLED pixel structure also includes a metal reflector, which is located between the first insulating dielectric layer and the second insulating dielectric layer, and is isolated and insulated from the metal interconnect rewiring, lead-out structure, first ohmic contact structure and second ohmic contact structure; the orthographic projection of the reflector on the insulating dielectric layer overlaps with the orthographic projection of the light-emitting area of ​​the pixel unit on the insulating dielectric layer.

[0011] Optionally, the first ohmic contact structure and the second ohmic contact structure are in the form of a ring or a strip.

[0012] Optionally, the stress buffer layer is an undoped gallium nitride layer, and / or the spacer layer is an undoped AlGaN layer.

[0013] According to another aspect of the present invention, a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging is provided, including a stress buffer layer and an epitaxial structure disposed on one side of the stress buffer layer. The epitaxial structure is provided with a plurality of closed isolation channels, which define the pixel structure of any embodiment of the present invention.

[0014] Optionally, the isolation channel extends from the surface of the epitaxial structure into the stress buffer layer.

[0015] According to another aspect of the present invention, a method for fabricating a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging is provided, comprising: Provide a stress buffer layer; Blue emitting units, green emitting units, and red emitting units are vertically grown on a stress buffer layer, as well as spacer layers between blue emitting units and green emitting units, and between green emitting units and red emitting units, to form an epitaxial structure. Shallow trench etching of epitaxial structures defines pixel units; An insulating dielectric layer is covered on the surface of the pixel unit, and a metal interconnect rewiring and lead-out structure are fabricated on the insulating dielectric layer.

[0016] Optionally, the blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit all include a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked together; Covering the surface of the pixel unit with an insulating dielectric layer includes: A first insulating dielectric layer is covered on the surface of the pixel unit; Starting from the first insulating dielectric layer, three first grooves and three second grooves are etched vertically in sequence. The three first grooves are etched and stop at the first semiconductor layer of the red light-emitting unit, the green light-emitting unit and the blue light-emitting unit, respectively. The three second grooves are etched and stop at the second semiconductor layer of the red light-emitting unit, the green light-emitting unit and the blue light-emitting unit, respectively. A third insulating dielectric layer is formed on the sidewall of each first groove and each second groove, and the bottom of the third insulating dielectric layer exposes a first semiconductor layer or a second semiconductor layer. A first ohmic contact structure is formed by filling a first groove with metal material, and a second ohmic contact structure is formed by filling a second groove with metal material.

[0017] Optionally, fabricating metal interconnect rewiring and lead-out structures in the insulating dielectric layer includes: A first metal lead-out layer, three second metal lead-out layers, three first interconnect lines, and three second interconnect lines are prepared on the surface of the first insulating dielectric layer away from the epitaxial structure. The three first interconnect lines are respectively connected to three first ohmic contact structures, the three second interconnect lines are respectively connected to three second ohmic contact structures, a first metal lead-out layer is connected to the three first interconnect lines, and the three second metal lead-out layers are respectively connected to the three second interconnect lines. A second insulating dielectric layer is covered on the surfaces of the first metal lead-out layer, the second metal lead-out layer, the first interconnect line, the second interconnect line, and the first insulating dielectric layer; a window is opened in the second insulating dielectric layer at the position corresponding to the first metal lead-out layer and the second metal lead-out layer, and the window exposes the corresponding first metal lead-out layer and the second metal lead-out layer; A conductive material is filled into the window to form a first lead-out structure on the first metal lead-out layer, and a second lead-out structure is formed on the second metal lead-out layer.

[0018] Optionally, after filling the window with conductive material, the process includes etching a second insulating dielectric layer of a certain thickness to expose the first lead-out structure and the second lead-out structure.

[0019] Optionally, before forming the epitaxial structure, the method further includes: growing a stress buffer layer on a sapphire substrate by lateral epitaxy using a hydride vapor phase epitaxy process, wherein the stress buffer layer is an undoped first gallium nitride layer.

[0020] Optionally, before growing a stress buffer layer on a sapphire substrate using hydride vapor phase epitaxy, the process further includes: A silicon nitride thin film is deposited on a sapphire substrate and patterned to form a periodic structure; the thickness of the silicon nitride thin film is less than the thickness of the stress buffer layer. Alternatively, a second gallium nitride layer can be grown on a sapphire substrate using an organic chemical vapor deposition process, and the surface of the second gallium nitride layer can be roughened using ion bombardment or wet etching; the thickness of the second gallium nitride layer is less than the thickness of the stress buffer layer.

[0021] Optionally, shallow trench etching epitaxial structures define pixel units, including: The epitaxial structure is etched using inductively coupled plasma reactive ion etching (ICP-IR) to form isolation channels. Atomic layer deposition is used to form a sidewall passivation layer on the sidewall of the isolation channel to passivate the sidewall of the epitaxial structure. Using plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition, silicon oxide is filled into the isolation trench to completely fill it. A planarization process is used to remove silicon oxide overflowing from the isolation channel, thereby planarizing the surface of the epitaxial structure.

[0022] Optionally, the spacer layer is undoped AlGaN.

[0023] This invention relates to a vertically stacked uLED pixel structure, a monolithically integrated full-color uLED microdisplay chip suitable for flip-chip packaging, and its fabrication method. By vertically stacking blue, green, and red light-emitting units, full-color display is achieved through monolithic integration. The blue, green, and red light-emitting units share the same emitting surface, reducing the planar area occupied by each pixel unit and improving display resolution. Simultaneously, shallow trenches filled with insulating dielectric are used to isolate adjacent pixel structures, further reducing pixel spacing and increasing pixel density. By placing the insulating dielectric layer on the surface of the red light-emitting unit, and embedding metal interconnect redistribution lines within the insulating dielectric layer, these lines are electrically connected to the blue, green, and red light-emitting units, respectively, and are led out from the insulating dielectric layer through lead-out structures electrically connected to the metal interconnect redistribution lines. This achieves metal interconnect redistribution within the insulating dielectric layer, eliminating the need for internal redistribution in the epitaxial layer. This avoids the use of through-silicon vias (TSVs), simplifies the fabrication process, simplifies the pixel wiring structure, optimizes the circuit layout, and makes the light-emitting chip suitable for flip-chip packaging based on thermo-bonding or hybrid bonding. Because the light-emitting chip has a flip-chip structure, the light emitted by the chip exits from the stress buffer layer. One side of the epitaxial layer of the chip contacts the active driver chip, rather than facing the ambient space, which helps with heat dissipation.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1This is a schematic diagram of a vertically stacked uLED pixel structure provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another vertically stacked uLED pixel structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another vertically stacked uLED pixel structure provided in an embodiment of the present invention; Figure 4 This is a cross-sectional view of a pixel structure provided in an embodiment of the present invention; Figure 5 This is a cross-sectional view of another pixel structure provided in an embodiment of the present invention; Figure 6 This is a cross-sectional view of another pixel structure provided in an embodiment of the present invention; Figure 7 This is a cross-sectional view of another pixel structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of another vertically stacked uLED pixel structure provided in an embodiment of the present invention; Figure 9 This is a cross-sectional view of a pixel structure provided in an embodiment of the present invention; Figure 10 This is a cross-sectional view of another pixel structure provided in an embodiment of the present invention; Figure 11 This is a cross-sectional view of another pixel structure provided in an embodiment of the present invention; Figure 12 This is a cross-sectional view of another pixel structure provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of the structure before the formation of the first ohmic contact structure and the second ohmic contact structure; Figure 14 This is a schematic diagram of the intermediate structure of a pixel unit provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of another pixel structure provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of the structure of a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging, provided by an embodiment of the present invention; Figure 17 This is a schematic diagram of the structure after the isolation channel is formed during the fabrication of a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging; Figure 18 yes Figure 17 A cross-sectional view obtained by cutting along KK'; Figure 19This is a flowchart illustrating a method for fabricating a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging, as provided in an embodiment of the present invention. Figure 20 This is a flowchart of covering the surface of a pixel unit with an insulating dielectric layer; Figure 21 This is a flowchart of the fabrication of metal interconnect rewiring and lead-out structures in an insulating dielectric layer. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] This invention provides a vertically stacked uLED pixel structure. Figure 1 This is a schematic diagram of a vertically stacked uLED pixel structure provided in an embodiment of the present invention. (Refer to...) Figure 1The vertically stacked uLED pixel structure sequentially includes: a stress buffer layer 400; a pixel unit 100, the structure of which includes: a blue light-emitting unit 110, a green light-emitting unit 120, and a red light-emitting unit 130 stacked vertically on the stress buffer layer 400, with spacer layers 500 respectively disposed between the blue light-emitting unit 110 and the green light-emitting unit 120, and between the green light-emitting unit 120 and the red light-emitting unit 130; an insulating dielectric layer 600 disposed on the surface of the red light-emitting unit 130; a metal interconnect redistribution line 700 embedded in the insulating dielectric layer 600, the metal interconnect redistribution line 700 being electrically connected to the blue light-emitting unit 110, the green light-emitting unit 120, and the red light-emitting unit 130; and a lead-out structure 800 electrically connected to the metal interconnect redistribution line 700 and led out from the side of the insulating dielectric layer 600 away from the red light-emitting unit 130.

[0030] The epitaxial layer is grown on the surface of the stress buffer layer 400 to release stress caused by lattice mismatch and prevent dislocations from diffusing into the functional layer of the epitaxial thin film. Optionally, an undoped thick GaN layer with a thickness of approximately 20 μm to 30 μm is grown on the surface of the sapphire substrate as the stress buffer layer 400 using hydride vapor phase epitaxy (HVPE) technology.

[0031] Blue light-emitting unit 110, green light-emitting unit 120, and red light-emitting unit 130 are vertically stacked to achieve full-color display. The blue light-emitting unit 110, green light-emitting unit 120, and red light-emitting unit 130 share the same light-emitting surface, which reduces the planar area occupied by the pixel unit and thus improves the display resolution. Spacer layers 500 are respectively provided between the blue light-emitting unit 110 and the green light-emitting unit 120, and between the green light-emitting unit 120 and the red light-emitting unit 130. Spacer layers 500 are insulating layers that isolate adjacent light-emitting units. A wide-bandgap semiconductor layer, such as undoped AlGaN, can be used as the spacer layer 500 to ensure that the light-emitting units 100, when vertically stacked, do not short-circuit with each other.

[0032] The pixel structure also includes an insulating dielectric layer 600 and metal interconnect redistribution lines 700. The insulating dielectric layer 600 is located on the surface of the red light-emitting unit 130, for example, on the surface of the red light-emitting unit 130 away from the green light-emitting unit 120. The insulating dielectric layer 600 is made of an insulating material, such as silicon dioxide. The metal interconnect redistribution lines 700 are embedded in the insulating dielectric layer 600 and are electrically connected to the blue light-emitting unit 110, the green light-emitting unit 120, and the red light-emitting unit 130, respectively. The metal interconnect redistribution lines 700 can be made of a metallic material. Since the metal interconnect redistribution lines 700 are located in the insulating dielectric layer 600, and the insulating dielectric layer 600 is located on the surface of the red light-emitting unit 130, the metal interconnect redistribution lines 700 are formed on the surface of the epitaxial layer. This eliminates the need for internal metal interconnect redistribution lines 700 within the epitaxial layer, avoiding the use of through-silicon vias (TSVs), simplifying the fabrication process, and optimizing the wiring structure and circuit layout.

[0033] The pixel structure also includes a lead-out structure 800, which can be made of a metallic material, such as a metal bump or a metal pillar. The lead-out structure 800 is connected to the metal interconnect redistribution line 700 and extends from the side of the insulating dielectric layer 600 away from the red light-emitting unit 130, facilitating connection between the lead-out structure 800 and an external driving circuit. The lead-out structure 800 can also be used to connect the driving circuit. For example, based on hybrid bonding thermocompression welding, the lead-out structure 800 can be interconnected with conductive bumps in the driving circuit, and the insulating dielectric layer 600 on the pixel structure surface can be bonded to the dielectric layer on the driving circuit surface. Thus, the driving circuit can transmit electrical signals to the pixel unit through the lead-out structure 800 and the metal interconnect redistribution line 700, thereby driving the pixel unit. Along the vertical stacking direction y of the light-emitting units in the pixel structure, the lead-out structure 800 is located on the first side of the pixel structure, and the light-emitting surface of the pixel structure is on the second side of the pixel unit. Along the vertical stacking direction y of the light-emitting units in the pixel structure, the first side and the second side are opposite each other.

[0034] The vertically stacked uLED pixel structure in this embodiment achieves full-color display through monolithic integration by vertically stacking blue, green, and red light-emitting units. This allows the blue, green, and red light-emitting units to share the same light-emitting surface, reducing the planar area occupied by the pixel unit and improving display resolution. An insulating dielectric layer is located on the surface of the red light-emitting unit, and metal interconnect redistribution lines are embedded within this layer. These metal interconnect redistribution lines are electrically connected to the blue, green, and red light-emitting units, respectively, and are led out from the insulating dielectric layer through lead-out structures electrically connected to them. This achieves metal interconnect redistribution within the insulating dielectric layer, eliminating the need for internal redistribution in the epitaxial layer. This avoids the use of through-silicon vias (TSVs), simplifies the fabrication process, streamlines the pixel unit wiring structure, optimizes the circuit layout, and makes the light-emitting chip suitable for flip-chip packaging based on thermo-bonding or hybrid bonding.

[0035] Figure 2 This is a schematic diagram of another vertically stacked uLED pixel structure provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of another vertically stacked uLED pixel structure provided in an embodiment of the present invention. Figure 4 This is a cross-sectional view of a pixel structure provided in an embodiment of the present invention. Figure 5 This is a cross-sectional view of another pixel structure provided in an embodiment of the present invention. Figure 6 This is a cross-sectional view of another pixel structure provided in an embodiment of the present invention. Figure 7 This is a cross-sectional view of another pixel structure provided in an embodiment of the present invention. Figure 4 Can correspond Figure 2 and Figure 3 Obtained by cutting along AA'. Figure 5 Can correspond Figure 3 Obtained by cutting along BB'. Figure 6 Can correspond Figure 3 Obtained by cutting along CC'. Figure 7 It can correspond. Figure 3 Obtained by cutting along DD'.

[0036] Figure 8 This is a schematic diagram of another vertically stacked uLED pixel structure provided in an embodiment of the present invention. Figure 9 This is a cross-sectional view of a pixel structure provided in an embodiment of the present invention. Figure 10 This is a cross-sectional view of another pixel structure provided in an embodiment of the present invention. Figure 11 This is a cross-sectional view of another pixel structure provided in an embodiment of the present invention. Figure 12 This is a cross-sectional view of another pixel structure provided in an embodiment of the present invention, wherein, Figure 9 Can correspond Figure 8 Obtained by cutting along EE'. Figure 10 Can correspond Figure 8 Obtained by cutting along FF'. Figure 11 Can correspond Figure 8 Obtained by cutting along GG'. Figure 12 It can correspond. Figure 8 Obtained by cutting along HH'.

[0037] Continue to refer to Figures 2-12 In some embodiments, the blue light-emitting unit 110, the green light-emitting unit 120, and the red light-emitting unit 130 each include a vertically stacked first semiconductor layer 101, a light-emitting layer 102, and a second semiconductor layer 103; the pixel structure also includes three first ohmic contact structures 221 and three second ohmic contact structures 321, which are vertically disposed on the blue light-emitting unit 110, the green light-emitting unit 120, and the red light-emitting unit 130; the three first ohmic contact structures 221 are electrically connected to the first semiconductor layer 101 of the blue light-emitting unit 110, the green light-emitting unit 120, and the red light-emitting unit 130 respectively; the three second ohmic contact structures 321 are electrically connected to the first semiconductor layer 101 of the blue light-emitting unit 110, the green light-emitting unit 120, and the red light-emitting unit 130 respectively; and the three first ohmic contact structures 221 and the three second ohmic contact structures 321 extend into the insulating dielectric layer 600.

[0038] Wherein, the first semiconductor layer 101 is an N-type semiconductor layer and the second semiconductor layer 103 is a P-type semiconductor layer; or the first semiconductor layer 101 is a P-type semiconductor layer and the second semiconductor layer 103 is an N-type semiconductor layer. The N-type semiconductor layer may include, for example, n-GaN, and the P-type semiconductor layer may include, for example, p-GaN. The light-emitting layer 102 may include, for example, a multiple quantum well (MQW) layer.

[0039] The first ohmic contact structure 221 and the second ohmic contact structure 321 each comprise a conductive material, such as a metallic material. The three first ohmic contact structures 221 are respectively designated as first ohmic contact structure A 2211, first ohmic contact structure B 2212, and first ohmic contact structure C 2213. Specifically, the first end of first ohmic contact structure A 2211 contacts the first semiconductor layer 101 of the red light-emitting unit 130, and the second end extends vertically to the insulating dielectric layer 600; the first end of first ohmic contact structure B 2212 contacts the first semiconductor layer 101 of the green light-emitting unit 120, and the second end extends vertically to the insulating dielectric layer 600; the first end of first ohmic contact structure C 2213 contacts the first semiconductor layer 101 of the blue light-emitting unit 110, and the second end extends vertically to the insulating dielectric layer 600.

[0040] The three second ohmic contact structures 321 are respectively designated as second ohmic contact structure A 3211, second ohmic contact structure B 3212, and second ohmic contact structure C 3213. Specifically, the first end of second ohmic contact structure A 3211 contacts the second semiconductor layer 103 of the red light-emitting unit 130, and the second end extends vertically to the insulating dielectric layer 600; the first end of second ohmic contact structure B 3212 contacts the second semiconductor layer 103 of the green light-emitting unit 120, and the second end extends vertically to the insulating dielectric layer 600; the first end of second ohmic contact structure C 3213 contacts the second semiconductor layer 103 of the blue light-emitting unit 110, and the second end extends vertically to the insulating dielectric layer 600. Thus, the three first ohmic contact structures 221 and the three second ohmic contact structures 321 all extend into the insulating dielectric layer 600, thereby enabling the electrical connection between the first ohmic contact structure 221 and the metal interconnect redistribution, as well as the electrical connection between the second ohmic contact structure 321 and the metal interconnect redistribution. This achieves the electrical connection between the first semiconductor layer 101 and the metal interconnect redistribution, and the electrical connection between the second semiconductor layer 103 and the metal interconnect redistribution, without the need to set the metal interconnect redistribution in the epitaxial layer, simplifying the wiring structure and fabrication process.

[0041] Figure 13 This is a schematic diagram of the structure before the formation of the first and second ohmic contact structures. Specifically, Figure 13 Can be with Figure 4 Corresponding, for reference Figures 2-7 ,or Figure 8-12 ,as well as Figure 13Optionally, the pixel structure has three first grooves 10 and three second grooves 20. The first groove 10 is recessed into the pixel structure from the side where the lead-out structure 800 is provided. The second groove 20 is recessed into the pixel structure from the side where the lead-out structure 800 is provided. A first ohmic contact structure 221 is provided in the first groove 10 and a second ohmic contact structure 321 is provided in the second groove 20. The bottom of the different first grooves 10 is located in the first semiconductor layer 101 of the different light-emitting units, and the bottom of the different second grooves 20 is located in the second semiconductor layer 103 of the different light-emitting units.

[0042] The first groove 10 and the second groove 20 can be formed by patterning the pixel structure. Specifically, during the fabrication of the pixel unit, the epitaxial structure can be patterned to form multiple pixel structures, with isolation channels formed between adjacent pixel structures. Then, the pixel structure is patterned to form the first groove 10 and the second groove 20 corresponding to each light-emitting unit. When patterning the pixel structure, the patterning process for the first groove 10 stops at the first semiconductor layer 101 corresponding to the light-emitting unit, and the patterning process for the second groove 20 stops at the second semiconductor layer 103 corresponding to the light-emitting unit. By placing the first ohmic contact structure 221 in the first groove 10 and the second ohmic contact structure 321 in the second groove 20, the first ohmic contact structure 221 and the second ohmic contact structure 321 are placed inside the pixel structure, thus providing better protection for the first ohmic contact structure 221 and the second ohmic contact structure 321.

[0043] Continue to refer to Figures 2-12 In some embodiments, the metal interconnect redistribution includes three first interconnect lines 222 and three second interconnect lines 322; the three first interconnect lines 222 are electrically connected to three first ohmic contact structures 221 in a one-to-one correspondence, and the three second interconnect lines 322 are electrically connected to three second ohmic contact structures 321 in a one-to-one correspondence.

[0044] The three first interconnecting lines 222 are respectively designated as first interconnecting line A 2221, first interconnecting line B 2222, and first interconnecting line C 2223. First interconnecting line A 2221 is electrically connected to first ohmic contact structure A 2211, first interconnecting line B 2222 is electrically connected to first ohmic contact structure B 2212, and first interconnecting line C 2223 is electrically connected to first ohmic contact structure C 2213. The three second interconnecting lines 322 are respectively designated as second interconnecting line A 3221, second interconnecting line B 3232, and second interconnecting line C 3223. Second interconnecting line A 3221 is electrically connected to second ohmic contact structure A 3211, second interconnecting line B 3232 is electrically connected to second ohmic contact structure B 3212, and second interconnecting line C 3223 is electrically connected to second ohmic contact structure C 3213.

[0045] Specifically, the first interconnect line 222 and the second interconnect line 322 each comprise a conductive material, such as a metallic material. The width of the first interconnect line 222 and the second interconnect line 322 is approximately 1 μm to 2 μm, and the thickness is approximately 500 nm to 1 μm. The arrangement of the first interconnect line 222 allows for more flexible positioning of the first ohmic contact structure 221 and the lead-out structure 800. When there is a gap between the first ohmic contact structure 221 and the lead-out structure 800, an electrical connection between them can be achieved through the first interconnect line 222. Similarly, the arrangement of the second interconnect line 322 allows for more flexible positioning of the second ohmic contact structure 321 and the lead-out structure 800. When there is a gap between the second ohmic contact structure 321 and the lead-out structure 800, an electrical connection between them can be achieved through the second interconnect line 322.

[0046] Continue to refer to Figures 2-12 In some embodiments, the lead-out structure 800 includes a first lead-out structure 210 and three second lead-out structures 310; the first lead-out structure 210 is electrically connected to three first interconnect lines 222, and the three second lead-out structures 310 are electrically connected to the three second interconnect lines 322 respectively.

[0047] The first lead-out structure 210 and the second lead-out structure 310 can be columnar, such as cylindrical. The diameter of the first lead-out structure 210 and the second lead-out structure 310 is between 3 μm and 5 μm, and the thickness is between 500 nm and 1 μm.

[0048] In this embodiment, the first lead-out structure 210 serves as the common electrode of the pixel structure and is electrically connected to all three first interconnect lines 222, thereby achieving electrical connection with the first semiconductor layer of each light-emitting unit in the pixel structure. The second lead-out structure 310 is an independent electrode, and the second lead-out structure 310 connected to each light-emitting unit in the pixel structure is different, and the different second lead-out structures 310 are mutually insulated. This pixel structure, while enabling independent light emission from the light-emitting units in the pixel unit, reduces the number of lead-out structures 800, simplifies the connection between the pixel structure and the driving circuit, thereby simplifying the design of the driving circuit and reducing the requirements for the driving circuit.

[0049] The pixel unit adopts an inverted structure. Blue light is emitted directly from the surface of the blue light-emitting unit 110 through the stress buffer layer 400. Green light is emitted after passing through the blue light-emitting unit 110 and the stress buffer layer 400. Red light is emitted after passing through the green light-emitting unit 120, the blue light-emitting unit 110, and the stress buffer layer 400 in sequence. The first lead-out structure 210, the second lead-out structure 310, the first interconnect line 222, and the second interconnect line 322 are respectively disposed on the surface of the red light-emitting unit 130 away from the green light-emitting unit 120. Figures 2-4 Of the three second lead-out structures 310 shown, the second lead-out structure 310 connected to the second interconnect line A 3221 is designated as second lead-out structure A 311, the second lead-out structure 310 connected to the second interconnect line B 3222 is designated as second lead-out structure B 312, and the second lead-out structure 310 connected to the second interconnect line C 3223 is designated as second lead-out structure C 313.

[0050] It should be noted that the first interconnect line 222 is only connected to the corresponding first ohmic contact structure 221, and is insulated from the first ohmic contact structure 221 and the second ohmic contact structure 321 corresponding to other light-emitting units in the pixel unit. For example, an insulating layer (not shown in the figure) is provided at the position of the first ohmic contact structure 221 or the second ohmic contact structure 321 that the first interconnect line 222 crosses. The same applies to the second interconnect line 322, which will not be described in detail here.

[0051] In some embodiments, the insulating dielectric layer 600 includes a first insulating dielectric layer 401 and a second insulating dielectric layer 402, with the first insulating dielectric layer 401 located between the red light-emitting unit 130 and the second insulating dielectric layer 402; a first interconnecting line 222, a second interconnecting line 322, a first lead-out structure 210, and three second lead-out structures 310 are disposed on the first insulating dielectric layer 401; the second insulating dielectric layer 402 covers the first interconnecting line 222, the second interconnecting line 322, the first lead-out structure 210, the three second lead-out structures 310, and the first insulating dielectric layer 401, with the free ends of the first lead-out structure 210 and the three second lead-out structures 310 exposed from the surface of the second insulating dielectric layer 402 away from the first insulating dielectric layer 401.

[0052] Optionally, the materials of the first insulating dielectric layer 401 and the second insulating dielectric layer 402 can be silicon dioxide. In this embodiment, the insulating dielectric layer 600 is a double-layer structure consisting of a first insulating dielectric layer 401 and a second insulating dielectric layer 402. The first interconnecting line 222, the second interconnecting line 322, the first lead-out structure 210, and three second lead-out structures 310 are disposed on the first insulating dielectric layer 401, which can insulate the structures that do not need to be electrically connected to the red light-emitting unit 130 from the red light-emitting unit 130. The first ohmic contact structure 221 extends vertically to the surface of the first insulating dielectric layer 401, thereby interconnecting with the first interconnecting line 222; the second ohmic contact structure 321 extends vertically to the surface of the first insulating dielectric layer 401, thereby interconnecting with the second interconnecting line 322.

[0053] A second insulating dielectric layer 402 is used to cover the first interconnect 222, the second interconnect 322, the first lead-out structure 210, the three second lead-out structures 310, and the first insulating dielectric layer 401. Metal interconnect rewiring is achieved inside the insulating dielectric layer 600. This simplifies the wiring structure and process by eliminating the need for through-silicon vias (TSVs), preventing the metal interconnect rewiring from being exposed and improving the reliability of the pixel structure. The free ends of the first lead-out structure 210 and the three second lead-out structures 310 are exposed from the surface of the second insulating dielectric layer 402 away from the first insulating dielectric layer 401, facilitating the connection of the first lead-out structure 210 and the three second lead-out structures 310 to the driving circuit.

[0054] Optionally, the first lead-out structure 210 is located in the central region of the second insulating dielectric layer 402, and the second lead-out structure 310 is located in the edge region of the second insulating dielectric layer 402, with the edge region surrounding the central region. This reduces the difference in length of the first interconnect lines 222 corresponding to different light-emitting units, making the lengths of the first interconnect lines 222 connected to different light-emitting units closer. Consequently, the voltage drops on the different first interconnect lines 222 are also closer, making the voltages transmitted to the first semiconductor layer 101 of different light-emitting units in the pixel unit closer, thereby improving the light-emitting effect.

[0055] like Figure 3 and Figure 8 As shown, optionally, the orthographic projection of the first lead-out structure 210 onto the pixel unit is located within the light-emitting region of the pixel structure, and the second lead-out structure 310 is located within the light-emitting region of the pixel structure. Figure 2 As shown, in some embodiments, the second lead-out structure 310 may also be disposed outside the light-emitting area, such as... Figure 2 , Figure 3 and Figure 8 As shown, the second lead-out structure 310 is closer to the edge of the pixel unit than the first lead-out structure 210.

[0056] The first lead-out structure 210 and the second lead-out structure 310 are projected onto the light-emitting area of ​​the pixel unit, which ensures that the first lead-out structure 210 and the second lead-out structure 310 do not occupy additional area outside the light-emitting area of ​​the pixel unit, thereby making the area of ​​the light-emitting area larger, optimizing the spatial layout and improving the light-emitting effect.

[0057] In some embodiments, the pixel structure further includes a metal reflector located between the first insulating dielectric layer and the second insulating dielectric layer, and is isolated and insulated from the metal interconnect rewiring, lead-out structure, first ohmic contact structure and second ohmic contact structure; the orthographic projection of the reflector on the insulating dielectric layer overlaps with the orthographic projection of the light-emitting area of ​​the pixel unit on the insulating dielectric layer.

[0058] The metal reflector can be a thin film of gold, silver, or aluminum. By placing the metal reflector between the first and second insulating dielectric layers, light incident on the metal reflector can be reflected to the light-emitting surface, thereby increasing the amount of light emitted and improving the brightness of the pixel unit.

[0059] Specifically, in the pixel structure, the first ohmic contact structure 221 connected to the red light-emitting unit 130 can be partially disposed between the first insulating dielectric layer 401 and the second insulating dielectric layer 402. In some embodiments, the first ohmic contact structure 221 connected to the red light-emitting unit 130 can overlap with the light-emitting area of ​​the pixel structure, thus making the area of ​​the first ohmic contact structure 221 connected to the red light-emitting unit 130 larger, so that the first ohmic contact structure 221 can act as a reflector to improve the light extraction efficiency.

[0060] like Figures 2-12 As shown, in some embodiments, the first ohmic contact structure 221 and the second ohmic contact structure 321 are in the form of a ring or a strip.

[0061] refer to Figure 2 and Figure 3 Optionally, the first ohmic contact structure 221 and the second ohmic contact structure 321 are alternately arranged, with the first ohmic contact structure 221 and the second ohmic contact structure 321 connected to the same light-emitting unit 100 being adjacent. The first ohmic contact structure 221 and / or the second ohmic contact structure 321 surround the light-emitting area of ​​the corresponding light-emitting unit. When both the first ohmic contact structure 221 and the second ohmic contact structure 321 corresponding to the light-emitting unit are annular, both the first ohmic contact structure 221 and the second ohmic contact structure 321 surround the corresponding light-emitting unit, and the light-emitting area of ​​the light-emitting unit is determined by the area contained in the inner ring of the ohmic contact structure in the corresponding first ohmic contact structure 221 and the second ohmic contact structure 321.

[0062] The first ohmic contact structure 221 and the second ohmic contact structure 321 are in a ring shape. On the one hand, this ensures that the first ohmic contact structure 221 and the second ohmic contact structure 321 are located close to the edge of the pixel unit, which is beneficial to increasing the light-emitting area. On the other hand, the ring-shaped first ohmic contact structure 221 has a larger contact area with the first semiconductor layer 101. Similarly, the ring-shaped second ohmic contact structure 321 has a larger contact area with the second semiconductor layer 103, thereby reducing the contact resistance and improving the light-emitting effect.

[0063] refer to Figures 2-7The pixel unit includes five annular ohmic contact structures, comprising two first ohmic contact structures 221 and three second ohmic contact structures 321. These five annular ohmic contact structures respectively contact the first semiconductor layer 101 or the second semiconductor layer 103 of three different light-emitting units (blue, green, and red). The first ohmic contact structures 221 and the second ohmic contact structures 321 are located within annular grooves, with a spacing of approximately 1 μm between the annular grooves.

[0064] Furthermore, the first ohmic contact structure 221 connected to the red light-emitting unit 130 can be enlarged to cover most of the area of ​​the pixel unit so that it can simultaneously act as a reflector to reflect the light waves emitted from the surface of the red light-emitting unit 130 near the first lead-out structure 210 back into the pixel unit and be emitted from the light-emitting side of the pixel structure.

[0065] Figure 14 This is a schematic diagram of the intermediate structure of the pixel structure provided in the embodiment of the present invention. Figure 15 This is a schematic diagram of another pixel unit structure provided in an embodiment of the present invention. Figure 14 and Figure 15 To and Figure 8 The corresponding 3D image, and Figure 14 This is a structural diagram before the formation of the first interconnect line, the second interconnect line, the first lead-out structure, and the second lead-out structure. (Refer to...) Figures 8-15 In other embodiments, the first ohmic contact structure 221 and the second ohmic contact structure 321 are strip-shaped. Optionally, the first ohmic contact structure 221 and the second ohmic contact structure 321 connected to at least one light-emitting unit are parallel to each other, and the light-emitting area of ​​the light-emitting unit 100 is formed between the first ohmic contact structure 221 and the second ohmic contact structure 321 connected to the light-emitting unit; the first ohmic contact structure 221 and the second ohmic contact structure 321 connected to different light-emitting units are located at different edges of the pixel unit.

[0066] Specifically, "strip" refers to a shape whose length-to-width ratio is greater than 1. A strip can be a straight strip with straight edges or an arc strip with curved edges. This embodiment of the invention does not impose any specific limitations on this.

[0067] by Figure 8 Taking a straight bar as an example, the first ohmic contact structure 221 can be parallel to the edge of the pixel unit, and the second ohmic contact structure 321 can be parallel to the edge of the pixel unit. The length of the first ohmic contact structure 221 can be less than the length of the edge of the pixel unit; the length of the second ohmic contact structure 321 can be less than the length of the edge of the pixel unit. In this way, it is ensured that the two ohmic contact structures at adjacent edges will not connect with each other, thus ensuring the yield and reliability of the pixel unit.

[0068] Optionally, the first ohmic contact structure 221 and the second ohmic contact structure 321 are strip-shaped. On the one hand, ensuring that the first ohmic contact structure 221 and the second ohmic contact structure 321 are positioned close to the edge of the pixel unit helps to increase the light-emitting area; on the other hand, the strip-shaped first ohmic contact structure 221 only occupies one edge of the pixel unit, and correspondingly, the strip-shaped second ohmic contact structure 321 also only occupies one edge of the pixel unit, making the total area occupied by the first ohmic contact structure 221 and the second ohmic contact structure 321 of each light-emitting unit relatively small, which helps to further increase the light-emitting area and improve the light-emitting effect.

[0069] refer to Figures 8-15 The pixel unit includes six strip-shaped ohmic contact structures, and the six annular ohmic contact structures include three first ohmic contact structures 221 and three second ohmic contact structures 321.

[0070] The first ohmic contact structure 221 is disposed in the first groove, and the second ohmic contact structure 321 is disposed in the second groove. The first ohmic contact structure 221 contacts the first semiconductor layer 101 at the bottom of the first groove, and the second ohmic contact structure 321 contacts the second semiconductor layer 103 at the bottom of the second groove. The first ohmic contact structure 221 and the second ohmic contact structure 321 extend upward into the first insulating layer 401 and are embedded in the first insulating layer 401 for subsequent in-chip metal interconnection. The first interconnect line 222 and the second interconnect line 322 can be located between the first insulating layer 401 and the second insulating layer 402. The first lead-out structure 210 and the second lead-out structure 310 can protrude from the surface of the second insulating layer 402 away from the first light-emitting unit 110.

[0071] Six strip-shaped ohmic contact structures are disposed near the six sides of the regular hexagonal pixel unit and contact the corresponding first semiconductor layer 101 or second semiconductor layer 103. Six strip-shaped grooves (including three first grooves and three second grooves) are located near the six sides of the regular hexagonal pixel unit, and their etched depth extends downwards to the first semiconductor layer 101 or second semiconductor layer 103 of the corresponding red, green, and blue light-emitting units 100. Five of the six strip-shaped ohmic contact structures contact the first semiconductor layer 101 or second semiconductor layer 103 at the bottom of the five strip-shaped grooves. The sidewalls of the five strip-shaped grooves are all covered by a passivation layer film. The remaining one of the six strip-shaped ohmic contact structures contacts the remaining side of the first semiconductor layer 101 on the surface of the first light-emitting unit 110 located in the regular hexagonal pixel unit. For each of the red, green, and blue light-emitting units, the corresponding first ohmic contact structure 221 and second ohmic contact structure 321 are respectively set on two parallel opposite sides of the regular hexagonal pixel unit (the area between the two parallel opposite sides is the light-emitting area of ​​the pixel unit) in order to maximize the use of the area of ​​the stacked light-emitting structures.

[0072] refer to Figure 4 , Figure 14 and Figure 15 Optionally, each edge of the pixel unit is provided with a first ohmic contact structure 221 or a second ohmic contact structure 321, and the distance between two ohmic contact structures at adjacent edges of the pixel unit is less than the length of the ohmic contact structure; wherein both ohmic contact structures at adjacent edges are first ohmic contact structures 221, or both are second ohmic contact structures 321, or one is a first ohmic contact structure 221 and the other is a second ohmic contact structure 321. This arrangement allows the first ohmic contact structures 221 and the second ohmic contact structures 321 to form a ring-like structure, concentrating the light-emitting area of ​​the stacked light-emitting structure within the area enclosed by the ring-like structure formed by the first ohmic contact structures 221 and the second ohmic contact structures 321, resulting in a larger effective light-emitting area. In addition, the distance between two ohmic contact structures at adjacent edges of a pixel unit is set to be less than the length of the ohmic contact structure, which makes the lengths of the first ohmic contact structure 221 and the second ohmic contact structure 321 longer. This results in a larger contact area between the first ohmic contact structure 221 and the first semiconductor layer 101, and a larger contact area between the second ohmic contact structure 321 and the second semiconductor layer 103, thereby reducing contact resistance and improving the light-emitting effect.

[0073] This invention also provides a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging. Figure 16This is a schematic diagram of the structure of a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging, provided by an embodiment of the present invention. Figure 17 This is a schematic diagram of the structure after the isolation channel is formed during the fabrication of a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging. Figure 18 yes Figure 17 The sectional view obtained by cutting along KK', see reference. Figures 16-18 The monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging includes a stress buffer layer 400 and an epitaxial structure disposed on one side of the stress buffer layer 400. Multiple closed isolation channels 503 are formed on the epitaxial structure, defining the pixel structure 502 of any embodiment of the present invention. The stress buffer layer 400 is grown on the surface of a substrate 501. The isolation channels 503 are filled with insulating material to form an insulating isolation layer 504.

[0074] The monolithically integrated full-color uLED microdisplay chip suitable for flip-chip packaging in this invention defines the pixel structure of any embodiment of the invention through multiple closed isolation channels on the epitaxial structure, possessing the beneficial effects of the pixel structure of any embodiment of the invention. Furthermore, by achieving wafer-level flip-chip packaging and vertical stacking of the red, green, and blue primary colors in the pixel unit through monolithic integration, light is emitted from the side of the stress buffer layer away from the epitaxial structure. Since the side of the epitaxial structure in the light-emitting chip away from the stress buffer layer is in contact with the active driver chip, rather than facing the ambient space, it helps to dissipate heat from the light-emitting chip.

[0075] In some embodiments, the isolation channel 503 extends from the surface of the epitaxial structure into the stress buffer layer 400, thereby ensuring that the isolation channel 503 can completely isolate adjacent pixel structures. The isolation channel 503 may be filled with an insulating material, such as silicon dioxide.

[0076] This invention also provides a method for fabricating a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging. Figure 19 This is a flowchart illustrating a method for fabricating a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging, as provided in an embodiment of the present invention. (Refer to...) Figure 19 The method for fabricating a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging includes: S10 provides a stress buffer layer.

[0077] Specifically, the stress buffer layer can be grown on the substrate. Optionally, the substrate is a sapphire substrate. In other embodiments of the present invention, the substrate can also be a substrate of other materials. The embodiments of the present invention are not specifically limited here.

[0078] S20. Blue luminescent units, green luminescent units, and red luminescent units are vertically grown on the stress buffer layer, as well as the spacer layers between the blue luminescent units and the green luminescent units, and between the green luminescent units and the red luminescent units, to form an epitaxial structure.

[0079] Optionally, the epitaxial layers for the blue, green, and red light-emitting units are tri-color GaN-based epitaxial layers, which are stacked to form a GaN composite epitaxial layer. Table 1 shows the structure, thickness, donor impurities, In composition ratio, and Al composition ratio of each layer of the substrate, stress buffer layer, and composite epitaxial layer. In Table 1, "Non" indicates no doping. The composite epitaxial layer is simplified to 11 layers (where the multi-quantum-well layer is considered as 1 layer). The blue light-emitting unit is first grown on a GaN-ON-Sapphire wafer, which has the following simplified structure: 1 layer doped with Si element (doping concentration approximately 1e). 18 to 1e 19 cm -3 One layer consists of an N-type GaN layer with a thickness of approximately 200 nm to 300 nm, used to provide electrons; one layer is a multi-quantum well structure composed of alternating InGaN / GaN layers with fewer than 5 quantum well pairs; and one layer is doped with Mg (doping concentration approximately 1e). 20 to 1e 21 cm -3 A GaN layer with a thickness of approximately 150 nm to 200 nm, serving as a P-type GaN layer, is used to provide holes. The InGaN quantum well, with an In composition of approximately 15% to 25% and a thickness of approximately 2 nm to 3 nm, is used to adjust the emission wavelength of the blue emitting unit. An undoped GaN layer, with a quantum barrier layer of approximately 10 nm to 15 nm thickness, is used to confine electrons and holes, promoting radiative recombination in the multiple quantum wells. As a low-power emitting unit, a few pairs of InGaN / GaN multiple quantum well layers are sufficient to achieve the brightness required for the microdisplay. Following this, an undoped AlGaN layer, with an Al composition of approximately 10% to 15%, with a thickness of only 20 nm to 30 nm, is grown on top of the P-type GaN layer on the surface of the blue emitting unit, serving as a spacer between the blue and green emitting unit epitaxial layers.

[0080] Next, the epitaxial layer forming the green light-emitting unit is grown on an undoped AlGaN spacer layer, as shown in Table 1. The epitaxial layer of the green light-emitting unit has the following epitaxial structure: a 1-layer Si-doped GaN layer (approximately 1e... 18 to 1e 19 cm -3 The first layer consists of an N-type GaN layer with a thickness of approximately 200 nm to 300 nm; a multi-quantum-well layer composed of several pairs of InGaN / GaN thin films stacked alternately; and a GaN layer doped with Mg (doping concentration approximately 1e).20 to 1e 21 cm -3 The InGaN layer in the multi-quantum well has an In content of approximately 25% to 35% and a thickness of approximately 2nm to 3nm, used to adjust the emission wavelength of the green emitting unit. The GaN quantum barrier layer has a thickness of approximately 10nm to 15nm and is used to confine electrons and holes within the quantum well. The number of InGaN / GaN pairs in the multi-quantum well is approximately 5 pairs or slightly less. Similarly, a single undoped AlGaN spacer layer with an Al content of approximately 10% to 15% and a thickness of approximately 20nm to 30nm is used to separate the green emitting unit from the red emitting unit.

[0081] Then, an epitaxial layer for forming red light-emitting units is grown on top of an undoped AlGaN spacer layer of the epitaxial layer for green light-emitting units. The epitaxial layer for red light-emitting units has the following epitaxial structure: a single Si-doped GaN layer (doping concentration approximately 1e). 18 to 1e 19 cm -3 The thickness is approximately 200 nm to 300 nm; one multi-quantum well layer, composed of several pairs of InGaN / AlInGaN thin films stacked alternately (approximately 5 pairs or fewer); one layer of doped Mg element (approximately 1e 20 to 1e 21 cm -3 The InGaN / GaN multi-quantum-well structure consists of a GaN layer with a thickness of approximately 150 nm to 200 nm. In the InGaN layer, the In content is approximately 35% to 45%, and the quantum well thickness is approximately 3 nm to 4 nm, used to adjust the emission wavelength of the InGaN / AlInGaN multi-quantum-well. The quantum barrier layer, AlInGaN, has an Al content of approximately 10% and an In content of approximately 3%, with slight variations in composition to adjust the lattice strain. The AlInGaN quantum barrier layer has a thickness of approximately 10 nm to 15 nm, used to confine electrons and holes and promote radiative recombination of electrons and holes within the quantum well. In each of the above epitaxial layers, the gradual variation of the In content in the quantum well layer and the selection of the quantum barrier layer material can adjust the lattice constant or strain of the quantum barrier layer; and by setting different In contents and thicknesses in the quantum well layers of the epitaxial layers for blue, green, and red emitting units (see Table 1 below), the color of the emitted light can be adjusted.

[0082] Table 1 S30, shallow trench etching epitaxial structure, defines pixel units.

[0083] Specifically, isolation channels can be formed after the epitaxial structure has grown, through patterning processes such as etching. Using shallow-channel isolation technology, common in integrated circuits, each pixel structure is isolated, further reducing the pixel pitch. Closed isolation channels are formed by etching the epitaxial structure using shallow channels, defining the pixel unit. The isolation channels can extend from the surface of the epitaxial structure into the stress buffer layer. The side length of a regular hexagonal pixel structure is approximately 5μm to 50μm. The width of the isolation channel is approximately 1μm to 3μm, used to isolate each pixel structure.

[0084] S40. An insulating dielectric layer is covered on the surface of the pixel unit, and a metal interconnect rewiring and lead-out structure are fabricated on the insulating dielectric layer.

[0085] Optionally, an insulating dielectric layer can be deposited on the surface of the pixel unit using PECVD or LPCVD processes. Metal interconnect redistribution lines can be fabricated within the insulating dielectric layer to embed them within it. Lead-out structures can be formed by patterning vias in the insulating dielectric layer, filling the vias with conductive material, and ensuring that the lead-out structures protrude from the insulating dielectric layer to facilitate connection between the lead-out structures and external driving circuitry.

[0086] The method for fabricating a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging according to embodiments of the present invention is used to prepare a monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging according to any embodiment of the present invention. It has the beneficial effects of the monolithic integrated full-color uLED microdisplay chip suitable for flip-chip packaging according to any embodiment of the present invention, which will not be repeated here.

[0087] The blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit all include a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked together. Figure 20 This is a flowchart of covering the surface of a pixel unit with an insulating dielectric layer, see reference. Figure 20 In some embodiments, covering the surface of the pixel unit with an insulating dielectric layer includes: S41. Cover the surface of the pixel unit with a first insulating dielectric layer.

[0088] The thickness of the first insulating dielectric layer is 1 μm to 2 μm, and the first insulating dielectric is deposited on the surface of the pixel unit. Optionally, PECVD or LPCVD technology can be used to deposit the first insulating dielectric layer.

[0089] S42. Starting from the first insulating dielectric layer, three first grooves and three second grooves are etched vertically in sequence. The three first grooves are etched and stop at the first semiconductor layer of the red light-emitting unit, the green light-emitting unit and the blue light-emitting unit, respectively. The three second grooves are etched and stop at the second semiconductor layer of the red light-emitting unit, the green light-emitting unit and the blue light-emitting unit, respectively.

[0090] For example, an annular or strip-shaped window is formed on the first insulating dielectric layer as a first groove corresponding to the red light-emitting unit, to expose the P-type GaN layer on the surface of the red light-emitting unit. Optionally, the ICP-RIE etching of the first insulating dielectric layer can use a fluorine-based precursor gas, such as CF4 and H2, or CHF3. Appropriately adjusting the gas ratio to achieve a relatively high selectivity allows the etching to stop smoothly on the surface of the GaN epitaxial layer.

[0091] The first insulating dielectric layer, or the photoresist thereon, can be used as a mask to further etch the P-type GaN layer (approximately 150 nm to 200 nm thick) and the InGaN / AlInGaN MQWs layer (approximately 65 nm to 100 nm thick in this example, with a maximum of 5 MQW pairs) of the red light-emitting unit, resulting in a second groove corresponding to the red light-emitting unit, which exposes the N-type GaN layer to fabricate an N-type ohmic contact. The window width on the first insulating dielectric layer and the trench width in the GaN epitaxial layer can be set between 0.5 μm and 2 μm. The diameter of the annular trench or the length of the strip trench can be adjusted according to the size of the pixel unit to ensure that each pixel has the maximum light-emitting area. The precursor gas for etching the GaN material in ICP-RIE can be a chlorine-based gas, such as BCl3, Cl2, or Ar. By appropriately adjusting the proportion of each gas and the RF power of the ICP-RIE device, the etching rate of InGaN and AlInGaN thin film materials with different compositions can be distinguished. In order to select a better etching ratio, ensure that the etching can be accurately stopped on the N-type GaN layer, and avoid insufficient or excessive etching.

[0092] Similar to the fabrication steps of the first and second trenches corresponding to the red emitting unit described above, the same method can be used to etch other annular or strip-shaped shallow trenches. The P-type GaN layer, MQW, N-type GaN layer, and AlGaN spacer layer on the red emitting unit are etched away, stopping at the P-type GaN layer of the green emitting unit, forming the first trench corresponding to the green emitting unit. In general, a GaN-based thin film material with a thickness of approximately 650 nm to 930 nm is etched away to form a shallow trench (first trench), exposing the P-type GaN layer on the surface of the green emitting unit. The GaN-based thin film material with a thickness of approximately 855 nm to 1215 nm is etched away to expose the N-type GaN layer of the green emitting unit, forming the second trench corresponding to the green emitting unit. The GaN-based thin film material with a thickness of approximately 1085 nm to 1545 nm is etched away to form a shallow trench (first trench), exposing the P-type GaN layer on the surface of the blue emitting unit. The GaN-based thin film material with a thickness of approximately 1295nm to 1855nm is etched away to expose the N-type GaN layer of the blue light-emitting unit, forming the second groove corresponding to the blue light-emitting unit.

[0093] By patterning the first insulating dielectric layer and the pixel unit, a first groove and a second groove are formed. In subsequent steps, a first ohmic contact structure is formed in the first groove, and a second ohmic contact structure is formed in the second groove. This ensures that the first ohmic contact structure and the second ohmic contact structure are not exposed to the external environment, which helps to improve the reliability of the light-emitting chip.

[0094] S43. A third insulating dielectric layer is formed on the sidewall of each first groove and each second groove, and the bottom of the third insulating dielectric layer exposes the first semiconductor layer or the second semiconductor layer.

[0095] After step S42, the mesa of all red, green, and blue light-emitting units has been formed, exposing the N-type or P-type GaN corresponding to each light-emitting unit. Therefore, the sidewalls of the epitaxial layer of each light-emitting unit exposed in the first and second trenches are then passivated. Using ALD technology, a third insulating dielectric layer is deposited, such as an ultrathin SiO2 film, optionally with a thickness between 5 nm and 10 nm, to cover the sidewalls of the shallow trenches and the surface of the epitaxial layer. Similarly, TEOS and O3, or BDEAS and H2O, can be selected as the precursor gases for depositing the ultrathin SiO2 layer.

[0096] Next, using photolithography and ICP-RIE vertical etching techniques, the ultrathin SiO2 covering the bottom of each shallow trench is etched away to expose the N-type GaN and P-type GaN layers of each light-emitting unit. Adjustments to the component ratios in the fluorine-based precursor gas used in dry etching, as well as adjustments to the RF power, are made to optimize the vertical etching process, ensuring that the ultrathin SiO2 layer at the bottom of the shallow trench can be successfully etched away while preventing damage to the SiO2 layer covering the sidewalls of the shallow trench.

[0097] Since the P-type GaN layer of the red emitting unit is the outermost layer of this monolithically vertically integrated tri-color emitting unit epitaxial structure, it can be exposed last. Similarly, a circular window with a diameter of approximately 3 μm to 5 μm is opened in the SiO2 passivation layer on the surface to expose the P-type GaN layer of the covered red emitting unit.

[0098] In other designs, the P-type ohmic contacts of the red light-emitting units are also designed as stripes adjacent to the edges of the regular hexagonal pixels. Therefore, the shape of the etched first insulating layer also needs to be strip-shaped and adjacent to one side of the regular hexagonal pixel unit.

[0099] Furthermore, in order to ensure that the red light emitted towards the red epitaxial layer, as well as a small amount of green and blue light that is not completely absorbed by the red epitaxial material, can be reflected back into the epitaxial layer and emitted in the opposite direction from the blue epitaxial layer and the HVPE-GaN layer, a reflector can be placed on the surface of the P-type GaN layer of the red light-emitting unit. For example, by appropriately increasing the area of ​​the circular P-type ohmic contact of the red light-emitting unit, the P-type ohmic contact can also function as a metal reflector.

[0100] S44. Fill the first groove with metal material to form a first ohmic contact structure, and fill the second groove with metal material to form a second ohmic contact structure.

[0101] In some embodiments, the P-type ohmic contact (e.g., as a first ohmic contact structure) and N-type ohmic contact (e.g., as a second ohmic contact structure) of each light-emitting unit are fabricated separately. The method involves first depositing the required metal thin film using PVD, followed by wet or dry etching to remove the metal thin film outside the bottom of the shallow trench, and then annealing and metallizing to form the ohmic contact. The P-type ohmic contact metal of the P-type GaN layer can be Ni / Au / Ni / Cu, and the N-type ohmic contact metal of the N-type GaN layer can be Ti / Al / Ti / Cu. The thickness of the metal layers for both types of ohmic contacts is approximately 100 nm to 200 nm, and the Cu layer on their surface can serve as a seed layer for subsequent electroplating processes. Annealing is performed under vacuum or N2 environment at 500 to 800 degrees Celsius for approximately 30 minutes to 1 hour to complete the metallization and form the ohmic contact.

[0102] In other embodiments, to simplify the process, the N-type and P-type ohmic contacts can use the same metal Al, supplemented by other metal layers such as TiCu. Therefore, the N-type and P-type metal layers can be deposited in a single PVD process, without the need for two steps.

[0103] Subsequently, Cu metal is electroplated into the first and second grooves to fill the trenches embedded in the first insulating dielectric layer. The thickness of the Cu layer is approximately 1 μm to 2 μm. The electroplating solution for Cu can be CuSiO4*5H2O, H2SiO4, and corresponding additives such as SPS, PEG, and JCB to ensure that the electroplated metal deposition process extends from the bottom of the trench upwards at an appropriate rate until the entire trench is filled, avoiding gaps left during the metal deposition process.

[0104] Figure 21 This is a flowchart illustrating the fabrication of metallic interconnect rewiring and lead-out structures within an insulating dielectric layer. (Refer to...) Figure 21 In some embodiments, fabricating metal interconnect rewiring and lead-out structures in an insulating dielectric layer includes: S45. A first metal lead-out layer, three second metal lead-out layers, three first interconnect lines, and three second interconnect lines are prepared on the surface of the first insulating dielectric layer away from the epitaxial structure. The three first interconnect lines are connected to three first ohmic contact structures respectively, the three second interconnect lines are connected to three second ohmic contact structures respectively, a first metal lead-out layer is connected to the three first interconnect lines, and the three second metal lead-out layers are connected to the three second interconnect lines respectively.

[0105] During the formation of the first and second ohmic contact structures, if the metal material of the first and second ohmic contact structures overflows from the first and second grooves, before step S45, the first insulating dielectric layer and the metal Cu embedded in the first insulating layer can be planarized to ensure that the surface of the metal Cu and the surface of the first insulating dielectric layer are flush. The thickness of the first insulating dielectric layer after thinning is approximately 900 nm to 1.9 μm, and the RMS roughness of the surface of the first insulating dielectric layer is maintained at RMS ≤ 1 nm.

[0106] S45 includes depositing a TiCu metal layer with a thickness of approximately 200 nm to 300 nm on the surface of the first insulating dielectric layer. The CuTi metal thin film is etched to form a first metal lead-out layer, three second metal lead-out layers, three first interconnect lines, and three second interconnect lines. In subsequent steps, the first lead-out structure may be formed on the first metal lead-out layer, and the second lead-out structure may be formed on the second metal lead-out layer.

[0107] S46. Cover the surfaces of the first metal lead-out layer, the second metal lead-out layer, the first interconnect, the second interconnect and the first insulating dielectric layer with a second insulating dielectric layer.

[0108] Specifically, a second insulating dielectric layer with a thickness of approximately 2 μm can be deposited using PECVD or LPCVD processes to cover the first metal lead layer, the second metal lead layer, the first interconnect, the second interconnect, and the first insulating dielectric layer. In some embodiments, after depositing the second insulating dielectric layer, the newly deposited second insulating dielectric layer is planarized, reducing its thickness by approximately 300 nm, thereby achieving surface planarization of the second insulating dielectric layer (RMS ≤ 1 nm).

[0109] S47. A window is opened at the position of the second insulating dielectric layer corresponding to the first metal lead-out layer and the second metal lead-out layer, and the window exposes the corresponding first metal lead-out layer and the second metal lead-out layer.

[0110] Optionally, four windows are etched on the surface of the second insulating dielectric layer to expose the first metal lead-out layer and three second metal lead-out layers, respectively. For example, the windows are circular in shape. The first ohmic contact structure, the second ohmic contact structure, the first interconnect line, and the second interconnect line all cover the underside of the second insulating dielectric layer.

[0111] S48. Fill the window with conductive material to form a first lead-out structure on the first metal lead-out layer and a second lead-out structure on the second metal lead-out layer.

[0112] Optionally, Cu metal is electroplated into four windows to fill the windows of the second insulating dielectric layer, forming Cu micropillars. The height of the Cu micropillars is approximately 2 μm.

[0113] In some embodiments, after filling the window with conductive material, the process includes etching a portion of a second insulating dielectric layer to expose a first lead-out structure and a second lead-out structure.

[0114] By etching a portion of the second insulating dielectric layer, the first and second lead structures are exposed. The four Cu micropillars are ensured to protrude slightly above the second insulating dielectric layer, with the protrusions approximately 50 nm high or slightly below 50 nm, forming the microbumps of the flip-chip package, i.e., the first and second lead structures.

[0115] In this process, the light-emitting chip can be flip-chip bonded to the CMOS active driver chip to achieve high-density vertical interconnects. The interconnect density is determined by the density of microbumps, i.e., the size and spacing of the microbumps, and the pixel density of the associated pixel units. The flip-chip bonding method can be thermo-press bonding based on hybrid bonding, where the first and second lead structures are Cu-Cu interconnected with the exposed Cu on the surface of the CMOS active driver chip, and the second insulating dielectric layer on the surface of the light-emitting chip is SiO2-SiO2 bonded to the dielectric layer on the surface of the CMOS active driver chip. Alternatively, the thickness of the second insulating dielectric layer (approximately 2 μm) and the height of the embedded microcopper pillars (approximately 3–4 μm) can be slightly increased, and the height of the microcopper pillars is made higher than the surface of the second insulating dielectric layer. The surface of the microcopper pillars is covered with a 500 nm–1 μm thick SnAg cap layer as a solder joint. Furthermore, In or Ni micropillars can be used to achieve even higher density and smaller size connections.

[0116] After completing the flip-chip packaging of the monolithically integrated full-color wafer and CMOS active driver chip, the sapphire substrate is laser-removed, leaving a gallium nitride stress buffer layer. Light emitted from the pixel structure exits from one end of the stress buffer layer. Because one side of the epitaxial layer of the light-emitting chip is in contact with the CMOS active driver chip, rather than facing the ambient space, it aids in heat dissipation.

[0117] In some embodiments, prior to forming the epitaxial structure, the method further includes: growing a stress buffer layer on a sapphire substrate by lateral epitaxy using a hydride vapor phase epitaxy process, wherein the stress buffer layer is an undoped first gallium nitride layer.

[0118] Specifically, using HVPE lateral epitaxy to grow GaN layers can reduce dislocations caused by lattice mismatch between the GaN layer and the sapphire substrate surface.

[0119] In some embodiments, to further improve crystal quality, before using hydride vapor phase epitaxy to grow a stress buffer layer on a sapphire substrate via lateral epitaxial growth, the method further includes: depositing a silicon nitride thin film on the sapphire substrate and patterning it to form a periodic structure; the thickness of the silicon nitride thin film is less than the thickness of the stress buffer layer. Patterning the SiN thin film on the sapphire substrate induces lateral epitaxial growth of the GaN thin film, reducing dislocation density.

[0120] In other embodiments, before growing a stress buffer layer on a sapphire substrate using hydride vapor phase epitaxy, the method further includes: growing a second gallium nitride layer on the sapphire substrate using an organic compound chemical vapor deposition process, and roughening the surface of the second gallium nitride layer using ion bombardment or wet etching; the thickness of the second gallium nitride layer is less than the thickness of the stress buffer layer.

[0121] Specifically, an undoped GaN thin layer (500 nm to 1 μm) can be pre-grown on a sapphire substrate at a low temperature (approximately 500–600 °C) using metal-organic chemical vapor deposition (MOCVD). The surface is then roughened using a chemical solution or dry etching. Lateral growth of an HVPEGaN epitaxial layer is then induced on the roughened surface of the GaN thin layer, helping to reduce the dislocation density in the thick GaN layer. The epitaxial structure grows on the surface of the stress buffer layer, releasing stress caused by lattice mismatch and preventing dislocation diffusion into the epitaxial structure.

[0122] In summary, HVPE can be used to grow thick GaN layers on sapphire substrates. Furthermore, roughened MOCVD GaN surfaces or patterned SiN layers can be used to promote lateral epitaxial growth, thereby reducing the dislocation density in thick GaN films.

[0123] In some embodiments, S30 shallow trench etching of the epitaxial structure to define pixel units includes: etching the epitaxial structure using an inductively coupled plasma reactive ion etching process to form an isolation channel; forming a sidewall passivation layer on the sidewall of the isolation channel using an atomic layer deposition process to passivate the sidewall of the epitaxial structure; filling the isolation channel with silicon oxide using a plasma-enhanced chemical vapor deposition process or a low-pressure chemical vapor deposition process to completely fill the isolation channel; and removing the silicon oxide overflowing from the isolation channel using a planarization process to planarize the surface of the epitaxial structure.

[0124] Optionally, inductively coupled plasma reactive ion etching (ICP-RIE) and chlorine-based precursor gas are used to etch the epitaxial structure, stopping at the surface of the stress buffer layer or inside the stress buffer layer. That is, the isolation channel extends from the surface of the epitaxial structure into the stress buffer layer, resulting in an isolation channel with a depth of about 2 μm or slightly greater than 2 μm, forming an isolation channel surrounding the pixel structure.

[0125] The sidewall passivation of the epitaxial structure is achieved using atomic layer deposition (ALD) technology. An ultrathin SiO2 layer with a thickness of approximately 5 nm to 10 nm is deposited in the isolation channel, covering the sidewalls of the epitaxial layer and the bottom of the isolation channel. BDEAS and H2O, or optionally TEOS and O3, can be used as precursor gases for the ALD deposition film. Filling the entire isolation channel requires ion-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). Optionally, TEOS / O3 is used as the precursor gas to deposit the SiO2 insulating layer in the channel at a low rate to avoid voids during the filling process. Subsequently, a planarization process is used to remove the silicon oxide overflowing from the isolation channel, planarizing the surface of the epitaxial structure. The subsequent insulating dielectric layer is formed on the planar surface of the epitaxial structure.

[0126] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and no limitation is imposed herein.

[0127] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A vertically stacked uLED pixel structure, characterized in that, In order, they include: Stress buffer layer; A pixel unit, the structure of which includes: a blue light-emitting unit, a green light-emitting unit and a red light-emitting unit stacked vertically in sequence on the stress buffer layer, wherein a spacer layer is provided between the blue light-emitting unit and the green light-emitting unit, and between the green light-emitting unit and the red light-emitting unit; An insulating dielectric layer is disposed on the surface of the red light-emitting unit; Metal interconnect rewires are embedded in the insulating dielectric layer and are electrically connected to the blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit. The lead-out structure is electrically connected to the metal interconnect rewire and extends from the side of the insulating dielectric layer away from the red light-emitting unit.

2. The vertically stacked uLED pixel structure of claim 1, wherein, The blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit each include a first semiconductor layer, a light-emitting layer, and a second semiconductor layer that are vertically stacked. The pixel structure further includes three first ohmic contact structures and three second ohmic contact structures, all of which are vertically disposed on the blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit. The three first ohmic contact structures are electrically connected to the first semiconductor layer of each of the blue, green, and red light-emitting units. The three second ohmic contact structures are also electrically connected to the first semiconductor layer of each of the blue, green, and red light-emitting units. All three first ohmic contact structures and all three second ohmic contact structures extend into the insulating dielectric layer.

3. The vertically stacked uLED pixel structure of claim 2, wherein, The metal interconnect rewiring includes three first interconnect lines and three second interconnect lines; the three first interconnect lines are electrically connected to the three first ohmic contact structures one-to-one, and the three second interconnect lines are electrically connected to the three second ohmic contact structures one-to-one.

4. The vertically stacked uLED pixel structure of claim 3, wherein, The lead-out structure includes a first lead-out structure and three second lead-out structures; the first lead-out structure is electrically connected to all three first interconnect lines, and the three second lead-out structures are electrically connected to the three second interconnect lines one-to-one.

5. The vertically stacked uLED pixel structure of claim 4, wherein, The insulating dielectric layer includes a first insulating dielectric layer and a second insulating dielectric layer, with the first insulating dielectric layer located between the red light-emitting unit and the second insulating dielectric layer; The first interconnect line, the second interconnect line, the first lead-out structure, and the three second lead-out structures are disposed on the first insulating dielectric layer; The second insulating dielectric layer covers the first interconnect, the second interconnect, the first lead structure, the three second lead structures, and the first insulating dielectric layer, and the free ends of the first lead structure and the three second lead structures are exposed from the surface of the second insulating dielectric layer away from the first insulating dielectric layer.

6. The vertically stacked uLED pixel structure of claim 5, wherein, It also includes a metal reflector, which is located between the first insulating dielectric layer and the second insulating dielectric layer, and is isolated and insulated from the metal interconnect rewiring, the lead-out structure, the first ohmic contact structure and the second ohmic contact structure; The orthographic projection of the reflector onto the insulating dielectric layer overlaps with the orthographic projection of the light-emitting area of ​​the pixel unit onto the insulating dielectric layer.

7. The vertically stacked uLED pixel structure of claim 2, wherein, The first ohmic contact structure and the second ohmic contact structure are in the form of a ring or a strip.

8. The vertically stacked uLED pixel structure of claim 1, wherein, The stress buffer layer is an undoped gallium nitride layer, and / or, The spacer layer is undoped AlGaN.

9. A monolithic integrated full-color uLED micro-display chip suitable for flip-chip packaging, characterized in that, It includes a stress buffer layer and an epitaxial structure disposed on one side of the stress buffer layer, wherein the epitaxial structure is provided with a plurality of closed isolation channels, and the isolation channels define the pixel structure according to any one of claims 1-8.

10. The monolithic integrated full-color uLED micro-display chip suitable for flip-chip packaging according to claim 9, wherein, The isolation channel extends from the surface of the epitaxial structure into the stress buffer layer.

11. A method for manufacturing a monolithic integrated full-color uLED micro-display chip suitable for flip-chip packaging, characterized in that, include: Provide a stress buffer layer; Blue light-emitting units, green light-emitting units, and red light-emitting units are vertically grown on a stress buffer layer, as well as spacer layers between the blue light-emitting units and the green light-emitting units, and between the green light-emitting units and the red light-emitting units, to form an epitaxial structure; Shallow trench etching is used to etch the epitaxial structure to define pixel units; An insulating dielectric layer is covered on the surface of the pixel unit, and a metal interconnect rewiring and lead-out structure are fabricated on the insulating dielectric layer.

12. The method of claim 11, wherein the method further comprises: The blue light-emitting unit, the green light-emitting unit, and the red light-emitting unit each include a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked together. The method of covering the surface of the pixel unit with an insulating dielectric layer includes: A first insulating dielectric layer is covered on the surface of the pixel unit; Starting from the first insulating dielectric layer, three first grooves and three second grooves are etched vertically in sequence. The three first grooves are etched to stop at the first semiconductor layer of the red light-emitting unit, the green light-emitting unit and the blue light-emitting unit, respectively. The three second grooves are etched to stop at the second semiconductor layer of the red light-emitting unit, the green light-emitting unit and the blue light-emitting unit, respectively. A third insulating dielectric layer is formed on the sidewall of each of the first grooves and each of the second grooves, and the bottom of the third insulating dielectric layer exposes the first semiconductor layer or the second semiconductor layer. A first ohmic contact structure is formed by filling the first groove with metal material, and a second ohmic contact structure is formed by filling the second groove with metal material.

13. The method of claim 12, wherein the method further comprises: The fabrication of the metal interconnect rewiring and lead-out structure in the insulating dielectric layer includes: A first metal lead-out layer, three second metal lead-out layers, three first interconnect lines, and three second interconnect lines are prepared on the surface of the first insulating dielectric layer away from the epitaxial structure. The three first interconnect lines are respectively connected to three first ohmic contact structures, the three second interconnect lines are respectively connected to three second ohmic contact structures, a first metal lead-out layer is connected to the three first interconnect lines, and the three second metal lead-out layers are respectively connected to the three second interconnect lines. A second insulating dielectric layer is covered on the surfaces of the first metal lead-out layer, the second metal lead-out layer, the first interconnect line, the second interconnect line, and the first insulating dielectric layer; a window is opened in the second insulating dielectric layer at a position corresponding to the first metal lead-out layer and the second metal lead-out layer, and the window exposes the corresponding first metal lead-out layer and the second metal lead-out layer; The window is filled with conductive material, a first lead-out structure is formed on the first metal lead-out layer, and a second lead-out structure is formed on the second metal lead-out layer.

14. The method of claim 13, wherein the method further comprises: After filling the window with conductive material, the process includes: The second insulating dielectric layer of a certain thickness is etched to expose the first lead structure and the second lead structure.

15. The method of claim 11, wherein the method further comprises: Before forming the epitaxial structure, the method further includes: A stress buffer layer, which is an undoped first gallium nitride layer, is grown laterally on a sapphire substrate using hydride vapor phase epitaxy.

16. The method of claim 15, wherein the method further comprises: Prior to the lateral epitaxial growth of a stress buffer layer on a sapphire substrate using hydride vapor phase epitaxy, the method further includes: A silicon nitride thin film is deposited on the sapphire substrate and patterned to form a periodic structure; the thickness of the silicon nitride thin film is less than the thickness of the stress buffer layer; Alternatively, a second gallium nitride layer is grown on a sapphire substrate using an organic chemical vapor deposition process, and the surface of the second gallium nitride layer is roughened using ion bombardment or wet etching; the thickness of the second gallium nitride layer is less than the thickness of the stress buffer layer.

17. The method of claim 11, wherein the method further comprises: The shallow trench etches the epitaxial structure to define pixel units, including: The epitaxial structure was etched using inductively coupled plasma reactive ion etching (ICP-IR) to form an isolation channel. A sidewall passivation layer is formed on the sidewall of the isolation channel using an atomic layer deposition process to passivate the sidewall of the epitaxial structure. Using plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition, silicon oxide is filled into the isolation trench to completely fill the isolation trench. A planarization process is used to remove the silicon oxide overflowing from the isolation channel, thereby planarizing the surface of the epitaxial structure.

18. The method of claim 11, wherein the method further comprises: The spacer layer is undoped AlGaN.

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