A semiconductor package structure and a method of manufacturing the same

Abstract

This invention provides a semiconductor packaging structure and its fabrication method. The fabrication method includes the following steps: providing a packaging substrate, the packaging substrate including a first surface and a second surface disposed opposite to each other; providing at least one chip, each chip having metal bumps on its active surface; bonding the active surface of the chip to the first surface of the packaging substrate; providing at least one heat dissipation silicon sheet; and attaching each heat dissipation silicon sheet to the side of each chip away from the packaging substrate to form a molding compound structure. The molding compound structure includes a first molding compound layer and a second molding compound layer with different coefficients of thermal expansion. The first molding compound layer fills the gap between the chip and the packaging substrate, and the second molding compound layer is located on the packaging substrate, encapsulating the first molding compound layer, the chip, and the heat dissipation silicon sheet, exposing the side of the heat dissipation silicon sheet away from the chip. The semiconductor packaging structure fabrication method of this invention can achieve both high heat dissipation performance and high reliability of the packaging structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and relates to a semiconductor packaging structure and its preparation method. Background Technology

[0002] As the core functional component of various electronic devices, the chip packaging process not only plays a crucial role in achieving electrical interconnection with external circuits, but also provides physical protection and heat dissipation control for the chip itself. Packaging performance directly affects the chip's operational stability and lifespan.

[0003] Among existing chip packaging technologies, FCCSP (Flip Chip Scale Package) is widely used. To improve its heat dissipation performance, resin encapsulation or the addition of a metal heat sink is commonly used. However, both of these solutions have significant technical drawbacks and are difficult to meet the application requirements of high-performance chips. Resin encapsulation, due to the low thermal conductivity of resin materials, has poor heat dissipation efficiency and cannot meet the heat dissipation requirements of high thermal design power (TDP) chips. Metal heat sink solutions face two major technical challenges: firstly, controlling the thickness of the metal heat sink is difficult, making it hard to flexibly adjust and adapt to the TDP of different chips; secondly, the significant difference in thermal expansion coefficients between the metal and the chip easily generates thermal stress during high-temperature packaging processes or actual use, leading to reliability issues such as warping and cracking of the package. Furthermore, some FCCSP packaging structures use direct heat dissipation by exposing the top of the chip. While this method can improve heat dissipation to some extent, when the chip is thick or subjected to external forces, the top of the chip is easily damaged and cracked, further affecting package reliability. In summary, existing FCCSP packaging technology is severely limited in the application scenarios of high thermal design power chips, making it difficult to simultaneously achieve high heat dissipation performance and packaging structure reliability, and failing to meet the chip packaging requirements of electronic devices moving towards high performance and miniaturization.

[0004] Therefore, how to provide a semiconductor packaging structure and its fabrication method that can improve the heat dissipation performance and reliability of the packaging structure, and is also suitable for large-scale mass production, has become an important problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor packaging structure and its preparation method, which solves the problems of insufficient heat dissipation performance, high thermal stress and high production cost of the packaging structure in the prior art, and makes it difficult to achieve both high heat dissipation performance and high packaging structure reliability.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor packaging structure, comprising the following steps:

[0008] A packaging substrate is provided, the packaging substrate including a first surface and a second surface disposed opposite to each other;

[0009] At least one chip is provided, and the active surface of each chip is provided with metal bumps;

[0010] The active surface of the chip is bonded to the first surface of the packaging substrate;

[0011] At least one heat dissipation silicon sheet is provided, and each of the heat dissipation silicon sheets is attached to the side of each chip away from the packaging substrate.

[0012] A molding compound structure is formed, the molding compound structure including a first molding compound layer and a second molding compound layer with different coefficients of thermal expansion. The first molding compound layer fills the gap between the chip and the packaging substrate. The second molding compound layer is located on the packaging substrate and wraps the first packaging compound layer, the chip and the heat dissipation silicon wafer, exposing the side of the heat dissipation silicon wafer away from the chip.

[0013] Optionally, before attaching the heat-dissipating silicon sheet to the side of the chip away from the packaging substrate, the method further includes forming a first thermally conductive adhesive layer on the side of the chip away from the packaging substrate.

[0014] Optionally, the thermal conductivity of the first thermally conductive adhesive layer is greater than 6 W / (m·K).

[0015] Optionally, forming the heat-dissipating silicon sheet includes the following steps:

[0016] Provide a silicon wafer;

[0017] The silicon wafer is ground and cut to obtain the heat dissipation silicon sheet with a preset thickness and preset size.

[0018] Optionally, the coefficient of thermal expansion of the heat dissipation silicon sheet is similar to or the same as that of the chip.

[0019] Optionally, the orthographic projection of the heat dissipation silicon sheet on the packaging substrate is located within the orthographic projection of the chip on the packaging substrate.

[0020] Optionally, the sidewall of the heat dissipation silicon sheet is aligned with the sidewall of the chip.

[0021] Optionally, the horizontal plane of the upper surface of the heat dissipation silicon wafer is not lower than the horizontal plane of the upper surface of the second molding compound layer.

[0022] The present invention also provides a semiconductor packaging structure, comprising:

[0023] A packaging substrate, the packaging substrate including a first surface and a second surface disposed opposite to each other;

[0024] At least one chip, each of which has metal bumps on its active surface, and the active surface of the chip is bonded to a first surface of the packaging substrate;

[0025] At least one heat dissipation silicon sheet, each of the heat dissipation silicon sheets being attached to the side of each chip away from the packaging substrate;

[0026] A molding compound structure includes a first molding compound layer and a second molding compound layer with different coefficients of thermal expansion. The first molding compound layer fills the gap between the chip and the packaging substrate. The second molding compound layer is located on the packaging substrate and encapsulates the first packaging compound layer, the chip, and the heat dissipation silicon wafer, exposing the side of the heat dissipation silicon wafer away from the chip.

[0027] Optionally, it may also include a first thermally conductive adhesive layer, which is located between the chip and the heat dissipation silicon wafer.

[0028] As described above, the method for fabricating a semiconductor packaging structure according to the present invention includes the following steps: providing a packaging substrate, the packaging substrate including a first surface and a second surface disposed opposite to each other; providing at least one chip, each chip having metal bumps on its active surface; bonding the active surface of the chip to the first surface of the packaging substrate; providing at least one heat dissipation silicon sheet; and attaching each heat dissipation silicon sheet to the side of each chip away from the packaging substrate to form a molding compound structure. The molding compound structure includes a first molding compound layer and a second molding compound layer with different coefficients of thermal expansion. The first molding compound layer fills the gap between the chip and the packaging substrate, and the second molding compound layer is located on the packaging substrate, and the second molding compound layer encapsulates the first packaging compound layer, the chip, and the heat dissipation silicon sheet, exposing the side of the heat dissipation silicon sheet away from the chip. The method for fabricating a semiconductor packaging structure according to the present invention has the following beneficial effects:

[0029] 1. By incorporating a heat dissipation silicon wafer into the packaging structure, the overall heat dissipation efficiency of the packaging structure is significantly improved. Compared with the existing direct encapsulation method using plastic, the design using a heat dissipation silicon wafer effectively avoids the bottleneck problem of heat conduction by the plastic encapsulation material layer, ensuring that the heat generated by the chip can be quickly and efficiently transferred to the heat dissipation silicon wafer, effectively reducing defects such as poor temperature distribution uniformity of the packaging structure.

[0030] 2. The thickness of the heat dissipation silicon wafer can be adjusted through a grinding process to adapt to different packaging requirements. Its coefficient of thermal expansion is similar to that of the chip, which reduces thermal mismatch stress and can effectively solve the problem of packaging cracks or warping caused by thermal expansion mismatch, thereby improving the stability and reliability of the packaging structure.

[0031] 3. The molding compound structure effectively mitigates packaging stress and reduces stress concentration caused by uneven thermal expansion by setting molding compound layers with different coefficients of thermal expansion in the gap between the chip and the packaging substrate and on the sidewalls of the chip and the heat sink. This further improves the mechanical strength and durability of the packaging structure.

[0032] 4. The packaging structure using heat dissipation silicon wafers has a simple process and is easy to mass-produce, which can significantly reduce the production cost of the packaging structure. At the same time, it improves process compatibility and design flexibility, making the packaging structure suitable for packaging various chip types. The size and position of the heat dissipation silicon wafer can be flexibly adjusted according to actual needs to meet the packaging requirements of different application scenarios.

[0033] 5. By exposing the top of the heat dissipation silicon wafer, not only is the heat dissipation efficiency improved, but the problem of the heat dissipation silicon wafer not working properly caused by the existing metal heat sink being wrapped in the plastic encapsulation material layer is also effectively avoided. Attached Figure Description

[0034] Figure 1 The diagram shown is a schematic of a packaging structure.

[0035] Figure 2 The diagram shown illustrates another type of packaging structure.

[0036] Figure 3 This is a schematic diagram of yet another packaging structure.

[0037] Figure 4 The diagram shows a process flow chart of the method for fabricating the semiconductor packaging structure of the present invention.

[0038] Figure 5 The diagram shows a schematic of the packaging substrate in the method for preparing the semiconductor packaging structure of the present invention.

[0039] Figure 6 The diagram shown is a schematic representation of the chip structure in the semiconductor packaging structure fabrication method of the present invention.

[0040] Figure 7 The diagram shown is a schematic of the structure obtained after bonding the chip to the packaging substrate in the semiconductor packaging structure preparation method of the present invention.

[0041] Figure 8 The diagram shown is a schematic of the structure obtained after the heat dissipation silicon sheet is attached to the chip in the semiconductor packaging structure preparation method of the present invention.

[0042] Figure 9 The diagram shown is a schematic diagram of the structure obtained after forming a plastic encapsulation structure in the semiconductor packaging structure preparation method of the present invention.

[0043] Figure 10 The diagram shown is another schematic diagram of the semiconductor packaging structure of the present invention.

[0044] Figure 11 The diagram shown is another schematic representation of the semiconductor packaging structure of the present invention.

[0045] Figure 12 The diagram shown represents another possible structure of the semiconductor packaging structure of the present invention.

[0046] Explanation of reference numerals in the attached figures

[0047] 101、201、301、401 Packaging substrate 102、202、302、402 chip 103、203、303 molding layer 104、204、305、406 Substrate solder ball 304 Metal heat sink 402' metal bumps 403 Thermal pads 404 Molded structure 4041 First sealing layer 4042 Second sealing layer 405 First thermally conductive adhesive layer 407 Passive components 408 Heat dissipation bumps S1~S5 step Detailed Implementation

[0048] Please see Figure 1 The diagram shows a packaging structure including a packaging substrate 101, a chip 102, a molding compound 103, and substrate solder balls 104. The molding compound 103 completely covers the chip 102, which seriously affects the heat dissipation performance of the chip 102. This limits the use of this structure on chips with high thermal design power (TDP).

[0049] Please see Figure 2 The diagram shows another packaging structure, which includes a packaging substrate 201, a chip 202, a molding compound 203, and substrate solder balls 204. The molding compound 203 covers the sidewalls of the chip 202 and exposes the top of the chip 202 to improve the heat dissipation performance of the chip 202. However, compared to... Figure 1 The packaging structure shown is as follows: Figure 2 Although the packaging structure shown can improve heat dissipation performance to a certain extent, it requires the top of the chip 202 to be exposed, which can easily cause damage to the chip 202 due to external forces.

[0050] Please see Figure 3The diagram shows another packaging structure, which includes a packaging substrate 301, a chip 302, a molding compound 303, a metal heat sink 304, and substrate solder balls 305. The metal heat sink 304 is bonded and fixed to the top of the chip 302 with thermally conductive adhesive. Figure 2 The packaging structure shown is as follows: Figure 3 While the illustrated packaging structure can prevent damage to the top of the chip 302 from external forces, the metal heat sink 304 has a high coefficient of thermal expansion. Since the metal heat sink 304 is embedded in the molding compound 303, if the chip 302 generates a large amount of heat, the metal heat sink 304 is prone to significant thermal expansion, which can cause cracks in the molding compound 303 and lead to packaging failure. This presents a thermal expansion mismatch issue, potentially affecting the stability and lifespan of the packaging structure. Furthermore, once the metal heat sink 304 is molded, its size and thickness cannot be easily adjusted to meet different thermal design power (TDP) requirements. During the packaging process, molding material may overflow onto the surface of the metal heat sink 304, reducing its heat dissipation effect and ultimately leading to poor heat dissipation and degraded electrical performance of the packaged device. In other words, this packaging structure cannot accommodate the volume differences between the chip 302 and the metal heat sink 304 during thermal expansion, and the size and thickness of the metal heat sink 304 cannot be adjusted after molding.

[0051] In response, the inventors of this application have improved the packaging structure and provided a semiconductor packaging structure and its preparation method, which can improve the heat dissipation performance of the packaging structure, take into account the reliability of the packaging structure, and is suitable for large-scale mass production.

[0052] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0054] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0055] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0056] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0057] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0058] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0059] Example 1

[0060] This embodiment provides a method for fabricating a semiconductor packaging structure. Please refer to [link / reference]. Figure 4 The diagram shows a process flow chart of a method for fabricating a semiconductor packaging structure according to the present invention, which includes at least the following steps:

[0061] S1: A packaging substrate is provided, the packaging substrate including a first surface and a second surface disposed opposite to each other;

[0062] S2: Provide at least one chip, wherein the active surface of each chip is provided with metal bumps;

[0063] S3: Bond the active surface of the chip to the first surface of the packaging substrate;

[0064] S4: Provide at least one heat dissipation silicon sheet, and attach each of the heat dissipation silicon sheets to the side of each chip away from the packaging substrate;

[0065] S5: Form a molding compound structure, the molding compound structure including a first molding compound layer and a second molding compound layer with different coefficients of thermal expansion, the first molding compound layer filling the gap between the chip and the packaging substrate, the second molding compound layer being located on the packaging substrate, and the second molding compound layer wrapping the first packaging compound layer, the chip and the heat dissipation silicon wafer and exposing the side of the heat dissipation silicon wafer away from the chip.

[0066] The following section, using a structural diagram, details the specific implementation methods for each of the above steps.

[0067] Please refer to the following first. Figure 5 Step S1: Provide a packaging substrate 401, the packaging substrate 401 including a first surface and a second surface disposed opposite to each other.

[0068] Specifically, the first surface of the packaging substrate 401 has a circuit layer (not shown in the figure) for connecting the circuit of the chip 402.

[0069] In this embodiment, the packaging substrate 401 is a printed circuit board made of FR4 material with a thickness of 1.6 mm and a surface roughness Ra≤0.8 μm.

[0070] Please see again Figure 6 Step S2: Provide at least one chip 402, and each chip 402 has a metal bump 402' on its active surface.

[0071] As an example, the chip 402 includes either active or passive components.

[0072] In this embodiment, the chip 402 is a BGA packaged microcontroller with dimensions of 20 mm × 15 mm × 1.2 mm, a main frequency of 120 MHz, and a maximum power consumption of 2 W. The bottom of the chip 402 is electrically connected to the first surface of the package substrate 401 through solder balls.

[0073] Please see again Figure 7 Step S3: Bond the active surface of the chip 402 to the first surface of the packaging substrate 401.

[0074] Specifically, the chip 402 is fixed on the first surface of the packaging substrate 401 by a soldering process, with the soldering temperature controlled within the range of 220℃~240℃ and the time controlled within the range of 3 s~5 s.

[0075] Please see again Figure 8 Step S4: Provide at least one heat dissipation silicon sheet 403, and attach each of the heat dissipation silicon sheets 403 to the side of each of the chips 402 away from the packaging substrate 401.

[0076] Specifically, the heat dissipation silicon wafer 403 is in thermal contact with the side of the chip 402 away from the packaging substrate 401, which can improve the heat dissipation performance of the chip 402. Furthermore, the size and thickness of the heat dissipation silicon wafer 403 can be adjusted through simple cutting, grinding and other processes to meet the packaging requirements of chips 402 with different thermal design power. The preparation and processing cost of the heat dissipation silicon wafer 403 is significantly lower than that of metal heat sinks, and it can be directly compatible with existing packaging production lines without additional equipment modifications, thus having a higher degree of freedom.

[0077] As an example, before attaching the heat dissipation silicon sheet 403 to the side of the chip 402 away from the packaging substrate 401, the method further includes forming a first thermally conductive adhesive layer 405 on the side of the chip 402 away from the packaging substrate 401.

[0078] As an example, the thermal conductivity of the first thermally conductive adhesive layer 405 is greater than 6 W / (m·K).

[0079] As an example, before attaching the heat-dissipating silicon wafer 403 to the side of the chip 402 away from the packaging substrate 401, a metal heat-dissipating layer is formed on the opposite side of the heat-dissipating silicon wafer 403 and the chip 402 (not shown in the figure). The metal heat-dissipating layer has a non-planar surface structure to increase the heat dissipation area. In other examples, a metal heat-dissipating layer may also be formed on the opposite side of the chip 402 and the heat-dissipating silicon wafer 403.

[0080] Specifically, the method for forming the metal heat dissipation layer includes either physical vapor deposition or electroplating.

[0081] In this embodiment, an aluminum layer with a thickness of 2 μm is formed on the opposite side of the heat dissipation silicon wafer 403 and the chip 402 using a physical vapor deposition process as the metal heat dissipation layer.

[0082] As an example, the thermal expansion coefficient of the heat dissipation silicon sheet 403 is similar to or the same as that of the chip 402, which can prevent thermal expansion from causing destructive cracks in the plastic encapsulation structure 404 and avoid plastic encapsulation cracks and warping problems.

[0083] As an example, forming the heat dissipation silicon wafer 403 includes the following steps:

[0084] (1) Provide a silicon wafer;

[0085] (2) Grind and cut the silicon wafer to obtain the heat dissipation silicon sheet 403 with a preset thickness and preset size.

[0086] Specifically, the thickness of the silicon wafer can be adjusted through a grinding process to adapt to different packaging requirements, such as adapting to different thermal design power (TDP) chip 402 packaging solutions.

[0087] As an example, the orthographic projection of the heat dissipation silicon wafer 403 on the packaging substrate 401 lies within the orthographic projection of the chip 402 on the packaging substrate 401. Specifically, the sidewall of the heat dissipation silicon wafer 403 is not flush with the edge of the chip 402, and the heat dissipation silicon wafer 403 completely covers the chip 402 and extends beyond the edge of the sidewall of the chip 402, so as to further improve the heat dissipation capacity of the heat dissipation silicon wafer 403.

[0088] For example, please refer to Figure 10 The sidewall of the heat dissipation silicon fin 403 is aligned with the sidewall of the chip 402.

[0089] In this embodiment, the heat dissipation silicon sheet 403 is a flat plate structure made of single-crystal silicon material, with a thickness of 0.5 mm and a coefficient of thermal expansion of 50 × 10⁻⁶. -7 / ℃~100×10 -7 The edge of the heat dissipation silicon wafer 403 is flush with the edge of the chip 402. The top of the heat dissipation silicon wafer 403 is in thermal contact with the top of the chip 402 through the first thermally conductive adhesive layer 405. The thermal conductivity of the first thermally conductive adhesive layer 405 is 10 W / (m·K), and the thickness is 0.2 mm.

[0090] Please see again Figure 9 Step S5 is executed: a molding compound structure 404 is formed. The molding compound structure 404 includes a first molding compound layer 4041 and a second molding compound layer 4042 with different coefficients of thermal expansion. The first molding compound layer 4041 fills the gap between the chip 402 and the packaging substrate 401. The second molding compound layer 4042 is located on the packaging substrate 401, and the second molding compound layer wraps the first packaging compound layer, the chip 402 and the heat dissipation silicon wafer 403 and exposes the side of the heat dissipation silicon wafer 403 away from the chip 402, thus obtaining a semiconductor packaging structure. The first molding compound layer 4041 and the second molding compound layer 4042 have different coefficients of thermal expansion, which can alleviate packaging stress.

[0091] Specifically, the heat dissipation silicon wafer 403 is at least partially embedded within the molding compound structure 404, with the molding compound structure 404 exposing the outer surface of the heat dissipation silicon wafer 403. This facilitates heat dissipation from the heat dissipation silicon wafer 403 to the outside. Simultaneously, the combination of the molding compound structure 404 and the heat dissipation silicon wafer 403 prevents damage to the top of the chip 402 from external forces. Furthermore, the coefficient of thermal expansion of the heat dissipation silicon wafer 403 is similar to that of the chip 402, thus preventing destructive cracks in the molding compound structure 404 caused by thermal expansion. The combination of the heat dissipation silicon wafer 403 and the molding compound structure 404 is simple, highly reliable, and suitable for mass production. In other words, the presence of the heat dissipation silicon wafer 403 and the molding compound structure 404 results in a package structure that possesses both high heat dissipation performance and high reliability, and is suitable for mass production.

[0092] It should be noted that by having the heat dissipation silicon sheet 403 in thermal contact with the chip 402 and exposed outside the plastic encapsulation structure 404, a highly efficient heat conduction path is formed, which improves the heat dissipation efficiency by about 20% to 30% compared with the resin solution.

[0093] As an example, the horizontal plane of the upper surface of the heat dissipation silicon wafer 403 is not lower than the horizontal plane of the upper surface of the second molding compound layer 4042, which can further enhance the heat dissipation capability of the encapsulation structure.

[0094] As an example, the second surface of the packaging substrate 401 is also provided with substrate solder balls 406 for connecting external circuits.

[0095] As an example, the coefficient of thermal expansion of the first molding compound layer 4041 is similar to that of the chip 402 to reduce thermal stress.

[0096] As an example, the molding compound 404 also includes a second thermally conductive adhesive layer (not shown in the figure). The second thermally conductive adhesive layer is located on the surface of the second molding compound 4042 and is used to ground the heat dissipation silicon wafer 403 to the second molding compound 4042. The second thermally conductive adhesive layer is preferably a conductive silver paste layer to achieve electromagnetic shielding function.

[0097] Specifically, the second thermally conductive adhesive layer is formed by coating, the thickness of the second thermally conductive adhesive layer is 0.1 mm, and the curing temperature is 150 ℃.

[0098] As an example, the process of forming the first molding compound layer 4041 and the second molding compound layer 4042 includes any one of inkjet printing, dispensing, compression molding, transfer molding, liquid sealing, vacuum lamination, or spin coating.

[0099] In this embodiment, the first molding compound layer 4041 is made of epoxy resin, with a coefficient of thermal expansion of 40 × 10⁻⁶. -7 / ℃~60×10 -7 The second molding compound layer, 4042, is made of polyurethane resin with a thermal expansion coefficient of 30 × 10⁻⁶ °C and a thickness of 0.3 mm. The temperature is / ℃. -7 / ℃~50×10 -7 The heat dissipation silicon wafer 403 has a thickness of 0.7 mm and a temperature of ℃. The heat dissipation silicon wafer 403 is in close contact with the top of the chip 402 through the first thermally conductive adhesive layer 405. The first molding compound layer 4041 firmly connects the chip 402 to the packaging substrate 401. The second molding compound layer 4042 surrounds the sidewall of the heat dissipation silicon wafer 403 and is in contact with the external environment. Most of the top of the heat dissipation silicon wafer 403 is exposed outside the molding compound structure 404, forming a good heat dissipation channel.

[0100] Specifically, the first molding compound layer 4041 is formed on the first surface of the packaging substrate 401 by inkjet printing process at a curing temperature of 120 ℃, and the second molding compound layer 4042 is formed on the first surface of the packaging substrate 401 by inkjet printing process at a curing temperature of 80 ℃.

[0101] As an example, the process also includes a baking step for the semiconductor packaging structure. Specifically, the entire structure is placed in an oven and baked at 120°C for 2 hours, then allowed to cool naturally to room temperature to obtain the final product.

[0102] As an example, the method also includes the steps of cutting and inspecting the semiconductor package structure to obtain a single semiconductor package structure.

[0103] For example, please refer to Figure 11 Passive components 407 are also provided on the first or second surface of the packaging substrate 401 to meet electrical requirements under special circumstances.

[0104] To more clearly demonstrate the effectiveness of this semiconductor packaging structure fabrication method, the heat dissipation performance of the FCCSP package structure prepared by this method was tested. The results are as follows: When the power consumption of the chip 402 is 1.5 W, the highest temperature of the package structure is 85 °C, and the heat dissipation efficiency can reach over 90%. Through the design of the heat dissipation silicon wafer 403 and the metal heat dissipation layer, the heat dissipation area is significantly increased, and the heat dissipation efficiency is further improved. Simultaneously, because the heat dissipation silicon wafer 403 is in close contact with the chip 402, the thermal expansion mismatch stress is greatly reduced, ensuring the mechanical strength and stability of the package structure.

[0105] The semiconductor packaging structure fabrication method of this embodiment combines a heat-dissipating silicon wafer with a plastic encapsulation structure, enabling the resulting packaging structure to have high heat dissipation performance while also ensuring high reliability, and making it suitable for mass production.

[0106] Example 2

[0107] This embodiment provides another method for fabricating a semiconductor package structure. The method for fabricating the semiconductor package structure in this embodiment is basically the same as the method for fabricating the semiconductor package structure in Embodiment 2, except that:

[0108] Please see Figure 12 The heat dissipation silicon wafer 403 has outwardly protruding heat dissipation bumps 408 on its sidewall, and the second molding compound layer 4042 has a receiving groove adapted to the heat dissipation bumps 408. The presence of the heat dissipation bumps 408 increases the contact area between the heat dissipation silicon wafer 403 and the external environment, further improving the heat dissipation efficiency, and also provides better adhesion for the heat dissipation silicon wafer 403.

[0109] In this embodiment, the length of the heat dissipation bump 408 along the protruding direction is 0.5 mm, and it forms a horizontal difference of 0.5 mm with the sidewall of the chip 402. Through this design, the heat dissipation area of ​​the top of the heat dissipation silicon wafer 403 is increased by 15%, and the heat dissipation efficiency is improved by 5%.

[0110] It should be noted that the receiving groove is used to accommodate the heat dissipation bump 408, and its design needs to take into account the dimensional deviation of the heat dissipation silicon wafer 403 and the thickness of the second molding compound layer 4042.

[0111] The semiconductor packaging structure fabrication method of this embodiment can further improve the heat dissipation efficiency of the packaging structure by adding heat dissipation bumps, and is suitable for the packaging needs of various chip types, with good practical value and prospects for promotion and application.

[0112] Example 3

[0113] This embodiment provides a semiconductor packaging structure; please refer to [further details]. Figure 9The semiconductor packaging structure includes: a packaging substrate 401, at least one chip 402, at least one heat dissipation silicon wafer 403, and a molding compound structure 404. The packaging substrate 401 includes a first surface and a second surface disposed opposite to each other. Each chip 402 has a metal bump 402' on its active surface, and the active surface of the chip 402 is bonded to the first surface of the packaging substrate 401. Each heat dissipation silicon wafer 403 is correspondingly attached to the side of each chip 402 away from the packaging substrate 401. The molding compound structure 404 includes a first molding compound layer 4041 and a second molding compound layer 4042 with different coefficients of thermal expansion. The first molding compound layer 4041 fills the gap between the chip 402 and the packaging substrate 401. The second molding compound layer 4042 is located on the packaging substrate 401, and the second molding compound layer encapsulates the first packaging compound layer, the chip 402, and the heat dissipation silicon wafer 403, exposing the side of the heat dissipation silicon wafer 403 away from the chip 402.

[0114] Specifically, the heat dissipation silicon wafer 403 is in thermal contact with the side of the chip 402 away from the packaging substrate 401, which improves the heat dissipation performance of the chip 402. Furthermore, the heat dissipation silicon wafer 403 is at least partially embedded within the molding compound 404, with the outer surface of the molding compound 404 exposed, facilitating heat dissipation from the heat dissipation silicon wafer 403 to the outside. Additionally, the size and thickness of the heat dissipation silicon wafer 403 can be adjusted through simple cutting and polishing processes to meet the packaging requirements of chips 402 with different thermal design power (TDP).

[0115] It should be noted that the semiconductor packaging structure of this embodiment can be prepared by the semiconductor packaging structure preparation method described in Embodiment 1 or Embodiment 2, or by other preparation methods.

[0116] As an example, the chip 402 includes either active or passive components. In this embodiment, the chip 402 is a BGA-packaged microcontroller with dimensions of 20 mm × 15 mm × 1.2 mm, a main frequency of 120 MHz, and a maximum power consumption of 2 W.

[0117] As an example, the semiconductor packaging structure also includes a first thermally conductive adhesive layer 405, which is located between the chip 402 and the heat dissipation silicon wafer 403 to achieve good contact between the chip 402 and the heat dissipation silicon wafer 403.

[0118] As an example, the thermal conductivity of the first thermally conductive adhesive layer 405 is greater than 6 W / (m·K). In this embodiment, the thermal conductivity of the first thermally conductive adhesive layer 405 is 10 W / (m·K), and the thickness is 0.2 mm.

[0119] As an example, the semiconductor package structure further includes a metal heat dissipation layer located on the side of the heat dissipation silicon wafer 403 and the chip 402 facing each other, or on the side of the chip 402 and the heat dissipation silicon wafer 403 facing each other. The metal heat dissipation layer has a non-planar surface structure to increase the heat dissipation area. In this embodiment, the heat dissipation layer uses an aluminum layer with a thickness of 2 μm.

[0120] As an example, the thermal expansion coefficient of the heat dissipation silicon sheet 403 is similar to or the same as that of the chip 402, which can prevent thermal expansion from causing destructive cracks in the plastic encapsulation structure 404.

[0121] As an example, the orthographic projection of the heat dissipation silicon sheet 403 on the packaging substrate 401 is located within the orthographic projection of the chip 402 on the packaging substrate 401.

[0122] As an example, the horizontal plane of the upper surface of the heat dissipation silicon wafer 403 is not lower than the horizontal plane of the upper surface of the second molding compound layer 4042.

[0123] As an example, the second surface of the packaging substrate 401 is also provided with substrate solder balls 406 for connecting external circuits.

[0124] For example, please refer to [link / reference]. Figure 10 The sidewall of the heat dissipation silicon fin 403 is aligned with the sidewall of the chip 402.

[0125] As an example, the coefficient of thermal expansion of the first molding compound layer 4041 is similar to that of the chip 402 to reduce thermal stress.

[0126] As an example, the molding compound 404 also includes a second thermally conductive adhesive layer (not shown in the figure). The second thermally conductive adhesive layer is located on the surface of the second molding compound 4042 and is used to ground the heat dissipation silicon wafer 403 to the second molding compound 4042. The second thermally conductive adhesive layer is preferably a conductive silver paste layer to achieve electromagnetic shielding function.

[0127] For example, please refer to [link / reference]. Figure 11 Passive components 407 are also provided on the first or second surface of the packaging substrate 401 to meet electrical requirements under special circumstances.

[0128] For example, please refer to [link / reference]. Figure 12The heat dissipation silicon wafer 403 has outwardly protruding heat dissipation bumps 408 on its sidewall, and the second molding compound layer 4042 has a receiving groove adapted to the heat dissipation bumps 408. The presence of the heat dissipation bumps 408 increases the contact area between the heat dissipation silicon wafer 403 and the external environment, further improving the heat dissipation efficiency, and also provides better adhesion for the heat dissipation silicon wafer 403.

[0129] The semiconductor packaging structure in this embodiment adopts a heat-dissipating silicon sheet and a plastic encapsulation structure, which can balance the high heat dissipation performance and reliability of the packaging structure.

[0130] In summary, the semiconductor packaging structure fabrication method of the present invention includes the following steps: providing a packaging substrate, the packaging substrate including a first surface and a second surface disposed opposite to each other; providing at least one chip, each chip having metal bumps on its active surface; bonding the active surface of the chip to the first surface of the packaging substrate; providing at least one heat dissipation silicon sheet; and attaching each heat dissipation silicon sheet to the side of each chip away from the packaging substrate to form a molding compound structure. The molding compound structure includes a first molding compound layer and a second molding compound layer with different coefficients of thermal expansion. The first molding compound layer fills the gap between the chip and the packaging substrate, and the second molding compound layer is located on the packaging substrate, and the second molding compound layer encapsulates the first packaging compound layer, the chip, and the heat dissipation silicon sheet, exposing the side of the heat dissipation silicon sheet away from the chip. The semiconductor packaging structure fabrication method of the present invention can improve the heat dissipation performance of the packaging structure, take into account the reliability of the packaging structure, and is suitable for large-scale mass production. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0131] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor packaging structure, characterized in that, The method comprises the following steps: providing a packaging substrate, the packaging substrate comprising a first surface and a second surface arranged oppositely; providing at least one chip, an active surface of each chip being provided with a metal bump; bonding the active surface of the chip to the first surface of the packaging substrate; providing at least one heat dissipation silicon wafer, each heat dissipation silicon wafer being attached to a surface of each chip away from the packaging substrate correspondingly; forming a plastic encapsulation structure, the plastic encapsulation structure comprising a first plastic encapsulation layer and a second plastic encapsulation layer with different coefficients of thermal expansion, the first plastic encapsulation layer being filled in a gap between the chip and the packaging substrate, the second plastic encapsulation layer being located on the packaging substrate, and the second plastic encapsulation layer wrapping the first plastic encapsulation layer, the chip and the heat dissipation silicon wafer and exposing a surface of the heat dissipation silicon wafer away from the chip.

2. The method of claim 1, wherein: Before the heat dissipation silicon wafer is attached to the surface of the chip away from the packaging substrate correspondingly, a step of forming a first heat conductive glue layer on the surface of the chip away from the packaging substrate is further included.

3. The method of claim 2, wherein: The first heat conductive glue layer has a thermal conductivity greater than 6 W / (m·K).

4. The method of claim 1, wherein The forming of the heat dissipation silicon wafer comprises the following steps: providing a silicon wafer; grinding and cutting the silicon wafer to obtain the heat dissipation silicon wafer with a preset thickness and a preset size.

5. The method of claim 1, wherein: The heat dissipation silicon wafer has a coefficient of thermal expansion similar to or the same as that of the chip.

6. The method of claim 1, wherein: A normal projection of the heat dissipation silicon wafer on the packaging substrate is located within a normal projection of the chip on the packaging substrate.

7. The method of claim 1, wherein: A sidewall of the heat dissipation silicon wafer is arranged in alignment with a sidewall of the chip.

8. The method of claim 1, wherein: A horizontal plane where a top surface of the heat dissipation silicon wafer is located is not lower than a horizontal plane where a top surface of the second plastic encapsulation layer is located.

9. A semiconductor package structure, comprising: The method comprises: a packaging substrate, the packaging substrate comprising a first surface and a second surface arranged oppositely; at least one chip, an active surface of each chip being provided with a metal bump, the active surface of the chip being bonded to the first surface of the packaging substrate; at least one heat dissipation silicon wafer, each heat dissipation silicon wafer being attached to a surface of each chip away from the packaging substrate correspondingly; a plastic encapsulation structure, the plastic encapsulation structure comprising a first plastic encapsulation layer and a second plastic encapsulation layer with different coefficients of thermal expansion, the first plastic encapsulation layer being filled in a gap between the chip and the packaging substrate, the second plastic encapsulation layer being located on the packaging substrate, and the second plastic encapsulation layer wrapping the first plastic encapsulation layer, the chip and the heat dissipation silicon wafer and exposing a surface of the heat dissipation silicon wafer away from the chip.

10. The semiconductor package structure of claim 9, wherein: A first heat conductive glue layer is further included, the first heat conductive glue layer being located between the chip and the heat dissipation silicon wafer.

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