Apparatus including thyristor rectifiers

Abstract

This invention discloses an apparatus including a silicon controlled rectifier (SCR). The apparatus includes: a substrate; a plurality of floating wells disposed within the substrate and spaced apart from each other, belonging to a first conductivity type; a plurality of electrodes disposed on the substrate; a ring disposed within the substrate and surrounding the plurality of floating wells, belonging to a second conductivity type; a peripheral well disposed within the substrate and surrounding the ring, belonging to the first conductivity type; and a first buried layer disposed within the substrate and connected to the ring, belonging to the second conductivity type. The plurality of floating wells are interconnected at their respective ends and disposed between the first buried layer and the upper surface of the substrate.

Description

Technical Field

[0001] This invention relates to an apparatus including a silicon controlled rectifier. Background Technology

[0002] The content described in this section is only to provide background information for this embodiment and does not constitute prior art.

[0003] To protect the device from malfunctions and damage, electrostatic discharge (ESD) protection is necessary. To achieve ESD protection, a thyristor rectifier capable of bidirectional current control can be used.

[0004] In devices including silicon controlled rectifiers (SCRs), current may flow into the substrate due to the formation of parasitic SCRs. Therefore, there is a need for devices including SCRs that are structurally designed to prevent current from flowing into the substrate. Summary of the Invention

[0005] The problem the invention aims to solve

[0006] The purpose of this invention is to provide a device including a silicon controlled rectifier that can prevent electrostatic discharge.

[0007] The objectives of this invention are not limited to those mentioned above. Other objectives and advantages of this invention not mentioned can be understood through the following description and will become more apparent through embodiments of this invention. Furthermore, it is obvious that the objectives and advantages of this invention can be achieved through methods and combinations thereof described in the claims.

[0008] means for solving problems

[0009] The device including a silicon controlled rectifier according to an embodiment of the present invention includes: a substrate; a plurality of floating wells disposed within the substrate and spaced apart from each other, belonging to a first conductivity type; a plurality of electrodes disposed on the substrate; a ring disposed within the substrate and surrounding the plurality of floating wells, belonging to a second conductivity type; a peripheral well disposed within the substrate and surrounding the ring, belonging to the first conductivity type; and a first buried layer disposed within the substrate and connected to the ring, belonging to the second conductivity type, wherein the plurality of floating wells are interconnected at their respective ends and disposed between the first buried layer and the upper surface of the substrate.

[0010] Furthermore, the peripheral trap and the ring are connected to one of the plurality of electrodes.

[0011] Furthermore, the plurality of floating wells includes a first floating well, a second floating well, a third floating well, and a fourth floating well, and the plurality of electrodes includes a first cathode electrode, an anode electrode, and a second cathode electrode. The present invention includes: a first well, disposed within the substrate between the first floating well and the second floating well, belonging to the second conductivity type; a second well, disposed within the first well, belonging to the first conductivity type; a third well, disposed within the substrate between the second floating well and the third floating well, belonging to the second conductivity type; and a fourth well, disposed within the third well, belonging to the second conductivity type.

[0012] Furthermore, the second well is connected to the first cathode electrode, and the fourth well is connected to the anode electrode.

[0013] Furthermore, the first portion of the ring is disposed between the first portion of the peripheral well and the first floating well, and the first portion of the peripheral well and the first portion of the ring are connected to the first cathode electrode.

[0014] Furthermore, the present invention includes: a fifth well disposed within the third well and belonging to the first conductivity type; a sixth well disposed within the substrate between the third floating well and the fourth floating well and belonging to the second conductivity type; and a seventh well disposed within the sixth well and belonging to the second conductivity type.

[0015] Furthermore, the second well is connected to the first cathode electrode, the fourth well is connected to the anode electrode, and the seventh well is connected to the second cathode electrode.

[0016] Furthermore, the first portion of the ring is disposed between the first portion of the peripheral well and the first floating well, and the first portion of the peripheral well and the first portion of the ring are connected to the first cathode electrode. The second portion of the ring is disposed between the second portion of the peripheral well and the fourth floating well, and the second portion of the peripheral well and the second portion of the ring are connected to the second cathode electrode.

[0017] Furthermore, the first floating trap, the second floating trap, the third floating trap, the fourth floating trap, the first trap, the second trap, the third trap, the fourth trap, the fifth trap, the sixth trap, and the seventh trap are disposed between the first portion of the ring and the second portion of the ring, and the first portion of the ring and the second portion of the ring are disposed between the first portion of the outer trap and the second portion of the outer trap.

[0018] Furthermore, the present invention also includes: an eighth well, disposed within the substrate between the first floating well and the second floating well, belonging to the second conductivity type; a ninth well, disposed within the substrate between the second floating well and the third floating well, belonging to the second conductivity type; and a tenth well, disposed within the substrate between the third floating well and the fourth floating well, belonging to the second conductivity type, wherein the first well and the second well are disposed within the eighth well, the third well, the fourth well, and the fifth well are disposed within the ninth well, and the sixth well and the seventh well are disposed within the tenth well, wherein the impurity concentration of the eighth well is lower than the impurity concentration of the first well, the impurity concentration of the ninth well is lower than the impurity concentration of the third well, and the impurity concentration of the tenth well is lower than the impurity concentration of the sixth well.

[0019] Furthermore, the eighth well includes an insertion portion of the eighth well inserted into the first well, the insertion portion of the eighth well being connected to the second well, and due to the insertion portion of the eighth well, the first well is divided into a first part of the first well and a second part of the first well.

[0020] Furthermore, the present invention also includes a second buried layer, which is disposed within the substrate between the plurality of floating traps and the first buried layer, and belongs to the first conductivity type.

[0021] The device including a silicon controlled rectifier according to an embodiment of the present invention includes: a substrate; a first portion and a second portion of a peripheral well, disposed separately within the substrate; a first portion and a second portion of a ring, disposed separately within the substrate between the first portion and the second portion of the peripheral well; a first floating well, a second floating well, and a third floating well, disposed separately within the substrate between the first portion and the second portion of the ring, belonging to a first conductivity type; a first well, disposed within the substrate between the first floating well and the second floating well, belonging to a second conductivity type; a second well, disposed within the first well and connected to a first cathode electrode, belonging to the first conductivity type; a third well, disposed within the substrate between the second floating well and the third floating well, belonging to the second conductivity type; a fourth well, disposed within the third well and connected to an anode electrode, belonging to the second conductivity type; and a fifth well, disposed within the third well and connected to the anode electrode, belonging to the first conductivity type, wherein the first portion of the peripheral well, the first portion of the ring, and the second well are connected to the first cathode electrode.

[0022] Furthermore, the present invention also includes: a fourth floating well, disposed within the substrate between the first portion of the ring and the second portion of the ring, and spaced apart from the third floating well; a sixth well, disposed within the substrate between the third floating well and the fourth floating well, belonging to the second conductivity type; and a seventh well, disposed within the sixth well and connected to the second cathode electrode, belonging to the second conductivity type, wherein the second portion of the peripheral well, the second portion of the ring, and the seventh well are connected to the second cathode electrode.

[0023] Furthermore, the present invention also includes: an eighth well, disposed within the substrate between the first floating well and the second floating well, belonging to the second conductivity type; a ninth well, disposed within the substrate between the second floating well and the third floating well, belonging to the second conductivity type; and a tenth well, disposed within the substrate between the third floating well and the fourth floating well, belonging to the second conductivity type, wherein the first well and the second well are disposed within the eighth well, the third well, the fourth well, and the fifth well are disposed within the ninth well, and the sixth well and the seventh well are disposed within the tenth well, wherein the impurity concentration of the eighth well is lower than the impurity concentration of the first well, the impurity concentration of the ninth well is lower than the impurity concentration of the third well, and the impurity concentration of the tenth well is lower than the impurity concentration of the sixth well.

[0024] Furthermore, the eighth well includes an insertion portion of the eighth well inserted into the first well, the insertion portion of the eighth well being connected to the second well, and due to the insertion portion of the eighth well, the first well is divided into a first part of the first well and a second part of the first well.

[0025] Furthermore, the present invention also includes a first buried layer disposed within the substrate and connected to the ring, belonging to the second conductivity type, and the first floating trap, the second floating trap, and the third floating trap are disposed between the first buried layer and the upper surface of the substrate.

[0026] Furthermore, the present invention also includes a second buried layer, which is disposed within the substrate between the first floating well, the second floating well, and the third floating well and the first buried layer, and belongs to the first conductivity type.

[0027] The effects of the invention

[0028] The device of the present invention, which includes a silicon controlled rectifier, can reduce the current flowing into the substrate by including a floating trap and a ring, thereby preventing electrostatic discharge.

[0029] The above-mentioned content and the specific effects of the present invention will be described together in the following description of specific embodiments. Attached Figure Description

[0030] Figure 1 This is a top view of an apparatus including a silicon controlled rectifier for illustrating some embodiments of the present invention.

[0031] Figure 2 For along Figure 1 A sectional view cut off by line A-A'.

[0032] Figure 3 For along Figure 1 A sectional view cut off by line A-A'.

[0033] Figure 4 For along Figure 1 A sectional view cut off by line A-A'.

[0034] Figure 5 For along Figure 1 A sectional view cut off by line A-A'.

[0035] Figure 6 This is a graph illustrating the effect of a silicon controlled rectifier in some embodiments of the present invention. Detailed Implementation

[0036] The terms or words used in this specification and the claims should not be construed as limited to their common or dictionary meanings. Based on the principle that inventors may define the concepts of terms or words to best illustrate their invention, they should be interpreted in accordance with the meanings and concepts consistent with the technical concept of this invention. Furthermore, the embodiments described in this specification and the structures shown in the figures are merely one embodiment of the invention and do not represent all the technical ideas of the invention. Therefore, at the time of filing this application, there may be various equivalent technical solutions and examples that can be modified and applied.

[0037] The terms "first," "second," "A," and "B," as used in this specification and the claims of the invention, may be used to describe various structural elements, but the structural elements should not be limited to these terms. These terms are used only to distinguish one structural element from other structural elements. For example, without departing from the scope of this invention, a first structural element may be named a second structural element, and similarly, a second structural element may be named a first structural element. The term "and / or" may include a combination of multiple related description items or any one of multiple related description items.

[0038] The terminology used in this specification and the claims is for illustrative purposes only and does not limit the invention. Unless otherwise defined in the context, singular expressions include plural expressions. Terms such as "comprising" or "having" in this application should be understood as not precluding the presence or additional possibilities of features, numbers, steps, actions, structural elements, components, or combinations thereof described in the specification.

[0039] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0040] Terms defined in commonly used dictionaries should be interpreted as having the same meaning as the relevant technology in the context, and should not be interpreted in an idealized or overly formalized sense unless explicitly defined in this application. Furthermore, the various structures, processes, techniques, or methods included in the embodiments of this invention can be shared to the extent that they are not technically contradictory.

[0041] The following will refer to Figure 1 and Figure 2 The present invention will describe some embodiments of a device including a silicon controlled rectifier.

[0042] Figure 1 This is a top view of an apparatus including a silicon controlled rectifier for illustrating some embodiments of the present invention. Figure 2 For along Figure 1 A sectional view cut off along line A-A'. Figure 1 For clarity, illustrations of multiple electrodes have been omitted.

[0043] Reference Figure 1 and Figure 2 The device including a silicon controlled rectifier in some embodiments of the present invention may include a substrate 100, a plurality of floating wells (FW), a plurality of electrodes E1, E2, E3, a ring (IR), and a peripheral well (SDW).

[0044] For example, substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Conversely, substrate 100 may be a silicon substrate, or other materials, such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, substrate 100 may be a structure in which an epitaxial layer is formed on a substrate.

[0045] Multiple floating wells (FWs) can be disposed within the substrate 100. The multiple floating wells (FWs) can be of a first conductivity type. The multiple floating wells (FWs) can be spaced apart from each other. The multiple floating wells (FWs) can be interconnected at their respective ends.

[0046] For example, the plurality of floating wells (FWs) may include a first floating well (FW1), a second floating well (FW2), a third floating well (FW3), and a fourth floating well (FW4). The first floating well (FW1), the second floating well (FW2), the third floating well (FW3), and the fourth floating well (FW4) may be respectively disposed within the substrate 100. The first floating well (FW1), the second floating well (FW2), the third floating well (FW3), and the fourth floating well (FW4) may each extend from the upper surface to the lower surface portion of the substrate 100 within the substrate 100.

[0047] The first floating well FW1, the second floating well FW2, the third floating well FW3, and the fourth floating well FW4 can be separated from each other. Other structural elements (e.g., the first well W1, the third well W3, and the sixth well W6) can be arranged between each of the first floating well FW1, the second floating well FW2, the third floating well FW3, and the fourth floating well FW4.

[0048] The first floating trap FW1, the second floating trap FW2, the third floating trap FW3, and the fourth floating trap FW4 can each extend in the same direction.

[0049] The first floating well FW1, the second floating well FW2, the third floating well FW3, and the fourth floating well FW4 can be interconnected at their respective ends. For example, at the respective ends of the first floating well FW1, the second floating well FW2, the third floating well FW3, and the fourth floating well FW4, they can be interconnected via a connecting floating well FWC. The connecting floating well FWC can be disposed within the substrate 100. The connecting floating well FWC can be of a first conductivity type. The connecting floating well FWC can be disposed at both ends of the first floating well FW1, the second floating well FW2, the third floating well FW3, and the fourth floating well FW4, such that the first floating well FW1, the second floating well FW2, the third floating well FW3, and the fourth floating well FW4 are interconnected. The connecting floating sink FWC can extend in a direction that intersects with the directions extending from the first floating sink FW1, the second floating sink FW2, the third floating sink FW3, and the fourth floating sink FW4, respectively.

[0050] Multiple floating wells (FWs) can be operated without being electrically connected to other devices.

[0051] A ring IR can be disposed within the substrate 100. The ring IR can be of a second conductivity type. The first conductivity type and the second conductivity type can be different from each other.

[0052] A ring IR can surround multiple floating wells (FWs). For example, multiple floating wells (FWs) can be positioned between a first portion IR1 and a second portion IR2 of the ring IR. The ring IR can be separated from the multiple floating wells (FWs).

[0053] A ring IR can extend from the upper surface of the substrate 100 to the lower surface of the substrate 100. The ring IR can be connected to a first buried layer BL1 disposed within the substrate 100. The first buried layer BL1 can be of a second conductivity type. A plurality of floating wells FW can be disposed between the first buried layer BL1 and the upper surface of the substrate 100.

[0054] For example, the ring IR can include multiple regions with different doping concentrations. For example, the closer the ring IR is to the upper surface from the lower surface of the substrate 100, the higher the doping concentration of the impurity of the second conductivity type may be. Or, for example, the closer the ring IR is to the upper surface from the lower surface of the substrate 100, the higher the doping concentration of the impurity of the second conductivity type may first decrease and then increase again.

[0055] A peripheral well SDW can be disposed within the substrate 100. The peripheral well SDW can be of a first conductivity type. For example, the peripheral well SDW can be of the same conductivity type as the substrate 100. The peripheral well SDW can surround a ring IR. For example, a ring IR and a plurality of floating wells FW can be disposed between a first portion SDW1 and a second portion SDW2 of the peripheral well SDW. The peripheral well SDW can be spaced apart from the ring IR.

[0056] For example, the first part IR1 of the ring IR can be located between the first floating trap FW1 and the first part SDW1 of the outer trap SDW. For example, the second part IR2 of the ring IR can be located between the fourth floating trap FW4 and the second part SDW2 of the outer trap SDW.

[0057] The peripheral well SDW can extend from the upper surface to the lower surface portion of the substrate 100 within the substrate 100.

[0058] Multiple electrodes E1, E2, and E3 can be disposed on the substrate 100. These electrodes may include a first cathode electrode E1, an anode electrode E2, and a second cathode electrode E3, which are spaced apart from each other. The first cathode electrode E1 and the second cathode electrode E3 may be the same electrode.

[0059] The peripheral well SDW and ring IR can be connected to one of the multiple electrodes E1, E2, E3. By connecting the peripheral well SDW and ring IR to one of the multiple electrodes E1, E2, E3 and connecting them to the ground terminal, the amount of current flowing into the substrate 100 during device operation can be significantly reduced.

[0060] A first well W1 can be disposed between a first floating well FW1 and a second floating well FW2. The first well W1 can be disposed within the substrate 100. The first well W1 can be of a second conductivity type. A device isolation film 110 can be disposed between the first well W1 and the first floating well FW1. A device isolation film 110 can be disposed between the first well W1 and the second floating well FW2. Within the substrate 100, the first well W1 can extend from the upper surface to the lower surface portion of the substrate 100.

[0061] In the first well W1, the upper surface side of the substrate 100 may include a region where the doping concentration of an impurity of a second conductivity type is higher than the doping concentration of the first well W1.

[0062] The second well W2 can be disposed within the first well W1. The second well W2 can be disposed within the substrate 100. The second well W2 can be of a first conductivity type. For example, the doping concentration of the second well W2 can be higher than the doping concentration of the substrate 100 of the first conductivity type. The second well W2 can be disposed on the upper surface side of the substrate 100. In the first well W1, the region with a higher doping concentration of impurities of the second conductivity type can be separated from the second well W2 by the device isolation film 110.

[0063] The first well W1 and the second well W2 can be connected to the first cathode electrode E1. Furthermore, the first cathode electrode E1 can be connected to the ring IR and the outer well SDW. For example, the first cathode electrode E1 can be connected to the first portion IR1 of the ring IR and the first portion SDW1 of the outer well SDW. That is, the first cathode electrode E1 can be connected to the first well W1, the second well W2, the first portion IR1 of the ring IR, and the first portion SDW1 of the outer well SDW.

[0064] The third well W3 can be disposed between the second floating well FW2 and the third floating well FW3. The third well W3 can be disposed within the substrate 100. The third well W3 can be of a second conductivity type. Within the substrate 100, the third well W3 can extend from the upper surface to the lower surface portion of the substrate 100.

[0065] The fourth well W4 can be disposed within the third well W3. The fourth well W4 can be disposed within the substrate 100. The fourth well W4 can be of a second conductivity type. For example, the doping concentration of the fourth well W4 can be higher than that of the third well W3. The fourth well W4 can be disposed on the upper surface side of the substrate 100.

[0066] The fifth well W5 can be disposed within the third well W3. The fifth well W5 can be disposed within the substrate 100. The fifth well W5 can be of a first conductivity type. For example, the doping concentration of the fifth well W5 can be higher than the doping concentration of the substrate 100 of the first conductivity type. The fifth well W5 can be disposed on the upper surface side of the substrate 100.

[0067] In the third well W3, the upper surface of the substrate 100 may include a region separated from the fourth well W4 and the fifth well W5, wherein the doping concentration of impurities of the first conductivity type is higher than the doping concentration of the substrate 100. In the third well W3, the fourth well W4 and the fifth well W5 may be separated by the device isolation film 110.

[0068] The third well W3, the fourth well W4, and the fifth well W5 can be connected to the anode electrode E2.

[0069] The sixth well W6 can be disposed between the third floating well FW3 and the fourth floating well FW4. The sixth well W6 can be disposed within the substrate 100. The sixth well W6 can be of the second conductivity type. Within the substrate 100, the sixth well W6 can extend from the upper surface to the lower surface portion of the substrate 100.

[0070] In the sixth well W6, the upper surface side of the substrate 100 may include a region where the doping concentration of an impurity of the first conductivity type is higher than the doping concentration of the substrate 100 of the first conductivity type.

[0071] The seventh well W7 can be disposed within the sixth well W6. The seventh well W7 can be disposed within the substrate 100. The seventh well W7 can be of a second conductivity type. For example, the doping concentration of the seventh well W7 can be higher than that of the sixth well W6. The seventh well W7 can be disposed on the upper surface side of the substrate 100.

[0072] The sixth well W6 and the seventh well W7 can be connected to the second cathode electrode E3. Furthermore, the second cathode electrode E3 can be connected to the ring IR and the outer well SDW. For example, the second cathode electrode E3 can be connected to the second portion IR2 of the ring IR and the second portion SDW2 of the outer well SDW. That is, the second cathode electrode E3 can be connected to the sixth well W6, the seventh well W7, the second portion IR2 of the ring IR, and the second portion SDW2 of the outer well SDW.

[0073] Anode electrode E2, fourth well W4, third well W3, second floating well FW2, first well W1, and second well W2 can form a unidirectional thyristor rectifier. Anode electrode E2, fifth well W5, third well W3, third floating well FW3, sixth well W6, and seventh well W7 can form a thyristor rectifier in another direction.

[0074] The second buried layer BL2 can be disposed within the substrate 100. The second buried layer BL2 can be disposed between the first buried layer BL1 and the plurality of floating wells (FWs). The second buried layer BL2 can be disposed within a ring IR. For example, the second buried layer BL2 can be disposed between a first portion IR1 and a second portion IR2 of the ring IR. The second buried layer BL2 can be of a first conductivity type. The second buried layer BL2 can be electrically connected to the plurality of floating wells (FWs).

[0075] The following will refer to Figure 1 and Figure 3 Devices including silicon controlled rectifiers according to some embodiments of the present invention will be described. For clarity, descriptions that are repeated in the present description will be omitted.

[0076] Figure 3 For along Figure 1 A sectional view cut off by line A-A'.

[0077] Reference Figure 1 and Figure 3 In some embodiments of the present invention, the device including the silicon controlled rectifier may not include the second buried layer BL2.

[0078] The following will refer to Figure 1 and Figure 4 Devices including silicon controlled rectifiers according to some embodiments of the present invention will be described. For clarity, descriptions that are repeated in the present description will be omitted.

[0079] Figure 4 For along Figure 1 A sectional view cut off by line A-A'.

[0080] Reference Figure 1 and Figure 4 The device including a silicon controlled rectifier in some embodiments of the present invention may further include an eighth well W8, a ninth well W9, and a tenth well W10.

[0081] In some embodiments of the present invention, the device including a silicon controlled rectifier may include a second buried layer BL2, or may not include a second buried layer BL2.

[0082] An eighth well W8 may be disposed between the first floating well FW1 and the second floating well FW2. The eighth well W8 may be disposed within the substrate 100. The eighth well W8 may be of a second conductivity type. Within the substrate 100, the eighth well W8 may extend from the upper surface to the lower surface portion of the substrate 100. The first well W1 and the second well W2 may be disposed within the eighth well W8. The concentration of impurities of the second conductivity type in the eighth well W8 may be lower than the concentration of impurities of the second conductivity type in the first well W1.

[0083] A ninth well W9 can be disposed between the second floating well FW2 and the third floating well FW3. The ninth well W9 can be disposed within the substrate 100. The ninth well W9 can be of a second conductivity type. Within the substrate 100, the ninth well W9 can extend from the upper surface to the lower surface portion of the substrate 100. The third well W3, the fourth well W4, and the fifth well W5 can be disposed within the ninth well W9. The concentration of impurities of the second conductivity type in the ninth well W9 can be lower than the concentration of impurities of the second conductivity type in the third well W3.

[0084] The tenth well W10 can be disposed between the third floating well FW3 and the fourth floating well FW4. The tenth well W10 can be disposed within the substrate 100. The tenth well W10 can be of the second conductivity type. Within the substrate 100, the tenth well W10 can extend from the upper surface to the lower surface portion of the substrate 100. The sixth well W6 and the seventh well W7 can be disposed within the tenth well W10. The concentration of impurities of the second conductivity type in the tenth well W10 can be lower than the concentration of impurities of the second conductivity type in the sixth well W6.

[0085] The following will refer to Figure 1 and Figure 5 Devices including silicon controlled rectifiers according to some embodiments of the present invention will be described. For clarity, descriptions that are repeated in the present description will be omitted.

[0086] Figure 5 For along Figure 1 A sectional view cut off by line A-A'.

[0087] Reference Figure 1 and Figure 5 The apparatus including a silicon controlled rectifier in some embodiments of the present invention may include a first insertion portion IN81, a second insertion portion IN91, a third insertion portion IN92, and a fourth insertion portion IN101.

[0088] The eighth well W8 may include a first insertion portion IN81. The first insertion portion IN81 may be a part of the eighth well W8 inserted into the first well W1. The first insertion portion IN81 may be connected to the second well W2. Due to the first insertion portion IN81, the second well W2 and the eighth well W8 may be directly connected. Due to the first insertion portion IN81, the first well W1 may be divided into a first part W1_1 and a second part W1_2. The second well W2 may be disposed between the first part W1_1 and the second part W1_2 of the first well W1. On the upper surface side of the substrate 100, a region where the doping concentration of an impurity of the second conductivity type is higher than the doping concentration of the first well W1 may be disposed within the first part W1_1 of the first well W1 and connected to the first cathode electrode E1.

[0089] The ninth well W9 may include a second insertion portion IN91 and a third insertion portion IN92. The second insertion portion IN91 may be a part of the ninth well W9 inserted into the third well W3. The second insertion portion IN91 may be connected to the eleventh well W11. Because of the second insertion portion IN91, the eleventh well W11 and the ninth well W9 can be directly connected. The third insertion portion IN92 may be another part of the ninth well W9 inserted into the third well W3. The third insertion portion IN92 may be connected to the fifth well W5. Because of the third insertion portion IN92, the fifth well W5 and the ninth well W9 can be directly connected.

[0090] Due to the second insertion portion IN91 and the third insertion portion IN92, the third well W3 can be divided into a first portion W31, a second portion W32, and a third portion W33. The eleventh well W11 can be disposed between the first portion W31 and the second portion W32 of the third well W3. The fifth well W5 can be disposed between the second portion W32 and the third portion W33 of the third well W3. The fourth well W4 can be disposed within the second portion W32 of the third well W3 and connected to the anode electrode E2. The eleventh well W11 can be connected to the anode electrode E2.

[0091] The tenth well W10 may include a fourth insertion portion IN101. The fourth insertion portion IN101 may be a part of the tenth well W10 inserted into the sixth well W6. The fourth insertion portion IN101 may be connected to the twelfth well W12. Due to the fourth insertion portion IN101, the tenth well W10 and the twelfth well W12 can be directly connected. Due to the fourth insertion portion IN101, the sixth well W6 can be divided into a first part W61 and a second part W62. The twelfth well W12 may be disposed between the first part W61 and the second part W62 of the sixth well W6. The seventh well W7 may be disposed within the second part W62 of the sixth well W6 and connected to the second cathode electrode E3. The twelfth well W12 may be connected to the second cathode electrode E3.

[0092] The following will refer to Figure 6 The effects of devices including silicon controlled rectifiers according to some embodiments of the present invention will be described. For clarity, descriptions that are repeated in the present description will be omitted.

[0093] Figure 6 This is a graph illustrating the effect of a silicon controlled rectifier in some embodiments of the present invention.

[0094] Reference Figures 1 to 6 , Figure 6The x-axis represents the voltage of the anode electrode E2 (unit: voltage), and the y-axis represents the current flowing into the substrate 100 (unit: A / mm).

[0095] The first curve G1 relates to a device including a bidirectional silicon controlled rectifier (SCR), the SCR comprising a floating well of a second conductivity type. The device can generate a parasitic SCR via a substrate of a first conductivity type, a floating well of the second conductivity type, and a buried layer of the second conductivity type. Referring to the first curve G1, it can be seen that the current (Isub) flowing into the substrate 100 increases sharply with the voltage of the anode electrode E2.

[0096] The second curve G2 relates to a case where the thyristor rectifier does not include a floating well of the first conductivity type and only includes wells of the first conductivity type and wells of the second conductivity type. Referring to the second curve G2, it can be seen that the current (Isub) flowing into the substrate 100 increases sharply with the voltage of the anode electrode E2.

[0097] The third curve G3 relates to the apparatus including a silicon controlled rectifier according to an embodiment of the present invention. Referring to the third curve G3, it can be seen that with the voltage of the anode electrode E2, there is no range in which the current (Isub) flowing into the substrate 100 increases sharply. That is, the apparatus including a silicon controlled rectifier according to an embodiment of the present invention can achieve bidirectional operation by making the silicon controlled rectifier include a floating well of a first conductivity type, and the amount of current flowing into the substrate can be significantly reduced by connecting the peripheral well and the ring together with the cathode electrode.

[0098] The above description is merely an illustrative illustration of the technical concept of this embodiment. For those skilled in the art, various modifications and variations can be made without departing from the essential characteristics of this embodiment. Therefore, this embodiment is not intended to limit the technical concept of this embodiment, but rather to illustrate it. The scope of the technical concept of this embodiment is not limited to these embodiments. The scope of protection of this embodiment should be interpreted by the appended claims, and all technical concepts within their equivalent scope should be interpreted as being included within the scope of the claims of this embodiment.

Claims

1. A device including a silicon controlled rectifier, characterized in that, include: substrate; Multiple floating wells are disposed within the substrate, spaced apart from each other, and belong to the first conductivity type; Multiple electrodes are disposed on the substrate; A ring, disposed within the substrate and surrounding the plurality of floating wells, belongs to the second conductivity type; A peripheral well, disposed within the substrate and surrounding the ring, belongs to the first conductivity type; and The first buried layer, disposed within the substrate and connected to the ring, belongs to the second conductivity type. The plurality of floating traps are interconnected at their respective ends and are disposed between the first buried layer and the upper surface of the substrate.

2. The device including a silicon controlled rectifier according to claim 1, characterized in that, The peripheral trap and the ring are connected to one of the plurality of electrodes.

3. The device including a silicon controlled rectifier according to claim 1, characterized in that, The plurality of floating traps includes a first floating trap, a second floating trap, a third floating trap, and a fourth floating trap. The plurality of electrodes includes a first cathode electrode, an anode electrode, and a second cathode electrode. The device including the silicon controlled rectifier includes: The first well, located within the substrate and disposed between the first floating well and the second floating well, belongs to the second conductivity type; The second well is disposed within the first well and belongs to the first conductivity type; The third well, located within the substrate and disposed between the second floating well and the third floating well, belongs to the second conductivity type; and The fourth well, located within the third well, belongs to the second conductivity type.

4. The apparatus including a silicon controlled rectifier according to claim 3, characterized in that, The second well is connected to the first cathode electrode. The fourth well is connected to the anode electrode.

5. The apparatus including a silicon controlled rectifier according to claim 4, characterized in that, The first portion of the ring is disposed between the first portion of the outer well and the first floating well. The first portion of the peripheral trap and the first portion of the ring are connected to the first cathode electrode.

6. The apparatus including a silicon controlled rectifier according to claim 3, characterized in that, include: The fifth well, located within the third well, belongs to the first conductivity type; The sixth well, located within the substrate and situated between the third and fourth floating wells, belongs to the second conductivity type. as well as The seventh well, located within the sixth well, belongs to the second conductivity type.

7. The apparatus including a silicon controlled rectifier according to claim 6, characterized in that, The second well is connected to the first cathode electrode. The fourth well is connected to the anode electrode. The seventh well is connected to the second cathode electrode.

8. The apparatus including a silicon controlled rectifier according to claim 7, characterized in that, The first portion of the ring is disposed between the first portion of the outer well and the first floating well. The first portion of the peripheral trap and the first portion of the ring are connected to the first cathode electrode. The second portion of the ring is disposed between the second portion of the outer trap and the fourth floating trap. The second portion of the peripheral trap and the second portion of the ring are connected to the second cathode electrode.

9. The apparatus including a silicon controlled rectifier according to claim 6, characterized in that, The first floating well, the second floating well, the third floating well, the fourth floating well, the first well, the second well, the third well, the fourth well, the fifth well, the sixth well, and the seventh well are disposed between the first part of the ring and the second part of the ring. The first portion of the ring and the second portion of the ring are disposed between the first portion of the outer perimeter well and the second portion of the outer perimeter well.

10. The apparatus including a silicon controlled rectifier according to claim 9, characterized in that, Also includes: The eighth well, located within the substrate and disposed between the first floating well and the second floating well, belongs to the second conductivity type; The ninth well, located within the substrate and disposed between the second floating well and the third floating well, belongs to the second conductivity type; and The tenth well, located within the substrate between the third and fourth floating wells, belongs to the second conductivity type. The first and second wells are disposed within the eighth well. The third, fourth, and fifth wells are disposed within the ninth well. The sixth and seventh wells are disposed within the tenth well. The concentration of impurities in the eighth well is lower than the concentration of impurities in the first well. The concentration of impurities in the ninth well is lower than the concentration of impurities in the third well. The concentration of impurities in the tenth well is lower than the concentration of impurities in the sixth well.

11. The apparatus including a silicon controlled rectifier according to claim 10, characterized in that, The eighth well includes an insertion portion of the eighth well inserted into the first well. The insertion portion of the eighth well is connected to the second well. Due to the insertion portion of the eighth well, the first well is divided into a first part of the first well and a second part of the first well.

12. The apparatus including a silicon controlled rectifier according to claim 1, characterized in that, It also includes a second buried layer, which is disposed within the substrate between the plurality of floating traps and the first buried layer, and belongs to the first conductivity type.

13. An apparatus including a silicon controlled rectifier, characterized in that, include: substrate; The first and second portions of the peripheral well are spaced apart from each other within the substrate; The first and second portions of the ring are disposed within the substrate, between the first portion of the peripheral well and the second portion of the peripheral well, and are spaced apart from each other. The first floating well, the second floating well, and the third floating well are disposed within the substrate between the first portion of the ring and the second portion of the ring, spaced apart from each other, and belong to the first conductivity type. The first well, located within the substrate and positioned between the first floating well and the second floating well, belongs to the second conductivity type; The second well is disposed inside the first well and connected to the first cathode electrode, and belongs to the first conductivity type; The third well, located within the substrate and positioned between the second floating well and the third floating well, belongs to the second conductivity type; A fourth well, disposed within the third well and connected to the anode electrode, belongs to the second conductivity type; and The fifth well, disposed within the third well and connected to the anode electrode, belongs to the first conductivity type. The first portion of the peripheral trap, the first portion of the ring, and the second trap are connected to the first cathode electrode.

14. The apparatus including a silicon controlled rectifier according to claim 13, characterized in that, Also includes: A fourth floating trap is disposed within the substrate, between the first portion of the ring and the second portion of the ring, and spaced apart from the third floating trap; The sixth well, located within the substrate and disposed between the third and fourth floating wells, belongs to the second conductivity type; and The seventh well, disposed within the sixth well and connected to the second cathode electrode, belongs to the second conductivity type. The second portion of the outer well, the second portion of the ring, and the seventh well are connected to the second cathode electrode.

15. The apparatus including a silicon controlled rectifier according to claim 14, characterized in that, Also includes: The eighth well, located within the substrate and disposed between the first floating well and the second floating well, belongs to the second conductivity type; The ninth well, located within the substrate and disposed between the second floating well and the third floating well, belongs to the second conductivity type; and The tenth well, located within the substrate between the third and fourth floating wells, belongs to the second conductivity type. The first well and the second well are disposed within the eighth well. The third, fourth, and fifth wells are disposed within the ninth well. The sixth and seventh wells are disposed within the tenth well. The concentration of impurities in the eighth well is lower than the concentration of impurities in the first well. The concentration of impurities in the ninth well is lower than the concentration of impurities in the third well. The concentration of impurities in the tenth well is lower than the concentration of impurities in the sixth well.

16. The apparatus including a silicon controlled rectifier according to claim 15, characterized in that, The eighth well includes an insertion portion of the eighth well inserted into the first well. The insertion portion of the eighth well is connected to the second well. Due to the insertion portion of the eighth well, the first well is divided into a first part of the first well and a second part of the first well.

17. The apparatus including a silicon controlled rectifier according to claim 13, characterized in that, It also includes a first buried layer, disposed within the substrate and connected to the ring, belonging to the second conductivity type. The first floating trap, the second floating trap, and the third floating trap are disposed between the first buried layer and the upper surface of the substrate.

18. The apparatus including a silicon controlled rectifier according to claim 17, characterized in that, It also includes a second buried layer, which is disposed within the substrate between the first floating well, the second floating well, and the third floating well and the first buried layer, and belongs to the first conductivity type.

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