Analog-to-digital converter with built-in charge-based capacitance measurement

Abstract

An ADC with built-in charge-based capacitance measurement is described. Examples include: multiple capacitors coupled in parallel to an input voltage at a common node; multiple drivers, each coupled to a corresponding capacitor opposite the common node; a first switch coupled to the common node to couple the common node to ground in response to a second clock signal from a timing generator; a second switch coupled to the common node to couple the common node to a reference voltage in response to a third clock signal from the timing generator; successive logic circuitry configured to control each driver to alternately drive the second clock signal to a selected capacitor or couple a selected capacitor to ground; and measurement logic including a current sensor for measuring the current through the common node and configured to determine the capacitance of the selected capacitor.

Description

Cross-references to related applications

[0001] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 537,559, filed December 12, 2023, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0002] All aspects of this disclosure relate to charge-based capacitor measurements in general, and more specifically to the measurement of capacitors in circuits (e.g., analog-to-digital converters) having multiple capacitors in parallel. Background Technology

[0003] Integrated circuit designers have discovered many ways to replace many other electronic circuit components with transistors or transistor-like components. Nevertheless, many circuits still require capacitors, which are used in modern silicon devices. Capacitors are particularly important for radio frequency and analog interfaces, whether analog-to-digital converters (ADCs) or digital-to-analog converters (DACs), especially capacitor-controlled digital-to-analog converters (CDACs). Some of these capacitors are formed in a semiconductor substrate using conductive regions (e.g., doped silicon) isolated by dielectric regions (e.g., silicon-based oxides).

[0004] Integrated circuit designers can design capacitors by relying on past experience, modeling software, and post-placement extraction to estimate capacitor performance. In some circuits, the physical parameters of the capacitor can determine the circuit performance and affect whether it functions properly. Test wafers can be produced for specific integrated circuits. This allows the integrated circuit to operate as a whole with the expected inputs and outputs. The capacitor design can then be modified to improve results for another test run. Summary of the Invention

[0005] The following content presents an overview of one or more embodiments to provide a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] An ADC with built-in charge-based capacitance measurement is described. Examples include: a timing generator configured to receive a first clock signal; a plurality of capacitors coupled in parallel to an input voltage at a common node; a plurality of drivers each coupled to a corresponding capacitor opposite the common node, each driver coupled to a second clock signal to drive the capacitor using the second clock signal; a first switch coupled to the common node and configured to couple the common node to ground in response to the second clock signal from the timing generator; a second switch coupled to the common node and configured to couple the common node to a reference voltage in response to a third clock signal from the timing generator; successive logic circuitry configured to control each driver to alternately drive the second clock signal to a selected capacitor or couple the selected capacitor to ground; and measurement logic including a current sensor for measuring the current through the common node and configured to determine the capacitance of the selected capacitor among the plurality of capacitors.

[0007] In another example, an analog-to-digital converter (ADC) includes: a timing generator configured to receive a first clock signal; an n-voltage input port; a first plurality of capacitors coupled in parallel to the n-voltage input port at a first common node; a plurality of drivers, each coupled to a corresponding capacitor opposite the first common node, each driver coupled to a second clock signal to drive the capacitor using the second clock signal; a p-voltage input port; a second plurality of capacitors coupled in parallel to the p-voltage input port at a second common node; and a second plurality of drivers, each coupled to a corresponding capacitor among the second plurality of capacitors opposite the second common node, each driver coupled to a third clock signal. The signal is used to drive the corresponding capacitor using the third clock signal; a first switch coupled to the first common node and configured to couple the first common node to ground in response to the second clock signal from the timing generator; a second switch coupled to the first common node and configured to couple the first common node to a reference voltage in response to the third clock signal from the timing generator; successive logic circuitry configured to control each driver to alternately drive the second clock signal to a selected capacitor or couple the selected capacitor to ground; and measurement logic including a current sensor for measuring the current through the first common node and configured to determine the capacitance of the selected capacitor of the first plurality of capacitors.

[0008] In another example, a method includes: driving a plurality of capacitors of an analog-to-digital converter (ADC) using a first clock signal via a plurality of drivers, each driver being coupled to a respective capacitor; coupling a common node to ground in response to a second clock signal, the common node being coupled to each of the plurality of capacitors opposite the respective driver; coupling the common node to a reference voltage in response to a third clock signal; controlling each driver to alternately drive the first clock signal to a selected capacitor or couple the selected capacitor to ground; and measuring the current through the common node to determine the capacitance of the selected capacitor among the plurality of capacitors.

[0009] To achieve the foregoing and related objectives, one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and accompanying figures illustrate certain exemplary aspects of one or more embodiments in detail. However, these aspects are merely indications of a number of ways in which the principles of the various embodiments may be employed, and the described embodiments are intended to cover all such aspects and their equivalents. Attached Figure Description

[0010] Figure 1 This is a circuit diagram of the example SAR ADC 100.

[0011] Figure 2 This is a circuit diagram of a test circuit for a capacitor used in an integrated circuit, according to various aspects of this disclosure.

[0012] Figure 3 The circuit diagram of a SAR ADC with CBCM is based on various aspects of this disclosure.

[0013] Figure 4 This is a circuit diagram of the capacitor under test configured within the ADC according to various aspects of this disclosure.

[0014] Figure 5 It is a timing diagram of the clock signal used for testing capacitors according to various aspects of this disclosure.

[0015] Figure 6 This is a circuit diagram of the capacitor under test configured within the ADC according to various aspects of this disclosure.

[0016] Figure 7 This is a conceptual diagram illustrating the operation of measurements under different states, based on various aspects of this disclosure.

[0017] Figure 8 This is a process flowchart illustrating an example of a method for a built-in charge-based measurement within an ADC, according to various aspects of this disclosure. Detailed Implementation

[0018] The detailed descriptions following, illustrated with reference to the accompanying drawings, are intended as descriptions of various configurations and are not intended to represent the only configurations in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed descriptions include specific details. However, these concepts can be practiced without these specific details. In some instances, to avoid ambiguity regarding such concepts, well-known structures and components are shown in block diagram form.

[0019] When capacitors on integrated circuits are extremely small, even small structural differences can cause a significant change in their value. However, silicon verification of CDAC designs is challenging because capacitors are so small, and there isn't always a direct way to access and measure them within the ADC. Since very small features are influenced by other nearby features, accurately characterizing capacitors by fabricating test circuitry rather than perfectly replicating the entire system may not be feasible. The techniques and structures described in this paper can be used to characterize a set of capacitors prior to mass production and also to test capacitors used in mass-production systems. This testing can be used for calibration, adjustment, or verification.

[0020] SAR (Successive Approximation Register) ADCs are widely used in various integrated circuit chips, chipsets, and chiplets. A SAR ADC contains multiple CDACs (Capacitor Digital-to-Analog Converters), which are a crucial component of the SAR ADC's accuracy. Utilizing multiple CDACs, the accuracy of each CDAC (especially any mismatch between DAC units) directly impacts the overall ADC performance. In this document, DAC is used to refer to both the CDAC and other types of DACs that can benefit from capacitor testing.

[0021] Figure 1 This is a circuit diagram of an example SAR ADC 100. The input signal has a first p-voltage input port 102 and an n-voltage input port 106. The first p-voltage input port is used to receive the p-side or positive terminal of the voltage on p-line 104, and the n-voltage input port is used to receive the n-side or negative terminal of the voltage on n-line 108. The voltage across p-line 104 and n-line 108 is sampled at switch 110, which determines the sampling frequency across p-line 104 and n-line 108 for sample-and-hold functionality. p-line 104 is coupled to the positive terminal of comparator 126, and n-line 108 is coupled to the negative terminal of comparator 126. The comparator compares the relative potentials on each line and sends the output signal to SAR logic 120, which generates a converted digital representation of the input analog voltage. SAR logic 120 is an example of a successive logic circuit.

[0022] The N-bit SAR ADC has: a series of N-1 upper DAC units 112-1, 112-2, 112-3...112-n, each coupled in parallel to p-line 104; and a series of N-1 lower DAC units 114-1, 114-2, 114-3...114-n, each coupled in parallel to n-line 108. Each DAC unit includes a capacitor 116 and a buffer (e.g., an inverter 118) coupled to a capacitor opposite to the corresponding p-line 104 or n-line 108 to control the operation of the coupled capacitor. Each corresponding upper and lower DAC unit pair has different capacitances and forms an approximation unit. As shown, the (n-1)th upper DAC unit 112-n and the (n-1)th lower DAC unit 114-n have the same capacitance denoted as 1C, where 1 is a factor of 1 and C is a unit capacitance value. The first upper DAC unit 112-1 and the first lower DAC unit 114-1 have denoted as 2 N-2 The same capacitance of C, where 2 N-2 It is a factor of the same unit capacitance value C. The approximation unit generates voltages successively to provide successive approximation. Inverter 118 is coupled to SAR logic 120, which controls the operation of inverter 118 to drive current into capacitor 116 or bleed capacitor 116. SAR logic 120 has: a p-control line 122 for independently controlling each of the upper DAC units 112-1, 112-2, 112-3...112-n; and a lower control line 124 for independently controlling each of the lower DAC units 114-1, 114-2, 114-3...114-n. In some examples, only the upper DAC unit or the lower DAC unit exists. In some examples, both the upper DAC unit and the lower DAC unit are used, but at different times. In some examples, the p-side coupled to p-line 104 or the n-side coupled to n-line 108 is turned on based on the result from comparator 126. Both sides should provide approximately the same result, except that the result on the p-side is positive and the result on the n-side is negative.

[0023] In operation, relative and equivalent upper and lower DAC units are coupled to sample the voltage across p-line 104 and n-line 108 respectively by activating corresponding capacitors, passing through corresponding drivers, and transmitting the result to comparator 126. This is repeated for each corresponding upper and lower DAC unit pair to obtain a measurement for each DAC unit pair. Each DAC unit pair has different capacitances to sense voltages at different levels and establish an n-bit voltage value at the comparator. Comparator 126 transmits the relative voltage for each DAC unit to SAR logic 120, which determines the digital voltage value and also controls the operation of SAR ADC 100.

[0024] A SAR ADC is shown as an example of an ADC that operates using capacitors, and for this ADC, the accuracy of the capacitors is important both relative to each other and relative to external physical constants. Aspects of the invention can be applied to many other types of capacitors in ADCs and to other circuitry different from that of ADCs. A SAR ADC can also be configured for a single voltage relative to a reference voltage or ground voltage. Other control, sampling, and measurement circuitry different from that shown herein can be used. The SAR ADC 100 can be configured using 8 or 10 pairs of DAC units or any other number. The DAC unit pairs can operate individually or in different combinations to obtain a greater number of different capacitance values.

[0025] Figure 2 This is a circuit diagram of a capacitor test circuit 200 for use in an integrated circuit (e.g., a SAR ADC). The circuit is in the form of an ADC with a built-in CBCM (charge-based capacitance measurement) timing block. The input signal has a first p-voltage input port 202 and an n-voltage input port 206, the first p-voltage input port being used to receive voltage on the p-side or positive terminal for p-line 204, and the n-voltage input port being used to receive voltage on the n-side or negative terminal for n-line 208. p-line 204 and n-line 208 can be the same lines as the main signal input lines used in the ADC, for example, p-line 104 and n-line 108. The p-line is coupled from source to drain through a top pMOS (p-type metal-oxide-semiconductor) transistor 212 to a bottom node 226. The bottom node 226 is also coupled to the bottom side of a top nMOS (n-type metal-oxide-semiconductor) transistor 224 and a capacitor labeled CDAC 210. n-line 208 runs from the source to the drain via bottom pMOS transistor 232 to node 236, which is also coupled to the drain of the bottom nMOS transistor and the top side of CDAC 210. CDAC 210 represents the capacitor of the ADC or other integrated circuit to be measured.

[0026] Bottom node 226 is further coupled from drain to source to ground 250 via top nMOS transistor 224. Bottom node 236 is further coupled from drain to source to ground 250 via bottom nMOS transistor 234. The gates of both top pMOS transistor 222 and top nMOS transistor 224 are coupled to clock line 228. The gate of bottom pMOS transistor 232 is coupled to clock p line 238, and the gate of bottom nMOS transistor 234 is coupled to clock n line 242. Clock line 228 (e.g., a first clock line), clock n line 242 (e.g., a second clock line), and clock p line 238 (e.g., a third clock line) are all generated and controlled by the CBCM timing block.

[0027] Top pMOS transistor 222 and top r 224 form a buffer and driver for CDAC 210. During a clock pulse, a potential from p-line 204 is applied to the bottom of CDAC 210. When clock p-line 238 is low and clock n-line 242 is low, bottom pMOS transistor 232 charges CDAC 210. When clock n-line 242 is high and clock p-line 238 is high, bottom nMOS transistor 234 discharges CDAC 210. This configuration allows CDAC to be charged to a voltage across p-line 204 and n-line 208, and then allowed to discharge, depending on the state of the gate signal at each of these transistors. Each such charge change causes current to flow from either p-line 204 or n-line 208. The voltage for p-line 204 and n-line 208 should be approximately the same, i.e., Vref. The absolute current entering the N-voltage input port 202 is measured by measurement logic 246. Connecting the CDAC's top plate and associated circuitry to Vin, and connecting the CDAC's bottom plate and associated circuitry to Vip, is not required. Vin and Vip are interchangeable. This is illustrated in more detail below. Figure 4 Measurement logic 440 and Figure 6 The measurement logic 640 includes a current sensor for measuring the current through a common node in different states of a parallel capacitor circuit. The measurement logic, or another higher-level external component, can use the current measurement to determine the capacitance of one or more of these capacitors. The resulting capacitance measurement can be determined by the CBCM logic 240.

[0028] SAR ADCs or any parallel capacitor circuitry and test circuitry can be formed in any suitable integrated circuit die, which can be considered any integrated circuit formed on a wafer and subsequently diced, removed, or otherwise extracted from the wafer. The wafer can be silicon, glass, gallium nitride, or any other suitable material used to form the integrated circuit. The parallel capacitor circuitry and test circuitry can be integrated into a System-on-Chip (SoC), which may include one or more chips or chiplets in a single package. The SoC may have a processor and one or more chiplets coupled to that processor. The SoC's structure can be adapted to suit different applications and may include all types of current packaging options from different manufacturers and manufacturing processes.

[0029] Figure 3 This is a circuit diagram of a SAR ADC with a CBCM 300, indicating how the test circuit (e.g., Figure 2 The test circuit 200 is integrated into the capacitor circuit (e.g., Figure 1Example from the SAR ADC 100. The input signal has a first p-voltage input port 302, which receives the p-side signal of the voltage coupled to the successive upper DAC unit 312. A second n-voltage input port 306 receives the negative n-side signal of the voltage coupled to the successive lower DAC unit 314. The voltage at the p-voltage input port 302 is sampled at switch 310-2, and the voltage at the n-voltage input port 306 is sampled at switch 310-1. Switches 310-1 and 310-2 determine the sampling frequency used for the sample-and-hold function. Measurements for each DAC unit pair are performed successively to produce multiple measurements to comparator 326, as described above. The output of comparator 326 is coupled to SAR logic 320, which generates a multi-bit representation of the analog voltages at the p-voltage input port 302 and the n-voltage input port 306. SAR logic is an example of successive logic circuitry used to control the operation of each CDAC (e.g., to measure voltages successively). These SAR ADC sections may be similar to or identical to a reference SAR ADC. Figure 1 The SAR ADC described.

[0030] Each DAC unit 312, 314 includes at least a capacitor 316 and an inverter 318. The capacitor is coupled to a voltage line connected in parallel with the other DAC units, and the inverter is coupled to a capacitor opposite the voltage line. Although the inverter 318 is shown, a buffer or another switching control circuit may be used as a driver to control the respective DAC unit. The inverter 318 is controlled by clock lines 322, 324 from the SAR logic to operate sequentially as a SAR ADC.

[0031] The test circuit is either built-in or integrated with a SARADC by adding several lines and transistors coupled to the CBCM logic 340, as described herein. A p-line from the p-voltage input port 302 is coupled to a top-side common node 352, which is coupled to the top side of each upper DAC unit in the upper DAC unit 312. If switch 310-2 is open (as shown), the p-voltage input port 302 is coupled from source to drain to the top-side common node 352 via a top pMOS transistor 342. The top-side common node 352 is also coupled to ground 354 via a top nMOS transistor 344. The gate of the top pMOS transistor is controlled by a clock p-line 346 from the CBCM logic 340, and the gate of the top nMOS transistor is controlled by a clock n-line 348 from the CBCM logic 340. This operation is compatible with… Figure 2 The bottom pMOS transistor 232 and bottom nMOS transistor 234 operate in the same way. The bottom side of the capacitor in the upper DAC unit 312 is coupled to an inverter that acts as a driver, which can be used with... Figure 2The top pMOS transistor 222 and top nMOS transistor 224 operate in the same or similar manner as described. Each inverter can be coupled to a reference voltage using the top reference voltage switch 356. Each inverter can be coupled to an n-voltage input port 306 using the n-line switch 358. With the top reference voltage switch 356 closed and the n-line switch 358 open, the inverters of the upper DAC unit 312 are powered by the internal reference voltage Vref via the top reference voltage switch 356 for normal ADC operation. For CBCM operation, the n-line switch 358 is closed, while the top reference voltage switch 356 can be closed or opened depending on whether the internal reference voltage Vref or an external reference voltage is used. The capacitors of selected DAC units of the upper DAC unit 312 can be charged to the reference voltage. With the n-line switch 356 open, the capacitors of selected DAC units of the upper DAC unit 312 can be charged to the voltage applied to the input port.

[0032] The n-voltage input port 306 is coupled to a bottom-side common node 362, which is coupled to the top side of each DAC cell in the lower DAC cell 314. If switch 310-1 is open (as shown), the n-voltage input port 306 is coupled from source to drain to the top-side common node 362 via a bottom pMOS transistor 382. The top-side common node 362 is also coupled to ground 354 via a bottom nMOS transistor 384. The gate of the bottom pMOS transistor is controlled by a clock p-line 386 from the CBCM logic 340, and the gate of the bottom nMOS transistor is controlled by a clock n-line 388 from the CBCM logic 340. The bottom side of the capacitors in the lower DAC cell 314 is coupled to an inverter that acts as a driver. Each inverter can be powered by an internal reference voltage Vref using the bottom reference voltage switch 366. Each inverter can be coupled to the p-voltage input port 302 and powered by a voltage from Vip using the p-line switch 368. This operation is the same as or similar to that described above for the upper DAC unit 312.

[0033] By using a driver (e.g., an inverter) already coupled to the clock side of each DAC unit for each capacitor, the test circuit requires very little additional space and components. Very few additional transistors are required by sharing pMOS and nMOS control transistors with another control transistor pair for all upper DAC units in upper DAC unit 312 and all lower DAC units in lower DAC unit 314. Testing for each capacitor is controlled by several switches and the existing control capabilities of SAR logic 320. The circuit shown and described can be modified to suit different ADC configurations and other circuits with capacitors. As mentioned, in some examples, the ADC has only a single group of DAC units (either top or bottom), in which case either the top or bottom control transistor can be removed.

[0034] As shown, the wiring-equipped measurement facility and the capability supplied by the CBCM logic can be directly integrated into the SARADC to measure the capacitance of the CDAC with high accuracy (even down to the sub-nanofarad level). The measurement facility allows for capacitance measurement via direct current measurement and knowledge of the applied voltage (referred to herein as the reference voltage), thus the measurement facility is non-invasive for the CDAC. This measurement facility has minimal impact on the performance of the SAR ADC. The ADC input can be used as the reference voltage input, so no additional voltage or measurement pad is required. The added devices (e.g., several switches) are very small, and therefore the area required to implement them on the integrated circuit die is extremely small. The driver is reused as a control element during measurement, further reducing the required additional area, and also allowing for flexible sections of all or some of the upper DAC unit 312 and lower DAC unit 314 within the CDAC.

[0035] The circuit architecture described in this article can be implemented on one or more ICs, chips, chiplets, modules, interposers, packages, system printed circuit boards (PCBs), etc. The circuit architecture described in this article can also be manufactured using various process technologies, such as complementary metal-oxide-semiconductor (CMOS), NMOS, PMOS, bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0036] According to various aspects of this disclosure, elements, or any portion thereof, or any combination thereof, may be implemented within a processing system including processors and chiplets, or individually within a chip or chiplet. Applicable circuitry can be used within microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuitry, and other suitable hardware. Circuitry may be integrated into components of a System-on-a-Chip (SoC). An SoC may be configured to operate as or include a central processing unit, graphics processor, dedicated processor, volatile memory, non-volatile memory, input / output controller, or any other suitable component having a processor or controller and chiplets.

[0037] Figure 4 This is a circuit diagram of the capacitor under test configured within the ADC 402. Cdut 404 represents the capacitor under test. Cfix 408 represents all other capacitors in the ADC. In the example above, if n=8, there are 8 capacitors in a parallel DAC unit, and Cfix 408 represents the other 7 capacitors. As the measurement moves to each capacitor of the ADC, the capacitor represented by Cdut 404 will change to measure each capacitor of the ADC, and the remaining capacitors represented by Cfix 408 will change to exclude the most recently measured capacitor. Cdut 404 is represented as having a top side and a bottom side. The bottom side is coupled to the capacitor represented by Cfix 408. Figure 3 The driver 406 (shown as an inverter) of the inverter 318. Top-side coupling to the driver 406 (shown as an inverter). Figure 3 The input voltage at node 432 is located at the n-th voltage input port 306. For example, in... Figure 3 In this configuration, the node is coupled to the top side of all capacitors in the capacitors of the successive lower DAC unit 314. Cfix 408 indicates as follows: Figure 3 The other capacitors shown all have a driver similar to the driver 406 of Cdut 404.

[0038] Figure 5This is a timing diagram of the clock signals used to test the capacitor. For testing the Cdut 404, the CBCM timing generator 434 receives a clock input and generates a first clock signal 430, a second clock signal (p clock signal) 424, and a third clock signal (n clock signal) 428. The first clock signal 430 is similar to or the same as the input first clock signal, but for the purposes of this description, it has a negligible delay. In this example, the first clock signal is shown as a square wave with equally spaced positive or high periods and equally spaced negative or low periods. This square wave is an idealized waveform but is sufficient for understanding the operation of the test circuit. The n clock signal 428 is low, where a positive pulse is centered within each high period of the first clock signal 430 and shorter than that high period. The p clock signal 424 is high, where a negative pulse is centered within each low period of the first clock signal and shorter than that low period. Frequency divider logic, delay chains, or any other suitable sequential logic or combination of sequential logic can be used to generate the clock signal from the clock input. Figure 5 The signal.

[0039] After the measurement is completed, the CBCM timing generator can stop until the next test. Although only one capacitor is shown as the device under test (Cdut), each capacitor in Cfix also has a driver and the connections shown for the device under test can be reconfigured for different capacitors. Switches and drivers can be reconfigured to measure different capacitors, and in a similar manner, drivers can be configured to measure multiple capacitors simultaneously. In such an example, Cdut 404 represents two or more selected capacitors controlled by the CBCM timing generator 434.

[0040] During measurement, the bottom side of Cfix 408 is coupled to ground or a low level (the drawing has been modified to include the inverter for Cfix). This ground or low level can be the internal ground 410 of ADC 402 or a low level, such as the low period of a first clock signal. Node 432, coupled to the top side of Cfix 408 and Cdut 404, can be coupled to the same internal ground 410 via ground switch 426. Ground switch 426 is represented by a transistor having a source coupled to node 432 and a drain coupled to internal ground 410. The gate is coupled to the n-clock signal 428. When the n-clock signal 428 is high, ground switch 426 closes, connecting the node to ground. Node 432 is also coupled to an input voltage, which is an external reference voltage 412, via reference switch 422. Reference switch 422 is represented by a transistor having a source coupled to the external reference voltage 412 and a drain coupled to node 432. The gate is coupled to the p-clock signal 424. When the p-clock signal 424 is low, the gate closes, connecting the node to the reference voltage. In this context, "external" refers to a voltage outside of the ADC 402 but may be inside a larger system, die, integrated circuit, or chip, including the ADC 402.

[0041] An external reference voltage 412 is provided at the n-input port 416 of the ADC 402, coupled via reference switch 422, as described above. The external reference voltage 412 is also provided at the p-input port 414 of the driver 406 of the ADC 402, coupled to the bottom side of Cdut 404. When Cdut 404 is charged to the external reference voltage 412, and when Cfix 408 is charged to the reference voltage, a current 418 will exist across the n-input port 416 and the p-input port 414. This current flow can be measured in measurement logic 440 to determine capacitance.

[0042] Figure 6 This is a circuit diagram of the capacitor under test configured within the ADC 602. In this example, the ADC 602 and the test circuit are identical, except that the reference voltage 612 is internal to the ADC. The reference voltage is on the inside of the p-input port 614. Current 618 can flow externally through the p-input port 614 to the n-input port 616. This allows current 618 to be measured externally in measurement logic 640. In some examples, the current is measured internally, and p-input port 614 and n-input port 615 are not used.

[0043] The capacitance of Cdut can be measured by measuring the current. First, Cdut 404 and Cfix 408 are discharged. Cdut is not driven by the clock (CLK). This occurs when the clock is low, the n clock is high, and the p clock is high. Next, Cdut 404 and Cfix 408 are charged when the p clock goes low, closing the reference switch 422. The current 418 flowing into the parallel Cdut 404 and Cfix 408 is measured to determine the total system capacitance. This can be represented by Equation 1: ItestS=(Cfix+Cdut)·Vref·Fclk (Equation 1) Where ItestS is the average current consumed by all capacitors in the group, Cfix is ​​the capacitance of Cfix capacitor, Cdut is the capacitance of the device under test, Vref is the reference voltage, and Fclk is the rate of change of the clock pulse.

[0044] When the p clock returns high and the n clock goes high, the capacitor then discharges again. After discharging and the n clock returns low, when the clock goes low, the first clock signal 430 is then established to the driver 406, shown here as an inverter, such that the reference voltage at the p input port 414 is applied to the bottom side of Cdut 404. This charges Cdut 404. Then, the p clock goes low, and this charges Cfix 408 to the reference voltage, but does not charge Cdut 404, which is already at the external reference voltage 412. The current 418 used to charge Cfix 408 is measured to determine the capacitance of Cfix 408. This can be expressed by Equation 2: ItestFix = Cfix·Vref·Fclk (Equation 2)

[0045] By comparing the two currents, the capacitance of the device under test, Cdut 404, can be determined as shown in Equation 3: Cdut=(ItestS-ItestFix) / (Vref·Fclk) (Equation 3) These measurements and capacitance determinations can be performed in measurement logic 440.

[0046] Figure 7 This is a conceptual diagram illustrating the operation of a measurement facility through different measurement states (such as being applied to a selected capacitor). In the first state 701, it could be an ADC (e.g., Figure 3The device under test, Cdut 710, of one or more capacitors 316 of one or more DAC units in the upper DAC unit 312 or lower DAC unit 314 of the SAR ADC, is coupled to ground 712 on one side (e.g., via its inverter 318) and to node 714 on the other side. The node is also coupled to ground 712 via switch 718. Therefore, the voltage at node 714 is indicated as 0V. This also applies to the charge on the two capacitors, indicated in the figures as Qfix=Qdut=0. Switch 718 can be implemented in many different ways, and in one example, corresponds to bottom nMOS transistor 384. The remaining capacitors Cfix 716 in the single row (e.g., lower DAC unit 314) are also coupled to node 714 on one side and to ground on the other side. The capacitors can all be grounded via a clock input to each corresponding driver (not shown) of each capacitor. Depending on the system polarity and the driver coupled to the first clock signal, the clock can be high or low to present a ground connection.

[0047] In the second state 702, grounding switch 718 is opened, removing the circuit from node 714 to ground 712 from the operation of the capacitor. The capacitor remains grounded relative to node 714, thus maintaining the 0V state of node 714.

[0048] In state 703, Cdut 710 is switched. The bottom side opposite node 714 switches from ground 712 to the reference voltage (Vref) or high. In the conceptual diagram, the high voltage at Vref 720 is indicated at the top of the diagram, and the low voltage or ground 712 is indicated at the bottom of the diagram. An intermediate voltage is shown in the middle between these two. The voltage is fixed in place in the diagram, and the capacitor moves to show the change in connection. The capacitor Cdut is charged from ground 712 or the low voltage (e.g., 0V at 714) to the higher voltage (e.g., Vref). This switching can be accomplished by applying a high signal from the CBCM logic to the capacitor driver.

[0049] As shown, the system charge is the combination of the charge on the device under test (Cdut) and the charges on the other capacitors (Qfix). Both charge values ​​must be zeroed together; for example, Qfix + Qdut = 0. For the device under test (Cdut), the charge Qdut is determined by the capacitance of Cdut factored by the voltage change ΔV at node 714 and the reference voltage Vref. This can be expressed as: Qdut = Cdut * (ΔV - Vref). The charge on the other capacitors (Qfix) can be determined by the capacitance of the other capacitors (Cfix) factored by the voltage change ΔV at node 714 (which is the change seen by the other capacitors). This can be expressed as Qfix = Cfix * ΔV. The current used to supply this charge can be measured as the current to the other capacitors (Cfix), indicated above as Itest*Fix.

[0050] In state 704, node 714 is pulled up to the reference voltage via switch 722. This switch can represent, for example, the bottom pMOS transistor 382, ​​which connects the n-voltage input port 306 to the reference voltage, Vref 720. Other switches are closed or opened based on the p-clock and n-clock signals from the CBCM logic, together with the first clock signal. In state 704, since both sides are coupled to the reference voltage, the charge Qdut on the device under test is zero, i.e., Qdut = 0. The charge Qfix on the other capacitors is now determined by the voltage at node 714 (which, in this state, is coupled to Vref 720). Cfix 716 remains coupled to ground on the bottom side as it is in all six states shown herein. Therefore, the charge is capacitance Cfix multiplied by voltage Vref, i.e., Qfix = Cfix * Vref.

[0051] In state 705, node 714 is disconnected from the reference voltage via the same switch 722. These are the same connections presented in state 703, but the state of the capacitor changes after state 704. After being coupled to the reference voltage, the voltage at node 714 is now Vref. This voltage is maintained for a short time by the other capacitor Cfix.

[0052] In state 6, 706, the bottom side of the device under test, Cdut, is disconnected from the reference voltage and reconnected to ground as in state 1, 701. Node 714 is allowed to float. As current flows from node 714 through all the capacitors in these capacitors to ground 712, the voltage at node 714 can be described as Vref - ΔV, i.e., the amount of voltage change in the reference voltage as current flows to ground. The charge on both the device under test, Cdut 710, and the other capacitors, Cfix 716, can be characterized with respect to this voltage, for example, Qdut = Cdut(Vref - ΔV), Qfix = Cfix(Vref - ΔV). The total system charge can be characterized only with respect to the reference voltage, for example, Qfix + Qdut = CfixVref. The current used to provide this charge can be measured and used as the current in all the capacitors in the capacitors indicated above as ItestS.

[0053] Using ItestFix and ItestS, the capacitance of the device under test (DUT) Cdut 710 can be determined. The system can return to first state 701 to repeat the measurement or perform another measurement on the same or a different DUT. The states cycle under CBCM logic control: from first state 701 through each state to sixth state 706 and back to first state. Measurements can be performed to characterize capacitors for design or manufacturing and calibration can be performed after a period of use.

[0054] Figure 8 This is a process flowchart illustrating an example of a method for built-in charge-based measurement within an ADC or other parallel capacitor circuit. At 802, the method begins by driving multiple capacitors using a first clock signal via multiple drivers, each driver coupled to a respective capacitor. At 804, the method continues by coupling a common node to ground in response to a second clock signal. The common node is coupled to each of the multiple capacitors opposite a respective driver. The method includes: at 806, coupling the common node to a reference voltage in response to a third clock signal; and at 808, controlling each driver to alternately drive the first clock signal to a selected capacitor or couple a selected capacitor to ground.

[0055] The method may further include: discharging a plurality of capacitors during a second clock signal level; and charging the capacitors during a third clock signal level. In some examples, the method may further include: charging all capacitors in the capacitor during the second clock signal level; and charging all capacitors in the capacitor except for selected capacitors during the third clock signal level.

[0056] At 810, the method further includes performing a measurement of the current through a common node to determine the capacitance of a selected capacitor among a plurality of capacitors. Determining the capacitance of the selected capacitor can be performed by comparing the charging currents of all capacitors in that capacitor with the charging currents of all capacitors in that capacitor except the selected capacitor.

[0057] As used herein, “or” is intended to be interpreted as inclusive unless otherwise explicitly stated. For example, “a or b” could include only a, only b, or a combination of a and b. As used herein, the phrase “at least one of” or “one or more of” refers to any combination of those items, including a single member. For example, “at least one of a, b, or c” is intended to cover the following examples: only a, only b, only c, a combination of a and b, a combination of a and c, a combination of b and c, and a combination of a, b, and c.

[0058] The various exemplary components, logic elements, logic blocks, modules, circuits, operations, and algorithmic processes described in conjunction with the specific embodiments disclosed herein can be implemented as electronic hardware, firmware, software, or a combination of hardware, firmware, or software, including the structures disclosed in this specification and their structural equivalents. This interchangeability of hardware, firmware, and software has been generally described in terms of its functionality and exemplified in the various exemplary components, blocks, modules, circuits, and processes described above. Whether this functionality is implemented in hardware, firmware, or software depends on the specific application and the design constraints imposed on the overall system.

[0059] The various exemplary logic blocks, modules, and circuits described in conjunction with the exemplary aspects disclosed herein can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic element, discrete hardware component, or any combination thereof. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0060] The following provides an overview of various embodiments of this disclosure.

[0061] Example 1: An analog-to-digital converter (ADC) circuit comprising: a timing generator configured to receive a first clock signal; a plurality of capacitors coupled in parallel to an input voltage at a common node; a plurality of drivers each coupled to a corresponding capacitor opposite the common node, each driver coupled to a second clock signal to drive the capacitor using the second clock signal; a first switch coupled to the common node and configured to couple the common node to ground in response to the second clock signal from the timing generator; a second switch coupled to the common node and configured to couple the common node to a reference voltage in response to a third clock signal from the timing generator; successive logic circuitry configured to control each driver to alternately drive the second clock signal to a selected capacitor or couple the selected capacitor to ground; and measurement logic including a current sensor for measuring current through the common node and configured to determine the capacitance of the selected capacitor of the plurality of capacitors.

[0062] Example 2: According to the circuit described in Example 1, wherein the timing generator sets the first switch to discharge the plurality of capacitors during a second clock signal level, and sets the second switch to charge the capacitors during a third clock signal level.

[0063] Example 3: According to the circuit described in Example 2, wherein the first switch includes an n-type metal-oxide-semiconductor transistor having a gate and a drain, the gate being coupled to the timing generator and the drain being coupled to ground.

[0064] Example 4: The circuit according to Example 2 or 3, wherein the second switch includes a p-type metal-oxide-semiconductor transistor having a gate and a source, the gate being coupled to the timing generator and the source being coupled to the reference voltage.

[0065] Example 5: A circuit according to any one or more of Examples 1 to 4, wherein the successive logic circuit configures the driver to charge all capacitors in the capacitor during a second clock signal level, and configures the driver to charge all capacitors in the capacitor except the selected capacitor during a third clock signal level.

[0066] Example 6: According to the circuit described in Example 5, the measuring circuit is configured to determine the capacitance of the selected capacitor by comparing the charging current of all capacitors in the capacitor with the charging current of all capacitors in the capacitor except the selected capacitor.

[0067] Example 7: The circuit according to any one or more of Examples 1 to 6, wherein the reference voltage is an external reference voltage.

[0068] Example 8: The circuit according to any one or more of Examples 1 to 7, wherein the capacitor and the corresponding driver form the digital-to-analog converter unit of the ADC.

[0069] Example 9: An analog-to-digital converter (ADC) comprising: a timing generator configured to receive a first clock signal; an n-voltage input port; a first plurality of capacitors coupled in parallel to the n-voltage input port at a first common node; a plurality of drivers each coupled to a corresponding capacitor opposite to the first common node, each driver coupled to a second clock signal to drive the capacitor using the second clock signal; a p-voltage input port; a second plurality of capacitors coupled in parallel to the p-voltage input port at a second common node; and a second plurality of drivers each coupled to a corresponding capacitor among the second plurality of capacitors opposite to the second common node, each driver coupled to a third clock signal. A clock signal to drive the corresponding capacitor using the third clock signal; a first switch coupled to the first common node and configured to couple the first common node to ground in response to the second clock signal from the timing generator; a second switch coupled to the first common node and configured to couple the first common node to a reference voltage in response to the third clock signal from the timing generator; successive logic circuitry configured to control each driver to alternately drive the second clock signal to a selected capacitor or couple the selected capacitor to ground; and measurement logic including a current sensor for measuring the current through the first common node and configured to determine the capacitance of the selected capacitor of the first plurality of capacitors.

[0070] Example 10: According to the ADC of Example 9, wherein the timing generator sets the first switch to discharge a plurality of capacitors during a second clock signal level, and sets the second switch to charge the capacitors during a third clock signal level.

[0071] Example 11: An ADC according to Example 9 or 10, wherein the successive logic circuit configures the driver to charge all capacitors in the capacitor during a second clock signal level, and configures the driver to charge all capacitors in the capacitor except the selected capacitor during a third clock signal level.

[0072] Example 12: According to the ADC of Example 11, the measurement circuit is configured to determine the capacitance of the selected capacitor by comparing the charging current of all capacitors in the capacitor with the charging current of all capacitors in the capacitor except the selected capacitor.

[0073] Example 13: A method comprising: driving a plurality of capacitors of an analog-to-digital converter (ADC) using a plurality of drivers with a first clock signal, each of the plurality of drivers being coupled to a corresponding capacitor; coupling a common node to ground in response to a second clock signal, the common node being coupled to each of the plurality of capacitors opposite to a corresponding driver; coupling the common node to a reference voltage in response to a third clock signal; controlling each driver to alternately drive the first clock signal to a selected capacitor or to couple the selected capacitor to ground; and measuring the current through the common node to determine the capacitance of the selected capacitor of the plurality of capacitors.

[0074] Example 14: According to the method of Example 13, the method further includes: discharging the plurality of capacitors during a second clock signal level; and charging the capacitors during a third clock signal level.

[0075] Example 15: The method according to any one or more of Examples 13 to 14, the method further comprising: charging all capacitors in the capacitor during a second clock signal level; and charging all capacitors in the capacitor except the selected capacitor during a third clock signal level.

[0076] Example 16: According to the method of Example 15, determining the capacitance of the selected capacitor includes comparing the charging current of all capacitors in the capacitor with the charging current of all capacitors in the capacitor except the selected capacitor.

[0077] Example 17: The method according to any one or more of Examples 13 to 16, the method further comprising setting a first switch coupled to the common node in response to a second clock signal from the timing generator to couple the common node to ground, thereby discharging the plurality of capacitors during the second clock signal level.

[0078] Example 18: According to the method of Example 17, the method further includes setting a second switch coupled to the common node in response to the third clock signal from the timing generator to couple the common node to a reference voltage, thereby charging the capacitor during the third clock signal level.

[0079] Example 19: The method according to any one or more of Examples 13 to 18, wherein controlling each driver includes: setting the driver to charge all capacitors in the capacitor during a second clock signal level; and setting the driver to charge all capacitors in the capacitor except the selected capacitor during a third clock signal level.

[0080] Example 20: According to the method of Example 19, determining the capacitance includes determining the capacitance of the selected capacitor by comparing the charging current of all capacitors in the capacitor with the charging current of all capacitors in the capacitor except the selected capacitor.

Claims

1. An analog-to-digital converter (ADC) circuit, the ADC circuit comprising: A timing generator, the timing generator being configured to receive a first clock signal; Multiple capacitors, which are connected in parallel at a common node and coupled to the input voltage; Multiple drivers, each driver being coupled to a corresponding capacitor opposite the common node, and each driver being coupled to a second clock signal to drive the capacitor using the second clock signal; A first switch, coupled to the common node and configured to couple the common node to ground in response to a second clock signal from the timing generator; A second switch, coupled to the common node and configured to couple the common node to a reference voltage in response to a third clock signal from the timing generator; A successive logic circuit, configured to control each driver to alternately drive the second clock signal to a selected capacitor or couple the selected capacitor to ground; and Measurement logic, which includes a current sensor for measuring the current through the common node and is configured to determine the capacitance of the selected capacitor of the plurality of capacitors.

2. The circuit of claim 1, wherein the timing generator sets the first switch to discharge the plurality of capacitors during a second clock signal level, and sets the second switch to charge the capacitors during a third clock signal level.

3. The circuit of claim 2, wherein the first switch comprises an n-type metal-oxide-semiconductor transistor having a gate and a drain, the gate being coupled to the timing generator and the drain being coupled to ground.

4. The circuit of claim 2, wherein the second switch comprises a p-type metal-oxide-semiconductor transistor having a gate and a source, the gate being coupled to the timing generator and the source being coupled to the reference voltage.

5. The circuit of claim 1, wherein the successive logic circuit configures the driver to charge all capacitors in the capacitor during a second clock signal level, and configures the driver to charge all capacitors in the capacitor except the selected capacitor during a third clock signal level.

6. The circuit of claim 5, wherein the measuring circuit is configured to determine the capacitance of the selected capacitor by comparing the charging current of all capacitors in the capacitor with the charging current of all capacitors in the capacitor except the selected capacitor.

7. The circuit according to claim 1, wherein the reference voltage is an external reference voltage.

8. The circuit of claim 1, wherein the capacitor and the corresponding driver form a digital-to-analog converter unit of the ADC.

9. An analog-to-digital converter (ADC), the analog-to-digital converter (ADC) comprising: A timing generator, the timing generator being configured to receive a first clock signal; n Voltage input port; A plurality of capacitors are connected in parallel at a first common node and coupled to the n voltage input port; Multiple drivers, each driver being coupled to a corresponding capacitor opposite the first common node, and each driver being coupled to a second clock signal to drive the capacitor using the second clock signal; p-voltage input port; The second plurality of capacitors are coupled in parallel to the p voltage input port at the second common node; The second plurality of drivers, each of the second plurality of drivers being coupled to a corresponding capacitor of the second plurality of capacitors opposite to the second common node, each driver being coupled to a third clock signal to drive the corresponding capacitor using the third clock signal; A first switch, coupled to the first common node and configured to couple the first common node to ground in response to a second clock signal from the timing generator; A second switch is coupled to the first common node and configured to couple the first common node to a reference voltage in response to a third clock signal from the timing generator; A successive logic circuit, configured to control each driver to alternately drive the second clock signal to a selected capacitor or couple the selected capacitor to ground; and Measurement logic, which includes a current sensor for measuring the current through the first common node and is configured to determine the capacitance of the selected capacitor of the first plurality of capacitors.

10. The ADC of claim 9, wherein the timing generator sets the first switch to discharge a plurality of capacitors during a second clock signal level, and sets the second switch to charge the capacitors during a third clock signal level.

11. The ADC of claim 9, wherein the successive logic circuitry configures the driver to charge all capacitors in the capacitor during a second clock signal level, and configures the driver to charge all capacitors in the capacitor except the selected capacitor during a third clock signal level.

12. The ADC of claim 11, wherein the measurement circuit is configured to determine the capacitance of the selected capacitor by comparing the charging current of all capacitors in the capacitor with the charging current of all capacitors in the capacitor except the selected capacitor.

13. A method, the method comprising: Multiple capacitors of an analog-to-digital converter (ADC) are driven by multiple drivers using a first clock signal, each driver being coupled to a corresponding capacitor; In response to a second clock signal, a common node is coupled to ground, the common node being coupled to each of the plurality of capacitors opposite a respective driver; The common node is coupled to a reference voltage in response to a third clock signal; Control each driver to alternately drive the first clock signal to a selected capacitor or couple the selected capacitor to ground; as well as The current through the common node is measured to determine the capacitance of the selected capacitor among the plurality of capacitors.

14. The method according to claim 13, further comprising: The plurality of capacitors are discharged during the second clock signal level; And to charge the capacitor during the third clock signal level.

15. The method according to claim 13, further comprising: During the second clock signal level, all capacitors in the capacitor are charged. And during the third clock signal level, all capacitors in the capacitor except the selected capacitor are charged.

16. The method of claim 15, wherein determining the capacitance of the selected capacitor comprises comparing the charging current of all capacitors in the capacitor with the charging current of all capacitors in the capacitor except the selected capacitor.

17. The method according to claim 13, further comprising: In response to the second clock signal from the timing generator, a first switch coupled to the common node is set to couple the common node to ground, thereby discharging the plurality of capacitors during the second clock signal level.

18. The method according to claim 17, further comprising: In response to the third clock signal from the timing generator, a second switch coupled to the common node is set to couple the common node to a reference voltage, thereby charging the capacitor during the third clock signal level.

19. The method of claim 13, wherein controlling each driver comprises: The driver is configured to charge all capacitors in the capacitor during the second clock signal level. And configure the driver to charge all capacitors in the capacitor except the selected capacitor during the third clock signal level.

20. The method of claim 19, wherein determining the capacitance comprises determining the capacitance of the selected capacitor by comparing the charging current of all capacitors in the capacitor with the charging current of all capacitors in the capacitor except the selected capacitor.

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