Analog-to-digital converter with built-in charge-based capacitance measurement
By integrating charge-based capacitance measurement technology into the analog-to-digital converter, the problem of difficulty in measuring the accuracy of capacitors in integrated circuits is solved, achieving high-accuracy capacitance measurement and improving circuit performance.
CN122319604APending Publication Date: 2026-06-30QUALCOMM INC
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Patent Information
- Application Number
- CN202480076525.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-12
- Filing Date
- 2024-11-27
- Publication Date
- 2026-06-30
AI Technical Summary
Technical Problem
In integrated circuits, especially in analog-to-digital converters (ADCs), the accuracy of capacitors is difficult to measure and calibrate accurately during manufacturing, leading to unstable circuit performance.
Method used
The capacitor's capacitance is measured using a built-in charge-based capacitance measurement (CBCM) technology, which integrates a SAR ADC with a timing generator, driver, switch and successive logic circuit. The capacitance value is determined by a current sensor.
Benefits of technology
This enables highly accurate measurement of capacitors, even down to the sub-nanofarad level, reducing intrusive impact on the circuit and improving the overall performance of the ADC.
✦ Generated by Eureka AI based on patent content.
Abstract
An ADC with built-in charge-based capacitance measurement is described. An example includes a plurality of capacitors coupled in parallel to an input voltage at a common node; a plurality of drivers, each coupled to a respective capacitor opposite the common node; a first switch coupled to the common node to couple the common node to ground in response to a second clock signal from the timing generator; a second switch coupled to the common node to couple the common node to a reference voltage in response to a third clock signal from the timing generator; a successive logic circuit configured to control each driver to alternately drive a second clock signal to a selected capacitor or couple the selected capacitor to ground; and measurement logic including a current sensor for measuring a current through the common node and configured to determine a capacitance of the selected capacitor.
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