A water pump variable frequency short circuit identification method based on IGBT body diode voltage drop slope

Abstract

This application provides a short-circuit identification method for water pump frequency converters based on the IGBT body diode voltage drop slope, applied to the short-circuit protection system of a water pump frequency converter controller. The method includes: real-time capture of the collector-emitter forward voltage drop signal generated by the lower arm insulated gate bipolar transistor during the inductive load freewheeling phase; continuous discrete voltage sampling at a preset sampling frequency during the effective freewheeling period; obtaining the instantaneous voltage drop change rate between adjacent sampling points through digital differential logic; comparing the absolute value of the instantaneous voltage drop change rate with a preset critical slope threshold and a time window threshold to perform dual determination; and triggering a hardware logic blocking drive signal when a short-circuit fault is detected at the output terminal.

Description

Technical Field

[0001] This application relates to the fields of power electronics technology and motor drive fault diagnosis, specifically to a method for identifying short circuits in water pump frequency converters and a short circuit protection system based on the voltage drop slope of the IGBT body diode. Background Technology

[0002] Existing short-circuit protection mechanisms in variable frequency pump control systems generally fall into a technical bias: they heavily rely on external sensors (such as Hall current sensors or precision shunt resistors) to determine overcurrent conditions by measuring the absolute current amplitude in the circuit. This defense paradigm contains a fundamental physical and logical paradox: the magnetic induction delay of the current sensor and the indispensable low-pass filtering effect in the signal conditioning circuit inevitably introduce a response lag of hundreds of microseconds on the system time axis. More critically, the traditional amplitude comparison method lacks an intrinsic understanding of the dynamic evolution of current, failing to effectively separate the high-amplitude excitation surge current at motor startup from the destructive real short-circuit current in the time dimension. This superposition of static threshold and hysteresis response often results in the protection execution point being later than the irreversible thermal breakdown critical point of the power semiconductor device when facing extreme short-circuit conditions with extremely high current rise rates, constituting the ceiling of traditional passive current threshold protection theory. Summary of the Invention

[0003] To address the aforementioned issues, firstly, this application provides a short-circuit identification method for water pump frequency converters based on the IGBT body diode voltage drop slope. This method captures the first forward voltage drop signal generated by the insulated-gate bipolar transistor during the inductive load freewheeling phase, acquires a discrete voltage sequence within the effective freewheeling period, calculates the instantaneous voltage drop rate of change, and performs dual judgment logic by combining a preset critical slope threshold and a time window threshold. This application abandons the passive defense method relying on external, high-inertial-speed sensors with significant hysteresis, transforming the device's own body diode into a high-frequency sensing node with extremely high bandwidth. By exploring the voltage transient evolution law caused by the charge storage effect in the body diode base region during the initial stage of short-circuit current surge, it achieves predictive capture of extremely high dynamic risks.

[0004] The method includes: capturing in real time the first forward voltage drop signal generated by the insulated gate bipolar transistor (IGBT) of the lower bridge arm in the power bridge arm during the inductive load freewheeling phase; continuously sampling the first forward voltage drop signal at a preset sampling frequency during the effective freewheeling period after the lower bridge arm IGBT is turned off to obtain a discrete voltage sequence containing multiple sampling points; obtaining the instantaneous voltage drop change rate based on the voltage values ​​of adjacent sampling points and the sampling period in the discrete voltage sequence; comparing the absolute value of the instantaneous voltage drop change rate with a preset critical slope threshold, and performing dual judgment logic in combination with a preset time window threshold to output a short-circuit fault judgment result; when the short-circuit fault judgment result indicates that a short-circuit fault has occurred at the output terminal, triggering a hardware interlock mechanism to block the drive signal of the power bridge arm.

[0005] Optionally, during the effective freewheeling period after the lower arm insulated gate bipolar transistor is turned off, the first forward voltage drop signal is continuously sampled at a preset sampling frequency to obtain a discrete voltage sequence containing multiple sampling points. This includes: setting the sampling start point of the effective freewheeling period within a first preset delay time window after the falling edge of the gate drive signal of the lower arm insulated gate bipolar transistor; setting the sampling end point of the effective freewheeling period within a second preset delay time window before the next pulse width modulation turn-on command is issued; and obtaining the discrete voltage sequence at the preset sampling frequency set within a first preset megahertz frequency range within the time interval defined by the sampling start point and the sampling end point.

[0006] Optionally, the instantaneous voltage drop change rate is obtained based on the voltage values ​​and sampling period of adjacent sampling points in the discrete voltage sequence, including: extracting a first voltage value corresponding to the current sampling time in the discrete voltage sequence; extracting a second voltage value corresponding to the previous sampling time immediately adjacent to the current sampling time in the discrete voltage sequence; obtaining the difference between the first voltage value and the second voltage value; and dividing the difference by the sampling period determined by the preset sampling frequency to obtain the instantaneous voltage drop change rate.

[0007] Optionally, the absolute value of the instantaneous voltage drop change rate is compared with a preset critical slope threshold, and a dual judgment logic is executed in conjunction with a preset time window threshold to output a short-circuit fault judgment result, including: extracting the absolute value of the instantaneous voltage drop change rate in real time; when the absolute value is greater than the critical slope threshold, starting an internal timer counter to accumulate the time; determining whether the condition that the absolute value is greater than the critical slope threshold is continuously maintained; if so, accumulating the duration of the internal timer counter, and when the duration exceeds the time window threshold, generating a short-circuit fault judgment result indicating that a short-circuit fault has occurred at the output terminal.

[0008] Optionally, the method further includes a dynamic temperature compensation step, which includes: acquiring the current junction temperature of the lower bridge arm insulated gate bipolar transistor in real time; constructing a temperature drift correction factor based on a preset reference temperature value, a preset temperature compensation coefficient, and the current junction temperature value; multiplying the acquired instantaneous voltage drop change rate with the temperature drift correction factor to generate a corrected instantaneous voltage drop change rate; and substituting the corrected instantaneous voltage drop change rate into the dual-determination logic for replacement comparison.

[0009] Optionally, when the short-circuit fault determination result indicates a short-circuit fault at the output terminal, a hardware interlock mechanism is triggered to block the drive signal of the power bridge arm, including: sending an emergency block command to the drive chip controlling the power bridge arm through the hardware interlock channel configured by the hardware interlock mechanism; forcibly pulling down the gate drive level of all insulated-gate bipolar transistors in the power bridge arm based on the emergency block command; synchronously blocking the signal output path of the pulse width modulation generator that provides control signals to the power bridge arm; writing the discrete voltage sequence data when the short-circuit fault determination result is triggered into the configured non-volatile storage module, and sending a short-circuit fault status code to an external monitoring terminal.

[0010] Optionally, the method further includes an adaptive sampling logic step, which includes: acquiring the current duty cycle parameter of the pulse width modulation signal in real time; when the current duty cycle parameter is less than a preset duty cycle threshold, increasing the number of sampling points of the discrete voltage sequence and executing multi-point average slope calculation logic to substitute the calculated multi-point average slope value as the instantaneous voltage drop change rate into the dual determination logic; when the current duty cycle parameter is greater than or equal to the duty cycle threshold, switching the sampling mode to a preset three-point fast sampling mode.

[0011] Secondly, this application provides a short-circuit protection system, which includes a three-phase inverter bridge, a high-speed sampling module, and a central processing module. This architecture, without increasing the power loss of the main circuit, uses high common-mode rejection differential sampling and hardware-level pipelined computation to concretize the aforementioned endogenous slope prediction logic into a highly reliable physical entity.

[0012] Optionally, the high-speed sampling module includes a differential amplifier architecture with a high common-mode rejection ratio. The differential amplifier architecture includes: a pair of high-voltage isolation resistors, one end of which is connected to the collector and emitter of the lower bridge arm insulated-gate bipolar transistor, and the other end of which is connected to the input of the differential amplifier; a second-order active low-pass filter, which is connected in series at the output of the differential amplifier, and the cutoff frequency of the second-order active low-pass filter is configured within a set ratio range of the preset sampling frequency; a transient voltage suppressor and a clamping diode group, which are respectively disposed at the input of the differential amplifier and at the signal input of the analog-to-digital converter included in the high-speed sampling module.

[0013] Optionally, the central processing module includes a field-programmable gate array or a digital signal processor, and the central processing module is internally configured with a hardware acceleration logic unit; a direct memory access channel is configured between the high-speed sampling module and the central processing module, and the direct memory access channel is used to transmit the sampled data to the high-speed register array in real time for the hardware acceleration logic unit to perform pipelined calculations.

[0014] This application has the following beneficial effects: By constructing a digital differential system with dual judgment logic and an extremely narrow time window, this application significantly reduces the total response time of short circuit protection from hundreds of microseconds to the sub-microsecond level. At the same time, the system also has the ability to be immune to and distinguish between startup surges and actual short circuits, changing the protection performance of the water pump frequency converter from passive loss prevention after power failure to active empowerment, extending the service life of the power module and ensuring the continuous and safe operation of the fluid transportation system. Attached Figure Description

[0015] Figure 1 A schematic diagram of the overall process for identifying a pump frequency converter short circuit based on the voltage drop slope of the IGBT body diode is provided in this application.

[0016] Figure 2 A schematic diagram of the high-speed sampling circuit provided in this application;

[0017] Figure 3 The logic diagram for short-circuit fault determination provided in this application;

[0018] Figure 4 The waveform diagrams showing the comparison of the body diode voltage drop slope under different operating conditions provided in this application are shown. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0021] This embodiment provides a method for identifying short circuits in water pump frequency converters based on the slope of the IGBT body diode voltage drop. In a specific implementation, this method employs a hardware-software collaborative architecture that extracts and calculates the rate of change of the forward voltage drop of the body diode in real time during the turn-off freewheeling phase of the insulated gate bipolar transistor (IGBT). This enables rapid identification of abnormal current surges based on the transient waveform characteristics of the rate of change and a programmable time window. This method solves the technical problems of severe protection response lag, high hardware cost, and easy false triggering caused by startup surges in existing technologies based on absolute amplitude detection by current sensors. It achieves the beneficial effects of short circuit interruption within sub-microsecond delays, shielding normal high-amplitude surge fluctuations, and eliminating the need for external high-power sensing elements.

[0022] S100 captures in real time the first positive voltage drop signal generated by the insulated gate bipolar transistor in the lower arm of the power bridge arm during the inductive load freewheeling phase.

[0023] The water pump frequency converter controller includes a core three-phase inverter bridge that performs energy conversion. This three-phase inverter bridge is constructed from six power branches. Each three-phase inverter bridge comprises three independent phase arms, each equipped with an upper-arm insulated-gate bipolar transistor (IGBT) and a corresponding lower-arm IGBT. The lower-arm IGBT has a body diode physically integrated in reverse parallel within its internal silicon wafer structure. This body diode exhibits unidirectional conductivity. During the normal switching cycle of a pulse-width modulation (PWM) signal, when a central processing module applies a low-level turn-off command to the gate of the lower-arm IGBT, the main conductive channel of the lower-arm IGBT quickly closes. Simultaneously, the upper-arm IGBT, due to being in a set dead-time locked state or a specific space vector turn-off state, also maintains its main conductive channel blocked. Because the stator winding of the water pump motor exhibits significant inductive load characteristics, according to the law of electromagnetic induction, the magnetic field energy stored in the leakage inductance and magnetizing inductance of the stator winding must be released through a closed physical circuit to maintain the continuity of the phase current. The release path of this phase current is forced to shift to the body diode inside the lower bridge arm insulated-gate bipolar transistor (IGBT). Under this forced injection of reverse phase current, the body diode enters a natural forward conduction state. This natural forward conduction state establishes a potential difference between the collector and emitter of the lower bridge arm IGBT with a polarity opposite to that of normal conduction; this potential difference is defined as the first forward voltage drop signal. The physical essence of the first forward voltage drop signal is the superposition of the barrier voltage drop of the body diode and the base region bulk resistance voltage drop.

[0024] Those skilled in the art should understand that the basic hardware entities involved in this embodiment, such as the three-phase inverter bridge, insulated gate bipolar transistor, and conventional signal processing controller, can all be implemented using mature standardized topologies in the field of power electronics and motor drives. Therefore, their internal transistor-level schematics will not be described in detail here.

[0025] Due to the rapid surge in current under short-circuit conditions, the minority carrier injection concentration and distribution gradient in the base region inside the body diode will undergo drastic transient reconstruction. The first forward voltage drop signal maps this dynamic change in microscopic carrier concentration. To extract the weak transient reconstruction signal, the method includes using a high-speed sampling module connected in parallel to the collector and emitter networks of the lower bridge arm insulated-gate bipolar transistor. The high-speed sampling module includes a first-stage high-voltage impedance matching network, a second-stage differential operational amplifier network, and a third-stage analog-to-digital converter network. The first-stage high-voltage impedance matching network blocks the common-mode DC bus voltage of several hundred volts. The second-stage differential operational amplifier network extracts millivolt-level voltage drop fluctuations with an extremely high common-mode rejection ratio. The third-stage analog-to-digital converter network converts the continuous analog voltage drop into digital dimensions for subsequent logic operations.

[0026] For example, the three-phase inverter bridge has a bus voltage of It operates in a DC network. The lower bridge arm insulated gate bipolar transistor is at a rated current of The load state. When the lower bridge arm insulated gate bipolar transistor is in Upon receiving a shutdown command, the stator leakage inductance of the water pump motor is forcibly reduced. The freewheeling current flows through the body diode. The body diode enters the conducting state. The first-stage high-voltage impedance matching network includes two diodes with resistance values ​​of... A high-voltage thin-film resistor. The second-stage differential operational amplifier network receives the signal attenuated by the high-voltage thin-film resistor. During the stable freewheeling phase, a specific value is generated across the body diode. The first positive voltage drop signal. The differential operational amplifier network conditions it to a level suitable for the analog-to-digital converter. to Within the range, for example, output one The analog signal. When a phase-to-phase short-circuit fault occurs in the system, the equivalent parasitic inductance drops sharply, causing the freewheeling current to... Time The slope spikes dramatically. This extreme rate of current rise causes a rapid accumulation of base charge storage effect within the body diode, resulting in a dramatic change in its equivalent impedance. The first forward voltage drop signal is extremely short. From the inside Rapidly sinking to The analog output of the high-speed sampling module synchronously reflects this slope change, continuously feeding the voltage sequence containing fault frequency domain characteristics to the central processing module.

[0027] S200, during the effective freewheeling period after the lower bridge arm insulated gate bipolar transistor is turned off, the first forward voltage drop signal is continuously sampled at a preset sampling frequency to obtain a discrete voltage sequence containing multiple sampling points.

[0028] S210, the sampling start point of the effective freewheeling period is set within the first preset delay time window after the falling edge of the gate drive signal of the lower bridge arm insulated gate bipolar transistor.

[0029] The falling edge of the gate drive signal switching from high to low marks the start of the insulated-gate bipolar transistor (IGBT) turn-off process. At this instant, a severe resonance process occurs in the main circuit caused by stray inductance and junction capacitance. This resonance process leads to high-frequency, high-amplitude voltage overshoot and oscillating circulating current between the collector and emitter. The voltage signal generated in this region cannot accurately reflect the steady-state or quasi-steady-state conduction physical characteristics of the body diode. The method includes employing a masking interval mechanism set at a specific timing. The first preset delay time window is used to force the analog-to-digital conversion network to remain dormant or ignore its conversion results during this period of strong electromagnetic interference. The starting point of the first preset delay time window is aligned with the starting point of the falling edge of the gate drive signal. The length of the first preset delay time window is finely configured to be greater than the sum of the IGBT tail current decay time and the parasitic oscillation decay time.

[0030] For example, the central processing module issues a falling-edge trigger command. The gate drive signal voltage from Scroll down The first preset delay time window is configured as follows: .exist to Within the range, the collector-emitter voltage experiences a change from... arrive The blocked ascent and accompanied by high altitude The spike overshoot. The analog-to-digital conversion network here... No data is recorded during this period. Until... At a certain moment, the internal high-speed counter overflows and releases the sampling enable signal. At this point, the oscillation has completely decayed, and the body diode is in a stable freewheeling conduction trajectory, which is established as the true sampling start point.

[0031] S220, the sampling endpoint of the effective continuous current period is set within a second preset delay time window before the next pulse width modulation turn-on command is issued.

[0032] Similarly, as the next half-bridge conduction cycle approaches, when the gate of the upper or lower bridge arm begins to receive the pre-charge high-level signal, the charging current pulse of the drive circuit will also be coupled to the main power circuit through the Miller capacitance, causing the reference ground potential to bounce and signal glitches. The second preset delay time window is used to terminate the sampling operation in advance to ensure that the acquired dataset is absolutely pure. The effective freewheeling period is strictly clamped between the sampling start point and the sampling end point, forming a safe observation corridor that is only affected by the dynamics of the load current.

[0033] For example, it is known that the next pulse width modulation turn-on command will be... The second preset delay time window is configured as follows: The event manager logic of the central processing module is in The analog-to-digital conversion enable signal is deactivated precisely at the designated time. This establishes... The time is the sampling endpoint.

[0034] S230, within the time interval defined by the sampling start point and the sampling end point, the discrete voltage sequence is obtained according to the preset sampling frequency set within the first preset megahertz frequency range.

[0035] The preset sampling frequency must satisfy the Nyquist sampling theorem and be significantly higher than the fundamental frequency of the motor load and the carrier frequency of the pulse width modulation. The preset sampling frequency is designed to capture the sub-microsecond voltage ramp induced by the extremely high rate-of-rise current in the body diode. The analog-to-digital conversion network is driven by a direct memory access (DMA) controller, continuously performing quantization operations on peripheral clock cycles without consuming processor core computing resources. The converted discrete quantities are pipelined into a pre-allocated high-speed circular buffer. The set of data arranged chronologically within the circular buffer constitutes the discrete voltage sequence.

[0036] For example, the preset sampling frequency is set to The first preset megahertz frequency range is... Therefore, the sampling period is determined as follows: From the starting point To the finish line The duration of the composition is During the effective continuous flow period, the analog-to-digital conversion network performs a total of [number] operations. This is a sequential quantization. The discrete voltage sequence is represented by a one-dimensional array containing 11 values. Characterization. Under normal load, the contents of the array are specifically as follows: , , ...The changes in adjacent values ​​are minimal. However, under an output short-circuit fault, the array contents at the same time step become: , , The dramatic discretization difference of the discrete voltage sequence in the time domain provides a high-fidelity data foundation for subsequent digital differential logic.

[0037] S300, based on the voltage values ​​and sampling period of adjacent sampling points in the discrete voltage sequence, obtain the instantaneous voltage drop change rate.

[0038] The central processing module is internally configured with a dedicated hardware digital signal processing arithmetic logic unit. Whenever a new sampled value is updated in the circular buffer, the arithmetic logic unit is awakened by a hardware interrupt. The method includes using the finite difference method to perform discrete differentiation processing on the discrete voltage sequence.

[0039] The arithmetic logic unit first performs a read operation to extract the first voltage value corresponding to the current sampling time in the discrete voltage sequence. The first voltage value reflects the forward voltage drop state of the body diode at this moment. Next, the arithmetic logic unit extracts the second voltage value corresponding to the previous sampling time immediately adjacent to the current sampling time in the discrete voltage sequence through address offset.

[0040] The arithmetic logic unit uses a built-in adder to perform binary two's complement subtraction to obtain the difference between the first voltage value and the second voltage value. This difference represents the absolute increment of the signal within one atomic time tick. Subsequently, the arithmetic logic unit divides the difference by the sampling period, determined by the preset sampling frequency, to obtain the instantaneous voltage drop rate of change. Since the sampling period is a globally fixed constant in the hardware system, the division operation is optimized in the field-programmable gate array (FPGA) to multiply the difference by a fixed scaling factor, thereby ensuring that the calculation process is completed in a closed loop within a single-core clock cycle.

[0041] For example, assuming the preset sampling frequency is still Then the sampling period When a short circuit occurs in the system, in the... At each sampling time, the first voltage value is extracted. Extract the immediately preceding sampling time. The second voltage value The arithmetic logic unit first calculates the difference. Then, a division (multiplication scaling) operation is performed: instantaneous rate of change of pressure drop. .Should That is, it is pushed into the comparator network of the next step as a decision source.

[0042] S400, compare the absolute value of the instantaneous voltage drop change rate with a preset critical slope threshold, and perform dual judgment logic in combination with a preset time window threshold to output a short circuit fault judgment result.

[0043] In order to completely eliminate the deception of the protection logic by the high excitation current during the water pump motor startup process, the method constructs a two-dimensional joint defense mechanism of "amplitude-time", namely the dual judgment logic.

[0044] The comparison logic unit within the central processing module extracts the absolute value of the instantaneous voltage drop rate of change in real time. This absolute value conversion operation removes polarity interference caused by reverse current, focusing only on the drastic degree of voltage drop change. One end of the comparison logic unit receives this absolute value, and the other end is connected to a register containing a preset critical slope threshold. When the absolute value exceeds the critical slope threshold, an internal high-frequency timer / counter is triggered by an enable signal, starting to accumulate time from zero.

[0045] The system must determine whether the condition that the absolute value is greater than the critical slope threshold remains continuously true. This requires the instantaneous rate of change of voltage drop to maintain a monotonous, high-intensity surge to filter out isolated data glitches caused by spatial electromagnetic radiation or accidental analog-to-digital conversion flip errors. Once the absolute value of any cycle falls below the critical slope threshold, the internal timer counter is immediately reset. If so, the duration of the internal timer counter is accumulated. When the duration exceeds the time window threshold, the system logic gate array outputs a high-level state, generating a short-circuit fault determination result indicating a short-circuit fault at the output terminal.

[0046] For example, for a rated current of In a certain type of device, the critical slope threshold is calibrated as The time window threshold is configured as follows: (equivalent to needing to cross continuously) indivual (sampling period).

[0047] Scenario 1: At the moment of cold start-up of the water pump motor, a peak value is generated. The normal surge current. Due to the stator inductance. The strong suppression effect results in a gradual change in current. The calculated absolute value... .because The comparator does not flip, and the internal timer / counter remains silent. The system perfectly shields against surge-induced malfunctions.

[0048] Scenario 2: The contactor near the inverter actuates, generating high-frequency spatial radiation. The analog-to-digital converter is affected by this interference, and during a certain cycle, it outputs an absolute value. The distorted data. Because... The internal timer / counter starts, and the time taken is... However, in the next cycle, the interference disappeared, and the absolute value fell back to... Due to continuous condition failure and accumulated time The timer reset to zero, and the protection was not triggered.

[0049] Scenario 3: Hard short-circuit fault occurs. Absolute value of the first cycle. The timer started to The absolute value of the second period If the continuous condition is met, the timer will accumulate to... .because All AND gate ports of the dual-decision logic are set high. The hardware logic in... The level immediately flips within the delay, outputting the short-circuit fault determination result without any doubt.

[0050] S500, when the short-circuit fault determination result indicates that a short-circuit fault has occurred at the output terminal, a hardware interlock mechanism is triggered to block the drive signal of the power bridge arm.

[0051] At the moment the short-circuit fault determination result is obtained, the software-level interrupt response is still relatively slow due to the depth of the instruction pipeline and context switching. This method includes constructing a faster path using logic gates with purely hardware routing.

[0052] The digital logic core of the central processing module sends an emergency block command to the enable port of the driver chip controlling the power bridge arm through a hardware interlock channel (such as an error control pin) configured by the hardware interlock mechanism. This command does not pass through any software buffer registers in its propagation path. Upon receiving this low-level active signal, the driver chip, based on its internal totem-pole push-pull circuit structure, uses a low-impedance path to forcibly pull down the gate drive level of all insulated-gate bipolar transistors in the power bridge arm to a set negative voltage region (e.g., ...). or This forces the carriers in the conductive channel to be exhausted within microseconds, thus shutting off the short-circuit current.

[0053] While performing a shutdown operation on the lower-level hardware, the method simultaneously performs a synchronous blocking operation on the upper-level logic to block the signal output path of the pulse width modulation generator that provides control signals to the power bridge arm. The comparison match output pin of the core timer is forced to a high-impedance state. The system activates the direct memory access controller, completely moves the discrete voltage sequence data stored in the circular buffer when the short-circuit fault determination result is triggered, and writes it to the configured non-volatile memory module (such as EEPROM), forming a "black box" waveform slice at the time of the fault. Finally, a specially coded short-circuit fault status code is sent to the external monitoring terminal via the communication bus, and the entire inverter system is suspended into a deadlock protection state until manual physical reset intervention.

[0054] For example, when S400 is When a short circuit is confirmed, the hardware logic gate is in... Change the interlock pin level. The driver chip in Responds to and pulls all 6 drive signals low. The short-circuit current must rise before reaching the turn-off safe operating area boundary of the insulated-gate bipolar transistor (e.g., 5 times the rated current). The internal circuit was completely severed. Subsequently, a total of 20 sampling points, including those before and after the malfunction, were collected. When array data is consumed The entire data is written to the EEPROM. The bus broadcasts a data packet with the signature 0xEA05 to the host computer, indicating that the lower bridge arm has detected a fatal slope mutation anomaly.

[0055] Those skilled in the art should understand that the hardware interlocking logic gate circuits, the internal totem-pole push-pull circuits of the driver chip, the pulse width modulation generator, and the non-volatile memory modules involved in this step are all standard general-purpose devices in the existing digital circuit and power drive fields. Their specific internal transistor-level circuit structures or physical memory cell arrangements are conventional technical means in this field and will not be described in detail here.

[0056] S600, Dynamic Temperature Compensation Mechanism

[0057] The intrinsic physical properties of the body diode inside an insulated-gate bipolar transistor (IGBT) determine that its forward voltage drop characteristic exhibits a strong negative temperature dependence. Under high-temperature environments caused by long-term full-load operation, the intrinsic body diode voltage drop will decrease with increasing temperature. This can easily lead to severe calibration drift of the critical slope threshold originally calibrated at room temperature, potentially causing a decrease in protection sensitivity or even missed detection under high-temperature conditions. To overcome this limitation of semiconductor physics, this method deeply embeds junction temperature observation and dynamic parameter correction mechanisms into the short-circuit identification system, forming a closed-loop dynamic temperature compensation logic.

[0058] The method includes acquiring the current junction temperature of the lower-arm insulated-gate bipolar transistor (IGBT) in real time. A negative temperature coefficient (NTC) thermistor is surface-mount packaged on the power module substrate of the IGBT. A separate analog-to-digital conversion channel periodically scans the voltage across the thermistor at a low sampling frequency and maps it to a precise Celsius temperature using a built-in lookup table interpolation algorithm.

[0059] Those skilled in the art will understand that the voltage divider sampling circuit and corresponding independent analog-to-digital conversion channel for NTC thermistors described above are conventional temperature sensor hardware conditioning interfaces in the prior art, and can be implemented using standard resistor bridge or series voltage divider topologies. Therefore, their specific circuit diagrams will not be described in detail.

[0060] After obtaining the junction temperature, the central processing module constructs a temperature drift correction factor that varies linearly or non-linearly based on a preset reference temperature value, a preset temperature compensation coefficient, and the current junction temperature value. The reference temperature value is usually calibrated as the nominal laboratory temperature. The temperature compensation coefficient is provided by the power module manufacturer or obtained through experimental fitting in a constant temperature bath, reflecting the relative voltage drop offset corresponding to each degree Celsius temperature rise.

[0061] Within one processing cycle, the arithmetic logic unit extracts the calculated, uncompensated instantaneous voltage drop change rate from S300. Subsequently, a hardware multiplication instruction is executed to multiply the acquired instantaneous voltage drop change rate by the calculated temperature drift correction factor, generating a corrected instantaneous voltage drop change rate that is immune to temperature drift effects. Finally, the corrected instantaneous voltage drop change rate is substituted into the dual-determination logic described in S400, completely replacing the original value, and entered into the comparison network for comparison.

[0062] For example, the system reads the resistance value of the NTC thermistor as... The current junction temperature value is obtained through a table lookup algorithm. The preset reference temperature value is... The temperature compensation coefficient determined through preliminary experimental fitting is: .

[0063] The system first calculates the temperature drift correction factor, using the following formula: .

[0064] Substitute the values: (Dimensionless).

[0065] At this point, if the current original instantaneous pressure drop change rate is calculated in stage S300... .

[0066] Due to the high temperature, the absolute amplitude of the signal is compressed. The system generates a corrected rate of change of instantaneous voltage drop through a product operation:

[0067] .

[0068] Assume the critical slope threshold in S400 is fixed as If using uncorrected absolute values The system will experience short-circuit failures at high temperatures. However, using the corrected absolute value... Because the compensated values ​​were substituted and compared, the dual-judgment logic was correctly triggered, perfectly offsetting the impact on the Gundam. Sensitivity drift caused by temperature rise.

[0069] S700, Adaptive Sampling Logic Steps

[0070] In practical water pump speed control applications, the fundamental frequency of the inverter output voltage is constantly changing, which directly causes the duty cycle parameter of the pulse width modulation signal to fluctuate frequently over a wide range. This drastic change in duty cycle leads to significant stretching or compression of the time window (effective freewheeling period) left for the body diode to continue flowing after the insulated gate bipolar transistor (IGBT) is turned off. If a constant sampling point planning mechanism is maintained, massive amounts of redundant data will be generated and buffer resources will be consumed under extremely small duty cycles (extremely long freewheeling periods), while under extremely large duty cycles (extremely short freewheeling periods), insufficient sampling points may lead to differential logic failure. This method provides a closed-loop adaptive sampling logic step.

[0071] The method includes real-time acquisition of the current duty cycle parameter of the pulse width modulation signal. The control loop operation node within the central processing module actively broadcasts the current duty cycle register value to the protection management module each time a carrier update is interrupted.

[0072] The protection management module makes a branch judgment based on the received information: when the current duty cycle parameter is less than the preset duty cycle threshold, it means that the current state is a long continuous current state. At this time, the module dynamically adjusts the transfer count value of the direct memory access controller to increase the number of sampling points of the discrete voltage sequence. More sampling points give the system room to perform more in-depth noise reduction operations. The system will switch and execute the multi-point average slope calculation logic to use the calculated multi-point average slope value as the instantaneous voltage drop change rate into the dual judgment logic. That is, multiple consecutive (e.g., 5 or 7) sampling differences are summed in a sliding window and averaged to filter out small high-frequency random noise with an extremely excellent signal-to-noise ratio, greatly improving the stability during long-cycle operation.

[0073] Conversely, when the current duty cycle parameter is greater than or equal to the duty cycle threshold, it means that the follow-through time window has been extremely compressed, and time resources become the most critical constraint. At this time, the module immediately switches the sampling mode to the preset three-point fast sampling mode. The system intensively acquires three high-frequency data points within a very short time and uses the simplest first-to-last difference mode to quickly obtain the slope conclusion, abandoning lengthy filtering calculations and focusing all computing power on ensuring the real-time performance of the identification, resolutely preventing short-circuit features from escaping the narrow observation corridor.

[0074] For example, the preset duty cycle threshold is configured as follows: The pulse width modulation carrier period is .

[0075] Scenario A: The water pump is in a low-speed, constant-pressure water supply state, and the current duty cycle parameter obtained in real time is: .because The continuous flow time is extremely ample (theoretically up to 1000 hours). The system dynamically expands the number of sampling points to... Frame data. Execute multi-point average slope calculation logic: Take a window containing values ​​from 5 consecutive frames (e.g., frames 10 to 14), and calculate the instantaneous voltage drop rate of change within 4 adjacent periods (assuming it is...). ), calculate its average value Use Instead of using single-point interpolation to perform the judgment, it completely smooths out the issues caused by high-frequency parasitic inductance. Tiny burrs.

[0076] Scenario B: The water pump is instructed to operate at full speed at its rated high frequency, and the current duty cycle parameter spikes to [value missing]. .because The theoretical follow-through time has been compressed to an extreme degree. Left and right. After removing the delayed occlusion windows before and after, the total effective sampling window time is less than [amount missing]. At this point, the system immediately switches to three-point fast sampling mode. Within the allowed time slot, it samples at the highest... Frequency is quickly latched and read only Frame voltage data: The arithmetic logic unit skips any filtering loops and proceeds directly from the formula. Within a single clock cycle, a slope scalar containing the averaging effect is obtained rapidly and aggressively, and then pushed into the threshold comparator without hesitation, successfully safeguarding the safety baseline of short-circuit protection under extreme time pressure.

[0077] To ensure the complex computational logic involved in this specific embodiment is clearly explained, the reference unit system for each parameter in the core mathematical and physical computational model adopted in this application is defined here. The voltage signal dimensions (such as the first positive voltage drop signal, discrete voltage values, etc.) are all expressed in standard volts (V) or millivolts (mV); the time metrics (including sampling period, time window threshold, delay time, etc.) are uniformly specified in microseconds (μs) or nanoseconds (ns) to match the high-speed sampling frequency; the transient derived dimensions—instantaneous voltage drop change rate and critical slope threshold—derived from the above two items through differential operations are in volts per microsecond (V / μs). In the temperature compensation model, the physical dimension of the junction temperature and the reference temperature is degrees Celsius (°C), while the dimension of the compensation coefficient is (1 / °C), and the compensation factor generated by their product is a purely dimensionless scalar without physical units.

[0078] This embodiment further provides a short-circuit protection system. The system uses a set of solid-state hardware entities to transform the abstract computational process defined by software instructions into physically executable microscopic electrical signal flows. The short-circuit protection system is explicitly configured to execute the logical flows of the various method embodiments described above.

[0079] In the following description of the system embodiments, those skilled in the art should understand that, for the basic functional modules constituting the short-circuit protection system, unless specific parameter configurations or connection relationships are specifically specified, the specific underlying hardware implementation methods (such as internal transistor-level schematics, specific chip package models, etc.) of circuit units such as operational amplifiers, analog-to-digital converters, low-pass filters, and logic gate arrays can all be directly constructed using standard commercial circuits or chip architectures that are generally mature in the relevant technical fields. The essence of this application lies in the specific combination and timing coordination of these standardized hardware nodes based on a novel slope determination logic. Therefore, in order to maintain the conciseness of the application documents and avoid obscuring the core focus of the present invention, the following will focus on describing the logical connection relationships and signal interaction links between the hardware modules, rather than exhaustively listing the microscopic physical structures of the basic circuits.

[0080] The energy exchange core of the short-circuit protection system is a three-phase inverter bridge. The three-phase inverter bridge consists of a DC bus capacitor bank, three parallel, large-section, multi-layered busbars, and six sets of half-bridge insulated-gate bipolar transistor (IGBT) modules pressed onto a heat sink. Each phase lower arm of the three-phase inverter bridge is equipped with an IGBT with an integrated body diode; it serves as both a valve for system energy output and a natural, low-cost sensing node for this identification method.

[0081] To establish a high-fidelity data path for sensing nodes operating under severe electromagnetic pulse conditions, the system is equipped with a high-speed sampling module constructed from a multilayer anti-interference printed circuit board. This high-speed sampling module is physically connected in parallel to the collector and emitter pins of the lower bridge arm insulated-gate bipolar transistor (IGBT) to extract and acquire the weak first forward voltage drop signal in real time. The high-speed sampling module includes a complex analog front-end processing chain.

[0082] Specifically, a step-down attenuation network comprising a pair of high-voltage isolation resistors is configured at the entry point of the analog front-end processing link. One end of the pair of high-voltage isolation resistors is directly soldered to the collector and emitter of the lower bridge arm insulated-gate bipolar transistor using extremely short traces, while the other end is led out in parallel and connected to the input of the differential amplifier. The differential amplifier architecture has a high common-mode rejection ratio exceeding 100 dB, which can strongly reject co-current interference caused by common-mode ground bounce.

[0083] Between the output of the differential amplifier and the reference ground, the hardware engineer serially installed a second-order active low-pass filter. This second-order active low-pass filter consists of a precision operational amplifier and a low-temperature coefficient resistor-capacitor matrix. To perfectly match the Nyquist frequency limits of the back-end digital acquisition, the cutoff frequency of the second-order active low-pass filter is strictly and rigidly configured by the hardware component parameters within a set percentage range of the preset sampling frequency (typically set between 40% and 45% of the sampling frequency), forming a physical barrier against aliasing.

[0084] Furthermore, as the last line of hardware defense under extreme operating conditions, the ingress network is densely packed with overvoltage suppression components. Transient voltage suppressors are soldered in parallel after the high-voltage isolation resistor to absorb peak avalanche energy from surges in the main circuit. Clamping diode groups (composed of ultra-low dropout Schottky diodes) are connected in reverse parallel at the input of the differential amplifier and at the vulnerable signal input of the analog-to-digital converter included in the high-speed sampling module, clamping any abnormal signals exceeding the safe voltage limit to the chip's physical tolerance limit (e.g., ...). to )Inside.

[0085] The command and control center of the short-circuit protection system is a highly integrated central processing module. This central processing module maintains a stable and high-speed communication connection with the high-speed sampling module and the drive control chip of the three-phase inverter bridge through differential signal traces and optocoupler isolation channels. The central processing module is a silicon chip containing a field-programmable gate array (FPGA) digital core or a high-performance multi-core digital signal processor (DSP) chip.

[0086] To address the time overhead caused by soft interrupt calls in traditional processor architectures, the central processing module (CPU) utilizes a dedicated hardware acceleration logic unit built using a hardware description language to allocate silicon area. Furthermore, a direct memory access (DMA) channel, directly connecting to the data layer, is allocated and activated between the high-speed sampling module (specifically referring to the high-speed analog-to-digital converter chip peripheral) and the CPU. This DMA channel is specifically designed to continuously transfer and transmit the sampled data bus stream to a high-speed register array within a specific address space within the field-programmable gate array (FPGA) without disrupting the core processing cycle.

[0087] Once the high-speed register array accumulates data meeting the preset quantity (such as the three or more points mentioned in the aforementioned adaptive sampling), the system's built-in pipeline architecture immediately performs a single-cycle subtraction (calculating the instantaneous voltage drop rate of change) and multiple parallel comparator matrices (performing the dual determination logic of absolute value comparison and cumulative time window determination) through hard-wired logic gates. This pure hardware interlock architecture, which eliminates software intervention from analog signal acquisition and memory relocation to feature comparison, compresses the total execution clock cycle of the protection loop to the extreme range of tens of nanoseconds. Combined with the inherent tens of nanoseconds shutdown delay of the peripheral driver IC, it exhibits a total response performance of less than one microsecond (sub-microsecond level) on a macroscopic time scale, constructing a defensive entity for extreme short-circuit conditions. In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units mentioned above can be implemented in hardware.

[0088] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for identifying short circuits in water pump frequency converters based on the voltage drop slope of the IGBT body diode, characterized in that, The method includes: Real-time capture of the first positive voltage drop signal generated by the insulated gate bipolar transistor in the lower arm of the power bridge arm during the inductive load freewheeling phase; During the effective freewheeling period after the lower bridge arm insulated gate bipolar transistor is turned off, the first positive voltage drop signal is continuously sampled at a preset sampling frequency to obtain a discrete voltage sequence containing multiple sampling points. Based on the voltage values ​​and sampling period of adjacent sampling points in the discrete voltage sequence, the instantaneous voltage drop change rate is obtained; The absolute value of the instantaneous voltage drop change rate is compared with a preset critical slope threshold, and a dual judgment logic is executed in combination with a preset time window threshold to output a short circuit fault judgment result. When the short-circuit fault determination result indicates that a short-circuit fault has occurred at the output terminal, a hardware interlock mechanism is triggered to block the drive signal of the power bridge arm.

2. The method according to claim 1, characterized in that, During the effective freewheeling period after the lower bridge arm insulated gate bipolar transistor is turned off, the first forward voltage drop signal is continuously sampled at a preset sampling frequency to obtain a discrete voltage sequence containing multiple sampling points, including: The sampling start point of the effective freewheeling period is set within the first preset delay time window after the falling edge of the gate drive signal of the lower bridge arm insulated gate bipolar transistor; The sampling endpoint of the effective continuous current period is set within the second preset delay time window before the next pulse width modulation turn-on command is issued; Within the time interval defined by the sampling start point and the sampling end point, the discrete voltage sequence is obtained according to the preset sampling frequency set within the first preset megahertz frequency range.

3. The method according to claim 1, characterized in that, Based on the voltage values ​​and sampling periods of adjacent sampling points in the discrete voltage sequence, the instantaneous voltage drop rate of change is obtained, including: Extract the first voltage value corresponding to the current sampling time from the discrete voltage sequence; Extract the second voltage value from the discrete voltage sequence corresponding to the previous sampling time that is immediately adjacent to the current sampling time; Obtain the difference between the first voltage value and the second voltage value; Divide the difference by the sampling period determined by the preset sampling frequency to obtain the instantaneous voltage drop change rate.

4. The method according to claim 1, characterized in that, The absolute value of the instantaneous voltage drop change rate is compared with a preset critical slope threshold, and a dual-judgment logic is performed in conjunction with a preset time window threshold to output a short-circuit fault determination result, including: The absolute value of the instantaneous rate of change of pressure drop is extracted in real time; When the absolute value is greater than the critical slope threshold, the internal timer counter is started to accumulate the time. Determine whether the condition that the absolute value is greater than the critical slope threshold remains continuously true; If so, the duration of the internal timer counter is accumulated, and when the duration exceeds the time window threshold, a short-circuit fault determination result indicating that a short-circuit fault has occurred at the output terminal is generated.

5. The method according to claim 1, characterized in that, The method further includes a dynamic temperature compensation step, which includes: The current junction temperature of the lower bridge arm insulated gate bipolar transistor is obtained in real time. A temperature drift correction factor is constructed based on a preset reference temperature value, a preset temperature compensation coefficient, and the current junction temperature value. The obtained instantaneous pressure drop change rate is multiplied by the temperature drift correction factor to generate the corrected instantaneous pressure drop change rate. The corrected instantaneous pressure drop rate is substituted into the dual-determination logic for replacement comparison.

6. The method according to claim 1, characterized in that, When the short-circuit fault determination result indicates that a short-circuit fault has occurred at the output terminal, a hardware interlock mechanism is triggered to block the drive signal of the power bridge arm, including: An emergency blocking command is sent to the driver chip controlling the power bridge arm through the hardware interlock channel configured by the hardware interlock mechanism. Based on the emergency shutdown command, the gate drive level of all insulated gate bipolar transistors in the power bridge arm is forcibly pulled low; Synchronous blocking of the signal output path of the pulse width modulation generator that provides control signals to the power bridge arm; The discrete voltage sequence data that triggers the short-circuit fault determination result is written into the configured non-volatile storage module, and the short-circuit fault status code is sent to the external monitoring terminal.

7. The method according to claim 1, characterized in that, The method further includes an adaptive sampling logic step, which includes: Real-time acquisition of the current duty cycle parameter of the pulse width modulation signal; When the current duty cycle parameter is less than the preset duty cycle threshold, the number of sampling points of the discrete voltage sequence is increased, and the multi-point average slope calculation logic is executed so that the calculated multi-point average slope value is used as the instantaneous voltage drop change rate and substituted into the dual judgment logic. When the current duty cycle parameter is greater than or equal to the duty cycle threshold, the sampling mode is switched to the preset three-point fast sampling mode.

8. A short-circuit protection system, characterized in that, The short-circuit protection system is configured to perform the pump frequency converter short-circuit identification method based on the IGBT body diode voltage drop slope as described in any one of claims 1 to 7, and the short-circuit protection system includes: A three-phase inverter bridge, wherein each lower bridge arm of the three-phase inverter bridge is provided with a lower bridge arm insulated gate bipolar transistor with an integrated body diode; A high-speed sampling module is connected in parallel to the collector and emitter of the lower bridge arm insulated gate bipolar transistor to acquire the first forward voltage drop signal. The central processing module is communicatively connected to the high-speed sampling module and the three-phase inverter bridge. The central processing module is configured to perform continuous voltage sampling, calculate the instantaneous voltage drop rate of change, and execute the dual-determination logic.

9. The short-circuit protection system according to claim 8, characterized in that, The high-speed sampling module includes a differential amplification architecture with a high common-mode rejection ratio, the differential amplification architecture comprising: A pair of high-voltage isolation resistors, one end of which is connected to the collector and emitter of the lower bridge arm insulated gate bipolar transistor, and the other end of which is connected to the input terminal of the differential amplifier; A second-order active low-pass filter is connected in series at the output of the differential amplifier, and the cutoff frequency of the second-order active low-pass filter is configured to be within a set ratio range of the preset sampling frequency. A transient voltage suppressor and a clamping diode group are respectively configured at the input terminal of the differential amplifier and at the signal input of the analog-to-digital converter included in the high-speed sampling module.

10. The short-circuit protection system according to claim 8, characterized in that, The central processing module includes a field-programmable gate array or a digital signal processor, and the central processing module is internally configured with a hardware acceleration logic unit; a direct memory access channel is configured between the high-speed sampling module and the central processing module, and the direct memory access channel is used to transmit the sampled data to the high-speed register array in real time for the hardware acceleration logic unit to perform pipelined calculations.

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