Low-cost low-speed usb circuit control method

Abstract

This invention discloses a low-cost, low-speed USB circuit control method. It collects bus transmission timing signals, port voltage fluctuation data, and peripheral access status information through an embedded USB fault diagnosis platform to construct a multi-dimensional operational dataset. Based on a differential timing coupling mapping model, it mines the nonlinear coupling relationship of timing signals. A low-speed bus power consumption balancing model regulates power distribution, and a hardware timing error correction algorithm compensates for timing deviations. A low-cost control module converts the corrected parameters into hardware drive signals to achieve data transmission and peripheral control. The fault diagnosis platform monitors operational feedback data in real time and dynamically adjusts model parameters and control strategies. This method eliminates the need for high-cost dedicated chips and solves the problems of accumulated timing deviations and uneven power distribution in traditional methods through multi-model collaboration and closed-loop control. It reduces hardware costs while improving circuit control accuracy, stability, and operational efficiency.

Description

Technical Field

[0001] This invention relates to the field of USB circuit control technology, and in particular to a low-cost, low-speed USB circuit control method. Background Technology

[0002] With the increasing application of low-speed USB interfaces in various low-cost electronic devices, the stability of their circuit control, the rationality of power consumption, and the real-time nature of fault diagnosis have become core directions for technological optimization. Currently, low-speed USB circuits often face challenges such as transmission timing being easily affected by the number of peripherals connected and voltage fluctuations. Furthermore, traditional control schemes rely on high-cost dedicated chips or complex algorithm frameworks, resulting in high hardware costs and making it difficult to meet the low-cost design requirements of small and medium-sized electronic devices. Simultaneously, in scenarios with multiple peripherals connected concurrently, low-speed USB circuits frequently experience problems such as uneven bus power distribution and accumulated timing deviations, affecting data transmission reliability. Existing control methods often lack a coordinated regulation mechanism for timing coupling relationships and power consumption balance, necessitating the development of an integrated solution that balances low cost and control accuracy.

[0003] Existing technologies have two significant drawbacks: First, the timing control accuracy is insufficient. Traditional methods often employ single-dimensional timing correction strategies, failing to fully consider the nonlinear coupling relationships between bus transmission timing, clock signal timing, and synchronization signal timing. This makes it impossible to accurately capture timing deviations caused by the superposition of multiple factors, and it lacks a dynamic adaptive error correction mechanism, causing the accumulation of timing deviations to affect data transmission stability. Second, the power consumption allocation is not reasonable. Existing solutions have not established a power balancing model adapted to scenarios with multiple peripherals connected, but only adjust the power output based on a fixed power allocation strategy. This results in insufficient power supply to some peripherals under high load conditions and wasted power consumption under low load conditions. At the same time, it does not combine port voltage fluctuations and peripheral equivalent impedance characteristics for dynamic power consumption adjustment, making it difficult to achieve a balance between power consumption and performance under low-cost hardware architectures. Summary of the Invention

[0004] In order to overcome the shortcomings and deficiencies of the existing technology, the present invention provides a low-cost, low-speed USB circuit control method.

[0005] The technical solution adopted in this invention is a low-cost, low-speed USB circuit control method, comprising the following steps: S1, collecting bus transmission timing signals, port voltage fluctuation data, and peripheral access status information of the low-speed USB circuit through an embedded USB fault diagnosis platform to establish a multi-dimensional circuit operation status dataset; S2, performing dynamic correlation analysis on the collected bus transmission timing signals based on a differential timing coupling mapping model to mine the nonlinear coupling relationship between timing signals and generate timing feature vectors; S3, using a low-speed bus power consumption balancing model to fuse port voltage fluctuation data and peripheral access status information, and adjusting the output power allocation strategy of the circuit power supply module; S4, using a hardware timing error correction algorithm to perform error compensation calculation on the timing feature vector and power allocation strategy execution results to correct circuit transmission timing deviations; S5, using a low-cost, low-speed USB circuit control module to convert the corrected timing parameters and power allocation scheme into hardware drive signals to drive the circuit to complete data transmission and peripheral control operations; S6, the embedded USB fault diagnosis platform monitors the circuit operation feedback data in real time, compares and analyzes it with preset thresholds, and dynamically adjusts model parameters and control strategies.

[0006] Furthermore, the expression for the differential temporal coupling mapping model is: ,

[0007] in, These are the differential timing coupling coefficients. These are the time-series weighting coefficients. For data transmission timing difference, For data reception timing difference, This is the timing difference of the clock signal. For the timing difference of the synchronization signal, This is the coupling adjustment coefficient. This refers to the bus transmission delay time. For peripheral response delay time, This is the timing synchronization phase angle.

[0008] Furthermore, the expression for the low-speed bus power consumption balancing model is: ,

[0009] in, To balance the output power, This is the power consumption adjustment coefficient. This is the actual voltage at the port. This is the bus load current. Let i be the equivalent resistance of the i-th peripheral. Let i be the equivalent capacitance of the i-th peripheral. This is the power compensation coefficient. This represents the circuit's maximum output power. This represents the current actual power consumption. The attenuation coefficient is... This represents the current number of connected peripherals. The number of peripherals is the baseline.

[0010] Furthermore, the expression for the hardware timing error correction algorithm is as follows: ,

[0011] in, This is the corrected timing error. This is the error correction factor. This represents the measured timing error. The angular frequency of the clock signal. This is the phase error value. This is the cumulative correction factor. Let be the error component of the j-th time-series node. Let be the phase offset angle of the j-th timing node. This represents the total number of time-series nodes.

[0012] Furthermore, the state monitoring model expression of the embedded USB fault diagnosis platform is as follows: ,

[0013] in, For condition monitoring index, For voltage monitoring weights, This is the actual voltage of the external device. This is the standard voltage value. For time-series monitoring weights, This is the actual transmission time. For standard transmission time, As the fault monitoring weight, For the number of faulty data frames, This represents the total number of data frames transmitted.

[0014] Furthermore, the drive signal generation model of the low-cost, low-speed USB circuit control module is as follows: ,

[0015] in, For hardware-driven signal strength, For driving coefficients, To correct the timing parameters, To balance output power, To control the equivalent resistance of the circuit, For signal amplitude coefficients, The driving signal angular frequency is t, where t is the time variable. This refers to the amount of data transmitted.

[0016] Further, step S2 includes the following sub-steps: S21, extracting the rising edge trigger time, falling edge trigger time, and signal duration calibration timing parameters from the bus transmission timing signal to construct an initial timing dataset; S22, dividing the initial timing dataset into a transmitting end timing subset and a receiving end timing subset according to the transmission direction, and calculating the timing statistical feature values ​​of the two subsets respectively; S23, calculating the coupling strength between different timing parameters through a differential timing coupling mapping model, and removing redundant parameters with coupling strength lower than a set threshold; S24, performing feature fusion on the filtered timing parameters to generate a timing feature vector with uniform dimension, providing data support for subsequent error correction.

[0017] Further, S3 includes the following sub-steps: S31, performing sliding window sampling on the port voltage fluctuation data to obtain voltage peak, valley, and average voltage characteristic parameters; S32, statistically analyzing the peripheral type, access sequence, and operating mode in the peripheral access status information to establish a peripheral power consumption requirement database; S33, inputting the voltage characteristic parameters and peripheral power consumption requirement data into the low-speed bus power consumption balancing model to calculate the optimal power allocation ratio for each peripheral; S34, generating power supply module control commands based on the power allocation ratio to adjust the output voltage and current allocation scheme of the power supply circuit.

[0018] Further, step S4 includes the following sub-steps: S41, collecting actual timing data during circuit transmission, comparing it with standard timing data, and calculating the initial timing error value; S42, analyzing the distribution characteristics of the initial timing error and determining whether the error source is clock drift, transmission delay, or synchronization deviation; S43, based on the hardware timing error correction algorithm, selecting the corresponding correction strategy for different error sources and calculating the error compensation amount; S44, superimposing the error compensation amount into the original timing parameters to generate corrected timing control parameters, thereby reducing the impact of timing deviation on transmission performance.

[0019] Further, S5 includes the following sub-steps: S51, receiving the corrected timing parameters and power allocation scheme, and parsing the control logic and parameter thresholds therein; S52, converting the parsed control information into digital control signals, and transmitting them to the low-cost drive circuit through the I / O interface; S53, the drive circuit adjusts the conduction state of the internal switching transistors and the parameters of the filter circuit according to the digital control signals to generate hardware drive signals adapted to the peripherals; S54, transmitting the hardware drive signals to the USB port and peripheral interface to control the peripheral startup, data transmission and state switching operations, and complete the circuit control closed loop.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] This invention proposes a low-cost, low-speed USB circuit control method, achieving cost reduction in low-speed USB circuit control without relying on high-cost dedicated chips. By simplifying the hardware architecture and optimizing algorithm logic, it reduces design and application costs while significantly improving control accuracy and stability. It deeply mines the nonlinear correlations of various timing signals through a differential timing coupling mapping model, accurately capturing the root causes of timing deviations. Combined with a hardware timing error correction algorithm, it specifically compensates for errors, effectively overcoming the shortcomings of traditional methods such as singular timing control and accumulated deviations. Simultaneously, a low-speed bus power consumption balancing model integrates port voltage fluctuations and peripheral status data to dynamically adjust the power allocation strategy, achieving reasonable power distribution in scenarios with multiple peripheral connections. This solves the problems of fixed power distribution, insufficient power supply under high loads, and wasted power under low loads in existing technologies. Furthermore, the real-time monitoring and dynamic parameter tuning mechanism of the fault diagnosis platform ensures that the control strategy adaptively optimizes according to the circuit's operating state, further improving data transmission reliability and circuit operating efficiency, comprehensively considering both low-cost characteristics and high-performance requirements. Attached Figure Description

[0022] Figure 1 This is a flowchart illustrating the overall process of the method of the present invention.

[0023] Figure 2 This is a flowchart of method step S2 of the present invention;

[0024] Figure 3 This is a flowchart of method step S3 of the present invention;

[0025] Figure 4 This is a flowchart of method step S4 of the present invention;

[0026] Figure 5 This is a flowchart of step S5 of the method of the present invention;

[0027] Figure 6 This is a circuit diagram of the USB receiver control circuit of the present invention;

[0028] Figure 7 This is a circuit diagram of the USB transmission control circuit of the present invention. Detailed Implementation

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] like Figure 1As shown, a low-cost, low-speed USB circuit control method includes the following steps: S1, collecting bus transmission timing signals, port voltage fluctuation data, and peripheral access status information of the low-speed USB circuit through an embedded USB fault diagnosis platform to establish a multi-dimensional circuit operation status dataset; S2, performing dynamic correlation analysis on the collected bus transmission timing signals based on a differential timing coupling mapping model to mine the nonlinear coupling relationship between timing signals and generate timing feature vectors; S3, using a low-speed bus power consumption balancing model to fuse port voltage fluctuation data and peripheral access status information, and adjusting the output power allocation strategy of the circuit power supply module; S4, using a hardware timing error correction algorithm to perform error compensation calculation on the timing feature vector and power allocation strategy execution results to correct circuit transmission timing deviations; S5, using a low-cost, low-speed USB circuit control module to convert the corrected timing parameters and power allocation scheme into hardware drive signals to drive the circuit to complete data transmission and peripheral control operations; S6, the embedded USB fault diagnosis platform monitors the circuit operation feedback data in real time, compares and analyzes it with preset thresholds, and dynamically adjusts model parameters and control strategies.

[0031] The core implementation of step S1 involves using an embedded USB fault diagnosis platform to acquire multi-dimensional circuit operation data and construct a dataset. This platform integrates a signal acquisition module, a data storage unit, and an interface adapter circuit, adaptable to the port specifications of different types of low-speed USB circuits. During acquisition, the signal acquisition module continuously captures bus transmission timing signals at a fixed sampling frequency, set between 100kHz and 500kHz, to ensure accurate capture of subtle changes in timing signals. Simultaneously, it acquires port voltage fluctuation data, with voltage acquisition accuracy controlled within ±0.01V, covering the typical operating voltage range of low-speed USB circuits. Peripheral access status information is acquired in real time through the platform's interface detection unit, including data such as the number of peripherals connected, access duration, and plug / unplug status. The interface detection unit's response time is no more than 1ms to avoid missing instantaneous access status. The acquired bus transmission timing signals include key timing points such as data transmission time, reception time, and clock synchronization signal trigger time. Port voltage fluctuation data includes parameters such as real-time voltage value, voltage change rate, and peak voltage occurrence time. Peripheral access status information includes peripheral identifier and working mode request. The three types of data mentioned above are aligned and integrated according to timestamps. After removing invalid data and outliers, a multi-dimensional circuit operation status dataset is established. The dataset includes no less than 10 feature items, including timing dimension, voltage dimension, and peripheral status dimension. This provides comprehensive and accurate data support for subsequent model analysis, ensuring that the subsequent control strategy is based on the real and complete circuit operation status.

[0032] Step S2 performs dynamic correlation analysis on the acquired bus transmission timing signals based on the differential timing coupling mapping model, uncovering nonlinear coupling relationships and generating timing feature vectors. In this process, the bus transmission timing signals are first preprocessed by removing high-frequency noise and interference signals using a signal filtering unit. The filter cutoff frequency is set to 10kHz to retain the effective characteristics of the timing signals. Subsequently, the model decomposes the preprocessed timing signals into multiple dimensions, extracting independent timing parameters such as data transmission timing, reception timing, clock signal timing, and synchronization signal timing. Then, it calculates the differential data between each timing parameter, including the time difference and rate of change difference between different timing parameters. Using the model's built-in coupling relationship analysis algorithm, nonlinear correlation calculations are performed on the differential data, focusing on analyzing the mutual influence between transmission and reception timing, and between clock and synchronization timing. This captures the dynamic coupling characteristics of timing signals as the number of peripherals connected changes and voltage fluctuations. This analysis process uses an iterative calculation method, with the number of iterations set to 50 to 100 to ensure the sufficiency of coupling relationship discovery. During the correlation analysis, the model automatically identifies key coupling nodes in the time series signal, records the coupling strength and influence weight of each node, and eliminates weak correlations with coupling strength below a set threshold. The threshold is dynamically adjusted based on the circuit's operating scenario, ranging from 0.1 to 0.3. Finally, feature extraction and vector transformation are performed on the time series parameters corresponding to the filtered effective coupling relationships. The coupling characteristics, trend characteristics, and key node characteristics of the time series signal are quantified into numerical indicators, generating fixed-dimensional time series feature vectors. The vector dimension is set to 20 to 50 dimensions to ensure feature comprehensiveness while avoiding dimensional redundancy that could affect subsequent computational efficiency.

[0033] Step S3 employs a low-speed bus power balancing model to fuse port voltage fluctuation data and peripheral access status information, adjusting the output power distribution strategy of the circuit power supply module. During implementation, time-series analysis is first performed on the port voltage fluctuation data, dividing it into stable and fluctuating periods. The criterion for a stable period is that the voltage change amplitude does not exceed 0.05V within 50ms. For fluctuating periods, characteristic parameters such as fluctuation frequency and amplitude are further analyzed. Simultaneously, peripheral access status information is categorized and statistically analyzed, grouped by peripheral type, power consumption level, and operating mode. The average power consumption requirement, peak power consumption requirement, and power consumption variation pattern of each group of peripherals are determined. Power consumption levels are divided into three categories: low power, medium power, and high power, corresponding to power consumption ranges of 0 to 50mW, 50mW to 200mW, and 200mW to 500mW, respectively. The processed voltage data and peripheral status data are input into a low-speed bus power balancing model. The model uses a multi-source data fusion algorithm to weight the two types of data, with the voltage data weighting coefficient set to 0.3 to 0.5 and the peripheral status data weighting coefficient set to 0.5 to 0.7. The data weights are updated in real time during the fusion process to adapt to dynamically changing circuit states. Based on the fusion results, the model calculates the optimal power supply for each peripheral. Combining this with the maximum output power limit of the circuit power supply module, a power allocation scheme is formulated. The scheme clearly defines the power supply priority, real-time power supply, and power adjustment step size for each peripheral. The power supply priority is dynamically ranked according to the peripheral's operational importance and power consumption requirements. The power adjustment step size is set to 1mW to 10mW to avoid sudden power fluctuations impacting the circuit. Finally, the power allocation scheme is converted into control signals for the power supply module, regulating the output voltage and current distribution ratio to achieve precise power allocation and ensure that each peripheral receives power resources appropriate to its operating state.

[0034] Step S4 utilizes a hardware timing error correction algorithm to calculate error compensation for the timing feature vector and power allocation strategy execution results, correcting circuit transmission timing deviations. During implementation, the timing feature vector generated in S2 and the actual execution data of the power allocation strategy in S3 are first acquired, including parameters such as the actual power supply and power supply response time of each peripheral. Each feature item in the timing feature vector is compared one by one with preset standard timing parameters to calculate the initial timing error. The error calculation uses a combination of absolute and relative error to ensure the accuracy of error assessment. The standard timing parameters are set according to the low-speed USB protocol specification and circuit design requirements, including key indicators such as data transmission delay and clock synchronization deviation. Simultaneously, the impact of the power allocation strategy execution results on timing is analyzed. By comparing the timing changes before and after power adjustment, the correlation between power allocation and timing deviation is determined. The correlation analysis uses statistical analysis methods with a sample size of no less than 100 groups to ensure the reliability of the analysis results. Based on a hardware timing error correction algorithm, differentiated compensation strategies are formulated for different types of timing errors. For errors caused by clock drift, phase adjustment compensation is used; for errors caused by transmission delay, time offset compensation is used; and for errors caused by synchronization deviation, signal trigger timing calibration is used. The algorithm calculates the specific error compensation amount based on the error type, error magnitude, and power allocation influence coefficient. A dynamic adjustment factor is introduced during the compensation calculation process, ranging from 0.8 to 1.2, to adapt to the error correction requirements under different operating conditions. Finally, the error compensation amount is superimposed on the original timing parameters to generate corrected timing control parameters. The corrected data transmission delay error is controlled within ±1μs, and the clock synchronization deviation is controlled within ±0.5μs, significantly reducing the impact of timing deviations on circuit operation.

[0035] Step S5 uses a low-cost, low-speed USB circuit control module to convert the corrected timing parameters and power allocation scheme into hardware drive signals. The drive circuit completes data transmission and peripheral control operations. This control module uses a low-cost microcontroller as the core control unit, along with analog signal conversion circuits, power drive circuits, and interface circuits, keeping the overall hardware cost within a preset range. During implementation, the control module first receives the corrected timing parameters and power allocation scheme through a data interface. The data interface uses a universal serial interface with a transmission rate set to 1Mbps to 10Mbps to ensure real-time and complete data transmission. The core control unit parses the received data, extracting key information from the timing control parameters such as data transmission interval, clock signal frequency, and synchronization signal trigger conditions, as well as parameters from the power allocation scheme such as power supply voltage and current thresholds for each peripheral. The parsing process uses a modular approach, with a parsing delay of no more than 5ms. Subsequently, the core control unit generates digital control signals based on the parsing results. These digital control signals are output to the analog signal conversion circuit through I / O ports, converting them into analog drive signals. The conversion accuracy is set to 12 bits to ensure the precision of the drive signals. The analog drive signal output from the analog signal conversion circuit is transmitted to the power drive circuit. The power drive circuit amplifies the signal, with the amplification factor set from 10 to 100 times according to the peripheral drive requirements, ensuring the drive signal meets the circuit's driving capability requirements. Finally, the amplified hardware drive signal is transmitted to the USB port and peripheral interface through the interface circuit, controlling key components such as the peripheral's power switch and data transmission enable terminal. This drives the peripheral to start operating according to the corrected timing parameters and power supply, completing data transmission and reception operations, and achieving closed-loop execution of circuit control.

[0036] Step S6 involves the embedded USB fault diagnosis platform monitoring circuit operation feedback data in real time, comparing it with preset thresholds, and dynamically adjusting model parameters and control strategies. During implementation, the platform collects various feedback data during circuit operation in real time through the monitoring module, including parameters such as the actual operating current, voltage, data transmission success rate, and real-time timing deviation of each peripheral. The sampling interval of the monitoring module is set to 10ms to 50ms to ensure timely capture of changes in circuit operating status. The collected feedback data undergoes noise reduction and deduplication processing by the data preprocessing unit to remove environmental interference and invalid data generated during data transmission. The preprocessed feedback data is stored in a data cache unit according to category, with a cache unit capacity of no less than 1MB to meet temporary data storage requirements. The platform compares the processed feedback data with preset thresholds one by one. These preset thresholds include voltage threshold range, current threshold range, timing deviation threshold, and data transmission success rate threshold. Each threshold is set according to low-speed USB circuit design standards, peripheral operating requirements, and actual application scenarios, and supports online modification. During the comparative analysis, if all feedback data are within the preset threshold range, the circuit is deemed to be operating normally, and the current model parameters and control strategy are maintained. If any parameter exceeds the threshold range, the platform initiates anomaly analysis to determine the anomaly type, severity, and cause. Anomaly analysis employs a combination of rule matching and statistical analysis, with an analysis time not exceeding 100ms. Based on the anomaly analysis results, the platform dynamically adjusts key parameters of the differential timing coupling mapping model, the low-speed bus power consumption balancing model, and the hardware timing error correction algorithm. Simultaneously, it optimizes power allocation ratios and timing control parameters in the control strategy. The adjustment process adopts a gradual approach, with each adjustment not exceeding 10% to avoid excessive adjustments that could lead to circuit instability and ensure the circuit remains in optimal operating condition.

[0037] Preferably, the expression for the differential temporal coupling mapping model is: ,

[0038] in, These are the differential timing coupling coefficients. These are the time-series weighting coefficients. For data transmission timing difference, For data reception timing difference, This is the timing difference of the clock signal. For the timing difference of the synchronization signal, This is the coupling adjustment coefficient. This refers to the bus transmission delay time. For peripheral response delay time, This is the timing synchronization phase angle.

[0039] Specifically, the differential timing coupling mapping model is based on the multi-dimensional correlation characteristics of timing signals in low-speed USB circuits. First, it identifies the core influencing factors of timing coupling as the timing difference between transmission and reception, the timing difference between clock and synchronization signals, and transmission and response delays. It quantifies the relative changes of each timing parameter through differential operations, then introduces trigonometric functions to characterize the timing synchronization phase relationship, and logarithmic operations to depict the nonlinear impact of delay time. Finally, it combines weighting coefficients and adjustment coefficients to achieve precise quantification of the coupling relationship. Through extensive experimental data analysis, the influence weights of different timing parameters on the coupling effect are statistically determined, with the timing weighting coefficient ranging from 0.6 to 0.9 and the coupling adjustment coefficient ranging from 0.3 to 0.5. Then, based on the phase representation characteristics of trigonometric functions and the nonlinear fitting capability of logarithmic functions, a multi-parameter collaborative coupling calculation framework is constructed to ensure that the model can cover the timing coupling patterns under different operating scenarios. Regarding parameter values, the timing difference parameter is acquired in real time via an embedded USB fault diagnosis platform at a sampling frequency of 100kHz to 500kHz. The delay time parameter is determined based on the circuit hardware characteristics and peripheral specifications, ranging from 1μs to 10μs. The synchronization phase angle is obtained through timing signal phase detection, ranging from 0 to π. During implementation, the model first receives the acquired timing data of various types, and sequentially performs difference operations, logarithmic operations, and trigonometric function operations according to the formula logic, outputting the timing coupling coefficient. This provides a quantitative basis for subsequent timing feature extraction, breaking through the limitations of traditional single timing analysis, accurately capturing the nonlinear correlation between multiple timing signals, and providing accurate data support for timing error correction.

[0040] Preferably, the expression for the low-speed bus power consumption balancing model is: ,

[0041] in, To balance the output power, This is the power consumption adjustment coefficient. This is the actual voltage at the port. This is the bus load current. Let i be the equivalent resistance of the i-th peripheral. Let i be the equivalent capacitance of the i-th peripheral. This is the power compensation coefficient. This represents the circuit's maximum output power. This represents the current actual power consumption. The attenuation coefficient is... This represents the current number of connected peripherals. The number of peripherals is the baseline.

[0042] Specifically, a low-speed bus power balancing model addresses the power allocation requirements of low-speed USB circuits with multiple peripheral access scenarios. Port voltage, load current, and peripheral equivalent parameters are the core influencing factors. Based on the fundamental principles of power transmission, the model quantifies the cumulative impact of multiple peripheral equivalent parameters through summation operations. An exponential function is introduced to characterize the nonlinear adjustment effect of peripheral quantity changes on power allocation. Weighting coefficients are then used to balance the influence weights of voltage data and peripheral status data. In the derivation process, the basic power allocation logic is first derived based on the circuit power consumption calculation formula. Then, experimental analysis is conducted to understand the power consumption variation patterns under different peripheral quantities and voltage fluctuation amplitudes. An exponential function is introduced to compensate for the limitations of fixed allocation strategies. Simultaneously, weighted calculations are used to fuse multi-source data to ensure the model adapts to dynamically changing circuit states. The power consumption adjustment coefficient ranges from 0.7 to 1.2, and the power compensation coefficient ranges from 0.4 to 0.8, both based on the power supply module performance parameters. Port voltage is monitored in real-time with an accuracy of ±0.01V via a signal acquisition module, and load current is monitored from 1mA to 50mA. The equivalent resistance and capacitance of peripherals are determined according to the peripheral hardware specifications, with resistance ranging from 1kΩ to 100kΩ and capacitance from 1nF to 100nF. The attenuation coefficient is obtained through fitting multiple sets of experimental data, ranging from 0.5 to 0.9. The baseline number of peripherals is set to 3 to 5, representing the average number of connections in common application scenarios. During implementation, the model first receives voltage fluctuation data and peripheral status information, performs summation, weighting, and exponential calculations, outputs balanced power, and converts it into power supply module control commands to regulate the output voltage and current distribution ratio. This is significant in achieving dynamic power consumption distribution in scenarios with multiple peripheral connections, avoiding insufficient power supply under high loads and wasted power under low loads, achieving a balance between power consumption and performance in a low-cost architecture.

[0043] Preferably, the expression for the hardware timing error correction algorithm is: ,

[0044] in, This is the corrected timing error. This is the error correction factor. This represents the measured timing error. The angular frequency of the clock signal. This is the phase error value. This is the cumulative correction factor. Let be the error component of the j-th time-series node. Let be the phase offset angle of the j-th timing node. This represents the total number of time-series nodes.

[0045] Specifically, the hardware timing error correction algorithm is based on the multi-source cause analysis of timing errors. It identifies measured timing errors, clock signal angular frequency, phase errors, and error components at each timing node as core influencing parameters. Combining the principles of linear and cumulative error compensation, it quantifies the synergistic effect of angular frequency and phase errors through division operations, introduces a cosine function to characterize the modulation effect of phase shift on the error, and then balances the correction weights of different error sources through weighted coefficients and cumulative coefficients. In the derivation process, experiments are first conducted to verify the influence of error sources such as clock drift, transmission delay, and synchronization deviation, determining that the error correction coefficient ranges from 0.8 to 1.2, and the cumulative correction coefficient ranges from 0.6 to 0.9. Then, based on the accuracy of linear correction and the comprehensiveness of cumulative correction, a multi-error-source collaborative correction framework is constructed to ensure the targeted and effective nature of error compensation. The measured timing error was obtained by comparing standard timing parameters with the acquired data, ranging from 0.1μs to 5μs. The clock signal angular frequency was set based on the circuit clock module specifications, ranging from 1MHz to 10MHz. The phase error value was measured by the phase detection module, ranging from 0 to π / 2. The error components of each timing node were obtained by acquiring node signals, ranging from 0.05μs to 2μs. The total number of timing nodes was set to 8 to 16, covering the key timing nodes of the circuit. During implementation, the algorithm first acquires various error parameters, performs division, cosine, and cumulative summation operations, and outputs the corrected timing error, which is then superimposed on the original timing parameters. Its significance lies in breaking through the limitations of traditional single error correction, achieving accurate compensation for multi-source timing errors, controlling timing deviations within ±0.5μs, and improving data transmission stability.

[0046] Preferably, the state monitoring model expression of the embedded USB fault diagnosis platform is: ,

[0047] in, For condition monitoring index, For voltage monitoring weights, This is the actual voltage of the external device. This is the standard voltage value. For time-series monitoring weights, This is the actual transmission time. For standard transmission time, As the fault monitoring weight, For the number of faulty data frames, This represents the total number of data frames transmitted.

[0048] Specifically, the embedded USB fault diagnosis platform's status monitoring model is based on the multi-dimensional assessment needs of fault diagnosis. It uses voltage deviation, timing deviation, and fault data proportion as core monitoring indicators. Combining the weighted summation principle, it quantifies the relative deviation of each indicator through proportional calculation, and then balances the importance of different monitoring dimensions through weighting coefficients. The influence weights of common fault types in low-speed USB circuits (voltage anomaly, timing deviation, data transmission error) are analyzed, determining that the voltage monitoring weight ranges from 0.3 to 0.5, the timing monitoring weight ranges from 0.3 to 0.4, and the fault monitoring weight ranges from 0.2 to 0.3. Based on the deviation representation capability of proportional calculation, a multi-indicator collaborative monitoring framework is constructed to ensure comprehensive capture of fault states. Regarding parameter values, the actual voltage of the peripheral device is monitored in real time through the port voltage acquisition module, and the standard voltage value is set to a fixed range according to the low-speed USB protocol. The actual transmission time is measured by the timing acquisition module, ranging from 10μs to 100μs, and the standard transmission time is set to the optimal transmission duration specified by the protocol. The number of fault data frames and the total number of transmitted data frames are statistically analyzed by the data verification module. The total number of transmitted data frames is statistically analyzed every 1000 to 10000 frames to ensure the reliability of the statistical results. During implementation, the model first receives monitoring data from each dimension, completes proportional calculations and weighted summation calculations, and outputs a status monitoring index. When the index exceeds a preset threshold (0.1 to 0.2), an abnormal alarm is triggered, realizing comprehensive and real-time monitoring of the circuit's operating status. This provides a basis for dynamic adjustment of control strategies and improves the reliability of circuit operation and fault early warning capabilities.

[0049] Preferably, the drive signal generation model of the low-cost, low-speed USB circuit control module is as follows: ,

[0050] in, For hardware-driven signal strength, For driving coefficients, To correct the timing parameters, To balance output power, To control the equivalent resistance of the circuit, For signal amplitude coefficients, The driving signal angular frequency is t, where t is the time variable. This refers to the amount of data transmitted.

[0051] Specifically, the low-cost, low-speed USB circuit control module drive signal generation model is based on the mapping relationship between drive signals and control parameters. It uses corrected timing parameters, balanced output power, and the equivalent resistance of the control circuit as core influencing factors. Combining the amplitude modulation principle of signal generation, it quantifies the synergistic influence of control parameters through division operations, introduces a sine function to characterize the periodicity of the drive signal, and then balances signal strength and control accuracy through drive coefficients and amplitude coefficients. In the derivation process, the influence of control parameters on drive signal strength is first analyzed based on the circuit drive principle, determining that the drive coefficient range is 0.5 to 1.0 and the signal amplitude coefficient range is 0.3 to 0.6. Then, based on the periodicity of the sine function and the proportional adjustment capability of division operations, a multi-parameter collaborative signal generation framework is constructed to ensure that the drive signal adapts to hardware drive requirements. The corrected timing parameters are the optimized timing data output by S4, ranging from 1μs to 20μs; the balanced output power is the power distribution data output by S3, ranging from 10mW to 500mW; the equivalent resistance of the control circuit is determined according to the hardware specifications of the control module, ranging from 100Ω to 1kΩ; the angular frequency of the drive signal is set from 1kHz to 10kHz, the time variable is continuously valued according to the real-time runtime, and the amount of data transmitted is quantized according to the bytes transmitted each time, ranging from 1 byte to 1024 bytes. During implementation, the model first receives the corrected timing parameters and power distribution data, performs division, sine, and square root operations, outputs the hardware drive signal strength, and transmits it to the peripheral interface after power amplification. This achieves accurate conversion of control parameters to hardware drive signals, ensuring that the strength and frequency of the drive signal match the peripheral control requirements, and achieving efficient and stable circuit driving effects under a low-cost hardware architecture.

[0052] Preferred, such as Figure 2 As shown, step S2 includes the following sub-steps: S21, extracting the rising edge trigger time, falling edge trigger time, and signal duration calibration timing parameters from the bus transmission timing signal to construct an initial timing dataset; S22, dividing the initial timing dataset into a transmitting end timing subset and a receiving end timing subset according to the transmission direction, and calculating the timing statistical feature values ​​of the two subsets respectively; S23, calculating the coupling strength between different timing parameters through a differential timing coupling mapping model, and removing redundant parameters with coupling strength lower than a set threshold; S24, performing feature fusion on the filtered timing parameters to generate a timing feature vector with uniform dimension, providing data support for subsequent error correction.

[0053] Specifically, step S2 involves applying a differential timing coupling mapping model in four sub-steps to generate timing feature vectors. S21 first extracts key parameters of the bus transmission timing signal using the signal acquisition unit of the embedded USB fault diagnosis platform, including the rising edge trigger time, falling edge trigger time, and signal duration. The acquisition resolution is set to 0.1 μs to ensure the accuracy of timing parameter capture. These discrete parameters are then integrated in chronological order to construct an initial timing dataset. Each record in the dataset includes at least 8 timing feature points, laying the foundation for subsequent analysis. S22 uses a data classification algorithm to split the initial timing dataset according to the transmission direction, clearly dividing it into a transmitting-end timing subset and a receiving-end timing subset. The mean, variance, extreme values, and other timing statistical feature values ​​of the two subsets are calculated separately. The statistical sample size for each group is at least 500 to ensure the representativeness of the feature values. This classification process enables directional analysis of the timing signal. S23 invokes the differential temporal coupling mapping model, inputs the statistical feature values ​​of two subsets, and calculates the coupling strength between different time-series parameters. The coupling strength calculation adopts an iterative operation method, with the number of iterations set to 80. A coupling strength threshold of 0.2 is set to eliminate redundant parameters below this threshold, reducing interference from invalid data in subsequent processing. S24 utilizes a feature fusion algorithm to reduce the dimensions and integrate information of the filtered effective time-series parameters, transforming multi-dimensional parameters into time-series feature vectors with a unified dimension of 30. This retains core time-series information while reducing data dimensionality, providing structurally sound and comprehensive data support for error correction in step S4. The entire process takes less than 10ms, meeting real-time control requirements.

[0054] Preferred, such as Figure 3 As shown, step S3 includes the following sub-steps: S31, performing sliding window sampling on the port voltage fluctuation data to obtain voltage peak, valley, and average voltage characteristic parameters; S32, statistically analyzing the peripheral type, access sequence, and operating mode in the peripheral access status information to establish a peripheral power consumption requirement database; S33, inputting the voltage characteristic parameters and peripheral power consumption requirement data into the low-speed bus power consumption balancing model to calculate the optimal power allocation ratio for each peripheral; S34, generating power supply module control commands based on the power allocation ratio to adjust the output voltage and current distribution scheme of the power supply circuit.

[0055] Specifically, step S3 consists of four sub-steps that implement the dynamic power allocation strategy through a low-speed bus power consumption balancing model. Step S31 uses a sliding window sampling method to process port voltage fluctuation data. The window size is set to 50ms, and the sliding step size is 10ms to ensure that instantaneous voltage fluctuations and trend changes are captured. During sampling, the peak, valley, and average voltage values ​​are recorded simultaneously. The voltage measurement accuracy is controlled within ±0.01V. At least 100 sets of voltage characteristic parameters are obtained through continuous sampling to comprehensively reflect the port voltage status. Step S32 uses an interface detection module to statistically analyze peripheral access status information, including peripheral type, access sequence, and operating mode. The detection response time is no more than 1ms to avoid missing instantaneous access status. Subsequently, a peripheral power consumption requirement database is established based on the peripheral power consumption characteristics. The database includes the static power consumption, dynamic power consumption range, and power consumption change curves of various peripherals, covering at least 15 common low-speed USB peripheral types. S33 inputs voltage characteristic parameters and peripheral power consumption requirements into the low-speed bus power balancing model. The model data fusion uses a weighted summation algorithm, with voltage data weighted at 0.4 and peripheral status data weighted at 0.6. The model calculates and outputs the optimal power allocation ratio for each peripheral, retaining the ratio accuracy to three decimal places to ensure fine-grained power distribution. S34 converts the power allocation ratio into control commands for the power supply module. These commands use digital signal format with a transmission rate of 1Mbps, regulating the output voltage and current distribution scheme of the power supply circuit. The voltage adjustment step is 0.05V, and the current adjustment step is 1mA, preventing sudden power surges from impacting the circuit and achieving dynamic adaptation of power resources to ensure power supply stability when multiple peripherals are operating simultaneously.

[0056] Preferred, such as Figure 4 As shown, step S4 includes the following sub-steps: S41, collecting actual timing data during circuit transmission, comparing it with standard timing data, and calculating the initial timing error value; S42, analyzing the distribution characteristics of the initial timing error and determining whether the error source is clock drift, transmission delay, or synchronization deviation; S43, based on the hardware timing error correction algorithm, selecting the corresponding correction strategy for different error sources, and calculating the error compensation amount; S44, superimposing the error compensation amount into the original timing parameters to generate corrected timing control parameters, reducing the impact of timing deviation on transmission performance.

[0057] Specifically, step S4 comprises four sub-steps that construct a precise compensation process for timing deviations using a hardware timing error correction algorithm. S41 acquires actual timing data during circuit transmission via a timing acquisition module at a frequency of 200kHz. Simultaneously, it retrieves preset standard timing data, which is based on the low-speed USB protocol specification and includes 12 key indicators such as data transmission delay and clock synchronization deviation. The actual timing data is compared one by one with the standard data, and the initial timing error is calculated using a combination of absolute and relative errors, with an error calculation accuracy of 0.01μs to ensure the accuracy of error assessment. S42 performs statistical analysis on the initial timing error, using histogram analysis to determine the error distribution type and correlation analysis to locate the error source, clearly distinguishing between three causes: clock drift, transmission delay, and synchronization deviation. The analysis process uses a sample size of no less than 200 groups to ensure the reliability of error source identification and provide a basis for targeted correction. S43, based on a hardware timing error correction algorithm, formulates differentiated compensation strategies for different error sources. Clock drift is compensated using phase adjustment, transmission delay using time offset compensation, and synchronization deviation using signal trigger timing calibration. A dynamic adjustment factor is introduced, ranging from 0.9 to 1.1, to dynamically adjust the compensation intensity according to the error magnitude. The specific error compensation amount is calculated, with 60 iterations to ensure accuracy. S44 adds the calculated error compensation amount to the original timing parameters to generate corrected timing control parameters. The corrected data transmission delay error is controlled within ±0.3μs, and the clock synchronization deviation is controlled within ±0.2μs, significantly reducing the impact of timing deviations on data transmission and providing accurate timing basis for the generation of drive signals in step S5.

[0058] Preferred, such as Figure 5 As shown, S5 includes the following sub-steps: S51, receiving the corrected timing parameters and power allocation scheme, and parsing the control logic and parameter thresholds therein; S52, converting the parsed control information into digital control signals, and transmitting them to the low-cost drive circuit through the I / O interface; S53, the drive circuit adjusts the conduction state of the internal switching transistor and the parameters of the filter circuit according to the digital control signals to generate hardware drive signals adapted to the peripherals; S54, transmitting the hardware drive signals to the USB port and peripheral interface to control the peripheral startup, data transmission and state switching operations, and complete the circuit control closed loop.

[0059] Specifically, step S5 comprises four sub-steps that convert and execute the corrected parameters into hardware drive signals, completing the closed-loop operation of circuit control. S51 receives the corrected timing parameters output from step S4 and the power allocation scheme defined in step S3. The data parsing module extracts the control logic, including key information such as data transmission interval, clock signal frequency, and power supply voltage threshold. The parsing module employs a parallel processing architecture, with a parsing delay not exceeding 3ms, ensuring rapid extraction of control information. Simultaneously, the parsing results are verified, with a 100% pass rate to prevent erroneous information from flowing into subsequent stages. S52 converts the parsed control information into standard digital control signals. These digital signals are in binary format with a 16-bit width and are transmitted to the low-cost drive circuit via a general-purpose I / O interface. The interface transmission rate is set to 5Mbps to ensure the real-time performance and integrity of the signal transmission. A parity check mechanism is used during transmission, with a parity bit ratio of 1 / 16, ensuring the reliability of the signal transmission. After receiving the digital control signal, the S53 driver circuit converts it into an analog drive signal through its internal D / A conversion module with a conversion accuracy of 12 bits. The analog signal is then amplified by a power amplifier circuit, with the amplification factor dynamically adjusted according to the peripheral device's requirements, ranging from 20x to 80x. Simultaneously, the cutoff frequency of the filter circuit is adjusted, ranging from 5kHz to 20kHz, to filter out high-frequency noise and generate a stable and suitable hardware drive signal. The S54 transmits the optimized hardware drive signal to the target peripheral device via the USB port and peripheral interface, controlling operations such as power-on, data transmission enable, and status switching. The signal transmission delay is no more than 2ms, ensuring timely response to control commands and orderly data transmission and reception. This achieves efficient circuit control under a low-cost architecture, adapting to the control needs of various types of low-speed USB peripherals.

[0060] Figure 6The USB receiver control circuit shown focuses on signal reception, processing, and buffering. It employs a modular architecture, consisting of 13 key units working together. The circuit input receives the bus transmission timing signal and clock signal. First, the SYNC detection unit identifies the synchronization signal, ensuring precise alignment between the receiver timing and the bus clock, providing a synchronization reference for subsequent data processing. The synchronized signal is then sent to the sampling and shifting unit, which performs signal acquisition and shifting operations at a set sampling frequency to match the transmission rate requirements of the low-speed USB circuit. The signal processing link includes an NRZI processing unit and a bit-filling processing unit. The former decodes the NRZI encoded signal transmitted from the bus into raw data, while the latter performs bit-filling verification and redundant bit removal to ensure data integrity. The data storage module consists of receive data buffer 0, receive data buffer 1, and a buffer selection unit. This dual-buffer design enables parallel storage and retrieval of data. The buffer selection unit dynamically switches buffer channels based on the circuit's operating status to prevent data loss. The circuit also includes a bit counter, a reset unit, and an EOP (End of Data) determination unit. The bit counter counts the number of bits received in real time, the reset unit can reset the circuit state in case of an abnormality, and the EOP determination unit is responsible for detecting the end of data transmission signal. When data reception is complete or an abnormality occurs, the EOP determination unit triggers an interrupt signal to notify the embedded USB fault diagnosis platform to respond to the status, forming a closed-loop logic for reception control. The overall circuit structure is simplified, eliminating the need for high-cost dedicated decoding chips, which aligns with the low-cost design philosophy.

[0061] Figure 6The circuit design is deeply adapted to the low-cost, low-speed USB circuit control method described in this application, fully supporting the precise control and low-cost requirements of the receiving end. From a technical principle perspective, the synchronization identification function of the SYNC detection unit directly responds to the timing synchronization requirements of the differential timing coupling mapping model in step S2 of this application. By capturing the rising and falling edge trigger times, it provides raw synchronization data for timing feature vector extraction. Its detection accuracy determines the accuracy of the timing coupling coefficient calculation, thereby ensuring the accuracy of error source location in the hardware timing error correction algorithm (step S4). The combination of the NRZI processing unit and the bit-filling processing unit, designed for the encoding specifications of low-speed USB data transmission, can effectively handle the nonlinear timing coupling effects in bus transmission and reduce the accumulation of timing deviations. This is consistent with the core improvement point of this application: "overcoming the monotony of traditional timing control methods." The design of dual buffers (receive data buffer 0 / 1) and a buffer selection unit corresponds to the storage requirements of the multi-dimensional circuit operation status dataset in step S1 of this application. It can buffer bus transmission timing signals, port voltage fluctuation related data, and peripheral access status feedback information in parallel, providing data support for the real-time monitoring of the embedded fault diagnosis platform (step S6). The linkage mechanism between the EOP determination unit and the interrupt signal can quickly respond to data reception anomalies, trigger the platform to calculate and analyze the status monitoring index, and realize the dynamic adjustment of the control strategy. The circuit as a whole does not use high-cost dedicated receiver chips. Through modular decomposition and simplified design, hardware costs are reduced while the stability and integrity of received data are ensured by the synergy of timing synchronization, encoding and decoding, and buffer scheduling, perfectly meeting the core design goals of low cost and high precision of this application.

[0062] Figure 7The USB transmit control circuit shown is centered on data buffering, encoding, and precise output. It employs a highly efficient and collaborative modular architecture, comprising 14 functional units, adapting to the low-cost and high-reliability requirements of low-speed USB circuits. The circuit's data source is the transmit buffer module, consisting of transmit data buffer 0, transmit data buffer 1, and a buffer selection unit. This dual-buffer design supports pre-storage and parallel data transfer. The buffer selection unit dynamically switches channels based on data transmission priority to avoid transmit congestion. The DMA (Direct Memory Access) unit is responsible for efficiently transferring external data to the transmit buffer, using a "decrement by 1" logic to count and manage data transmission, improving data throughput efficiency. The data processing link includes a bit stuffing unit and an NRZI unit. The bit stuffing unit adds redundant bits to the raw data according to the USB protocol specification to ensure transmission reliability, while the NRZI unit encodes the processed data into a bus-compatible NRZI signal. The timing control core consists of a transmit timer, a bit counter, and a zero-count trigger unit. The transmit timer generates a precise transmission timing reference, matching the corrected timing parameters in this application. The bit counter counts the number of bits of data to be transmitted in real time, and triggers a zero-count signal after the count reaches zero, which in turn triggers an EOP signal generation unit to generate a transmission end marker. The circuit output is a differential signal output unit, which converts the encoded digital signal into a bus-compatible differential drive signal. It also includes an interrupt signal interface to provide feedback to the control module when data transmission is complete or an anomaly occurs, achieving closed-loop control of the transmission process. The overall circuit balances low cost and transmission stability requirements through precise timing control, efficient data transfer, and a simplified encoding architecture.

[0063] Figure 7The circuit design closely aligns with the low-cost, low-speed USB circuit control method described in this application, fully supporting the generation of drive signals in step S5 and the adjustment of control strategies in step S6, from data transmission timing control and power consumption optimization to dynamic feedback. The transmit timer in the circuit is the core of precise timing control. The transmit timing reference it generates directly adopts the timing parameters corrected in step S4. Through linkage with the hardware timing error correction algorithm in this application, the transmit timing deviation is controlled within ±0.5μs, solving the problem of timing deviation accumulation in traditional methods. The combination of the bit counter and the zero-count trigger unit matches the timing feature vector calculated by the differential timing coupling mapping model in real time, ensuring dynamic adaptation of the transmit rate and bus timing, echoing the design concept of "multi-model collaborative timing control" in this application. The DMA unit and dual-buffer (transmit data buffer 0 / 1) design significantly improve data transfer efficiency and reduce CPU usage, which aligns with the "low-cost" design philosophy of this application. It eliminates the need for a high-cost data transmission controller, achieving efficient data scheduling through hardware logic. Simultaneously, the buffer selection unit dynamically adjusts data transmission priority based on the power allocation scheme output by the low-speed bus power balancing model in step S3. In scenarios with multiple peripherals accessing concurrently, it prioritizes data transmission for high-power peripherals, achieving a balance between power consumption and transmission efficiency. The encoding logic of the bit-filling processing unit and the NRZI unit strictly adheres to the low-speed USB protocol. Its encoding output is directly related to the drive signal generation model in step S5 of this application. By converting the corrected timing parameters and balancing power into encoded signals, which are then amplified by the differential signal output unit, a hardware drive signal adapted to the peripheral is generated, ensuring that the drive signal strength and frequency meet the peripheral's requirements. The linkage between the interrupt signal interface and the EOP signal generation unit enables real-time feedback of the transmission status. When the number of transmitted data frames is abnormal, the status monitoring of the embedded fault diagnosis platform can be triggered (step S6). By calculating the status monitoring index, the transmission timing or power allocation strategy is dynamically adjusted to form a closed loop of transmission-monitoring-adjustment, which fully supports the core objective of this application to improve the accuracy, stability and operating efficiency of circuit control.

[0064] USB low-speed devices have a transfer speed of 1.5Mbps, which is not very fast, allowing for software-assisted processing. Low-speed devices only support control and interrupt transfers, so the circuit design only needs to consider the implementation of these two types of transfers.

[0065] The "SYNC Detection Unit" is a dedicated circuit for SYNC detection. It detects the SOP signal generation by monitoring the level change on the bus as it switches from idle to K state. Then, it checks a series of I / O toggles to determine if it's a SYNC signal. If it is, the module sends a reset signal to the "Reset Unit," which resets all modules to prepare for subsequent operations. The module then controls the clock switch of the sampling shift unit, thereby controlling the operation of the sampling shift unit. The "SYNC Detection Unit" only operates during data reception; SYNC is disabled during USB transmission.

[0066] The differential signal passes through a comparator, which converts it into a signal represented by 0s and 1s. The sampling shift unit is mainly responsible for sampling the signal processed by the comparator. With the cooperation of the clock switch controlled by the SOP detection unit, the sampled signals are all considered as J or K signals, and 0 and 1 are used to represent the J and K states, respectively. The data is pushed into the NRZI unit for processing through a register.

[0067] USB uses Reverse Non-Return-to-Zero (NRZI) encoding at its underlying layer. In NRZI encoding, a single inversion of the signal level represents a bit 1. That is, a transition from a positive to a negative level, rather than the voltage value itself, represents a bit 1. Bit 0 is represented by a signal with no level change. The advantage of NRZI inverted encoding over NRZI level encoding is that because a level transition occurs every time a bit 1 is encountered, it provides a synchronization mechanism.

[0068] The "NRZI unit" is the circuit unit responsible for NRZI encoding. USB is a serial bus without an independent clock line; the receiver relies entirely on the transition edges of signal levels to recover the clock (e.g., NRZI encoding rule: 0 = level toggle, 1 = level unchanged). If multiple consecutive 1s appear, the signal level will not toggle for a long time. The receiver, lacking a new transition edge reference, will gradually deviate from the actual clock frequency, eventually leading to clock synchronization issues and incorrect data acquisition. Therefore, the USB protocol requires inserting a 0 signal after every six consecutive 1 signals to prevent synchronization loss. The receiver, upon receiving six consecutive 1s, simply deletes the following 0s to restore the original data. The "bit stuffing unit" is responsible for implementing this functionality.

[0069] Each time a bit of data is moved from the "bit stuffing unit" into the receive buffer, the "bit counter" automatically increments by 1. After receiving an EOP (End Pointer) and responding to the interrupt, the number of valid data bits in the buffer can be obtained through this "bit counter." This facilitates subsequent CRC check calculation to confirm the number of bits and data extraction.

[0070] Normal USB signals do not allow differential signals to be positive simultaneously. If this happens, an error should be reported. This can be achieved by using an AND gate to check if the differential signals are both high at the same time. If they are both high, a high output will be given to indicate a signal error.

[0071] The "EOP determination unit" will generate an interrupt response after detecting the EOP signal. At the same time, it will control the "buffer selection unit" to switch the buffer for the next USB data reception and turn off the clock of the "sampling shift unit" to stop data reception. The "buffer selection unit" will control the two buffers to be used interchangeably. When receiving data, the CPU can process the data in the other buffer. In this way, data processing and data reception can be carried out simultaneously without conflict.

[0072] The USB transmission process is performed via DMA. Before transmission, the "bit counter" is set to indicate the number of bits to be transmitted. The "transmission timer" triggers a DMA transfer at a low USB frequency of 1.5 MHz, transferring one bit of data at a time to the "bit stuffing processing unit". When the "bit counter" reaches 0, the "transmission timer" is turned off, stopping further data transmission. At the same time, the "EOP signal generation unit" generates an EOP signal, which is output through the "differential signal output unit" and generates an EOP interrupt to notify the CPU.

[0073] After being processed by the "NRZI unit" and the "bit stuffing processing unit," the data is output to the "differential signal output unit." The "differential signal output unit" is responsible for modulating the input signal into the corresponding USB differential signal for output. If a bit stuffing operation occurs in the "bit stuffing processing unit," it will control the "transmission timer" to pause for one transmission cycle, resuming the timer only after the bit stuffing data has been transmitted. In this design, USB SYNC transmission is achieved by sending 0x01 data; therefore, the first bit of the transmitted data packet must be 0x01.

[0074] A low-cost, low-speed USB circuit control method achieves a synergistic balance between low cost and high control performance. It eliminates the need for high-cost dedicated chips or complex hardware architectures. By simplifying control module design and optimizing algorithm logic, it significantly reduces circuit design, production, and application costs. Simultaneously, it constructs a multi-model collaborative control system to ensure control accuracy and stability. Through an embedded USB fault diagnosis platform, it achieves comprehensive acquisition and real-time monitoring of circuit operating status, providing data support for precise control. Combined with the synergistic effects of a differential timing coupling mapping model, a low-speed bus power consumption balancing model, and a hardware timing error correction algorithm, a closed-loop control mechanism is formed. This mechanism adapts to the dynamic changes in scenarios with multiple peripheral connections and specifically addresses timing deviations and uneven power consumption.

[0075] This method addresses the issue of insufficient precision in traditional timing control. Instead of relying on a single-dimensional correction strategy, it deeply explores the nonlinear coupling relationships between various timing signals to accurately locate the root cause of deviations. Then, it compensates for various timing deviations through a dynamic adaptive error correction mechanism, preventing the accumulation of deviations from affecting transmission stability. Addressing the problem of unreasonable power allocation, it abandons the fixed power allocation mode and dynamically adjusts the power allocation ratio by combining multi-dimensional information such as port voltage fluctuations, peripheral equivalent characteristics, and the number of connected devices. This achieves sufficient power supply under high load conditions and power saving under low load conditions, achieving a balance between power consumption and performance in a low-cost hardware architecture, and comprehensively improving the operational reliability and practicality of low-speed USB circuits.

[0076] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," "link," and "fix" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0077] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various equivalent changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A low-cost low-speed USB circuit control method, characterized by, Includes the following steps: S1. Collect bus transmission timing signals, port voltage fluctuation data, and peripheral access status information of the low-speed USB circuit using an embedded USB fault diagnosis platform to establish a multi-dimensional circuit operation status dataset. S2. Perform dynamic correlation analysis on the collected bus transmission timing signals based on a differential timing coupling mapping model to uncover nonlinear coupling relationships between timing signals and generate timing feature vectors. S3. Use a low-speed bus power consumption balancing model to fuse port voltage fluctuation data and peripheral access status information, and adjust the output power allocation strategy of the circuit power supply module. S4. Utilize a hardware timing error correction algorithm to calculate error compensation for the timing feature vectors and power allocation strategy execution results, correcting circuit transmission timing deviations. S5. Convert the corrected timing parameters and power allocation scheme into hardware drive signals using a low-cost low-speed USB circuit control module, driving the circuit to complete data transmission and peripheral control operations. S6. The embedded USB fault diagnosis platform monitors circuit operation feedback data in real time, compares it with preset thresholds, and dynamically adjusts model parameters and control strategies.

2. The low-cost, low-speed USB circuit control method according to claim 1, characterized in that, The expression for the differential temporal coupling mapping model is: ， in, These are the differential timing coupling coefficients. These are the time-series weighting coefficients. For data transmission timing difference, For data reception timing difference, This is the timing difference of the clock signal. For the timing difference of the synchronization signal, This is the coupling adjustment coefficient. This refers to the bus transmission delay time. For peripheral response delay time, This is the timing synchronization phase angle.

3. The low-cost, low-speed USB circuit control method according to claim 1, characterized in that, The expression for the low-speed bus power consumption balancing model is: ， in, To balance the output power, This is the power consumption adjustment coefficient. This is the actual voltage at the port. This is the bus load current. Let i be the equivalent resistance of the i-th peripheral. Let i be the equivalent capacitance of the i-th peripheral. This is the power compensation coefficient. This represents the circuit's maximum output power. This represents the current actual power consumption. The attenuation coefficient is... This represents the current number of connected peripherals. The number of peripherals is the baseline.

4. The low-cost, low-speed USB circuit control method according to claim 1, characterized in that, The expression for the hardware timing error correction algorithm is: ， in, This is the corrected timing error. This is the error correction factor. This represents the measured timing error. The angular frequency of the clock signal. This is the phase error value. This is the cumulative correction factor. Let be the error component of the j-th time-series node. Let be the phase offset angle of the j-th timing node. This represents the total number of time-series nodes.

5. The low-cost, low-speed USB circuit control method according to claim 1, characterized in that, The state monitoring model expression of the embedded USB fault diagnosis platform is: ， in, For condition monitoring index, For voltage monitoring weights, This is the actual voltage of the external device. This is the standard voltage value. For time-series monitoring weights, This is the actual transmission time. For standard transmission time, As the fault monitoring weight, For the number of faulty data frames, This represents the total number of data frames transmitted.

6. The low-cost, low-speed USB circuit control method according to claim 1, characterized in that, The drive signal generation model of the low-cost, low-speed USB circuit control module is as follows: ， in, For hardware-driven signal strength, For driving coefficients, To correct the timing parameters, To balance output power, To control the equivalent resistance of the circuit, For signal amplitude coefficients, The driving signal angular frequency is t, where t is the time variable. This refers to the amount of data transmitted.

7. The low-cost, low-speed USB circuit control method according to claim 1, characterized in that, S2 includes the following sub-steps: S21, extracting the rising edge trigger time, falling edge trigger time, and signal duration calibration timing parameters from the bus transmission timing signal to construct an initial timing dataset; S22, dividing the initial timing dataset into a transmitting end timing subset and a receiving end timing subset according to the transmission direction, and calculating the timing statistical feature values ​​of the two subsets respectively. S23, calculate the coupling strength between different time series parameters through the differential time series coupling mapping model, and remove redundant parameters whose coupling strength is lower than the set threshold; S24, perform feature fusion on the filtered time series parameters to generate a time series feature vector with uniform dimension, providing data support for error correction.

8. The low-cost, low-speed USB circuit control method according to claim 1, characterized in that, S3 includes the following sub-steps: S31, performing sliding window sampling on port voltage fluctuation data to obtain voltage peak, valley, and average voltage characteristic parameters; S32, statistically analyzing peripheral types, access sequences, and operating modes in peripheral access status information to establish a peripheral power consumption requirement database; S33, inputting voltage characteristic parameters and peripheral power consumption requirement data into a low-speed bus power consumption balancing model to calculate the optimal power allocation ratio for each peripheral; S34, generating power supply module control commands based on the power allocation ratio to adjust the output voltage and current allocation scheme of the power supply circuit.

9. A low-cost, low-speed USB circuit control method according to claim 1, characterized in that, The S4 includes the following sub-steps: S41, collecting actual timing data during circuit transmission, comparing it with standard timing data, and calculating the initial timing error value; S42, Analyze the distribution characteristics of the initial timing error and determine whether the error source is clock drift, transmission delay or synchronization deviation; S43, Based on the hardware timing error correction algorithm, select the corresponding correction strategy for different error sources and calculate the error compensation amount; S44 adds the error compensation amount to the original timing parameters to generate corrected timing control parameters, reducing the impact of timing deviations on transmission performance.

10. A low-cost, low-speed USB circuit control method according to claim 1, characterized in that, S5 includes the following sub-steps: S51, receiving the corrected timing parameters and power allocation scheme, and parsing the control logic and parameter thresholds therein; S52, converting the parsed control information into digital control signals, and transmitting them to the low-cost drive circuit through the I / O interface; S53, the drive circuit adjusts the conduction state of the internal switching transistors and the parameters of the filter circuit according to the digital control signals to generate hardware drive signals adapted to the peripherals; S54, transmitting the hardware drive signals to the USB port and peripheral interface to control the peripheral startup, data transmission and state switching operations, completing the circuit control closed loop.

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