Wide-voltage ultra-low-power hysteresis adjustable flip-flop and internet of things system node

Abstract

This application discloses a wide-voltage, ultra-low-power hysteresis-adjustable trigger and an IoT system node. The wide-voltage, ultra-low-power hysteresis-adjustable Schmitt trigger circuit and passive IoT system node include: a subthreshold adaptive bias module, a current-starved input stage, a programmable positive feedback array, an output shaping buffer stage, an antenna module, a wake-up receiver front-end module, and a digital baseband control module. This application can suppress microampere-level punch-through current under harsh power supply swing conditions, limiting global power consumption to the extremely low nanowatt range. Furthermore, through a combined filtering mechanism of time constant delay and discrete adjustable hysteresis width, it effectively cuts off dynamic RF spurious noise of different frequency bands and intensities, preventing false wake-ups of passive sensing nodes.

Description

Technical Field

[0001] This application relates to the field of microelectronic logic circuit design, specifically to a wide-voltage ultra-low power hysteresis adjustable trigger and an Internet of Things system node. Background Technology

[0002] In the wake-up receiver application environment of passive IoT nodes, the power supply provided by the ambient energy harvesting module exhibits fluctuating characteristics. After capturing weak radio frequency signals and extracting the signal envelope, the receiver needs to use a Schmitt trigger to shape the analog envelope signal accompanied by ambient background noise into a digital pulse with steep edges. This pulse serves as a high-priority external interrupt source within the system to wake up the main control chip, which is in a deep sleep state. Currently, the Schmitt triggers in general technical solutions mainly adopt a fixed aspect ratio complementary metal-oxide-semiconductor (CMOS) structure.

[0003] The aforementioned technical solutions have shortcomings in passive node application scenarios. When the ambient energy source causes a large-scale shift and jump in the supply voltage, the drain-source current of conventional transistors will exhibit abrupt changes. This uncontrolled change in current causes the hysteresis switching window of the trigger to drift significantly with voltage fluctuations, leading to the failure of the internal positive feedback mechanism under bias drop conditions and loss of signal shaping capability. In environments with sudden changes in RF noise floor, triggers with fixed hysteresis widths cannot effectively suppress high-frequency voltage jitter, resulting in stray digital pulses during circuit forward propagation. These stray pulses can frequently wake up the main control chip, causing the limited energy storage within the passive node to be rapidly consumed. Currently introduced threshold adjustment circuits based on resistor voltage divider networks or multi-channel current mirrors generate microamp-level static shoot-through bias currents. This current exceeds the nanowatt-level standby power budget limit that the passive node can handle, leading to the collapse of the entire front-end energy harvesting and voltage rail system. Summary of the Invention

[0004] This application provides a wide-voltage ultra-low power hysteresis adjustable trigger and an IoT system node, which solves the technical problems of existing fixed threshold triggers causing hysteresis window drift due to leakage current mutation under large-range power supply voltage fluctuations, and the inability to effectively filter high-frequency stray noise in environments with sudden changes in background noise, resulting in false system wake-up.

[0005] This application provides a wide-voltage, ultra-low-power, hysteresis-adjustable Schmitt trigger circuit, including a subthreshold adaptive bias module, a current-starved input stage, a programmable positive feedback array, and an output shaping buffer stage. The subthreshold adaptive bias module is connected in series between the global power rail and the ground rail, and internally contains transistors operating in the deep subthreshold region. It is configured to extract the transient potential of the supply voltage and generate a first bias node potential and a second bias node potential. The current-starved input stage includes pull-up networks and pull-down networks that are controlled and connected to the first bias node potential and the second bias node potential, respectively. The pull-up network and the pull-down network receive analog envelope signals and converge to an intermediate voltage node. The pull-up network and the pull-down network limit the charging and discharging current limits through the first bias node potential and the second bias node potential. The programmable positive feedback array is bridged between the intermediate voltage node and the power rail, and internally contains a group of adjustable transistors with a binary proportional width. The programmable positive feedback array receives a multi-bit digital control signal word and sets the conduction state of the adjustable transistor group and the feedback current injection strength based on the multi-bit digital control signal word. The output shaping buffer stage is cascaded to the intermediate voltage node and outputs a digital pulse signal.

[0006] In a preferred embodiment, the subthreshold adaptive bias module includes a plurality of series-connected diode-type metal-oxide-semiconductor field-effect transistors (MOSFETs). The gates and drains of the diode-connected MOSFETs are shorted. The plurality of series-connected diode-connected MOSFETs form a voltage divider network, with their voltage divider taps respectively led out as the first bias node potential and the second bias node potential.

[0007] In a preferred embodiment, the voltage divider network is configured such that when the voltage V of the global power rail... DD When the voltage rises to the high potential limit, the drain-source shoot-through current I of the diode-connected metal-oxide-semiconductor field-effect transistor will be... leak The physical clamp is located within the nanoampere level limit defined by the deep subthreshold region. The first bias node potential V bp With the second bias node potential V bn They respectively satisfy the preset voltage divider equation constraints. The first bias node potential V bp Configured to limit the peak charging current I of the downstream branch cp The second bias node potential V bn Configured to limit the peak discharge current I of the downstream branch cn .

[0008] In a preferred embodiment, the pull-up network within the current-starved input stage includes a first-type transistor, and the pull-down network includes a second-type transistor. The gate of the first-type transistor is connected to the first bias node potential. The gate of the second-type transistor is connected to the second bias node potential. The saturation leakage current of the first-type transistor and the second-type transistor limits the charge / discharge rate to the intermediate voltage node and performs low-pass time constant delay filtering on the input analog envelope signal before the node potential crosses a flip threshold.

[0009] In a preferred embodiment, the first type transistor is a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET), and the second type transistor is an N-channel MOSFET. The charge / discharge rate is controlled by an integral constant. The integral constant The drain saturation-limited current I of the first type transistor or the second type transistor sat and the lumped parasitic capacitance C of the intermediate voltage node mid The first type of transistor and the second type of transistor are jointly determined by the integration constant. For input waveforms with pulse width less than T noise The high-frequency AC noise level peaks are filtered out.

[0010] In a preferred embodiment, the programmable positive feedback array includes multiple parallel hysteresis feedback adjustment branches. Each hysteresis feedback adjustment branch is controlled by an independent bit in the multi-bit digital control signal word. The channel widths of the transistors in each hysteresis feedback adjustment branch are arranged according to a first ratio, a second ratio, and a third ratio. The first ratio, the second ratio, and the third ratio have a binary weighted distribution relationship.

[0011] In a preferred embodiment, the aspect ratio of the first, second, and third ratios is configured as 1:2:4. Each of the hysteresis feedback adjustment branches is correspondingly configured with a control word variable D. n Based on the control word bit variable D, which is in an active state. n Change the equivalent positive feedback on-resistance R of the equivalent connection to the intermediate voltage node. fb and equivalent intrinsic parasitic capacitance C fb Scale the forward flip hysteresis threshold width V according to discrete steps hys And maintain the forward flip hysteresis threshold width V hys The threshold window remains constant when the voltage on the power supply rail changes amplitude.

[0012] This application also provides a passive IoT system node, including an antenna module, a wake-up receiver front-end module, and a digital baseband control module. The antenna module receives radio frequency signals and outputs an analog envelope signal of the radio frequency signals. The wake-up receiver front-end module is electrically connected to the antenna module and receives the analog envelope signal. The wake-up receiver front-end module includes the aforementioned wide-voltage ultra-low-power hysteresis adjustable Schmitt trigger circuit. The wide-voltage ultra-low-power hysteresis adjustable Schmitt trigger circuit shapes the analog envelope signal and outputs the digital pulse signal. The digital baseband control module receives the digital pulse signal and triggers a system wake-up operation based on the digital pulse signal.

[0013] In a preferred embodiment, the passive IoT system node further includes an energy harvesting module. The energy harvesting module is connected in parallel to the antenna module to acquire the radio frequency energy of the received radio frequency signal and convert it into a DC power supply voltage. This DC power supply voltage is connected to the global power rail to provide operating power for the wide-voltage ultra-low-power hysteresis-adjustable Schmitt trigger circuit.

[0014] In a preferred embodiment, the wide-voltage ultra-low-power hysteresis-adjustable Schmitt trigger circuit matches the background noise floor amplitude V of the current radio frequency environment based on the received multi-bit digital control signal word. noise When a sudden change in the external energy field strength of the antenna module causes the DC supply voltage to fluctuate within the range of 0.6V to 3.3V in its envelope, the system maintains a forward flip hysteresis threshold width greater than the background noise amplitude V. noise And limit the static shoot-through leakage current I of the entire system node. total It is below the critical line of less than 50 nA in the nanowatt level.

[0015] Based on the above technical solutions, this application constructs a multi-level collaborative architecture that includes an adaptive bias network operating in deep subthreshold mode, a starvation-type current limiting structure, and a discrete binary programmable feedback array. This architecture can suppress microampere-level punch-through current phenomena under wide power supply swing conditions, limiting global power consumption to the nanowatt range. The system uses a combined filtering mechanism of time-constant charging / discharging delay and discrete adjustable hysteresis width to cut off dynamic RF spurious noise of different frequency bands and intensities, preventing false wake-up faults of passive sensing nodes. Attached Figure Description

[0016] Figure 1 This is a block diagram of the module structure of the wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit provided in the embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of the internal circuit topology and connection relationship of the wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit provided in the embodiment of the present invention.

[0018] Figure 3 This is a system connection logic diagram of a passive Internet of Things (IoT) system node provided in an embodiment of the present invention.

[0019] Explanation of reference numerals in the attached figures

[0020] In the diagram: 100 - Wide-voltage ultra-low-power hysteresis adjustable Schmitt trigger circuit; 101 - Subthreshold adaptive bias module; 102 - Current-starved input stage; 103 - Programmable positive feedback array; 104 - Output shaping buffer stage; 201 - Diode-connected metal-oxide-semiconductor field-effect transistor; 202 - Pre-input voltage divider network; 203 - Pull-up network; 204 - Pull-down network; 205 - Hysteresis feedback adjustment branch; 206 - Control switching transistor; 207 - Hysteresis adjustment transistor; 208 - First-stage static inverter; 209 - Last-stage static inverter; 300 - Passive IoT system node; 301 - Antenna module; 302 - RF energy envelope detector; 303 - Digital baseband control module; 304 - Main control chip; 305 - Passive environmental energy harvesting power management module; 2031 - Type I transistor; 2041 - Type II transistor. Detailed Implementation

[0021] To enable those skilled in the art to more clearly understand the technical solution of this application, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] This application provides a circuit and system solution for use under harsh energy harvesting and radio frequency reception conditions. Those skilled in the art will understand that the following description will be broken down into two system-level embodiments. Embodiment 1 focuses on disclosing the core transistor-level topology and parameter calculation logic of the wide-voltage, ultra-low-power circuit; Embodiment 2 focuses on disclosing the macroscopic component bridging and signal transmission application process of this circuit in a passive Internet of Things (IoT) environment.

[0023] Example 1

[0024] like Figure 1 and Figure 2 As shown, this embodiment provides a wide-voltage ultra-low-power hysteresis adjustable Schmitt trigger circuit 100. The wide-voltage ultra-low-power hysteresis adjustable Schmitt trigger circuit 100 is deployed on a silicon substrate, and its core architecture forms a closed-loop system from forward power supply current limiting management to backward feedback threshold adjustment. The main components sequentially include: a subthreshold adaptive bias module 101, a current-starved input stage 102, a programmable positive feedback array 103, and an output shaping buffer stage 104.

[0025] The electrical input of the subthreshold adaptive bias module 101 is connected to an external global power rail, and its ground terminal is connected to the system's ground rail. This module is configured to extract the transient voltage potential of the power rail and internally convert it to generate a stable first bias node potential V. bp and the second bias node potential V bn Specifically, the internal microstructure of the subthreshold adaptive bias module 101 includes multiple series-connected diode-type metal-oxide-semiconductor field-effect transistors (MOSFETs) 201. The subthreshold adaptive bias module 101 includes interconnected groups of diode-connected P-channel MOSFETs and N-channel MOSFETs. In the circuit connections of each group, the gates and drains of all diode-connected MOSFETs 201 are physically shorted, forming multiple stacked pre-input voltage divider networks 202. The pre-input voltage divider networks 202 have preset voltage divider taps along the voltage gradient direction leading outwards, respectively outputting the aforementioned first bias node potential V. bp Second bias node potential V bn .

[0026] To ensure operation within the power budget, all constituent transistors in the subthreshold adaptive bias module 101 are configured and constrained to operate within the deep subthreshold range. During circuit operation, the gate-source voltage of each constituent transistor is controlled to be below its corresponding transistor physical threshold voltage. The system implements an adaptive leakage current constraint mechanism, utilizing the exponential nonlinear impedance characteristics generated by carrier diffusion in the deep subthreshold region for clamping management. In a preferred embodiment, the microscopic calculation logic for this leakage current clamping is implemented using the following formula:

[0027]

[0028] Among them, I leak I0 represents the drain-source current flowing through the diode-connected metal-oxide-semiconductor field-effect transistor 201; I0 represents the fundamental reverse saturation constant current affected by the process structure; V0 GS V represents the actual bias voltage between the transistor's gate and source. TH V represents the threshold voltage critical point at which a transistor turns on; n represents the subthreshold slope ideality factor associated with the semiconductor interface states; T V represents the thermoelectric potential voltage constant that is directly proportional to the absolute temperature of the environment. DS This represents the voltage drop between the drain and source of a transistor.

[0029] Based on the equation established by the deep subthreshold characteristics, when the transient supply voltage of the global power rail experiences a significant shift (specifically configured within the range of 0.6V to 3.3V), even if the voltage level reaches the high potential limit, the subthreshold adaptive bias module 101 can suppress and converge the potentially microampere-level punch-through current through an exponentially increasing dynamic equivalent impedance. This mechanism physically clamps the global DC standby operating current range of the entire circuit structure within the nanowatt-level limit between 10nA and 50nA. Furthermore, the first bias node potential V... bp Configured to limit the peak charging current I of the downstream P-type branch cp Meanwhile, the second bias node potential V bn The corresponding configuration is to limit the peak discharge current I of the downstream N-type branch. cn By constructing a deep subthreshold current-limiting architecture at the energy input source stage, the charge safety of the subsequent sensitive switching circuit can be protected under conditions of wide fluctuations in ambient power supply.

[0030] The current-starved input stage 102 includes an internally interconnected pull-up network 203 and a pull-down network 204. The gate control terminal of the pull-up network 203 is connected to the first bias node potential V mentioned above. bp Controlled connection, the gate control terminal of pull-down network 204 is connected to the second bias node potential V bn Controlled connection. The signal input interfaces of pull-up network 203 and pull-down network 204 jointly receive the analog envelope signal extracted from the front-end components, and the drains of the main paths within the two networks are physically connected to converge, thereby leading outwards and generating a shared intermediate voltage node V. mid .

[0031] In terms of circuit architecture, the main body of the current-starved input stage 102 is composed of a top-current-limiting P-channel MOSFET, an input P-channel MOSFET, an input N-channel MOSFET, and a bottom-current-limiting N-channel MOSFET connected in series. The pull-up network 203 includes a first-type transistor 2031 with a P-channel MOSFET as its carrier; the pull-down network 204 includes a second-type transistor 2041 with an N-channel MOSFET as its carrier. The gate of the first-type transistor 2031 is connected to the first bias node potential V. bp To cut off excessive current, the gate of the second-type transistor 2041 is connected to the second bias node potential V. bn The pull-up network 203 and pull-down network 204 limit the charging and discharging current that the main circuit can transmit based on the received current-limiting bias parameters.

[0032] Specifically, the saturation leakage current of the first-type transistor 2031 and the second-type transistor 2041 limits the power to the intermediate voltage node V. mid The system utilizes the current-limiting delay characteristic to perform low-pass filtering calculation logic based on the charge and discharge rate for charge transport, i.e., defining state transition hysteresis through integration. In a preferred embodiment, the calculation logic for this low-pass time constant delay filtering is characterized by the following formula:

[0033]

[0034] in, Indicates the control of intermediate voltage node V mid The integral constant for the speed of state transition represents the theoretical time delay of the signal response; C mid Indicates intermediate voltage node V mid The equivalent lumped parasitic capacitance accumulated at a location reflects the energy storage capacitive characteristics within the physical node; V thinv I represents the critical potential step change that must be reached for a subsequent logic circuit to undergo a state transition; sat This indicates the drain saturation-limited current allowed to flow through the first-type transistor 2031 or the second-type transistor 2041 under current-limited conditions.

[0035] Since the charge / discharge rate is controlled by the integral constant According to the physical laws, when a high-frequency AC noise level peak is superimposed on the real analog envelope signal and enters the current-starved input stage 102, if the pulse width duration of this high-frequency spurious waveform is less than T... noise Then the transient minute charge it carries cannot be in I sat Under nanoampere-level current-limited injection rate, satisfying C mid The capacitor is fully charged to V thinv The required cumulative requirements. Through this natural time constant integral delay effect, the system physical level filters and truncates the response feedback to high-frequency noise floor, thereby preventing the node potential from crossing the flip threshold prematurely.

[0036] Furthermore, to suppress the channel length modulation effect and parasitic leakage current degradation within the silicon-based process, the current-starved input stage 102 employs an elongated physical structure configuration of the active region on a specific layout. Specifically, the transistor conductive channel widths of the first-type transistor 2031 and the second-type transistor 2041 are designed as follows: The corresponding transistor conductive channel length design is stretched to to The long channel specifications. It should be noted that the long channel ratio design scheme for a specific silicon substrate process is not limited to the above fixed values. Those skilled in the art can perform equivalent mapping and scaling operations on the above width and length ratio according to the design specifications of different substrate process generations (e.g., 180 nm or 65 nm nodes). As long as the parasitic effect suppression function of long channel is satisfied, the current limiting protection target of this application can also be achieved.

[0037] The programmable positive feedback array 103 is bridged at the intermediate voltage node V in the topology network. mid Between the global power supply rail and the ground rail. The programmable positive feedback array 103 includes multiple parallel hysteresis feedback regulation branches 205, specifically multiple parallel pull-up feedback branches and pull-down feedback branches. In terms of hardware composition, each hysteresis feedback regulation branch 205 internally contains a control switch transistor 206 (i.e., a complementary metal-oxide-semiconductor transmission gate switch) as a conduction control switch and a hysteresis regulation transistor 207 as a current regulation load, connected in series. The gate of each control switch transistor 206 receives and is controlled by an externally injected multi-bit digital control signal word. Among them, the pull-up feedback branch receives a multi-bit digital control word array signal S representing pull-up control. pull [2:0]; The pull-down feedback branch receives the multi-bit digital control word array signal S representing the pull-down control. push [2:0].

[0038] To provide a wide, configurable, and linearly varying hysteresis decision window, the physical dimensions of the hysteresis adjustment transistors 207 in each hysteresis feedback adjustment branch 205 are not designed with a proportional distribution, but rather with a non-uniform arrangement following a first, second, and third ratio set according to a stepped differential. The first, second, and third ratios exhibit an asymmetrical binary weight distribution relationship. Specifically, within an array group with 3 configuration bits, the binary weight hysteresis adjustment ratio coefficients are statically designed with a geometrically related size of 1:2:4.

[0039] The system executes discrete quantization scheduling calculation logic for the forward flip hysteresis threshold width based on the aforementioned geometric configuration, that is, mapping the currently activated external digital control word state to the corresponding channel physical impedance state. In a preferred embodiment, the calculation logic for this discrete channel width and impedance adjustment is presented through the following array of formulas:

[0040]

[0041]

[0042] Among them, W fb,nThis represents the actual fabrication channel width of the hysteresis regulating transistor 207 in the nth parallel branch; n represents the corresponding control word bit variable D connected to this branch. n The logical index bit; W0 represents the transistor base width scaling factor of the preset base width unit; based on this calculation logic, the transistor widths corresponding to the three parallel branches are precisely processed to W0, 2W0 and 4W0 respectively. V hys R represents the forward flip hysteresis threshold width formed by the circuit contention mechanism. in R represents the equivalent forward impedance parameter of the main circuit system. fb This indicates that after all feedback branches in the active conducting state are superimposed, the signal is sent to the intermediate voltage node V. mid The total equivalent positive feedback on-resistance exhibited by the injected compensation charge; f represents the voltage ratio mapping correlation function.

[0043] Based on this binary weighted array architecture, the programmable positive feedback array 103 can provide the system with a linear hysteresis width selection sequence of up to 8 levels. When a specific control word bit variable D of the multi-bit digital control signal word... n When assigned to the active conduction state, the corresponding specific control switch transistor 206 is turned on, and the hysteresis regulating transistor 207 connected in series with a specific weight width is connected and changes the equivalent positive feedback conduction impedance R of the entire circuit. fb This also changes the equivalent intrinsic parasitic capacitance C that exists at that node. fb By flexibly switching different conduction levels under varying noise environments, the system achieves discrete step-wise scaling of the forward flip hysteresis threshold width V. hys The control objective is to maintain the forward flip hysteresis threshold width V. hys Maintain a constant physical width of the threshold decision window when the external power supply rail voltage undergoes a swing transition.

[0044] The input of the output shaping buffer stage 104 is coupled to the intermediate voltage node V via cascaded leads. mid The internal core module of the output shaping buffer stage 104 is configured as a group of static inverters connected in series. In the specific signal chain structure, the gate input pin of the first-stage static inverter 208 is directly connected to obtain the intermediate voltage node V. mid The waveform shows a weak flipping motion after hysteresis filtering. After being amplified through multiple stages, the signal is driven outward from the drain output of the last stage static inverter 209, resulting in a standard digital pulse signal with steep edges and full swing characteristics.

[0045] In summary, the wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit provided in this application constrains the upper limit of DC shoot-through by subthreshold operating state, combines the long-channel integral charge delay effect of current starvation stage, and superimposes discrete stepped binary multi-feedback channel cooperative control. It can maintain leakage current at the nanowatt level in harsh power supply environments with voltage drop fluctuations of several times, and exhibits flexible and varied noise filtering and edge recovery and reshaping capabilities for complex RF environment noise floor.

[0046] Example 2

[0047] like Figure 3 As shown, this embodiment provides a passive IoT system node 300 assembled using the internal circuit architecture described in Embodiment 1. The passive IoT system node 300, as a closed hardware entity for external environment sensing and interaction, mainly includes an antenna module 301, a wake-up receiver front-end module, and a digital baseband control module 303.

[0048] Antenna module 301 faces the open radio frequency space and has an internal radio frequency antenna resonant structure configured to passively receive and capture high-frequency radio frequency signal carriers scattered in space. A tight physical and electrical connection is established between the wake-up receiver front-end module and antenna module 301. Internally, the front-end module has a radio frequency energy envelope detector 302 coupled to the signal inflow stage, and a core wide-voltage ultra-low-power hysteresis-adjustable Schmitt trigger circuit 100, as detailed in Embodiment 1, is arranged in series in the middle and rear stages.

[0049] In the macroscopic signal transmission link of the system, the RF energy envelope detector 302 extracts and purifies the baseband profile of the high-frequency alternating pulse RF signal collected and sent by the antenna module 301, and converts it downlink into an analog envelope signal with slowly varying envelope fluctuations. This extracted analog envelope signal is then seamlessly transmitted to the current-starved input stage signal receiving port of the wide-voltage ultra-low-power hysteresis-adjustable Schmitt trigger circuit 100. The wide-voltage ultra-low-power hysteresis-adjustable Schmitt trigger circuit 100 is responsible for determining and shaping the anti-interference threshold of the analog envelope signal, and then outputs a digital pulse signal from the subsequent pin.

[0050] The digital baseband control module 303 is located behind the receiver in the layout, and its hardware core houses the main control chip 304, which executes complex communication logic. The main control chip 304 has a dedicated trigger response terminal. The digital pulse signal output by the wide-voltage ultra-low-power hysteresis adjustable Schmitt trigger circuit 100 is directly transmitted to the wake-up interrupt pin of the main control chip 304 via printed circuit board traces. The digital baseband control module 303 is in a passive listening standby state. Once it receives an externally delivered toggle edge pulse signal, it immediately triggers the full hard wake-up operation procedure of the entire high-energy-consuming subsystem based on the digital pulse signal.

[0051] To achieve the internal energy closed-loop self-sufficiency of the passive IoT system node 300, the system, as the external front-end structure supporting the operation of the passive node, also integrates a key passive environmental energy harvesting power management module 305. The passive environmental energy harvesting power management module 305 includes an energy capture chip for collecting weak charges, supplemented by a supercapacitor energy storage hardware structure. This energy harvesting module is directly connected in parallel to the signal terminal network of the front-end antenna module 301, continuously extracting radio frequency energy from the received radio frequency signals and physically converting it into a DC power supply voltage to support the operation of the semiconductor system through a voltage doubler rectification mechanism. The generated DC power supply voltage is directly connected to the system's unified global power rail, thereby continuously providing the basic operating power guarantee for the wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit 100.

[0052] In the complex dynamic workflow, a forward pulse triggering relationship exists between the digital baseband control module 303 and the trigger circuit, while the main control terminal is configured with a control bus interface for feedback. The system executes automatic environmental noise adaptive shielding matching logic, that is, the wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit 100 uses the main control terminal's configured bus interface to receive multi-bit digital control signal words in real time and drive the array channel to conduct, so that the equivalent anti-interference hysteresis window formed is precisely matched and always slightly greater than the background noise amplitude V of the currently monitored space radio frequency environment. noise .

[0053] When the passive IoT system node 300 moves or the external energy field strength of the antenna module 301 changes abruptly, causing fluctuations in the energy captured by the front end, resulting in a severe envelope offset swing of the DC power supply voltage of the internal global track within the range of 0.6V to 3.3V, the system can maintain a constant forward flip hysteresis threshold width by relying on the synergistic clamping effect of the internal module's unique subthreshold bias protection network and long-channel filter structure. This ensures that the threshold width is greater than the background noise floor amplitude V. noise Meanwhile, the static shoot-through leakage current I of the entire system node... total It is defended and safely confined below the critical line of the ultimate nanowatt level, which is less than 50 nA limit standard.

[0054] In summary, this embodiment, by embedding a trigger buffer architecture containing deep hysteresis array adjustment and subthreshold leakage current defense mechanism between the passive antenna and the dormant baseband chip, not only prevents the global power consumption collapse crisis caused by sudden changes in the radio frequency environment, but also eliminates the phenomenon of the meager energy storage inside the system node being mistakenly awakened and consumed by background high-frequency noise by the mechanism of dynamically amplifying the anti-shake window by tracking the ambient noise floor. This improves the survival and deployment cycle and operational reliability of various passive sensing sensor networks in real complex spaces.

[0055] It should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A wide-voltage, ultra-low-power, hysteresis-adjustable Schmitt trigger circuit, characterized in that, include: The subthreshold adaptive bias module is connected in series between the global power rail and the ground rail. It contains transistors that operate in the deep subthreshold region and is configured to extract the transient potential of the supply voltage and generate the first bias node potential and the second bias node potential. A current-starved input stage includes a pull-up network and a pull-down network that are controlled to the first bias node potential and the second bias node potential, respectively. The pull-up network and the pull-down network receive an analog envelope signal and converge to an intermediate voltage node. The pull-up network and the pull-down network limit the charge and discharge current limits through the first bias node potential and the second bias node potential. A programmable positive feedback array is bridged between the intermediate voltage node and the power supply rail. It contains a group of regulating transistors with a binary proportional width, receives a multi-bit digital control signal word, and sets the conduction state of the regulating transistor group and the feedback current injection intensity based on the multi-bit digital control signal word. An output shaping buffer stage is cascaded to the intermediate voltage node and outputs a digital pulse signal.

2. The wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit as described in claim 1, characterized in that, The subthreshold adaptive bias module includes a plurality of diode-connected metal-oxide-semiconductor field-effect transistors arranged in series, wherein the gate and drain of the diode-connected metal-oxide-semiconductor field-effect transistors are shorted; the plurality of diode-connected metal-oxide-semiconductor field-effect transistors arranged in series form a voltage divider network, and the voltage divider taps are respectively led out as the first bias node potential and the second bias node potential.

3. The wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit as described in claim 2, characterized in that, The voltage divider network is configured such that when the voltage V of the global power rail... DD When the voltage rises to the high potential limit, the drain-source shoot-through current I of the diode-connected metal-oxide-semiconductor field-effect transistor will be... leak The physical clamp is located within the nanoampere level limit defined by the deep subthreshold region; the first bias node potential V bp With the second bias node potential V bn Each satisfies the preset voltage divider equation constraints, and the first bias node potential V bp Configured to limit the peak charging current I of the downstream branch cp The second bias node potential V bn Configured to limit the peak discharge current I of the downstream branch cn .

4. The wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit as described in claim 1, characterized in that, The pull-up network within the current-starved input stage includes a first-type transistor, and the pull-down network includes a second-type transistor; the gate of the first-type transistor is connected to the first bias node potential, and the gate of the second-type transistor is connected to the second bias node potential; the saturation leakage current of the first-type transistor and the second-type transistor limits the charge and discharge rate of the intermediate voltage node, and the input analog envelope signal is subjected to low-pass time constant delay filtering before the node potential crosses the flip threshold.

5. The wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit as described in claim 4, characterized in that, The first type of transistor is a P-channel metal-oxide-semiconductor field-effect transistor, and the second type of transistor is an N-channel metal-oxide-semiconductor field-effect transistor; the charge / discharge rate is controlled by an integral constant. The integral constant The drain saturation-limited current I of the first type transistor or the second type transistor sat and the lumped parasitic capacitance C of the intermediate voltage node mid Together, the first type of transistor and the second type of transistor are determined by the integration constant. For input waveforms with pulse width less than T noise The high-frequency AC noise level peaks are filtered out.

6. The wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit as described in claim 1, characterized in that, The programmable positive feedback array includes multiple parallel hysteresis feedback adjustment branches, each of which is controlled by an independent bit in the multi-bit digital control signal word; the channel widths of the transistors in each hysteresis feedback adjustment branch are arranged according to a first ratio, a second ratio, and a third ratio, and the first ratio, the second ratio, and the third ratio have a binary weight distribution relationship.

7. The wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit as described in claim 6, characterized in that, The aspect ratio of the first, second, and third ratios is configured as 1:2:4; each of the hysteresis feedback adjustment branches is configured with a corresponding control word variable D. n Based on the control word bit variable D which is in an active state n Change the equivalent positive feedback on-resistance R of the equivalent connection to the intermediate voltage node. fb and equivalent intrinsic parasitic capacitance C fb Scale the forward flip hysteresis threshold width V according to discrete steps hys And maintain the forward flip hysteresis threshold width V hys The threshold window remains constant when the voltage on the power supply rail changes amplitude.

8. A passive Internet of Things (IoT) system node, characterized in that, include: The antenna module receives radio frequency signals and outputs an analog envelope signal of the radio frequency signals; The wake-up receiver front-end module is electrically connected to the antenna module and receives the analog envelope signal. The wake-up receiver front-end module includes the wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit as described in claim 1. The wide-voltage ultra-low power hysteresis adjustable Schmitt trigger circuit shapes the analog envelope signal and outputs the digital pulse signal. The digital baseband control module receives the digital pulse signal and triggers a system wake-up operation based on the digital pulse signal.

9. The passive IoT system node as described in claim 8, characterized in that, It also includes an energy harvesting module, which is connected in parallel to the antenna module to acquire the radio frequency energy of the received radio frequency signal and convert it into a DC power supply voltage. The DC power supply voltage is connected to the global power rail to provide operating power for the wide voltage ultra-low power hysteresis adjustable Schmitt trigger circuit.

10. The passive IoT system node as described in claim 9, characterized in that, The wide-voltage ultra-low-power hysteresis adjustable Schmitt trigger circuit is based on the received multi-bit digital control signal word, matching the background noise amplitude V of the current radio frequency environment. noise When a sudden change in the external energy field strength of the antenna module causes the DC power supply voltage to fluctuate within the range of 0.6V to 3.3V, the forward flip hysteresis threshold width is maintained to be greater than the background noise amplitude V. noise The static shoot-through leakage current I of the entire system node is limited. total It is below the critical line of less than 50 nA in the nanowatt level.

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