A method for manufacturing a semiconductor structure

Abstract

This invention provides a method for fabricating a semiconductor structure, relating to the field of semiconductor technology. The method includes: providing a substrate, the substrate comprising a substrate, an oxide layer, a first gate, a second gate, and a first etch stop layer, wherein the oxide layer is formed on the surface of the substrate, a doped region is formed in the substrate between the first gate and the second gate, a first opening is formed within the first gate, and a second opening is formed within the doped region; removing the first etch stop layer, forming a first metal silicide layer within the first opening, and forming a second metal silicide layer within the second opening; forming a second etch stop layer and a dielectric layer on the surface of the substrate; etching the dielectric layer to expose the area of ​​the second etch stop layer used to form a contact plug and performing plasma modification treatment on it; and etching the second etch stop layer to form a contact hole. The fabrication method of this invention can effectively alleviate the leakage problem of semiconductor structures.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Technology

[0002] Contact plugs are pillar-shaped metal structures filled within contact holes in semiconductor manufacturing processes to connect underlying devices (such as source, drain, and gate) to external circuitry. When forming contact holes, an etch stop layer is typically placed on the sidewall of the gate to protect it from over-etching damage. Existing technologies have relatively poor etching precision for the etch stop layer, which can easily lead to leakage current problems in the semiconductor structure. Summary of the Invention

[0003] This invention provides a method for fabricating a semiconductor structure to alleviate the problem of leakage current in semiconductor structures.

[0004] The present invention provides a method for fabricating a semiconductor structure, comprising: A substrate is provided, the substrate including a substrate, an oxide layer, a first gate, a second gate, a first sidewall, a second sidewall, and a first etch stop layer, the oxide layer being formed on the surface of the substrate, the first gate and the second gate being disposed at a distance from each other on the surface of the oxide layer, a doped region being formed in the substrate between the first gate and the second gate, the first sidewall being formed on both sides of the first gate, the second sidewall being formed on both sides of the second gate, and the first etch stop layer being formed on the surfaces of the first gate, the second gate, the first sidewall, the second sidewall, and the oxide layer; A first opening is formed within the first gate, and a second opening is formed within the doped region; Remove the first etch stop layer, form a first metal silicide layer in the first opening, and form a second metal silicide layer in the second opening; A second etch stop layer and a dielectric layer are sequentially formed on the surface of the substrate; The dielectric layer is etched to expose the area of ​​the second etch stop layer used to form the contact plug; The region used to form the contact plug is subjected to plasma modification treatment; The second etch stop layer is etched to form a contact hole.

[0005] In one embodiment of the present invention, a first metal silicide layer is formed in the first opening, and a second metal silicide layer is formed in the second opening, comprising the following steps: A first metal layer is formed in the first opening, and a second metal layer is formed in the second opening; The first metal layer and the second metal layer are annealed, the first metal layer reacts with the first gate, and the second metal layer reacts with the doped region. The substrate is cleaned to remove the unreacted first metal layer and second metal layer, forming the first metal silicide layer and the second metal silicide layer.

[0006] In one embodiment of the present invention, both the first metal layer and the second metal layer are nickel-platinum alloy layers, the annealing temperature is 200~750℃, and the annealing time is 30~120s.

[0007] In one embodiment of the present invention, a first groove is formed on the first metal silicide layer, and a second groove is formed on the second metal silicide layer. The depth of the first groove and the second groove is 50~70 Å, the width of the first metal silicide layer on both sides of the first groove is 10~20 Å, and the width of the second metal silicide layer on both sides of the second groove is 10~20 Å.

[0008] In one embodiment of the present invention, when etching the second etching stop layer to form a contact hole, wet etching is used. The etching solution for the wet etching includes HF and NH4F, and the volume ratio of HF to NH4F is 1:5 to 1:7.

[0009] In one embodiment of the present invention, when the exposed second etch stop layer is subjected to plasma modification treatment, the source power is 30~100W, the bias power is 50~500W, the cavity pressure is 10~30mTorr, and the cavity temperature is 10~50℃.

[0010] In one embodiment of the present invention, when the exposed second etch stop layer is subjected to plasma modification treatment, the modification gas is a mixture of argon and hydrogen, wherein the flow rate of argon is 50~100 sccm, the flow rate of hydrogen is 20~50 sccm, and the flow rate ratio of argon to hydrogen is 2:1~5:1.

[0011] In one embodiment of the present invention, the area of ​​the second etch stop layer used to form the contact plug includes: the surface of the second etch stop layer corresponding to the first opening and the second opening.

[0012] In one embodiment of the present invention, the area of ​​the second etch stop layer used to form the contact plug further includes: the surface of the second etch stop layer corresponding to the first opening and the second opening.

[0013] In one embodiment of the present invention, after forming the contact hole, the preparation method further includes filling the contact hole with a conductive material to form a contact plug.

[0014] The beneficial effects of this invention are as follows: The method for fabricating a semiconductor structure proposed in this invention involves forming a first metal silicide layer within a first opening of a first gate, forming a second metal silicide layer within a second opening of a doped region, and then sequentially forming a second etch stop layer and a dielectric layer on the surface of a substrate. The dielectric layer is etched to expose the area of ​​the second etch stop layer used to form contact plugs. The area used to form contact plugs is then subjected to plasma modification treatment. Finally, the second etch stop layer is etched to form contact holes. An unexpected effect of this invention is that by performing plasma modification treatment on the area of ​​the second etch stop layer used to form contact plugs, it makes the area anisotropic during subsequent etching processes, improving the etching accuracy of the second etch stop layer, effectively alleviating the leakage current problem in the semiconductor structure, and significantly improving the yield of the semiconductor structure. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0016] In the attached diagram: Figure 1 The microstructure of contact holes formed in existing technologies; Figure 2 This is a flowchart illustrating the fabrication process of a semiconductor structure provided in one embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a substrate provided in one embodiment of the present invention; Figure 4 This is a schematic diagram of the formation of a first photoresist layer provided in one embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the formation of a first opening and a second opening according to an embodiment of the present invention; Figure 6 This is a schematic diagram of removing the first photoresist layer according to an embodiment of the present invention; Figure 7 This is a schematic diagram of removing the first etch stop layer according to an embodiment of the present invention; Figure 8 This is a schematic diagram illustrating the formation of a first metal silicide layer and a second metal silicide layer according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the formation of a second etch stop layer provided in one embodiment of the present invention; Figure 10This is a schematic diagram of the formation of a dielectric layer provided in one embodiment of the present invention; Figure 11 This is a schematic diagram of the formation of a bottom anti-reflective coating, an advanced patterned thin film, and a second photoresist layer according to an embodiment of the present invention. Figure 12 This is a schematic diagram of plasma modification treatment of the second etch stop layer provided in one embodiment of the present invention; Figure 13 This is a schematic diagram of forming a contact hole according to one embodiment of the present invention; Figure 14 This is a schematic diagram of forming a contact plug according to an embodiment of the present invention; Figure 15 This is a schematic diagram of the formation of a bottom anti-reflective coating, an advanced patterned thin film, and a second photoresist layer provided in another embodiment of the present invention; Figure 16 This is a schematic diagram of plasma modification treatment of the second etch stop layer provided in another embodiment of the present invention; Figure 17 This is a schematic diagram of the formation of a contact hole provided in another embodiment of the present invention; Figure 18 This is a schematic diagram of forming a contact plug according to another embodiment of the present invention.

[0017] The attached figures are labeled as follows: 10. Substrate; 100. Substrate; 110. Doped region; 111. Second opening; 112. Second metal silicide layer; 1121. Second trench; 200. Oxide layer; 300. First gate; 310. First sidewall; 311. First silicon oxide layer; 312. Silicon nitride layer; 313. Second silicon oxide layer; 320. First opening; 321. First metal silicide layer; 3211. First trench; 400. Second Gate; 410, Second sidewall; 500, First etch stop layer; 510, First photoresist layer; 600, Second etch stop layer; 700, Dielectric layer; 710, Second photoresist layer; 720, Bottom anti-reflective coating; 730, Advanced patterned thin film; 800, Contact hole; 810, First contact hole; 820, Second contact hole; 900, Contact plug; 910, First contact plug; 920, Second contact plug. Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0021] In this document, when referring to numerical ranges, unless otherwise specified, the distribution of selectable values ​​within a numerical range is considered continuous, including the two endpoints of the range (i.e., the minimum and maximum values), and every value between these two endpoints. When multiple numerical ranges are provided to describe a feature or property, these numerical ranges can be combined.

[0022] Research has found that when forming contact holes between adjacent gates, as the linewidth gradually decreases, the etch stop layer is prone to inward bowing distortion during the etching of the dielectric layer between adjacent gates. This causes the lateral size of the contact hole to expand excessively, exceeding the safe distance between it and the adjacent gate (e.g., ...). Figure 1 As shown in the red-marked area (the morphology is illustrated), this ultimately leads to a short circuit between the metal inside the contact hole and the gate, causing electrical failure of the device. During the formation of the shared contact hole for electrically connecting the gate and the source / drain doped regions, over-etching is easily achieved when etching the etch stop layer, which exposes the substrate between the gate and the metal silicide (e.g., ...). Figure 1 (As shown in the green-marked area), damage to the substrate can lead to material loss and severe leakage current, degrading device performance. Therefore, this invention provides a method for fabricating a semiconductor structure to alleviate leakage current problems and improve semiconductor structure performance.

[0023] Please see Figures 2 to 18 As shown, the present invention provides a method for preparing a semiconductor structure, comprising the following steps: S1, providing such Figure 3 The substrate 10 shown includes a substrate 100, an oxide layer 200, a first gate 300, a second gate 400, a first sidewall 310, a second sidewall 410, and a first etch stop layer 500. The oxide layer 200 is formed on the surface of the substrate 100. The first gate 300 and the second gate 400 are disposed at intervals on the surface of the oxide layer 200. A doped region 110 is formed in the substrate 100 between the first gate 300 and the second gate 400. The first sidewall 310 is formed on both sides of the first gate 300, and the second sidewall 410 is formed on both sides of the second gate 400. The first etch stop layer 500 is formed on the surfaces of the first gate 300, the second gate 400, the first sidewall 310, the second sidewall 410, and the oxide layer 200. S2, such as Figure 5 As shown, a first opening 320 is formed in the first gate 300, and a second opening 111 is formed in the doped region 110; S3, such as Figure 7 and Figure 8 As shown, the first etch stop layer 500 is removed, a first metal silicide layer 321 is formed in the first opening 320, and a second metal silicide layer 112 is formed in the second opening 111. S4, such as Figure 9 and Figure 10 As shown, a second etch stop layer 600 and a dielectric layer 700 are sequentially formed on the surface of the substrate 10; S5, such as Figure 12 and Figure 16 As shown, the dielectric layer 700 is etched to expose the area of ​​the second etch stop layer 600 used to form the contact plug 900; S6, such as Figure 12 and Figure 16 As shown, the region used to form the contact plug 900 is subjected to plasma modification treatment; S7, such as Figure 13 and Figure 17 As shown, the second etch stop layer 600 is etched to form the contact hole 800.

[0024] Please see Figure 3As shown, in step S1 of this invention, the substrate 100 can be any material suitable for forming a semiconductor structure, such as undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). This invention does not limit the specific material and thickness of the substrate 100, and the substrate 100 can be a P-doped semiconductor substrate or an N-doped semiconductor substrate. The doping type of the impurities can be flexibly set according to the desired semiconductor structure. In this embodiment, the substrate 100 is, for example, a silicon substrate.

[0025] In one embodiment, the substrate 10 is fabricated on the basis of the substrate 100, and the fabrication method of the substrate 10 is as follows: Please see Figure 3 As shown, in one embodiment of the present invention, an oxide layer 200 is formed on the surface of the substrate 100. The material of the oxide layer 200 can be silicon dioxide or similar materials, and the oxide layer 200 can be formed by any one of the following methods: dry oxygen oxidation, wet oxygen oxidation, or in-situ steam generation (ISSG). In this embodiment, for example, the oxide layer 200 is formed by dry oxygen oxidation. For example, the substrate 100 is placed in a furnace tube, oxygen is introduced, and the surface of the substrate 100 reacts with oxygen at a high temperature to generate a dense oxide layer 200. The preparation process of the substrate 10 may also include cleaning the substrate 100 before forming the oxide layer 200. By cleaning the substrate 100, impurities present on the surface of the substrate 100 can be removed, avoiding the impact of impurities on subsequent processes, thereby ensuring the performance of the device. For example, the substrate 100 can be cleaned using a cleaning solution or by purging the substrate 100 with a gas such as nitrogen.

[0026] Please see Figure 3 As shown, in one embodiment of the present invention, after forming the oxide layer 200, a first gate 300 and a second gate 400 are formed on the surface of the oxide layer 200, with the first gate 300 and the second gate 400 disposed at intervals on the surface of the oxide layer 200. The material of the first gate 300 and the second gate 400 is, for example, polysilicon, and the polysilicon can be P-type doped or N-type doped to ensure that the doping type of the polysilicon is different from the doping type of the substrate 100, thereby improving the performance of the semiconductor device. The thickness of the first gate 300 and the second gate 400 can be set according to actual needs.

[0027] Please see Figure 3As shown, in one embodiment of the present invention, after forming the first gate 300 and the second gate 400, a first sidewall 310 is formed on both sides of the first gate 300, and a second sidewall 410 is formed on both sides of the second gate 400 to protect the sidewalls of the first gate 300 and the second gate 400. The first sidewall 310 and the second sidewall 410 can be a single-layer structure or a stacked structure, and the materials of the first sidewall 310 and the second sidewall 410 include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, and boron nitride. In this embodiment, both the first sidewall 310 and the second sidewall 410 are stacked structures, including a first silicon oxide layer 311, a silicon nitride layer 312, and a second silicon oxide layer 313.

[0028] Please see Figure 3 As shown, in one embodiment of the present invention, after forming the first sidewall 310 and the second sidewall 410, ion implantation is performed in the substrate 100 between the first sidewall 310 and the second sidewall 410 to form a doped region 110. After forming the doped region 110, a first etch stop layer 500 is formed on the surfaces of the first gate 300, the second gate 400, the first sidewall 310, the second sidewall 410, and the oxide layer 200. The material of the first etch stop layer 500 can be a nitride layer. In this embodiment, the nitride layer is, for example, silicon nitride. The nitride layer can be prepared by any one of the following processes: low-pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition. For example, when preparing the nitride layer using a low-pressure chemical vapor deposition process, silicon nitride can be generated by reacting ammonia and dichlorosilane. By setting a first etching stop layer 500, damage to the first sidewall 310 and the second sidewall 410 can be reduced when the first opening 320 and the second opening 111 are subsequently formed.

[0029] Please see Figure 4 and Figure 5As shown, in step S2 of this invention, after forming the first etch stop layer 500, photoresist is coated on the first etch stop layer 500 to form a first photoresist layer 510. The type of photoresist material is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, photolithography processes such as mask exposure and development are used to pattern the coated photoresist. Using the patterned first photoresist layer 510 as a mask, the substrate 10 is etched, sequentially removing a portion of the first etch stop layer 500 and a portion of the first gate 300, forming a first opening 320 in the first gate 300. Then, a portion of the first etch stop layer 500 and the doped region 110 are sequentially removed, forming a second opening 111 in the doped region 110. The etching process on the substrate 10 can be performed using either dry etching or wet etching, for example, dry etching. The gases used in dry etching include one or more of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or hydrogen bromide (HBr), or combinations thereof with oxygen (O2).

[0030] Please see Figure 6 and Figure 7 As shown, in step S3 of the present invention, after forming the first opening 320 and the second opening 111, the first photoresist layer 510 and the first etch stop layer 500 are removed sequentially. For example, the first photoresist layer 510 is removed by wet cleaning or ashing treatment, and the first etch stop layer 500 is removed by methods such as dry etching, wet etching, or a combination of both. In this embodiment, phosphoric acid is used, for example, to remove the first etch stop layer 500.

[0031] Please see Figure 8 As shown, in one embodiment of the present invention, after removing the first etch stop layer 500, a first metal silicide layer 321 is formed in the first opening 320, and a second metal silicide layer 112 is formed in the second opening 111. Specifically, a first metal layer is formed in the first opening 320, and a second metal layer is formed in the second opening 111. The first and second metal layers are annealed, with the first metal layer reacting with the first gate 300 and the second metal layer reacting with the doped region 110. The substrate 10 is then cleaned to remove the unreacted first and second metal layers, resulting in the first metal silicide layer 321 and the second metal silicide layer 112. For example, both the first metal layer and the second metal layer are nickel-platinum alloy (NiPt) layers, and the annealing temperature is, for example, 200~750°C, such as any value among 200°C, 400°C, 600°C or 750°C, and the annealing time is, for example, 30~120s, such as any value among 30s, 50s, 80s, 100s or 120s.

[0032] For example, the substrate 10 is sequentially cleaned with a mixed solution of sulfuric acid and hydrogen peroxide (SPM) and a mixed solution of ammonia, hydrogen peroxide, and ultrapure water (APM) to remove the unreacted first and second metal layers. Exemplarily, when cleaning with SPM, the volume ratio of sulfuric acid to hydrogen peroxide is 3:1 to 5:1, such as any value from 3:1 to 5:1, and the cleaning temperature is 100 to 150°C, such as any value from 100°C, 120°C, 130°C, or 150°C. For example, when cleaning with APM, the volume ratio of ammonia, hydrogen peroxide, and ultrapure water is 1:1:5 to 1:2:7, and the cleaning temperature is 65 to 80°C, such as any value from 65°C to 80°C. In this invention, a first groove 3211 is formed on a first metal silicide layer 321, and a second groove 1121 is formed on a second metal silicide layer 112. The depth of the first groove 3211 and the second groove 1121 is 50~70 Å, for example, any value among 50 Å, 60 Å or 70 Å. The width of the first metal silicide layer 321 on both sides of the first groove 3211 is 10~20 Å, for example, any value among 10 Å, 15 Å or 20 Å. The width of the second metal silicide layer 112 on both sides of the second groove 1121 is 10~20 Å, for example, any value among 10 Å, 15 Å or 20 Å. Forming a first groove 3211 on the first metal silicide layer 321 and a second groove 1121 on the second metal silicide layer 112 can increase the contact area between the first metal silicide layer 321 and the second metal silicide layer 112 and the contact plug 900. This can effectively reduce contact resistance and parasitic series resistance, improve device driving capability and conduction current, and at the same time disperse current density to avoid electromigration, local overheating and device damage caused by current concentration. It can also optimize heat dissipation, improve operational reliability and service life, and improve the yield of semiconductor structures.

[0033] Please see Figure 9 As shown, in step S4 of the present invention, after forming the first metal silicide layer 321 and the second metal silicide layer 112, a second etch stop layer 600 is formed on the surface of the substrate 10. The second etch stop layer 600 covers the surface of the oxide layer 200, the surface of the first sidewall 310, the surface of the second sidewall 410, the surface of the first metal silicide layer 321, and the surface of the second metal silicide layer 112. In this embodiment, the material of the second etch stop layer 600 is, for example, silicon nitride, which can be prepared by any one of the following processes: low-pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition.

[0034] Please see Figure 10 As shown, in one embodiment of the present invention, after forming a second etch stop layer 600, a dielectric layer 700 is formed on the surface of the second etch stop layer 600. The material of the dielectric layer 700 is, for example, silicon dioxide. The present invention does not limit the deposition method of the dielectric layer 700; for example, the dielectric layer 700 can be formed by chemical vapor deposition (CVD) or high aspect ratio process CVD (HARP CVD). In this embodiment, the dielectric layer 700 is obtained, for example, by depositing tetraethyl orthosilicate (TEOS), specifically, by introducing tetraethyl orthosilicate and an oxygen-containing precursor, the oxygen-containing precursor including, for example, one of O2 or O3.

[0035] Please see Figure 11 As shown, in step S5 of the present invention, after forming the dielectric layer 700, photoresist is coated on the surface of the dielectric layer 700 to form a second photoresist layer 710. The type of photoresist material is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, the second photoresist layer 710 is obtained by photolithography processes such as mask exposure and development. In this embodiment, before forming the second photoresist layer 710, the preparation method further includes sequentially forming a bottom anti-reflection coating (BARC) 720 and an advanced patterning film (APF) 730 on the surface of the dielectric layer 700. The material of the bottom anti-reflection coating 720 is, for example, a cross-linked carbon-based polymer, and the material of the advanced patterning film 730 is, for example, amorphous carbon. The bottom anti-reflective coating 720 can suppress bottom reflection, eliminate photolithography standing wave effect, and improve pattern accuracy and linewidth stability. The advanced patterned thin film 730, as a hard mask with high etch selectivity, compensates for the poor etching resistance of photoresist, avoids rapid wear and deformation collapse of photoresist, ensures complete pattern transfer, optimizes the nitride layer etching profile morphology, and improves process window and chip fabrication yield. In this embodiment, the patterned second photoresist layer 710 exposes the corresponding area of ​​the first opening 320 and the corresponding area of ​​the second opening 111 on the surface of the advanced patterned thin film 730. Figure 11 (The area not covered by the second photoresist layer 710).

[0036] Please see Figure 12As shown, in one embodiment of the present invention, using a patterned second photoresist layer 710 as a mask, the advanced patterned thin film 730, the bottom anti-reflective coating 720, and the dielectric layer 700 are etched sequentially to remove the second photoresist layer 710, the advanced patterned thin film 730, and the bottom anti-reflective coating 720, exposing the surface of the second etch stop layer 600 for forming the area of ​​the contact plug 900. Figure 12 (The area not covered by the intermediate dielectric layer 700). Subsequently, the area of ​​the second etch stop layer 600 used to form the contact plug 900 is subjected to plasma modification treatment to make the second etch stop layer 600 anisotropic during subsequent etching, reducing lateral etching of the second etch stop layer 600. Exemplarily, when performing plasma modification treatment on the exposed second etch stop layer 600, the source power is used to dissociate the plasma. Adjusting the source power can control the plasma energy density, the number of active particles, and the bombardment intensity. In this invention, the source power is, for example, 30~100W, such as any value from 30W, 50W, 80W, or 100W. A bias power is applied to the second etch stop layer 600, and plasma ions are directionally accelerated and bombarded along the 10 normal direction of the substrate. This enhances vertical etching and surface modification, while suppressing lateral corrosion and disordered reactions, resulting in significant anisotropy in the modified second etch stop layer 600 in terms of microstructure, surface structure, and physicochemical properties. The bias power is, for example, 50~500W, such as any value from 50W, 100W, 200W, 400W, or 500W. The chamber pressure is 10~30mTorr, such as any value from 10mTorr, 20mTorr, or 30mTorr. The chamber temperature is 10~50℃, such as any value from 10℃, 30℃, or 50℃. The modified gas is, for example, a mixture of argon and hydrogen, with the argon flow rate being 50-100 sccm, such as any value within the range of 50-100 sccm, and the hydrogen flow rate being 20-50 sccm, such as any value within the range of 20-50 sccm, such as 20-50 sccm, 30-40-50 sccm, or 50-50 sccm. Another example is an argon to hydrogen flow rate ratio of 2:1 to 5:1, such as any value within the range of 2:1 to 5:1, such as 2:1, 3:1, 4:1, or 5:1.

[0037] Please see Figure 13As shown, in one embodiment of the present invention, after the region of the second etch stop layer 600 used to form the contact plug 900 is subjected to plasma modification treatment, the second etch stop layer 600 is etched to form the contact hole 800. Exemplarily, the second etch stop layer 600 is etched using wet etching. The wet etching solution includes HF and NH4F, and the volume ratio of HF to NH4F is 1:5 to 1:7, for example, any value from 1:5 to 1:7 such as 1:5, 1:6, or 1:7. In this embodiment, the contact hole 800 includes a first contact hole 810 and a second contact hole 820. The first contact hole 810 penetrates the dielectric layer 700 and the second etch stop layer 600 on the first gate 300 and exposes the first metal silicide layer 321. The second contact hole 820 penetrates the dielectric layer 700 and the second etch stop layer 600 on the doped region 110 and exposes the second metal silicide layer 112. This etching process exhibits excellent selectivity, efficiently removing the plasma-modified second etch stop layer 600 while exhibiting minimal corrosion and etching effects on the metal silicide layer, thus avoiding damage to the underlying first metal silicide layer 321 and second metal silicide layer 112. By plasma-modifying the second etch stop layer 600, lateral etching during the formation of the second contact hole 820 can be reduced, ensuring the spacing between the subsequently formed second contact plug 920 and the first gate 300 and second gate 400, reducing the risk of short circuits and mitigating leakage issues in the semiconductor structure.

[0038] Please see Figure 14 As shown, in one embodiment of the present invention, after forming the first contact hole 810 and the second contact hole 820, a conductive material is filled into the first contact hole 810 to form a first contact plug 910, and a conductive material is filled into the second contact hole 820 to form a second contact plug 920. The first contact plug 910 is connected to the first gate 300, and the second contact plug 920 is connected to the doped region 110. For example, a physical vapor deposition process can be used to form it, and the conductive material is, for example, tungsten.

[0039] Please see Figure 15As shown, in another embodiment of the present invention, after forming the dielectric layer 700, a bottom anti-reflection coating (BARC) 720 and an advanced patterning film (APF) 730 are sequentially formed on the surface of the dielectric layer 700. The material of the bottom anti-reflection coating 720 is, for example, a cross-linked carbon-based polymer, and the material of the advanced patterning film 730 is, for example, amorphous carbon. Photoresist is coated on the surface of the advanced patterning film 730 to form a second photoresist layer 710. The type of photoresist material is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, photolithography processes such as mask exposure and development are performed to obtain the patterned second photoresist layer 710. In this embodiment, the patterned second photoresist layer 710 exposes the corresponding area of ​​the first opening 320 and the corresponding area of ​​the second opening 111 on the surface of the advanced patterning film 730, as well as the corresponding area between them. Figure 15 (The area not covered by the second photoresist layer 710).

[0040] Please see Figure 16 As shown, in one embodiment of the present invention, using a patterned second photoresist layer 710 as a mask, the advanced patterned thin film 730, the bottom anti-reflective coating 720, and the dielectric layer 700 are etched sequentially to expose the surface of the second etch stop layer 600 for the area where the contact plug 900 is formed. Figure 16 (Area not covered by the intermediate dielectric layer 700). The area of ​​the second etch stop layer 600 used to form the contact plug 900 is subjected to plasma modification treatment to make the second etch stop layer 600 anisotropic during subsequent etching, thereby improving the etching accuracy of the second etch stop layer 600 and avoiding over-etching of the second etch stop layer 600 to expose the substrate 100 between the first sidewall 310 and the second metal silicide layer 112.

[0041] Please see Figure 17As shown, in another embodiment of the present invention, after plasma modification treatment is performed on the area of ​​the second etch stop layer 600 used to form the contact plug 900, the second etch stop layer 600 is etched to form the contact hole 800. In this embodiment, the contact hole 800 is a shared contact hole, which penetrates the dielectric layer 700 above the first gate 300 and the doped region 110, and exposes the first metal silicide layer 321 in the first gate 300, the second metal silicide layer 112 in the doped region 110, and the second etch stop layer 600 between the first sidewall 310 and the doped region 110. The height of the second etch stop layer 600 between the first sidewall 310 and the doped region 110 is adjusted according to actual needs. For example, the second etch stop layer 600 is etched using wet etching. The wet etching solution includes HF and NH4F, and the volume ratio of HF to NH4F is 1:5 to 1:7, such as any value in the range of 1:5, 1:6, or 1:7. This etching process has excellent selectivity, efficiently removing the plasma-modified second etch stop layer 600 while having a weak corrosion and etching effect on the metal silicide layer, without damaging the underlying first metal silicide layer 321 and second metal silicide layer 112. The removal status of the second etch stop layer 600 at the bottom of the shared contact hole can be confirmed by cross-sectional analysis: the initial height of the second etch stop layer 600 is measured as 'a' using a micro-section partial measurement, the remaining height of the second etch stop layer 600 after etching is measured by cross-sectional measurement, and the height of the second etch stop layer 600 on the surface of the second metal silicide layer 112 is 'c'; when c ≤ a At time b, the second etch stop layer representing the surface of the second metal silicide layer 112 is completely removed, and the shared contact hole is opened normally.

[0042] Please see Figure 18 As shown, in another embodiment of the present invention, after forming the shared contact hole, a conductive material is filled into the shared contact hole to form a shared contact plug. For example, a physical vapor deposition process can be used to form it, and the conductive material is, for example, tungsten. The shared contact plug electrically connects the first gate 300 and the doped region 110. In this embodiment, when etching the second etch stop layer 600 to form the shared contact hole, a portion of the second etch stop layer 600 between the first sidewall 310 and the doped region 110 can be retained to ensure that the substrate 100 between the first sidewall 310 and the doped region 110 is not exposed, thereby preventing the formed shared contact plug from contacting the substrate 100, effectively alleviating the problem of leakage current in the semiconductor structure, and greatly improving the yield of the semiconductor structure.

[0043] In summary, the semiconductor structure fabrication method proposed in this invention involves forming a first metal silicide layer within a first opening of a first gate, forming a second metal silicide layer within a second opening of a doped region, and then sequentially forming a second etch stop layer and a dielectric layer on the surface of a substrate. The dielectric layer is etched to expose the area of ​​the second etch stop layer used to form contact plugs. This area is then subjected to plasma modification treatment. Finally, the second etch stop layer is etched to form contact holes. An unexpected benefit of this invention is that by plasma modifying the area of ​​the second etch stop layer used to form contact plugs, it achieves anisotropy during subsequent etching, improving the etching precision of the second etch stop layer, effectively mitigating leakage current issues in semiconductor structures, and significantly improving the yield of semiconductor structures.

[0044] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate, an oxide layer, a first gate, a second gate, a first sidewall, a second sidewall, and a first etch stop layer, the oxide layer being formed on the surface of the substrate, the first gate and the second gate being disposed at a distance from each other on the surface of the oxide layer, a doped region being formed in the substrate between the first gate and the second gate, the first sidewall being formed on both sides of the first gate, the second sidewall being formed on both sides of the second gate, and the first etch stop layer being formed on the surfaces of the first gate, the second gate, the first sidewall, the second sidewall, and the oxide layer; A first opening is formed within the first gate, and a second opening is formed within the doped region; Remove the first etch stop layer, form a first metal silicide layer in the first opening, and form a second metal silicide layer in the second opening; A second etch stop layer and a dielectric layer are sequentially formed on the surface of the substrate; The dielectric layer is etched to expose the area of ​​the second etch stop layer used to form the contact plug; The region used to form the contact plug is subjected to plasma modification treatment; The second etch stop layer is etched to form a contact hole.

2. The preparation method according to claim 1, characterized in that, Forming a first metal silicide layer in the first opening and forming a second metal silicide layer in the second opening includes the following steps: A first metal layer is formed in the first opening, and a second metal layer is formed in the second opening; The first metal layer and the second metal layer are annealed, the first metal layer reacts with the first gate, and the second metal layer reacts with the doped region. The substrate is cleaned to remove the unreacted first metal layer and second metal layer, forming the first metal silicide layer and the second metal silicide layer.

3. The preparation method according to claim 2, characterized in that, Both the first metal layer and the second metal layer are nickel-platinum alloy layers, the annealing temperature is 200~750℃, and the annealing time is 30~120s.

4. The preparation method according to claim 1, characterized in that, A first groove is formed on the first metal silicide layer, and a second groove is formed on the second metal silicide layer. The depth of the first groove and the second groove is 50~70 Å. The width of the first metal silicide layer on both sides of the first groove is 10~20 Å, and the width of the second metal silicide layer on both sides of the second groove is 10~20 Å.

5. The preparation method according to claim 1, characterized in that, When etching the second etch stop layer to form contact holes, wet etching is used. The wet etching solution includes HF and NH4F, and the volume ratio of HF to NH4F is 1:5 to 1:

7.

6. The preparation method according to claim 1, characterized in that, When performing plasma modification treatment on the exposed second etch stop layer, the source power is 30~100W, the bias power is 50~500W, the cavity pressure is 10~30mTorr, and the cavity temperature is 10~50℃.

7. The preparation method according to claim 1, characterized in that, When performing plasma modification treatment on the exposed second etch stop layer, the modifying gas is a mixture of argon and hydrogen, with the argon flow rate being 50-100 sccm and the hydrogen flow rate being 20-50 sccm, and the argon to hydrogen flow rate ratio being 2:1-5:

1.

8. The preparation method according to claim 1, characterized in that, The area of ​​the second etch stop layer used to form the contact plug includes the surfaces of the second etch stop layer corresponding to the first opening and the second opening.

9. The preparation method according to claim 8, characterized in that, The area of ​​the second etch stop layer used to form the contact plug also includes the surface of the second etch stop layer corresponding to the first opening and the second opening.

10. The preparation method according to claim 1, characterized in that, After forming the contact hole, the preparation method further includes filling the contact hole with conductive material to form a contact plug.

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