A hardware-in-the-loop test system and method for a vehicle MCU three-level inverter
By constructing a hardware-in-the-loop test system with a high-precision FPGA model and dynamic operating condition simulation, the systematic testing problem of automotive three-level inverters on an 800V high-voltage platform was solved, achieving efficient and comprehensive verification results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 上海北汇信息科技有限公司
- Filing Date
- 2026-04-10
- Publication Date
- 2026-07-07
AI Technical Summary
Existing technologies are insufficient to meet the systematic testing requirements of automotive three-level inverters on an 800V high-voltage platform, especially in terms of high-voltage compatibility, system collaborative testing, and inverter model accuracy. Furthermore, reliance on physical bench testing results in high costs, long cycles, and low coverage of operating conditions.
A hardware-in-the-loop test system was constructed, which includes a high-precision FPGA model, dynamic operating condition simulation, and motor co-simulation. An NPC-type three-level topology was adopted, combined with a PMSM motor model and a fault injection module, to achieve full-dimensional verification of automotive three-level inverters.
It enables full-dimensional verification of automotive three-level inverters, ensuring the authenticity and comprehensiveness of the test, shortening the verification cycle, reducing costs, and meeting the high-efficiency, high-coverage verification needs of the automotive industry before mass production.
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Figure CN122346110A_ABST
Abstract
Description
Technical Field
[0002] This application relates to the technical field of semiconductor testing, and in particular to a hardware-in-the-loop testing system and method for automotive MCU three-level inverters. Background Technology
[0004] As the new energy vehicle industry develops towards longer driving range and faster charging, the 800V high-voltage platform has become a core trend for industry upgrades. Three-level inverters, with their core advantages of "low power device withstand voltage requirements, low output harmonics, and high energy conversion efficiency," are gradually replacing traditional two-level inverters and becoming the core actuator of electric drive systems. The performance of automotive three-level inverters directly determines the smoothness of vehicle power output, energy utilization efficiency, and operational safety. Their verification needs to cover three core dimensions: "device stress tolerance under high voltage environments, dynamic response under complex driving conditions, and coordinated adaptation with the drive motor."
[0005] However, existing technologies have fundamental limitations that make it difficult to meet the systematic testing needs of automotive applications: First, there is insufficient platform adaptability. Existing test solutions mostly focus on low-to-medium voltage scenarios of 300-400V, and have not designed specific test mechanisms for key characteristics such as transient voltage stress of power devices and bus current fluctuations on 800V high-voltage platforms, resulting in reliability verification under high-voltage environments being merely a formality. Second, there is a lack of system-wide collaborative testing. Existing technologies mostly test single indicators such as the switching characteristics and output harmonics of individual inverters, without building a real-time linkage simulation environment for "inverter-motor," which cannot verify system-level performance such as torque fluctuation suppression and efficiency matching, and is out of touch with real automotive scenarios. Moreover, there is an incomplete test architecture. Existing solutions mostly rely on physical bench testing, which not only requires the construction of high-cost high-voltage power supply systems and load simulation devices, but also has long test cycles and low operating condition coverage, making it difficult to meet the high-efficiency and high-coverage verification requirements of the automotive industry before mass production.
[0006] Finally, there are also issues with the simplistic simulation of dynamic operating conditions and the insufficient accuracy of inverter models. Existing simulations often use fixed loads or simple steady-state conditions, which cannot reproduce complex dynamic load change scenarios such as rapid acceleration, rapid deceleration, and hill driving, resulting in the controller's dynamic response capability not being fully verified. Furthermore, existing simulation models are not based on the actual switching logic of NPC-type three-level topology and lack the design for decoding switch states and accurately calculating phase and line voltages, making it difficult to reproduce the actual output characteristics of the inverter and affecting the authenticity of the test results. Summary of the Invention
[0008] To provide a systematic HIL test solution that is compatible with high-voltage platforms, covers dynamic operating conditions, supports motor coordination, and has a high-precision inverter model, this application provides a hardware-in-the-loop test system and method for automotive MCU three-level inverters.
[0009] In a first aspect, this application provides a hardware-in-the-loop testing system for an automotive MCU three-level inverter, employing the following technical solution:
[0010] A hardware-in-the-loop test system for an automotive MCU three-level inverter includes:
[0011] The MCU under test is adapted to an NPC-type three-level topology and is used to output multiple PWM control signals.
[0012] The simulation core module includes a three-level inverter model and a PMSM motor model. The three-level inverter model is used to decode the switch state and calculate the three-phase voltage in real time based on multiple PWM control signals and DC bus voltage. The PMSM motor model is used to calculate the motor operating state parameters based on the three-phase voltage.
[0013] The host computer is used to implement operating condition configuration, data monitoring, fault injection, and communication interaction.
[0014] The vehicle dynamic operating condition simulation subsystem is used to generate dynamic load torque and target speed commands to simulate sudden load changes in vehicles.
[0015] The MCU under test and the FPGA board are connected via a digital interface. The host computer is connected to the VT real-time simulation system equipped with the simulation core module and the MCU under test via a communication bus to form a complete closed-loop test link.
[0016] By adopting the above technical solutions, a HIL test system was constructed that includes a high-precision FPGA model, dynamic operating condition simulation, and motor co-simulation, realizing full-dimensional verification of automotive three-level inverters. This effectively solves the problems of lack of high-voltage adaptation, lack of system co-testing, insufficient inverter model accuracy, and reliance on physical test benches in existing technologies.
[0017] Optionally, the vehicle dynamic operating condition simulation subsystem presets typical vehicle driving conditions including WLTC cycle condition, CLTC cycle condition, FTP-75 cycle condition and US06 high-speed condition, and supports custom operating condition parameter configuration.
[0018] Optionally, the PMSM motor model is constructed based on the voltage equation in the stationary coordinate system, and the motor operating parameters are calculated by receiving the voltage signal after Clark transformation.
[0019] Optionally, the simulation core module supports DC bus voltage / current simulation, output phase voltage / current acquisition, power device temperature simulation, and motor feedback torque / speed acquisition.
[0020] Optionally, the host computer integrates a fault injection module, and the fault injection module supports fault types including overvoltage fault, overcurrent fault, overtemperature fault, IGBT open circuit fault, IGBT short circuit fault, communication bus fault, and sensor signal distortion fault.
[0021] Secondly, this application provides a hardware-in-the-loop testing method for a three-level inverter using an automotive MCU, employing the following technical solution:
[0022] A hardware-in-the-loop testing method for an automotive MCU three-level inverter includes the following steps:
[0023] S1: Fix the MCU under test that is compatible with the NPC three-level topology to the experimental platform, start the FPGA board of the VT real-time simulation system equipped with the simulation core module, and ensure that each hardware module is powered normally.
[0024] S2: Connect the multi-channel PWM control signals output by the MCU under test to the digital I / O port of the FPGA through a shielded cable, and establish a communication link between the host computer and the FPGA, and between the host computer and the MCU under test through the CAN bus;
[0025] S3: Download the pre-compiled three-level inverter model and PMSM motor model to the FPGA board, start the model initialization verification, and ensure that the model runs normally;
[0026] S4: Operating condition configuration and simulation start-up. The target driving conditions and test parameters are configured through the CANoe software installed on the host computer. The vehicle dynamic operating condition simulation subsystem is started, and dynamic load torque and target speed commands are generated and sent to the tested MUC and PMSM motor models.
[0027] S5: The MCU under test outputs multiple PWM control signals according to the preset control strategy. The three-level inverter model of the FPGA calculates the three-phase phase voltage and line voltage according to the PWM signal and the Udc decoded switch state. After Clark transformation, the voltage is input to the PMSM motor model. The PMSM motor model calculates the motor operating status parameters and feeds them back to the host computer and the MCU under test to form a closed-loop test and monitor key test parameters in real time.
[0028] S6: Test completion and result analysis. Stop the operating condition simulation, export the test data, and combine the fault injection test results to complete the performance evaluation of the MCU under test.
[0029] Optionally, the deployment process of the FPGA model in step S3 includes:
[0030] A three-level inverter model and a PMSM motor model are built in the MATLAB / Simulink environment. The three-level inverter model includes a switch state decoding module, a phase voltage calculation module, and a line voltage calculation module. After the model is compiled, it can be burned into the FPGA board chip with one click through the FPGA management software FPGA Manager.
[0031] In summary, this application includes at least one of the following beneficial technical effects:
[0032] This application constructs a HIL test system that includes a high-precision FPGA model, dynamic operating condition simulation, and motor co-simulation, achieving comprehensive verification of automotive three-level inverters. This effectively solves the problems of lack of high-voltage adaptation, gaps in system co-testing, insufficient inverter model accuracy, and reliance on physical test benches in existing technologies. By pre-setting multiple standard driving conditions and supporting custom conditions, it can comprehensively simulate complex dynamic load scenarios in vehicles. Combined with 10MHz high-sampling-rate data acquisition simulation, it accurately captures the transient characteristics of power devices under high voltage, ensuring the authenticity and comprehensiveness of the test. The three-level inverter model is based on the real switching logic of NPC topology. Through switch state decoding, accurate calculation of phase and line voltages, and combined with the PMSM motor model, it restores the real collaborative relationship between the inverter and the motor. The fault injection module can verify the fault diagnosis and protection capabilities of the tested MCU, providing comprehensive data support for controller optimization. Meanwhile, this invention eliminates the need for complex physical test benches, enabling systematic testing to be completed in a laboratory environment. This significantly shortens the verification cycle, reduces testing costs, and allows for flexible configuration of test conditions with high coverage. It can meet the high-efficiency, high-coverage verification requirements of the automotive industry before mass production, providing a reliable testing solution for the development of new energy vehicles using an 800V high-voltage platform. Attached Figure Description
[0034] Figure 1 This is the architecture diagram of the hardware-in-the-loop test system in this application.
[0035] Figure 2 This is the equivalent circuit diagram of the inverter switch in this application.
[0036] Figure 3 This is a block diagram of the FPGA-based inverter model in this application. Detailed Implementation
[0038] The embodiments of this application are described in detail below, and examples of the embodiments are shown in the accompanying drawings.
[0039] In the description of this specification, the references to "certain embodiments," "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples" refer to specific features, structures, materials, or characteristics described in connection with the described embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0040] This application discloses a hardware-in-the-loop test system for an automotive MCU three-level inverter, referring to... Figure 1 The system mainly consists of the MCU under test, an FPGA simulation core module, a VT real-time simulation system (model VT5838), a host computer (with CANoe software installed), and a vehicle dynamic operating condition simulation subsystem. The MCU under test is a vehicle three-level motor controller adapted to an NPC-type three-level topology, with 12 PWM signal outputs. Each phase arm corresponds to 4 PWM signals (A phase U1-U4, B phase V1-V4, C phase W1-W4), used to control the 12 switching transistors of the three-level inverter. The FPGA simulation core module is integrated into the VT5838 board, possessing high computing speed and parallel processing capabilities, enabling efficient operation of the three-level inverter model and the PMSM motor model. The host computer is an industrial control computer with CANoe software installed for operating condition configuration, data monitoring, and fault injection. The vehicle dynamic operating condition simulation subsystem is integrated into the CANoe software, generating dynamic load commands through preset or custom operating condition parameters.
[0041] During hardware deployment, the MCU under test is fixed on an anti-static test bench to ensure good heat dissipation; the VT5838 board is installed in the board chassis and connected to the host computer to achieve high-speed data transmission; the MCU under test and the FPGA board are connected by shielded twisted-pair cable to avoid the influence of external electromagnetic interference on the PWM signal; the communication bus adopts the CANFD bus with a communication rate of 2Mbps to ensure real-time communication between the host computer and each module; the DC bus voltage Udc analog signal is connected through the FPGA's analog input port for simulating the MCU bus voltage.
[0042] By adopting the above technical solutions, a HIL test system was constructed that includes a high-precision FPGA model, dynamic operating condition simulation, and motor co-simulation, realizing full-dimensional verification of automotive three-level inverters. This effectively solves the problems of lack of high-voltage adaptation, lack of system co-testing, insufficient inverter model accuracy, and reliance on physical test benches in existing technologies.
[0043] Specifically, the vehicle dynamic operating condition simulation subsystem has a built-in standard parameter library for WLTC cyclic operating condition, CLTC cyclic operating condition, FTP-75 cyclic operating condition and US06 high-speed operating condition, and the parameters of each operating condition strictly follow the corresponding industry standards.
[0044] For example, the vehicle speed-time curve and the duration of acceleration / deceleration phases in the CLTC operating condition. At the same time, this subsystem allows users to customize operating condition parameters through CANoe's panel, including acceleration time (0.5-10s), deceleration gradient (-500rpm / s to -50rpm / s), constant speed (500-15000rpm), and load change amplitude (50-600N・m).
[0045] After the simulation starts, the dynamic operating condition simulation subsystem calculates the dynamic load torque and target speed required by the current vehicle through a preset dynamic model according to the configured operating condition type. For example, in the high-speed stage of CLTC operating condition, the output target speed is maintained at 10,000-15,000 rpm, and the load torque is dynamically adjusted to 300-600 N·m according to the vehicle speed. In the rapid acceleration condition, the load torque changes abruptly from 100 N·m to 600 N·m within 1-3 seconds, simulating the load change scenario when the vehicle is overtaking, thereby verifying the dynamic response capability of the MCU under test.
[0046] Optionally, the PMSM motor model is a mathematical model of a vehicle permanent magnet synchronous motor, constructed based on the electromagnetic torque equation and the voltage equation in the stationary coordinate system. The core equations of this model include:
[0047] Electromagnetic torque equation: ,in This represents the number of pole pairs of the motor. It is a permanent magnet flux chain. , These are the d-axis and q-axis stator currents, respectively. , These are the d-axis and q-axis inductances, respectively.
[0048] Equations of motion: ,in For the moment of inertia of the motor, The electric angular velocity of the motor. For load torque, It is the coefficient of viscous friction;
[0049] Through the above equations, the model can calculate the actual speed, output torque, three-phase current and other operating parameters of the motor in real time, and restore the real collaborative relationship between the inverter and the motor.
[0050] Optionally, the data acquisition simulation step size of the simulation core module is set to 10MHz to ensure that the transient characteristics of power devices under high voltage can be captured, such as the switching transient voltage spikes of IGBTs and the rapid changes in the rising / falling edges of current.
[0051] The specific parameters for data acquisition are as follows: DC bus voltage Udc simulation range is 0-1000V (compatible with 800V high voltage platform), current simulation range is -1200 A to 1200A; output phase voltage ( , , The data acquisition range is 0-800V, the phase current acquisition range is -1200A to 1200A; the power device temperature simulation range is -50℃ to 210℃, covering the extreme ambient temperature of automotive applications; the acquired data includes DC bus voltage / current, three-phase output phase voltage / current, IGBT chip temperature, motor feedback torque / speed, etc.
[0052] Optionally, the fault injection module integrated in the host computer software CANoe (the fault injection module includes a fault injection board that can realize hard-wired fault injection) can simulate faults by modifying the input system variable parameters of the FPGA model or the fault injection board. Supported fault types include: overvoltage fault (DC bus voltage exceeds 900V), overcurrent fault (phase current exceeds 600A), overheating fault (IGBT temperature exceeds 150℃), IGBT open circuit fault (simulating open circuit of one or more IGBT switching transistors), IGBT short circuit fault (simulating short circuit of IGBT switching transistors), communication bus fault (CAN bus signal interruption or distortion), and sensor signal fault injection.
[0053] Fault injection can be triggered in two ways: one is manual triggering, where engineers can click the trigger button for the corresponding fault type through the Panel and set the fault duration; the other is automatic triggering, which is triggered according to preset operating conditions, such as automatically triggering an overheating fault under high-speed and high-load conditions (speed ≥12000rpm, torque ≥500N・m) to verify the fault diagnosis and protection mechanism of the MCU under test.
[0054] This application also discloses a hardware-in-the-loop testing system and method for automotive MCU three-level inverters, including the following steps:
[0055] Step S1: During hardware deployment, ensure that the power supply voltage of the MCU under test is 12V (automotive standard power supply), the power supply voltage of the VT5838 board is 12V, and the grounding terminals of each hardware module are reliably connected to avoid grounding interference.
[0056] Step S2: When connecting signals, the length of the shielded cable for the 12-channel PWM control signals shall not exceed 2m, and differential interfaces shall be used at both ends of the cable to reduce electromagnetic interference; the communication bus shall use twisted-pair shielded cable, and a 120Ω terminating resistor shall be installed at the bus terminal to ensure communication stability; the analog signal of the DC bus voltage Udc shall be connected to the MCU through a dedicated shielded cable to avoid voltage fluctuation interference.
[0057] Step S3: Before deploying the FPGA model, build the model in the MATLAB / Simulink environment using the DSP Builder module library. After the model is compiled, it can be burned into the VT5838 FPGA chip for operation with one click.
[0058] Step S4: When configuring the working condition, the user can select a single working condition or a combination of working conditions (such as the CLTC+US06 combination) and set the test duration (10-1800s).
[0059] Step S5: During the closed-loop test, the MCU under test adjusts the duty cycle of the 12 PWM control signals based on the three-phase current feedback from the PMSM motor model. The FPGA's three-level inverter model receives the PWM signals and Udc, decodes the switching states, and calculates the three-phase phase voltage and line voltage. These are then converted by Clark to... , The data is then input into the PMSM motor model. After the motor model is solved, the operating status parameters are fed back to the host computer and the MCU under test to form a closed-loop control. The host computer displays the change curves of various test parameters in real time.
[0060] In addition, MCU function tests can be performed, and fault injection boards can be used to inject faults into the inverter, such as short circuit, short ground, and open circuit faults.
[0061] Step S6: After the test is completed, CANoe automatically exports the test data, including PWM signal duty cycle, three-phase output voltage / current, motor speed / torque, power device temperature, etc. Engineers use this data to evaluate the dynamic response speed, control accuracy and fault handling capability of the MCU under test.
[0062] The deployment details of the FPGA model include:
[0063] First of all Figure 2 The equivalent circuit model shown is interpreted, and based on this diagram, we can establish an accurate mathematical model for real-time simulation on an FPGA. The diagram contains the following key components:
[0064] DC side: DC power supply Udc and two capacitors C1 and C2 connected in series. This represents the DC bus of a three-level inverter, where the midpoint (the junction of the two capacitors) is crucial for the potential reference.
[0065] For a three-level inverter, the output voltage of each phase arm (phases A, B, and C) relative to the DC bus midpoint (O) is... There are three possible states:
[0066] P state: ;
[0067] O state: ;
[0068] N state: ;
[0069] Switching function It's used to describe this state. We can define it as:
[0070] when This indicates that the output of this phase is at the P level;
[0071] when This indicates that the output of that phase is at a 0 level.
[0072] when This indicates that the output of that phase is at the N level; this does not refer to an actual physical switch, but is a mathematical concept, and the value of each switching function is determined by the controller's PWM signal.
[0073] Controlled voltage source: The other end of the switch is connected to the "drive motor". This is actually equivalent to a three-phase AC output voltage.
[0074] Load: The drive motor is usually represented in the equivalent circuit model as a series connection of an RL load (resistive-inductive load) and a back electromotive force.
[0075] A three-level inverter model and a PMSM motor model were constructed in the MATLAB / Simulink environment. The three-level inverter model includes a switch state decoding module, a phase voltage calculation module, and a line voltage calculation module. The specific design is as follows:
[0076] Switching status decoding module: Based on the combination logic of the four PWM signals of each phase arm of the NPC type three-level inverter, determine the switching status of the phase.
[0077] For phase A bridge arm (PWM signals U1-U4):
[0078] When U1 and U2 are turned on, it is determined to be in state P;
[0079] When U2 and U3 are turned on, it is determined to be in state 0;
[0080] When U3 and U4 are turned on, it is determined to be in state N; the decoding logic of phase B (V1-V4) and phase C (W1-W4) is the same as that of phase A, and the switching function is output after decoding;
[0081] like Figure 3 As shown, the implementation process of the equivalent circuit model in the HIL system is as follows:
[0082] 1. Input: The FPGA receives 12 actual PWM signals from the controller under test (MCU).
[0083] 2. Signal Decoding: The FPGA's internal logic decodes the switching state (i.e., switching function) of each phase in real time based on these 12 PWM signals. , , The value is 1, 0, or -1.
[0084] 3. Voltage calculation: According to the formula Calculate the three-phase output voltage in real time.
[0085] 4. Motor model solution: Solve the calculated three-phase voltages , , The input is fed into an FPGA-based mathematical model of the motor. This model calculates the new three-phase current based on the voltage, current motor state, and motor parameters. , , And motor speed and torque.
[0086] Phase voltage calculation module: based on switching function , , (Values are 1, 0, and -1, corresponding to P, O, and N states respectively) and the DC bus voltage Udc, obtained through the formula , , Calculate the three-phase phase voltages (voltages relative to the DC bus neutral point O);
[0087] Line voltage calculation module: The line voltage is obtained by subtraction from the phase voltage. The calculation formula is as follows: , , .
[0088] The PMSM motor model integrates a Clark converter module to convert the three-phase voltages. , , Convert to coordinate system , Substitute the values into the voltage equation in the stationary coordinate system and solve for the voltage.
[0089] stationary coordinate system ( Voltage equation in coordinate system:
[0090] ;
[0091] ;
[0092] in, and The input voltage after Clark transformation (the three-phase voltage output from the three-level inverter model) , , (obtained by conversion) For stator resistance, , They are respectively , Shaft stator current, , They are respectively , Rate of change of shaft stator current.
[0093] After the model is built and compiled, it can be programmed into the VT5838 FPGA chip with one click, fully utilizing the parallel processing advantages of the FPGA to achieve simultaneous decoding of three-phase switch states and parallel voltage calculation. The FPGA Manager software provides users with a convenient management interface, making FPGA chip programming and model deployment simple and easy. Users do not need to have in-depth knowledge of complex hardware description languages (such as VHDL or Verilog) to complete complex simulation tasks, greatly reducing the development threshold and workload.
[0094] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. A hardware-in-the-loop test system for an automotive MCU three-level inverter, characterized in that, include: The MCU under test is adapted to an NPC-type three-level topology and is used to output multiple PWM control signals. The simulation core module includes a three-level inverter model and a PMSM motor model. The three-level inverter model is used to decode the switch state and calculate the three-phase voltage in real time based on multiple PWM control signals and DC bus voltage. The PMSM motor model is used to calculate the motor operating state parameters based on the three-phase voltage. The host computer is used to implement operating condition configuration, data monitoring, fault injection, and communication interaction. The vehicle dynamic operating condition simulation subsystem is used to generate dynamic load torque and target speed commands to simulate sudden load changes in vehicles. The MCU under test is connected to the FPGA board, and the host computer is connected to the VT real-time simulation system equipped with the simulation core module and the MCU under test through a communication bus to form a complete closed-loop test link.
2. The hardware-in-the-loop test system for a vehicle MCU three-level inverter according to claim 1, characterized in that, The vehicle dynamic operating condition simulation subsystem presets typical vehicle driving conditions including WLTC cycle condition, CLTC cycle condition, FTP-75 cycle condition and US06 high-speed condition, and supports custom operating condition parameter configuration.
3. The hardware-in-the-loop test system for a vehicle-mounted MCU three-level inverter according to claim 1, characterized in that, The PMSM motor model is constructed based on voltage equations in a stationary coordinate system, and receives voltage signals after Clark transformation to calculate motor operating parameters.
4. The hardware-in-the-loop test system for a vehicle-mounted MCU three-level inverter according to claim 1, characterized in that, The simulation core module supports DC bus voltage / current simulation, output phase voltage / current acquisition, power device temperature simulation, and motor feedback torque / speed acquisition.
5. The hardware-in-the-loop test system for a vehicle-mounted MCU three-level inverter according to claim 1, characterized in that, The host computer integrates a fault injection module, which supports fault types including overvoltage fault, overcurrent fault, overtemperature fault, IGBT open circuit fault, IGBT short circuit fault, communication bus fault, and sensor signal distortion fault.
6. A hardware-in-the-loop testing method for an automotive MCU three-level inverter, applied to the hardware-in-the-loop testing system for the automotive MCU three-level inverter as described in any one of claims 1-5, characterized in that, Includes the following steps: S1: Fix the MCU under test that is compatible with the NPC three-level topology to the experimental platform, start the FPGA board of the VT real-time simulation system equipped with the simulation core module, and ensure that each hardware module is powered normally. S2: Connect the multi-channel PWM control signals output by the MCU under test to the digital I / O port of the FPGA through a shielded cable, and establish a communication link between the host computer and the FPGA, and between the host computer and the MCU under test through the CAN bus or Ethernet bus. S3: Download the pre-compiled three-level inverter model and PMSM motor model to the FPGA board, start the model initialization verification, and ensure that the model runs normally; S4: Operating condition configuration and simulation start-up. The target driving conditions and test parameters are configured through the CANoe software installed on the host computer. The vehicle dynamic operating condition simulation subsystem is started, and dynamic load torque and target speed commands are generated and sent to the tested MUC and PMSM motor models. S5: The MCU under test outputs multiple PWM control signals according to the preset control strategy. The three-level inverter model of the FPGA calculates the three-phase phase voltage and line voltage according to the PWM signal and the Udc decoded switch state. After Clark transformation, the voltage is input to the PMSM motor model. The PMSM motor model calculates the motor operating status parameters and feeds them back to the host computer and the MCU under test to form a closed-loop test and monitor key test parameters in real time. S6: Test completion and result analysis. Stop the operating condition simulation, export the test data, and combine the fault injection test results to complete the performance evaluation of the MCU under test.
7. The hardware-in-the-loop testing method for a vehicle MCU three-level inverter according to claim 6, characterized in that, The deployment process of the FPGA model in step S3 includes: A three-level inverter model and a PMSM motor model were constructed in the MATLAB / Simulink environment. The three-level inverter model includes a switch state decoding module, a phase voltage calculation module, and a line voltage calculation module. After the model is compiled using FPGA Manager software, it can be burned into the FPGA board chip with one click and run.