Conversion apparatus and method for interferometer data acquisition

Abstract

This invention provides a conversion device and method for interferometer data acquisition, comprising: a front-end signal input unit, a core processing unit, a back-end protocol output unit, a debugging and monitoring unit, and a power management unit. The conversion device described herein communicates with the interferometer using a custom data format, LVDS level, with a maximum speed of 100Mbps; data for each of the three axes is on a separate channel, ensuring transmission speed while improving communication stability; the raw data input from the interferometer is processed by an FPGA and converted into three BiSSC signals, corresponding to each of the previous channels, and finally output externally through a high-density DB15 connector; a gigabit EtherNet is designed, allowing monitoring of the communication status of all channels via the network port; a host computer interface is designed, which can output the position information waveforms detected by the three channels in real time, facilitating application debugging; and the BiSSC communication parameters can be adjusted via the network port, improving usability.

Description

Technical Field

[0001] This invention relates to a conversion device and method for data acquisition by an interferometer. Background Technology

[0002] In photolithography, wafer fabrication, and inspection-grade packaging test control systems, high precision is required for position information acquisition. While traditional long-stroke position sensors, such as optical grating rulers, offer high resolution, their measurement accuracy becomes insufficient as the speed and acceleration of the motion stage increase. The application of laser interferometers has significantly improved the position acquisition accuracy of the motion stage, achieving sub-nanometer positioning precision.

[0003] In displacement sensor development, the relationship between sensor data acquisition and actual movement distance is not linear, thus requiring calibration. This process necessitates providing a stable benchmark as a calibration reference. This benchmark must have a resolution greater than that of the displacement sensor to ensure accurate calibration. Laser interferometers, with their resolution covering various existing types of displacement sensors, are commonly used for calibrating and verifying newly designed sensors.

[0004] Currently, laser interferometer signal acquisition and transmission systems mainly fall into two technical categories: 1) Data acquisition based on motion control chassis: This is currently the most common form in the semiconductor industry. In the control chassis, the main control card configures the axis card's function registers via a control bus. The axis card transmits raw position data to the main control card via a dedicated data bus (P2Bus). The main control card then calculates the position based on the actual relative relationships of each axis. The axis card outputs incremental data, therefore a reference zero point is required during the calculation.

[0005] 2) Integrated laser interferometer, with the Attocube IDS3010 as a typical example: This model of laser interferometer supports simultaneous acquisition of three axes and position confirmation via a network-connected host computer. In other words, laser output, signal acquisition, and absolute position calculation are all completed internally.

[0006] The disadvantages of the above two technical approaches are as follows: 1) Data acquisition based on motion control chassis: The control unit is relatively large and usually needs to be installed on a dedicated rack, resulting in a distance from the motion stage being measured and complicated wiring. In addition to the control unit, a laser is required to provide an optical signal. The quality of the optical signal directly affects the position measurement accuracy, so the laser's operating status needs to be monitored, mainly its temperature change, which usually needs to be stabilized within ±2℃. The multi-axis interferometer is difficult to install and debug. The interferometer position must be specified in the optical path design, which increases the design difficulty of the motion stage system. At the same time, if the installation accuracy is not high, it will directly affect the signal quality, resulting in insufficient measurement accuracy.

[0007] 2) Integrated laser interferometer, with the Attocube IDS3010 as a typical example: The standard port only supports network communication and can only communicate with the official host computer. If you want to communicate with the main system to achieve closed-loop control of the motion table system, the steps are cumbersome, and all calculation operations can only be performed on the host computer. It cannot meet the requirements for independent closed-loop operation of the system and the closed-loop speed is slow. Summary of the Invention

[0008] The purpose of this invention is to provide a conversion device and method for data acquisition by an interferometer.

[0009] To address the above problems, the present invention provides a conversion device for data acquired by an interferometer, comprising: The system comprises a front-end signal input unit, a core processing unit, a back-end protocol output unit, a debugging and monitoring unit, and a power management unit. The front-end signal input unit is communicatively connected to the output of the laser interferometer, receiving the triaxial raw position differential signals output by the laser interferometer and outputting stable triaxial digital signals to the core processing unit based on these signals. The core processing unit is electrically connected to the front-end signal input unit, generating a triaxial standard BiSS-C protocol signal based on the stable triaxial digital signal. The back-end protocol output unit is electrically connected to the core processing unit, receiving the triaxial standard BiSS-C protocol signal and converting it into an RS422 level signal for output to an external motion controller. The debugging and monitoring unit is electrically connected to the core processing unit, providing a user-friendly interface for parameter configuration, data display, waveform monitoring, and zero-position calibration. The power management unit is electrically connected to the front-end signal input unit, core processing unit, back-end protocol output unit, and debugging and monitoring unit, converting the external DC input voltage into a multi-channel isolated regulated voltage to provide stable power to each unit.

[0010] Furthermore, in the above-mentioned device, the front-end signal input unit is communicatively connected to the output end of the laser interferometer, and is used to receive the triaxial original position differential signal output by the laser interferometer, and sequentially perform impedance matching, DC blocking filtering and differential-to-single-ended level conversion on the triaxial original position differential signal, and output a stable triaxial digital signal to the core processing unit. The core processing unit is electrically connected to the front-end signal input unit and is used to receive the triaxial stable digital signal, perform connection status verification, signal channel identification, output type identification and resolution identification, and perform timing parsing, data decoding and protocol encoding on the triaxial data in parallel to generate triaxial standard BiSS-C protocol signal; The back-end protocol output unit is electrically connected to the core processing unit and is used to receive the three-axis standard BiSS-C protocol signal, convert the standard BiSS-C protocol signal of each axis into an RS422 level signal, and output it synchronously to an external motion controller through a standard output interface. The debugging and monitoring unit is electrically connected to the core processing unit to build an Ethernet communication link, set up an embedded web server, provide an installation-free host computer interactive interface, and realize parameter configuration, data display, waveform monitoring and zero-point calibration functions. The power management unit is electrically connected to the front-end signal input unit, the core processing unit, the back-end protocol output unit, and the debugging and monitoring unit, respectively. It is used to convert the external DC input voltage into a multi-channel isolated regulated voltage to provide stable power supply to each unit and achieve input-output electrical isolation.

[0011] Furthermore, in the aforementioned device, the front-end signal input unit includes: a 26-pin SDR interface and a three-channel LVDS differential receiver circuit; wherein, The 26-pin SDR interface is used for physical docking with the laser interferometer to receive three raw LVDS differential signals along the X, Y, and Z axes. Each signal contains a pair of differential clocks and a pair of differential data. Each LVDS differential receiver circuit includes: a DC blocking capacitor, a terminating matching resistor, and an LVDS receiver chip, used to suppress signal reflection, filter high-frequency noise, and convert the LVDS differential signal into a single-ended digital signal.

[0012] Furthermore, in the aforementioned device, the core processing unit employs a Xilinx ZYNQ series heterogeneous processing chip, integrating an FPGA processing core and an ARM processing core; wherein, The FPGA processing core is used to implement parallel reception, timing analysis, data decoding, and BiSS-C protocol encoding and timing output of three single-ended digital signals of the X, Y, and Z axes to obtain three-axis standard BiSS-C protocol signals, which include three-axis standard BiSS-C clock signals and data signals. The ARM processing core is used to run an embedded operating system, build an embedded web server, and realize parameter storage, Ethernet communication, status monitoring, and data interaction with the host computer.

[0013] Furthermore, in the aforementioned device, the back-end protocol output unit includes: three independent RS422 level conversion circuits and one HDB15 output interface; wherein, Each RS422 level conversion circuit converts the single-axis standard BiSS-C clock signal and data signal output by the FPGA into RS422 differential signals. Each RS422 differential signal includes a differential clock signal and a differential data signal. The HDB15 output interface synchronously outputs three differential clock signals and three differential data signals, enabling direct interface with an external motion controller.

[0014] Furthermore, in the aforementioned device, the debugging and monitoring unit includes: a gigabit Ethernet PHY chip and a network transformer; wherein, the gigabit Ethernet supports 10, 100, and 1000 Mbps adaptive speeds; the gigabit Ethernet PHY chip is responsible for Ethernet physical layer signal encoding / decoding and link negotiation; the network transformer achieves electrical isolation, impedance matching, and common-mode interference suppression; the debugging and monitoring unit, as an Ethernet hardware path, provides a gigabit network physical transmission interface for the ARM core of the core processing unit, supporting network communication between the embedded web server and the host computer.

[0015] Furthermore, in the above-described device, the signal processing of the core processing unit includes: The X-axis signals include: AXIS1_CLK1_P and AXIS1_CLK1_N, which are X-axis clock differential signal pairs, connected to the LVDS_IN1_P and LVDS_IN1_N pins of the core processing unit, respectively; and AXIS1_DATA1_P and AXIS1_DATA1_N, which are X-axis data differential signal pairs, connected to the LVDS_IN2_P and LVDS_IN2_N pins of the core processing unit, respectively. The Y-axis signals include: AXIS2_CLK2_P and AXIS2_CLK2_N, which are Y-axis clock differential signal pairs, connected to the LVDS_IN3_P and LVDS_IN3_N pins of the core processing unit, respectively; and AXIS2_DATA2_P and AXIS2_DATA2_N, which are Y-axis data differential signal pairs, connected to the LVDS_IN4_P and LVDS_IN4_N pins of the core processing unit, respectively. The Z-axis signals include: AXIS3_CLK3_P and AXIS3_CLK3_N, which are Z-axis clock differential signal pairs, connected to the LVDS_IN5_P and LVDS_IN5_N pins of the core processing unit, respectively; and AXIS3_DATA3_P and AXIS3_DATA3_N, which are Z-axis data differential signal pairs, connected to the LVDS_IN6_P and LVDS_IN6_N pins of the core processing unit, respectively. Auxiliary input signals include: DDR_PG, which is the DDR power ready signal, connected to the DDR_PGOOD pin of the core processing unit, used to indicate the system memory power supply status; The core processing unit receives six LVDS differential signals from the left side, including: LVDS_IN1_P and LVDS_IN1_N, LVDS_IN2_P and LVDS_IN2_N, LVDS_IN3_P and LVDS_IN3_N, which correspond to the clock and data of the three axes respectively, and restore high-precision position data accordingly. The core processing unit re-encodes the six LVDS differential signals according to the BiSS-C protocol specification, generating single-ended clock and data signals. Through the output interface, it generates a set of single-ended signals for each axis, including: The X-axis has CLK1 and DATA1 terminals; the Y-axis has CLK2 and DATA2 terminals; and the Z-axis has CLK3 and DATA3 terminals. The core processing unit outputs JTAG debug signals F_TDI, F_TDO, F_TC and F_TMS through the debug interface for chip configuration and online debugging; The single-ended signal output from the core processing unit is sent to three completely independent BISS-C modules, namely: Block module, Block1 module and Block2 module. Each independent BISS-C module corresponds to one axis and is used to generate single-ended BiSS-C clock signal and single-ended BiSS-C data signal from the decoded three-axis position data according to the BiSS-C standard timing, and output them to the back-end protocol output unit.

[0016] The Block module corresponds to the X-axis. The internal output signals CLK1 and DATA1 of the core processing unit are connected to the input of the Block module. The Block module encodes the received position data using the BiSS-C protocol to generate single-ended BISS_CLK and BISS_DATA signals. The CLK_IN_P, CLK_IN_N, DATA_OUT_N, and DATA_OUT_P output by the Block module are brought out as internal ports of the module, outputting BISS_CLK_P1, BISS_CLK_N1, BISS_DATA_N1, and BISS_DATA_P1 signals, which serve as the input interface signals of the X-axis circuit corresponding to the back-end protocol output unit. Block1 corresponds to the Y-axis. The internal output signals CLK2 and DATA2 of the core processing unit are connected to the input terminals of Block1. Block1 encodes the received position data using the BiSS-C protocol to generate single-ended BISS_CLK and BISS_DATA signals. The output signals CLK_IN_P, CLK_IN_N, DATA_OUT_N, and DATA_OUT_P of Block1 are brought out as internal ports of the module, outputting BISS_CLK_P2, BISS_CLK_N2, BISS_DATA_N2, and BISS_DATA_P2, which serve as the input interface signals for the Y-axis circuit of the back-end protocol output unit. Block2 corresponds to the Z-axis. The internal output signals CLK3 and DATA3 of the core processing unit are connected to the input of Block2. Block2 encodes the received position data using the BiSS-C protocol to generate single-ended BISS_CLK and BISS_DATA signals. The output signals CLK_IN_P, CLK_IN_N, DATA_OUT_N, and DATA_OUT_P of Block2 are brought out as internal ports of the module, outputting BISS_CLK_P3, BISS_CLK_N3, BISS_DATA_N3, and BISS_DATA_P3, which serve as the input interface signals of the back-end protocol output unit corresponding to the Z-axis circuit.

[0017] The core processing unit provides four debugging interfaces: F_TDI, F_TDO, F_TCK, and F_TMS, forming a standard JTAG debugging interface for programming, online configuration, and troubleshooting of the core processing unit. The four interfaces output corresponding debugging signals: TDI debugging signal, TDO debugging signal, TCK debugging signal, and TMS debugging signal.

[0018] Furthermore, in the above-described device, the front-end signal input unit includes: Differential input interface with a total of 4 differential input signals: the first differential signal pair LVDS_IN5_P, LVDS_IN5_N; the second differential signal pair LVDS_IN6_P, LVDS_IN6_N; DC blocking capacitors C200, C201, C202, and C203 are used. LVDS_IN5_P is connected to DC blocking capacitor C200, which is connected to the RIN1+ pin of the U19 chip. LVDS_IN5_N is connected to DC blocking capacitor C201, which is connected to the RIN1- pin of the U19 chip. LVDS_IN6_P is connected to DC blocking capacitor C202, which is connected to the RIN4+ pin of the U19 chip. LVDS_IN6_N is connected to DC blocking capacitor C203, which is connected to the RIN4- pin of the U19 chip. The terminating matching resistors R131 and R135 are used. The two ends of the terminating matching resistor R131 are connected to the output nodes of DC blocking capacitors C200 and C201, and also between the RIN1+ and RIN1- pins of the core chip U19, to complete the impedance matching of the first differential line. The two ends of the terminating matching resistor R135 are connected to the output nodes of DC blocking capacitors C202 and C203, and also between the RIN4+ and RIN4- pins of the core chip U19. The core chip U19 includes: The input pins include: RIN1+ pin, used to receive the LVDS_IN5_P signal processed by DC blocking capacitor C200 and terminating matching resistor R131; RIN1- pin, used to receive the LVDS_IN5_N signal processed by DC blocking capacitor C201 and terminating matching resistor R131; RIN4+ pin 7 receives the LVDS_IN6_P signal processed by DC blocking capacitor C202 and terminating matching resistor R135; RIN4- pin receives the LVDS_IN6_N signal processed by DC blocking capacitor C203 and terminating matching resistor R135. The control and power supply pins include: the VCC pin, which is connected to the 3V3P_PREPHERY_IO-LVDS power supply and is used to power the chip; the EN pin, which is connected to the 3V3P_PREPHERY_IO-LVDS power supply and is used as the chip enable signal, active high; the GND pin, which is connected to digital ground DGND; and the EN pin, which is connected to DGND via resistor R136. When this pin is low-level enabled, it is pulled low to enable the chip to operate. Output pins include: ROUT1 pin for single-ended output of the first differential signal; ROUT4 pin for single-ended output of the second differential signal. Pull-up resistors and FPGA signal outputs include: ROUT1 pin 15 connected to resistor R132, resistor R132 connected to FPGA_IN_DI5; FPGA_IN_DI5 connected to resistor R133, resistor R133 connected to power supply 3V3P_PREPHERY_IO-LVDS; ROUT4 pin connected to FPGA_IN_DI6, FPGA_IN_DI6 connected to resistor R134, resistor R134 connected to power supply 3V3P_PREPHERY_IO-LVDS; The enable circuit includes: the EN pin is connected to resistor R136, and resistor R136 is connected to DGND.

[0019] Furthermore, in the above-mentioned device, the complete output circuit of one of the BiSS-C channels of the back-end protocol output unit includes: Power inputs include: 3V3P_PREPHERY_BISS, which is the FPGA-side power supply; 3V3P_PREPHERY_BISS is directly connected to the VDD1 pin of chip U7 to power the internal logic of chip U7; 3V3P_PREPHERY_BISS is also connected to the DE pin of chip U7 via resistor R55. Control and enable signals include: the DE pin, which is pulled up to 3V3P_PREPHERY_BISS through resistor R55, active high, enabling the chip to operate in transmit mode; the RE pin is pulled down to digital ground DGND through resistor R59, enabling low, and together with the DE pin, enabling the chip to enter transmit mode; the GND1 pin, GND1_1 pin, and GND1_2 pin are all connected to digital ground DGND; The data input signals include: BISS_CLK, which is connected to the RO pin of U7 after being current-limited by resistor R57, as a single-ended clock input; and BISS_DATA, which is connected to the DI pin of chip U7 after being current-limited by resistor R58. Pin VDD2 is 16. Pin VDD2 is connected to the isolation power supply V5P_ISO_BISS to power the differential output. Pins GND2_2, GND2_1, and GND2 are all connected to the isolation digital ground DGND_ISO. The differential output pins include: pin A, which is the positive differential output terminal of the clock signal; pin B, which is the inverted differential output terminal of the clock signal; pin Z, which is the inverted differential output terminal of the data signal; and pin Y, which is the positive differential output terminal of the data signal. Termination matching resistors include: resistor R56, which is connected between pins A and B to provide termination impedance matching for the clock differential pair; and resistor R60, which is connected between pins Y and Z to provide termination impedance matching for the data differential pair. The clock signal output link includes: pin A via fuse F9, outputting CLK_IN_P; pin B via fuse F10, outputting CLK_IN_N; The data signal output link includes: the Z pin outputs DATA_OUT_N via fuse F11; The Y pin outputs DATA_OUT_P via fuse F12; Overcurrent protection components, including resettable fuses F9, F10, F11 and F12, are connected in series in the differential output path.

[0020] According to another aspect of the present invention, a method for converting interferometer acquisition data is also provided, employing the conversion apparatus for interferometer acquisition data as described in any of the preceding claims, the method comprising: When the conversion device used for interferometer data acquisition is powered on, the power management unit converts the external DC voltage into a multi-channel isolated regulated voltage via DC / DC converter to power each unit; the core processing unit completes system initialization, FPGA logic loading, and peripheral configuration. The front-end signal input unit acquires the triaxial raw LVDS differential signal output by the laser interferometer through a 26-pin SDR interface. After impedance matching, DC blocking filtering and level conversion, the three LVDS differential receiving circuits are converted into three single-axis digital signals and output to the core processing unit. The core processing unit performs interferometer connection verification on the three-axis stable digital signal to determine whether the laser interferometer is effectively connected and whether the signal link is normal. If the connection verification passes, the core processing unit continues to perform identification and obtains the identification results, including: channel number identification, output type identification, measurement resolution identification, and obtains the interferometer's current working channel, data output mode, and physical measurement resolution; if the connection is abnormal, it enters a fault prompt state and waits for the connection to be restored before re-performing the verification; the data output modes include: absolute and incremental output modes; The core processing unit automatically completes the matching of working parameters based on the recognition results, including configuring the BiSS-C output bit width, communication rate, data format and resolution mapping parameters; The core processing unit listens for configuration commands from the host computer. If the user sends new working parameters through the host computer, the core processing unit overwrites the automatically matched working parameters with the new parameters; if no new parameters are received, the automatically matched default working parameters continue to be used. The core processing unit performs parallel decoding of the three single-axis digital signals based on the matched working parameters, completes protocol encoding according to the BiSS-C standard timing, and generates a three-axis standard BiSS-C protocol signal, wherein the three-axis standard BiSS-C protocol signal includes: a three-axis BiSS-C clock signal and a data signal; The back-end protocol output unit receives the three-axis standard BiSS-C protocol signal, converts the single-axis BiSS-C clock signal and data signal into RS422 differential signals, and synchronously outputs them to the external motion controller through the HDB15 interface to provide high-precision reference position feedback for displacement sensor calibration; wherein, the RS422 differential signal of each axis includes: differential clock signal and differential data signal; The debugging and monitoring unit obtains triaxial position data that is sourced, synchronized, and of the same value as the triaxial standard BiSS-C protocol signal from the core processing unit, calculates the relative distance between axes, and uploads it to the host computer via gigabit Ethernet in combination with the operating status and waveform data, so as to realize real-time monitoring and debugging of the calibration process.

[0021] The present invention has the following advantages: 1) The device has a high degree of integration and a small size, eliminating the need for an external control chassis, simplifying the wiring structure, shortening the optical path alignment time, and significantly improving the efficiency of equipment installation and debugging; 2) Outputs standard BiSS-C protocol signals, directly compatible with mainstream motion controllers such as ACS, ELMO, and Speedgoat, enabling plug-and-play functionality and reducing system integration difficulty and development costs; 3) Adopting the ZYNQ heterogeneous parallel processing architecture, the three axes receive, process, and output data independently, with no bus contention and no signal crosstalk. The data transmission latency is low and the real-time performance is strong, meeting the closed-loop control requirements of high-speed motion tables. 4) It has an embedded gigabit Ethernet and web server, providing a host computer interface that does not require installation. It supports parameter configuration, data monitoring, waveform recording, and one-click zeroing, greatly improving the convenience of debugging. 5) Front-end LVDS differential input, back-end RS422 differential output, end-to-end differential signal transmission, combined with electrical isolation design, strong anti-interference capability, long transmission distance, supports partitioned deployment of interferometer and motion controller; 6) It has an automatic power-on recognition function, which can automatically complete connection verification, channel recognition, type recognition, and resolution recognition. The parameters are configurable and can be adapted to multiple types of interferometers and multiple scene control needs. 7) The hardware architecture is modular, the signal processing is standardized, and the operation status is visualized. It has high overall reliability and strong applicability, and can be stably applied to the harsh industrial environment of high-end equipment such as semiconductor lithography and measurement. Attached Figure Description

[0022] Figure 1 This is a block diagram of a conversion device for interferometer data acquisition according to an embodiment of the present invention; Figure 2 This is a structural diagram of a data conversion device for interferometer acquisition according to an embodiment of the present invention; Figure 3 This is a control flowchart of a data conversion device for interferometer acquisition according to an embodiment of the present invention; Figure 4 This is a circuit architecture diagram of the core processing unit of an embodiment of the present invention; Figure 5 This is a schematic diagram of the board function distribution according to an embodiment of the present invention; Figure 6 This is a circuit architecture diagram of a front-end signal input unit according to an embodiment of the present invention; Figure 7 This is a circuit architecture diagram of a back-end protocol output unit according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the host computer interface according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the BiSSC control timing according to an embodiment of the present invention. Detailed Implementation

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] like Figure 1 As shown, the present invention provides a conversion device for interferometer data acquisition, comprising: a front-end signal input unit 101, a core processing unit 102, a back-end protocol output unit 103, a debugging and monitoring unit 104, and a power management unit 105.

[0025] The power management unit 105 is electrically connected to the front-end signal input unit 101, the core processing unit 102, the back-end protocol output unit 103, and the debugging and monitoring unit 104, respectively, and provides multi-channel isolated and regulated power supplies for the other four units.

[0026] The input terminal of the front-end signal input unit 101 is connected to an external laser interferometer, and the output terminal is connected to the core processing unit 102 to send the conditioned three-axis LVDS digital signal into the core processing unit.

[0027] The core processing unit 102 receives the signal output from the front-end signal input unit 101, and completes decoding, power-on self-verification, parameter matching, and BiSS-C protocol encoding. The single-ended BiSS-C signal after protocol encoding is output to the back-end protocol output unit 103. At the same time, it communicates bidirectionally with the debugging and monitoring unit 104 to upload running data and receive configuration instructions from the host computer.

[0028] The input terminal of the back-end protocol output unit 103 receives the single-ended BiSS-C signal output by the core processing unit 102, converts it into an RS422 differential signal carrying the BiSS-C protocol, and connects it to an industrial motion controller via the HDB15 / DB15 interface; at the same time, it is interconnected with the debugging and monitoring unit 104, and the status information is synchronized to the debugging and monitoring unit.

[0029] The debugging and monitoring unit 104 is bidirectionally connected to the core processing unit 102 and the back-end protocol output unit 103, respectively, and communicates with the host computer via Ethernet to realize parameter configuration, status monitoring, data uploading and debugging functions.

[0030] In one embodiment, the front-end signal input unit is communicatively connected to the output of the laser interferometer and is used to receive the triaxial raw position differential signal output by the laser interferometer, perform impedance matching, DC blocking filtering and differential-to-single-ended level conversion on the triaxial raw position differential signal in sequence, and output a stable triaxial digital signal to the core processing unit. The core processing unit is electrically connected to the front-end signal input unit and is used to receive the triaxial stable digital signal, perform connection status verification, signal channel identification, output type identification and resolution identification, and perform timing parsing, data decoding and protocol encoding on the triaxial data in parallel to generate triaxial standard BiSS-C protocol signal; The back-end protocol output unit is electrically connected to the core processing unit and is used to receive the three-axis standard BiSS-C protocol signal, convert the standard BiSS-C protocol signal of each axis into an RS422 level signal, and output it synchronously to an external motion controller through a standard output interface to provide position feedback for motion closed-loop control. Here, the TTL level signals of the standard BiSS-C protocol for each axis are converted to RS422 level signals; The debugging and monitoring unit is electrically connected to the core processing unit to build an Ethernet communication link, set up an embedded web server, provide an installation-free host computer interactive interface, and realize parameter configuration, data display, waveform monitoring and zero-point calibration functions. The power management unit is electrically connected to the front-end signal input unit, the core processing unit, the back-end protocol output unit, and the debugging and monitoring unit, respectively. It is used to convert the external DC input voltage into a multi-channel isolated regulated voltage to provide stable power supply to each unit and achieve input-output electrical isolation.

[0031] like Figure 2 As shown, in one embodiment, the front-end signal input unit includes: a 26-pin SDR interface and a three-channel LVDS differential receiver circuit.

[0032] The 26-pin SDR interface is used for physical docking with the laser interferometer, receiving three raw LVDS differential signals along the X, Y, and Z axes. Each signal contains a pair of differential clocks and a pair of differential data. Each LVDS differential receiver circuit includes a DC blocking capacitor, a 100Ω terminating resistor, and an LVDS receiver chip, used to suppress signal reflections, filter high-frequency noise, and convert the LVDS differential signal into a 3.3V single-ended digital signal.

[0033] like Figure 2 As shown, in one embodiment, the core processing unit uses a Xilinx ZYNQ series heterogeneous processing chip, integrating an FPGA processing core and an ARM processing core.

[0034] The FPGA processing core is used to implement parallel reception, timing analysis, data decoding, and BiSS-C protocol encoding and timing output of three single-ended digital signals along the X, Y, and Z axes, resulting in three-axis standard BiSS-C protocol signals. These three-axis standard BiSS-C protocol signals include a three-axis standard BiSS-C clock signal and a data signal. The ARM processing core is used to run an embedded operating system, build an embedded web server, and implement parameter storage, Ethernet communication, status monitoring, and data interaction with the host computer.

[0035] Here, the embedded web server is used to provide a browser-accessible, installation-free host computer interface, supporting absolute and incremental mode switching, resolution configuration, one-click zeroing, inter-axis distance calculation, real-time waveform display, and data saving.

[0036] like Figure 2 As shown, in one embodiment, the back-end protocol output unit includes: three independent RS422 level conversion circuits and an HDB15 output interface.

[0037] Each RS422 level conversion circuit converts the single-axis standard BiSS-C clock and data signals output by the FPGA into RS422 differential signals. Each RS422 differential signal includes a differential clock signal and a differential data signal. The HDB15 output interface synchronously outputs three differential clock signals and three differential data signals, enabling direct interface with an external motion controller.

[0038] like Figure 2 As shown, in one embodiment, the debugging and monitoring unit includes: a gigabit Ethernet PHY chip and a network transformer; wherein, the gigabit Ethernet supports 10, 100, and 1000 Mbps adaptive speeds; the gigabit Ethernet PHY chip is responsible for Ethernet physical layer signal encoding / decoding and link negotiation; the network transformer implements electrical isolation, impedance matching, and common-mode interference suppression; the debugging and monitoring unit, as an Ethernet hardware path, provides a gigabit network physical transmission interface for the ARM core of the core processing unit, supporting network communication between the embedded web server and the host computer.

[0039] like Figure 2 As shown, in one embodiment, the power management unit includes a wide-voltage DC input circuit, a multi-channel DC / DC conversion circuit, and an isolated power supply circuit.

[0040] The wide-voltage DC input circuit supports 12V-24V external power supply. The multi-channel DC / DC converter outputs a 1.0V core voltage, a 1.8V auxiliary voltage, a 3.3V IO voltage, or a 5V interface voltage. The isolation power supply circuit is used to electrically isolate the front-end input power supply from the back-end output power supply, improving adaptability to industrial electromagnetic environments.

[0041] Furthermore, the core processing unit continues to perform identification, obtaining identification results, including: channel number identification, output type identification, measurement resolution identification, and obtaining the current working channel of the interferometer, data output mode (absolute / incremental) and physical measurement resolution; and automatically completing the matching of working parameters based on the above identification results, including configuring the BiSS-C output bit width, communication rate, data format and resolution mapping parameters.

[0042] Furthermore, the device supports switching between absolute position output mode and incremental position output mode, the three-axis data channels are independent of each other, there is no bus contention or signal crosstalk, the single-axis communication rate is up to 10Mbps, and CRC check is supported.

[0043] The communication between the conversion device for interferometer data acquisition and the interferometer in this invention can adopt non-standard high-speed level and select SDR camera cable to ensure high speed and stability of front-end communication; the internal processor uses Xilinx's ZYNQ series processor, and three-channel data is received and transmitted in parallel to ensure data processing and transmission speed; the back-end adopts BiSSC communication transmission protocol interface, which is compatible with a variety of commercial controllers to improve applicability; a gigabit Ethernet port is reserved in the design to facilitate data monitoring and debugging.

[0044] Figure 4 This is a circuit architecture diagram of the core processing unit of the data conversion device for interferometer acquisition according to the present invention. Figure 4 The left side is connected to Figure 6 The front-end signal input unit is used to receive the LVDS differential signal output by the front-end signal input unit. Figure 4 The right side is connected to Figure 7 The back-end protocol output unit is used to drive three independent BISS-C conversion modules and output RS422 differential signals to the motion controller.

[0045] Figure 4 In this configuration, the LVDS differential signals output by the front-end signal input unit consist of a clock signal (CLK) and a data signal (DATA) for each axis, all transmitted using LVDS differential level (P / N differential pairs). This provides strong anti-interference capabilities and is suitable for high-speed, long-distance transmission. The LVDS differential signals output by the front-end signal input unit are connected to the input pins of the core processing unit (ZYNQ_Core) through six pairs of LVDS differential signals.

[0046] Figure 4 In this core processing unit (ZYNQ_Core), based on the Xilinx ZYNQ series chip, its core functions are: receiving 6 channels of LVDS differential signals, completing decoding, data synchronization, and preprocessing; performing parallel processing on three channels of data to provide clean and synchronized clock and data signals for subsequent BiSS-C protocol conversion; and integrating basic system management functions (such as DDR power status detection DDR_PGOOD) and a debug interface (JTAG).

[0047] Figure 4The output section consists of three independent BiSS-C protocol conversion modules. The three signals CLK1 / DATA1, CLK2 / DATA2, and CLK3 / DATA3 output from the core processing unit (ZYNQ_Core) are respectively fed into three independent BiSS-CBlock modules. These three independent BiSS-C protocol conversion modules convert the digital signals output from the core processing unit (ZYNQ_Core) into differential clock (BISS_CLK) and differential data (BISS_DATA) signals conforming to the BiSS-C protocol standard. The final output of these three independent BiSS-C protocol conversion modules still uses differential levels (P / N pairs) and is output externally through a DB15 connector to adapt to the BiSS-C interface of industrial controllers. The three data streams are processed independently and do not interfere with each other, ensuring the stability and low latency of multi-axis data transmission.

[0048] Figure 4 The F_TDI, F_TDO, F_TCK, and F_TMS signals in the lower right corner are the standard JTAG debugging interfaces of the core processing unit (ZYNQ_Core), used for chip program download, online debugging, and burning, and are essential interfaces during the development phase.

[0049] Figure 4 The fully differential signal link, from the input LVDS to the output BiSS-C, uses differential signal transmission throughout, which has extremely strong anti-interference ability and is suitable for complex electromagnetic environments in industrial sites; moreover, the three-axis parallel processing allows for independent input, processing, and output of three data channels, with no bus contention, fast transmission speed, and low latency, fully meeting the real-time requirements of motion table closed-loop control. Figure 4 Through modular design, the BiSS-C conversion module is an independent block that can be flexibly configured and supports subsequent expansion to include more axes or protocol types.

[0050] Specifically 1) Figure 4 The left side of the text is the input section, such as... Figure 6 The three independent LVDS differential signals output from the front-end signal input unit shown are used as signal sources and input to the core processing unit (ZYNQ_Core), including: The X-axis (AXIS1) signals include: AXIS1_CLK1_P and AXIS1_CLK1_N, which are X-axis clock differential signal pairs, connected to the LVDS_IN1_P and LVDS_IN1_N pins of the core processing unit (ZYNQ_Core) respectively; and AXIS1_DATA1_P and AXIS1_DATA1_N, which are X-axis data differential signal pairs, connected to the LVDS_IN2_P and LVDS_IN2_N pins of the core processing unit (ZYNQ_Core) respectively. The Y-axis (AXIS2) signals include: AXIS2_CLK2_P and AXIS2_CLK2_N, which are Y-axis clock differential signal pairs, connected to the LVDS_IN3_P and LVDS_IN3_N pins of the core processing unit (ZYNQ_Core) respectively; and AXIS2_DATA2_P and AXIS2_DATA2_N, which are Y-axis data differential signal pairs, connected to the LVDS_IN4_P and LVDS_IN4_N pins of the core processing unit (ZYNQ_Core) respectively. The Z-axis (AXIS3) signals include: AXIS3_CLK3_P and AXIS3_CLK3_N, which are Z-axis clock differential signal pairs, connected to the LVDS_IN5_P and LVDS_IN5_N pins of the core processing unit (ZYNQ_Core) respectively; and AXIS3_DATA3_P and AXIS3_DATA3_N, which are Z-axis data differential signal pairs, connected to the LVDS_IN6_P and LVDS_IN6_N pins of the core processing unit (ZYNQ_Core) respectively. Auxiliary input signals include: DDR_PG, which is the DDR power-ready signal, connected to the DDR_PGOOD pin of the core processing unit (ZYNQ_Core), used to indicate the system memory power supply status.

[0051] 2) Figure 4 The chip in the middle is the core processing unit (ZYNQ _Core). The core processing unit (ZYNQ _Core) receives the LVDS differential signal from the left, decodes and processes it, and outputs a single-ended signal to the BISS-C module on the right. The core processing unit (ZYNQ _Core) receives six LVDS differential signals from the left (LVDS_IN1_P and LVDS_IN1_N, LVDS_IN2_P and LVDS_IN2_N, LVDS_IN3_P and LVDS_IN3_N), which correspond to the clock and data of the three axes, respectively, and reconstructs high-precision position data.

[0052] The core processing unit (ZYNQ_Core) re-encodes the six LVDS differential signals (LVDS_IN1_P and LVDS_IN1_N, LVDS_IN2_P and LVDS_IN2_N, LVDS_IN3_P and LVDS_IN3_N) according to the BiSS-C protocol specification, generating single-ended clock and data signals. It then generates a set of single-ended signals for each axis through the output interface, including: The X-axis uses CLK1 (clock) and DATA1 (data) terminals; the Y-axis uses CLK2 (clock) and DATA2 (data) terminals; and the Z-axis uses CLK3 (clock) and DATA3 (data) terminals. The core processing unit (ZYNQ_Core) outputs JTAG debug signals F_TDI, F_TDO, F_TC and F_TMS through the debug interface for chip configuration and online debugging.

[0053] 3) Figure 4 The right side is the output section, which consists of three independent BISS-C protocol conversions and differential outputs, including: The single-ended signal output from the core processing unit (ZYNQ _Core) is fed into three completely independent BISS-C modules: Block Module, Block1 Module, and Block2 Module. Each independent BISS-C module corresponds to one axis and is used to generate single-ended BiSS-C clock and data signals from the decoded three-axis position data according to the BiSS-C standard timing, and then output them to... Figure 7 The backend protocol output unit is shown.

[0054] The Block module corresponds to the X-axis. The internal output signals CLK1 and DATA1 of the core processing unit (ZYNQ_Core) are connected to the input of the Block module. The Block module encodes the received position data using the BiSS-C protocol, generating single-ended BISS_CLK and BISS_DATA signals. The Block module outputs CLK_IN_P, CLK_IN_N, DATA_OUT_N, and DATA_OUT_P, which are brought out as internal ports, outputting BISS_CLK_P1, BISS_CLK_N1, BISS_DATA_N1, and BISS_DATA_P1 signals, respectively. Figure 6 The back-end protocol output unit shown corresponds to the input interface signal of the X-axis circuit.

[0055] Block1 corresponds to the Y-axis. The internal output signals CLK2 and DATA2 of the core processing unit (ZYNQ_Core) are connected to the input terminals of Block1 module. Block1 module performs BiSS-C protocol encoding on the received position data to generate single-ended BISS_CLK and BISS_DATA signals. The output signals CLK_IN_P, CLK_IN_N, DATA_OUT_N, and DATA_OUT_P of Block1 module are brought out as internal ports, outputting BISS_CLK_P2, BISS_CLK_N2, BISS_DATA_N2, and BISS_DATA_P2, respectively. Figure 6 The back-end protocol output unit shown corresponds to the input interface signal of the Y-axis circuit.

[0056] The Block2 module corresponds to the Z-axis. The internal output signals CLK3 and DATA3 of the core processing unit (ZYNQ_Core) are connected to the input terminals of the Block2 module. The Block2 module encodes the received position data using the BiSS-C protocol to generate single-ended BISS_CLK and BISS_DATA signals. The CLK_IN_P, CLK_IN_N, DATA_OUT_N, and DATA_OUT_P output by the Block2 module are brought out as internal ports of the module, outputting BISS_CLK_P3, BISS_CLK_N3, BISS_DATA_N3, and BISS_DATA_P3, which serve as the input interface signals of the back-end protocol output unit corresponding to the Z-axis circuit.

[0057] Debug signal connection: The core processing unit (ZYNQ _Core) brings out four debug interfaces: F_TDI, F_TDO, F_TCK and F_TMS, which form a standard JTAG debug interface for programming, online configuration and fault debugging of the core processing unit; the four interfaces output corresponding debug signals: TDI debug signal, TDO debug signal, TCK debug signal and TMS debug signal.

[0058] Figure 5 This is a hardware board functional distribution diagram of a data conversion device for interferometer acquisition according to an embodiment of the present invention. The interferometer signal input 1 is the interface on the left side of the board, namely the 26-pin SDR interface, which is used to receive the three-axis LVDS position data output by the interferometer.

[0059] The green terminal is power input 2, which is the power supply interface of the board and is used to provide power to the entire module.

[0060] Power supply 3 is the board power module, which is responsible for converting the input power into different voltages (such as 1.0V, 1.8V, 3.3V) required by ZYNQ, interface circuits, etc., to ensure the stable operation of each chip.

[0061] The DB15 interface on the right side of the board is signal output 4, namely the HDB15 connector, which outputs an RS422 level signal carrying the BiSS-C protocol, directly connected to the industrial controller.

[0062] The network port in the lower right corner is network interface 5, corresponding to the gigabit Ethernet port, which is used to connect to the host computer to realize data monitoring, parameter configuration and debugging.

[0063] The main chip (ZYNQ processor) in the middle of the board is signal processing 6, which is... Figure 3 The circuit architecture.

[0064] The storage chip next to ZYNQ (such as DDR memory / Flash) is used for data storage, storing program firmware, runtime data and configuration parameters to ensure stable module operation.

[0065] The circuit near the input interface is the interferometer signal conditioning and acquisition circuit 8, which is responsible for amplifying, filtering, and level conversion of the LVDS input signal, converting the original signal of the interferometer into a digital signal that can be directly processed by the ZYNQ.

[0066] Figure 6 This is a hardware interface diagram of the front-end signal input unit, used to receive the triaxial raw position differential signals from the interferometer. It uses an LVDS level interface and processes the signals into a level that the FPGA can receive through hardware design. The front-end signal input unit converts the LVDS differential signals from the interferometer into single-ended digital signals that the FPGA can directly recognize.

[0067] Figure 6 In the input signals LVDS_IN5_P / N and LVDS_IN6_P / N, these are two differential clock and data signals transmitted from the interferometer.

[0068] Front-end filtering and matching: C200~C203 are 100nF capacitors, which serve to block DC and filter, removing DC components and high-frequency noise from the signal; R131 and R135 are 100Ω resistors, used for differential signal termination matching, reducing signal reflection and ensuring transmission integrity.

[0069] Core chip U19 (LVDS receiver): This is a four-channel LVDS differential to single-ended receiver chip; the input differential signal enters from RIN1+ / RIN1- and RIN3+ / RIN4-, and after being processed internally by the chip, it outputs a single-ended digital signal from ROUT1 and ROUT4. The output signal is then pulled up by resistors R132, R133, R134, and R136 to be converted into FPGA-compatible 3.3V level signals (FPGA_IN_DI5, FPGA_IN_DI6).

[0070] Power supply and enable: 3V3P_PREPHERY_IO-LVDS supplies power to the chip, the EN pin controls the chip enable, and DGND is the digital ground.

[0071] Specifically, Figure 6 The connection relationships between the components of the front-end signal input unit are as follows: 1) Figure 6 The left-hand input section is the signal input terminal of the laser interferometer, including: Differential input interface with a total of 4 differential input signals: the first differential signal pair LVDS_IN5_P, LVDS_IN5_N; the second differential signal pair LVDS_IN6_P, LVDS_IN6_N; DC blocking capacitors C200, C201, C202, and C203 are used. Specifically, LVDS_IN5_P connects to DC blocking capacitor C200 (100nF / 50V), which is connected to the RIN1+ pin of chip U19; LVDS_IN5_N connects to DC blocking capacitor C201 (100nF / 50V), which is connected to the RIN1- pin of chip U19; LVDS_IN6_P connects to DC blocking capacitor C202 (100nF / 50V), which is connected to the RIN4+ pin of chip U19; LVDS_IN6_N connects to DC blocking capacitor C203 (100nF / 50V), which is connected to chip U19. The chip's RIN4 pin is used to filter out the DC component and low-frequency noise of the signal, allowing only the AC differential signal to pass through.

[0072] Termination matching resistors R131 and R135 are used. Termination matching resistor R131 (100Ω) is connected at both ends to the output nodes of DC blocking capacitors C200 and C201, and simultaneously connected between the RIN1+ and RIN1- pins of the core chip U19, completing the impedance matching of the first differential line. Termination matching resistor R135 (100Ω) is connected at both ends to the output nodes of DC blocking capacitors C202 and C203, and simultaneously connected between the RIN4+ and RIN4- pins of the core chip U19, completing the impedance matching of the second differential line. This achieves matching the 100Ω characteristic impedance of the LVDS transmission line, suppressing signal reflection and ensuring signal integrity.

[0073] 2) Figure 6 The core chip U19 (LVDS receiver) is located in the middle of the front-end signal input unit, and includes: The input pins include: RIN1+ (pin 2), used to receive the LVDS_IN5_P signal after processing by DC blocking capacitor C200 and terminating matching resistor R131; RIN1- (pin 1), used to receive the LVDS_IN5_N signal after processing by DC blocking capacitor C201 and terminating matching resistor R131; RIN2+ (pin 3) and RIN2- (pin 4), unused (crossed); RIN3+ (pin 6) and RIN3- (pin 5), unused (crossed); RIN4+ (pin 7), received the LVDS_IN6_P signal after processing by DC blocking capacitor C202 and terminating matching resistor R135; RIN4- (pin 8), received the LVDS_IN6_N signal after processing by DC blocking capacitor C203 and terminating matching resistor R135.

[0074] The control and power supply pins include: VCC (pin 13) connected to the 3V3P_PREPHERY_IO-LVDS power supply for powering the chip; EN (pin 16) connected to the 3V3P_PREPHERY_IO-LVDS power supply for the chip enable signal, active high; GND (pin 12) connected to digital ground DGND; and EN (pin 9) connected to DGND via resistor R136 (4.7kΩ). When this pin is low-level enabled, it is pulled low to enable the chip to operate.

[0075] The output pins include: ROUT1 (pin 15) is the single-ended output of the first differential signal; ROUT2 (pin 14) is unused (crossed); ROUT3 (pin 11) is unused (crossed); and ROUT4 (pin 10) is the single-ended output of the second differential signal.

[0076] 3) Figure 6 The right-side output section is the FPGA input interface, including: Pull-up resistors and FPGA signal outputs include: ROUT1 (pin 15) connected to R132 (4.7kΩ), R132 (4.7kΩ) connected to FPGA_IN_DI5; FPGA_IN_DI5 connected to R133 (4.7kΩ), R133 (4.7kΩ) connected to the 3V3P_PREPHERY_IO-LVDS power supply (pull-up); ROUT4 (pin 10) connected to FPGA_IN_DI6, FPGA_IN_DI6 connected to R134 (4.7kΩ), R134 (4.7kΩ) connected to the 3V3P_PREPHERY_IO-LVDS power supply (pull-up). The enable circuit includes: EN (pin 9) connected to R136 (4.7kΩ), and R136 (4.7kΩ) connected to DGND; used to pull the chip enable pin low to put the chip into a working state.

[0077] Figure 7 It is the core circuit of the back-end protocol output unit, and also the complete output circuit of one of the BiSS-C channels. It is used to convert the single-axis standard BiSS-C protocol signal output by the core processing unit into an industrial standard RS422 differential signal, and then output it to the motion controller through the HDB15 interface.

[0078] Specifically 1) Figure 7 The left input section is the FPGA-side single-ended signal input, including: The power input includes: 3V3P_PREPHERY_BISS, which is the FPGA-side power supply; 3V3P_PREPHERY_BISS is directly connected to the VDD1 pin (pin 1) of chip U7 to power the internal logic of chip U7; 3V3P_PREPHERY_BISS is also connected to the DE pin (pin 5) of U7 via resistor R55 (4.7KΩ), which is pulled high to enable and configure the chip to transmit mode; Control and enable signals include: DE (pin 5), which is pulled up to 3V3P_PREPHERY_BISS via R55, active high, enabling the chip to operate in transmit mode; RE (pin 4), which is pulled down to digital ground DGND via resistor R59 (4.7KΩ), enabling low, and together with the DE pin, enabling the chip to enter transmit mode; GND1 (pin 2), GND1_1 (pin 7), and GND1_2 (pin 8) are all connected to digital ground DGND, providing a reference ground for the left side of the chip; The data input signals include: BISS_CLK, which is connected to the RO pin (pin 3) of U7 after being current-limited by resistor R57 (33Ω) as a single-ended clock input; and BISS_DATA, which is connected to the DI pin (pin 6) of U7 after being current-limited by resistor R58 (33Ω) as a single-ended data input.

[0079] 2) Figure 7 The core chip in the middle is U7, an isolated RS422 transceiver. U7 is an isolated RS422 transceiver chip that converts a 3.3V single-ended signal to a 5V differential signal and provides electrical isolation. The right side of U7 is the power supply and ground, including: VDD2 (pin 16) is connected to the isolation power supply V5P_ISO_BISS to power the differential output; GND2_2 (pin 9), GND2_1 (pin 10) and GND2 (pin 15) are all connected to the isolation digital ground DGND_ISO to provide a reference ground for the right circuit and achieve electrical isolation from the left DGND. The differential output pins include: pin A (pin 14) is the positive differential output terminal of the clock signal; pin B (pin 13) is the inverted differential output terminal of the clock signal; pin Z (pin 12) is the inverted differential output terminal of the data signal; and pin Y (pin 11) is the positive differential output terminal of the data signal.

[0080] Termination matching resistors include: R56 (120Ω), which is connected between pins A and B to provide termination impedance matching for the clock differential pair; and R60 (120Ω), which is connected between pins Y and Z to provide termination impedance matching for the data differential pair.

[0081] 3) Figure 7 The right side is the output section, used for differential signal output from the motion controller side, including: The clock signal output link includes: pin A via fuse F9 (100mA / 60V), outputting CLK_IN_P (positive terminal of clock differential signal); pin B via fuse F10 (100mA / 60V), outputting CLK_IN_N (negative terminal of clock differential signal).

[0082] The data signal output link includes: the Z pin, via fuse F11 (100mA / 60V), outputs DATA_OUT_N (negative terminal of the data differential signal); The Y pin outputs DATA_OUT_P (positive terminal of data differential signal) via fuse F12 (100mA / 60V).

[0083] Overcurrent protection components, including F9, F10, F11, and F12, are all 100mA / 60V self-resetting fuses connected in series on the differential output path to prevent output short circuits or overcurrent damage to the chip and external devices.

[0084] Figure 8 This is an embedded host computer interface for a data conversion device for interferometer acquisition according to an embodiment of the present invention. The mode selection (DATA Mode) 11 is used to switch the output mode of the interferometer data, supporting two modes: absolute and incremental, to meet the needs of different types of industrial controllers.

[0085] Resolution option 12 allows you to configure the display and output resolution of position data (e.g., 1nm in the image) to match the measurement accuracy of the interferometer, making it convenient for use in scenarios with different accuracy levels.

[0086] Channel data (CH1 / CH2 / CH3) 13 is used to display the current position data of the triaxial interferometer in real time, in mm, allowing you to see the position reading of each axis intuitively and quickly determine the working status of the equipment.

[0087] Channel configuration (Offset and Set Current) 14 allows setting the position offset for each axis. The "Set Current" button enables one-click setting of the current position to zero, facilitating system calibration and zero-point adjustment, and solving the zero-point setting problem of incremental sensors.

[0088] The channel relationship (CH1-CH2 / CH3-CH2 Distance) 15 is used to display the relative distance between two axes in real time, which makes it convenient for you to monitor the synchronization status of the multi-axis motion table and check whether the positional relationship between the axes is normal.

[0089] The status display (Control Chart 16) shows the waveform graph below, which plots the position data curves of the three channels in real time. This provides a clear view of position changes, fluctuations, and stability, helping you troubleshoot signal noise, jitter, or abnormal jumps. The interface also supports pausing, resetting, and saving waveform data for convenient debugging and record-keeping.

[0090] The channel selection (Trigger Settings) provides trigger configuration for data acquisition, allowing you to set the trigger source, trigger level, trigger mode, and number of samples. This makes it easier for you to capture position data under specific conditions for more precise debugging and analysis.

[0091] Figure 9This is a standard control timing diagram of the BiSS-C protocol according to an embodiment of the present invention, wherein the Clock Line (MA) represents the clock line, which is sent by the master controller (such as ACS, ELMO) to control the entire communication rhythm; The Data Line (SL) refers to the data line, which is used by the slave device (a conversion device used for interferometer data acquisition) to transmit data back to the master device under clock control.

[0092] Specifically, a complete BiSS-C data frame (BiSS FRAME) consists of 5 stages: 1) IDLE idle state: Before communication begins, both lines are at a high level (logic 1), waiting for the host to initiate a communication request.

[0093] 2) Header Stage (comprising two key phases): The master starts sending clock pulses, and the slave responds and prepares data: Line Delay Compensation: After the master sends the first clock pulse, the slave pulls the data line low (logic 0). This step is to compensate for the transmission delay between the clock line and the data line, ensuring the accuracy of subsequent data sampling.

[0094] Slave Processing Time: When the slave pulls the data line high (logic 1), it is the slave's response signal, indicating that "the clock signal has been received and data is being prepared." After the master receives this signal, it knows that it can start receiving data.

[0095] 3) CDS Status Bits (Control & Data Start): This is the start marker for data transmission. The slave device sends the CDS bit, and once the master device receives it, it knows that valid location data is about to be transmitted.

[0096] 4) Data Channels: Data transmission phase Under the control of each clock pulse, the slave device sequentially sends position data: D_MSB to D_LSB: The position data is sent bit by bit from the high bit to the low bit, overwriting the absolute / incremental value data output by the interferometer; The host reads data at the clock's latch point to ensure the stability of data sampling.

[0097] 5) Timeout & IDLE: Ending phase After the data transmission is complete, the slave device pulls the data line low (logic 0), the master device stops transmitting the clock, and then both lines return to high level, entering an idle state, waiting for the next communication.

[0098] Figure 9 The CDM bit in the code is the control communication bit between the master and slave devices. It can be used for bidirectional communication and to implement functions such as parameter configuration.

[0099] Figure 9 The timing diagram is the standard timing specification of the BiSS-C communication protocol. It is a standard that the BiSS-C signals output by the conversion device used for interferometer data acquisition must strictly adhere to. As a slave device, the conversion device used for interferometer data acquisition needs to respond to the clock pulse of the master device according to this timing and send data at the correct time. Specifically, the conversion device used for interferometer data acquisition first generates a single-ended logic signal that conforms to the protocol requirements according to the standard timing. Then, it is converted into an RS422 differential electrical signal by the back-end protocol output unit for external output. The output RS422 differential signal strictly follows this BiSS-C timing standard in terms of logical timing.

[0100] The FPGA code for the conversion device used to acquire data from the interferometer needs to implement this complete timing logic in order to be correctly recognized by controllers such as ACS and ELMO. The delay compensation, processing time, and data sampling points in the timing must be strictly matched with the data output rhythm of the interferometer to ensure the accuracy of the position data.

[0101] like Figure 3 As shown, according to another aspect of the present invention, a method for converting data acquired by an interferometer is also provided, comprising the following steps: Step S1: Power on the conversion device for interferometer data acquisition. The power management unit converts the external DC voltage into a multi-channel isolated regulated voltage via DC / DC converter to power each unit. The core processing unit completes system initialization, FPGA logic loading, and peripheral configuration.

[0102] In step S2, the front-end signal input unit acquires the triaxial raw LVDS differential signal output by the laser interferometer through the 26-pin SDR interface. After impedance matching, DC blocking filtering and level conversion, the three LVDS differential receiving circuits are converted into three single-axis digital signals and output to the core processing unit. Step S3: The core processing unit performs an interferometer connection verification on the three-axis stable digital signal to determine whether the laser interferometer is effectively connected and whether the signal link is normal. Step S4: If the connection verification passes, the core processing unit continues to perform identification and obtains the identification results, including: channel number identification, output type identification, measurement resolution identification, and obtains the current working channel of the interferometer, data output mode (absolute / incremental) and physical measurement resolution; if the connection is abnormal, it enters the fault prompt state and waits for the connection to be restored before re-performing the verification. Step S5: The core processing unit automatically completes the matching of working parameters based on the recognition results, including configuring the BiSS-C output bit width, communication rate, data format, and resolution mapping parameters.

[0103] Step S6: The core processing unit listens for configuration commands from the host computer. If new working parameters are received, the configuration is updated; otherwise, the automatically matched working parameters are retained.

[0104] Here, step S5 is automatic matching: the core processing unit generates default operating parameters based on the interferometer recognition results.

[0105] Step S6 Host computer configuration: If the user sends new working parameters (such as modifying the communication rate, bit width, resolution, etc.) through the host computer, the core processing unit will overwrite the automatically matched working parameters with the new parameters; if no new parameters are received, the default working parameters automatically matched in S5 will continue to be used.

[0106] Step S7: Based on the matched working parameters, the core processing unit performs parallel decoding on the three single-axis digital signals, completes protocol encoding according to the BiSS-C standard timing, and generates a three-axis standard BiSS-C protocol signal, wherein the three-axis standard BiSS-C protocol signal includes: a three-axis BiSS-C clock signal and a data signal; Step S8: The back-end protocol output unit receives the three-axis standard BiSS-C protocol signal, converts the single-axis BiSS-C clock signal and data signal into RS422 differential signals, and synchronously outputs them to the external motion controller through the HDB15 interface to provide high-precision reference position feedback for displacement sensor calibration; wherein, the RS422 differential signal of each axis includes: differential clock signal and differential data signal; Step S9: The debugging and monitoring unit obtains three-axis position data that are of the same origin, synchronization and value as the three-axis standard BiSS-C protocol signal from the core processing unit, calculates the relative distance between axes, and uploads it to the host computer via gigabit Ethernet, combined with the running status and waveform data, to realize real-time monitoring and debugging of the calibration process.

[0107] Furthermore, in step S7, the back-end protocol output unit adopts an independent parallel processing architecture for the three-axis standard BiSS-C protocol, each completing data decoding, clock synchronization, protocol encoding and timing output, converting them into RS422 differential signals for the corresponding axes. The three axes do not interfere with each other, ensuring low latency and high stability of data transmission.

[0108] Furthermore, in step S9, the interface of the host computer is an embedded web interface, which can be directly accessed by external terminals by entering the device's IP address through a browser, without the need to install dedicated client software.

[0109] Specifically, the working principle of this invention is as follows: 1) The displacement sensor to be calibrated is installed on the motion table. While moving synchronously with the motion table, the displacement sensor to be calibrated outputs its measured position signal to the external motion controller. 2) The laser interferometer, serving as the calibration reference and the highest precision reference, synchronously measures the same motion stage with the displacement sensor and synchronously outputs a three-axis high-precision reference position signal (LVDS), which is then sent to the conversion device of this invention for interferometer data acquisition. 3) The conversion device for interferometer data acquisition of the present invention receives the reference position signal of the laser interferometer, i.e., the three-axis raw position differential signal, processes the three-axis raw position differential signal to obtain the three-axis standard BiSS-C protocol signal, and then outputs the three-axis standard BiSS-C protocol signal simultaneously in two paths: the first path is the control path, which converts the three-axis standard BiSS-C protocol signal into a three-axis RS422 differential protocol signal through the back-end protocol output unit and outputs it to the HDB15 interface; the second path is the monitoring path, which outputs the three-axis standard BiSS-C protocol signal to the debugging and monitoring unit. 4) The HDB15 interface outputs the RS422 differential protocol signal of the three axes to the external motion controller. Here, the external motion controller simultaneously acquires two data channels, one from the reference position of the laser interferometer and the other from the measurement position of the displacement sensor. The external motion controller can complete the calibration and error correction of the displacement sensor by comparing the two data channels. 5) The debugging and monitoring unit outputs the three-axis standard BiSS-C protocol signal, the three-axis reference position of the laser interferometer, the relative distance between axes, the real-time waveform, and the system status to the host computer, so as to realize real-time monitoring of the calibration process, viewing of reference data, and recording of curves.

[0110] In summary, this invention proposes a signal processing relay scheme to improve the applicability of integrated laser interferometers such as the Attocube IDS3010. This scheme treats the interferometer as a general-purpose position / distance sensor, employing a universal protocol interface for easy data interaction with commercial controllers. Integrated laser interferometers like the Attocube IDS3010 output position information in both incremental and absolute values. Currently, the commonly used sensor communication interface is the BiSSC protocol, supporting CRC checksums and achieving a maximum communication rate of 10Mbps. Commercially available controllers such as ACS, ELMO, and Speedgoat all contain external interfaces supporting the BiSSC protocol, allowing direct connection of interferometer signals via conversion modules. The conversion device used in this invention for interferometer data acquisition communicates with the interferometer using a custom data format at LVDS level, achieving a maximum speed of 100Mbps; data for each of the three axes is routed separately, ensuring both transmission speed and communication stability. The conversion device for interferometer data acquisition of the present invention processes the raw data input by the interferometer through FPGA, converts it into three BiSSC signals, corresponding to each of the previous signals, and finally outputs them to the outside through a high-density DB15 connector. This invention designs a gigabit EtherNet, which allows users to view the communication status of all channels via the network port. It also features a host computer interface that can output the position information waveforms of the three channels in real time, facilitating application debugging. Furthermore, the BiSSC communication parameters can be adjusted via the network port, enhancing the flexibility of use.

[0111] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0112] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0113] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the claims of the invention and their equivalents, the invention is also intended to include these modifications and variations.

Claims

1. A conversion device for data acquisition by an interferometer, characterized in that, include: The system comprises a front-end signal input unit, a core processing unit, a back-end protocol output unit, a debugging and monitoring unit, and a power management unit; among which, The front-end signal input unit is communicatively connected to the output end of the laser interferometer, and is used to receive the three-axis original position differential signal output by the laser interferometer, and output a three-axis stable digital signal to the core processing unit based on the three-axis original position differential signal. The core processing unit is electrically connected to the front-end signal input unit and is used to generate a triaxial standard BiSS-C protocol signal based on the triaxial stable digital signal. The back-end protocol output unit is electrically connected to the core processing unit and is used to receive the triaxial standard BiSS-C protocol signal, convert it into an RS422 level signal, and output it to an external motion controller. The debugging and monitoring unit is electrically connected to the core processing unit and is used to provide an installation-free host computer interactive interface to realize parameter configuration, data display, waveform monitoring and zero-point calibration functions. The power management unit is electrically connected to the front-end signal input unit, the core processing unit, the back-end protocol output unit, and the debugging and monitoring unit, respectively, and is used to convert the external DC input voltage into a multi-channel isolated regulated voltage to provide stable power supply for each unit.

2. The conversion device for interferometer data acquisition as described in claim 1, characterized in that, The front-end signal input unit is communicatively connected to the output of the laser interferometer and is used to receive the triaxial original position differential signal output by the laser interferometer. The triaxial original position differential signal is subjected to impedance matching, DC blocking filtering and differential-to-single-ended level conversion in sequence, and the triaxial stable digital signal is output to the core processing unit. The core processing unit is electrically connected to the front-end signal input unit and is used to receive the triaxial stable digital signal, perform connection status verification, signal channel identification, output type identification and resolution identification, and perform timing parsing, data decoding and protocol encoding on the triaxial data in parallel to generate triaxial standard BiSS-C protocol signal; The back-end protocol output unit is electrically connected to the core processing unit and is used to receive the three-axis standard BiSS-C protocol signal, convert the standard BiSS-C protocol signal of each axis into an RS422 level signal, and output it synchronously to an external motion controller through a standard output interface. The debugging and monitoring unit is electrically connected to the core processing unit to build an Ethernet communication link, set up an embedded web server, provide an installation-free host computer interactive interface, and realize parameter configuration, data display, waveform monitoring and zero-point calibration functions. The power management unit is electrically connected to the front-end signal input unit, the core processing unit, the back-end protocol output unit, and the debugging and monitoring unit, respectively. It is used to convert the external DC input voltage into a multi-channel isolated regulated voltage to provide stable power supply to each unit and achieve input-output electrical isolation.

3. The conversion device for interferometer data acquisition as described in claim 2, characterized in that, The front-end signal input unit includes: a 26-pin SDR interface and three-channel LVDS differential receiver circuitry; wherein, The 26-pin SDR interface is used for physical docking with the laser interferometer to receive three raw LVDS differential signals along the X, Y, and Z axes. Each signal contains a pair of differential clocks and a pair of differential data. Each LVDS differential receiver circuit includes: a DC blocking capacitor, a terminating matching resistor, and an LVDS receiver chip, used to suppress signal reflection, filter high-frequency noise, and convert the LVDS differential signal into a single-ended digital signal.

4. The conversion device for interferometer data acquisition as described in claim 3, characterized in that, The core processing unit uses a Xilinx ZYNQ series heterogeneous processing chip, integrating an FPGA processing core and an ARM processing core; among which, The FPGA processing core is used to implement parallel reception, timing analysis, data decoding, and BiSS-C protocol encoding and timing output of three single-ended digital signals of the X, Y, and Z axes to obtain three-axis standard BiSS-C protocol signals, which include three-axis standard BiSS-C clock signals and data signals. The ARM processing core is used to run an embedded operating system, build an embedded web server, and realize parameter storage, Ethernet communication, status monitoring, and data interaction with the host computer.

5. The conversion device for interferometer data acquisition as described in claim 4, characterized in that, The back-end protocol output unit includes: three independent RS422 level conversion circuits and one HDB15 output interface; wherein, Each RS422 level conversion circuit converts the single-axis standard BiSS-C clock signal and data signal output by the FPGA into RS422 differential signals. Each RS422 differential signal includes a differential clock signal and a differential data signal. The HDB15 output interface synchronously outputs three differential clock signals and three differential data signals, enabling direct interface with an external motion controller.

6. The conversion device for interferometer data acquisition as described in claim 5, characterized in that, The debugging and monitoring unit includes a gigabit Ethernet PHY chip and a network transformer; wherein, the gigabit Ethernet supports 10, 100 and 1000 Mbps adaptive speeds; the gigabit Ethernet PHY chip is responsible for Ethernet physical layer signal encoding and decoding and link negotiation; the network transformer realizes electrical isolation, impedance matching and common-mode interference suppression; the debugging and monitoring unit, as an Ethernet hardware path, provides a gigabit network physical transmission interface for the ARM core of the core processing unit, supporting network communication between the embedded web server and the host computer.

7. The conversion device for interferometer data acquisition as described in claim 1, characterized in that, The signal processing of the core processing unit includes: The X-axis signals include: AXIS1_CLK1_P and AXIS1_CLK1_N, which are X-axis clock differential signal pairs, connected to the LVDS_IN1_P and LVDS_IN1_N pins of the core processing unit, respectively; and AXIS1_DATA1_P and AXIS1_DATA1_N, which are X-axis data differential signal pairs, connected to the LVDS_IN2_P and LVDS_IN2_N pins of the core processing unit, respectively. The Y-axis signals include: AXIS2_CLK2_P and AXIS2_CLK2_N, which are Y-axis clock differential signal pairs, connected to the LVDS_IN3_P and LVDS_IN3_N pins of the core processing unit, respectively; and AXIS2_DATA2_P and AXIS2_DATA2_N, which are Y-axis data differential signal pairs, connected to the LVDS_IN4_P and LVDS_IN4_N pins of the core processing unit, respectively. The Z-axis signals include: AXIS3_CLK3_P and AXIS3_CLK3_N, which are Z-axis clock differential signal pairs, connected to the LVDS_IN5_P and LVDS_IN5_N pins of the core processing unit, respectively; and AXIS3_DATA3_P and AXIS3_DATA3_N, which are Z-axis data differential signal pairs, connected to the LVDS_IN6_P and LVDS_IN6_N pins of the core processing unit, respectively. Auxiliary input signals include: DDR_PG, which is the DDR power ready signal, connected to the DDR_PGOOD pin of the core processing unit, used to indicate the system memory power supply status; The core processing unit receives six LVDS differential signals from the left side, including: LVDS_IN1_P and LVDS_IN1_N, LVDS_IN2_P and LVDS_IN2_N, LVDS_IN3_P and LVDS_IN3_N, which correspond to the clock and data of the three axes, respectively. The core processing unit re-encodes the six LVDS differential signals according to the BiSS-C protocol specification, generating single-ended clock and data signals. Through the output interface, it generates a set of single-ended signals for each axis, including: The X-axis terminals CLK1 and DATA1; the Y-axis terminals CLK2 and DATA2; and the Z-axis terminals CLK3 and DATA3. The single-ended signal output from the core processing unit is sent to three completely independent BISS-C modules, including: Block module, Block1 module and Block2 module. Each independent BISS-C module corresponds to one axis and is used to generate single-ended BiSS-C clock signal and single-ended BiSS-C data signal from the decoded three-axis position data according to the BiSS-C standard timing, and output them to the back-end protocol output unit. The Block module corresponds to the X-axis. The internal output signals CLK1 and DATA1 of the core processing unit are connected to the input of the Block module. The Block module encodes the received signals CLK1 and DATA1 using the BiSS-C protocol to generate single-ended BISS_CLK and BISS_DATA signals. The Block module outputs BISS_CLK_P1, BISS_CLK_N1, BISS_DATA_N1, and BISS_DATA_P1 signals, which serve as the input interface signals for the X-axis circuit of the back-end protocol output unit. Block1 corresponds to the Y-axis. The internal output signals CLK2 and DATA2 of the core processing unit are connected to the input terminal of Block1 module. Block1 module performs BiSS-C protocol encoding on the received signals CLK2 and DATA2 to generate single-ended BISS_CLK and BISS_DATA signals. Block1 module outputs BISS_CLK_P2, BISS_CLK_N2, BISS_DATA_N2, and BISS_DATA_P2 as input interface signals for the Y-axis circuit of the back-end protocol output unit. Block2 corresponds to the Z-axis. The internal output signals CLK3 and DATA3 of the core processing unit are connected to the input of Block2 module. Block2 module performs BiSS-C protocol encoding on the received signals CLK3 and DATA3 to generate single-ended BISS_CLK and BISS_DATA signals. Block2 module outputs BISS_CLK_P3, BISS_CLK_N3, BISS_DATA_N3, and BISS_DATA_P3 as input interface signals for the Z-axis circuit of the back-end protocol output unit. The core processing unit provides four debugging interfaces: F_TDI, F_TDO, F_TCK, and F_TMS, forming a standard JTAG debugging interface for programming, online configuration, and troubleshooting of the core processing unit. The four interfaces output corresponding debugging signals: TDI debugging signal, TDO debugging signal, TCK debugging signal, and TMS debugging signal.

8. The conversion device for interferometer data acquisition as described in claim 1, characterized in that, The front-end signal input unit includes: Differential input interface with a total of 4 differential input signals: the first differential signal pair LVDS_IN5_P, LVDS_IN5_N; the second differential signal pair LVDS_IN6_P, LVDS_IN6_N; DC blocking capacitors C200, C201, C202, and C203 are used. LVDS_IN5_P is connected to DC blocking capacitor C200, which is connected to the RIN1+ pin of the U19 chip. LVDS_IN5_N is connected to DC blocking capacitor C201, which is connected to the RIN1- pin of the U19 chip. LVDS_IN6_P is connected to DC blocking capacitor C202, which is connected to the RIN4+ pin of the U19 chip. LVDS_IN6_N is connected to DC blocking capacitor C203, which is connected to the RIN4- pin of the U19 chip. The terminating matching resistors R131 and R135 are used. The two ends of the terminating matching resistor R131 are connected to the output nodes of DC blocking capacitors C200 and C201, and also between the RIN1+ and RIN1- pins of the core chip U19, to complete the impedance matching of the first differential line. The two ends of the terminating matching resistor R135 are connected to the output nodes of DC blocking capacitors C202 and C203, and also between the RIN4+ and RIN4- pins of the core chip U19. The core chip U19 includes: The input pins include: RIN1+ pin, used to receive the LVDS_IN5_P signal after processing by DC blocking capacitor C200 and terminating matching resistor R131; RIN1- pin, used to receive the LVDS_IN5_N signal after processing by DC blocking capacitor C201 and terminating matching resistor R131; RIN4+ pin 7 receives the LVDS_IN6_P signal after processing by DC blocking capacitor C202 and terminating matching resistor R135; RIN4- pin receives the LVDS_IN6_N signal after processing by DC blocking capacitor C203 and terminating matching resistor R135. The control and power supply pins include: the VCC pin, which is connected to the 3V3P_PREPHERY_IO-LVDS power supply and is used to power the chip; the EN pin, which is connected to the 3V3P_PREPHERY_IO-LVDS power supply and is used as the chip enable signal, active high; the GND pin, which is connected to digital ground DGND; and the EN pin, which is connected to DGND via resistor R136. When this pin is low-level enabled, it is pulled low to enable the chip to operate. Output pins include: ROUT1 pin for single-ended output of the first differential signal; ROUT4 pin for single-ended output of the second differential signal. Pull-up resistors and FPGA signal outputs include: ROUT1 pin 15 connected to resistor R132, resistor R132 connected to FPGA_IN_DI5; FPGA_IN_DI5 connected to resistor R133, resistor R133 connected to power supply 3V3P_PREPHERY_IO-LVDS; ROUT4 pin connected to FPGA_IN_DI6, FPGA_IN_DI6 connected to resistor R134, resistor R134 connected to power supply 3V3P_PREPHERY_IO-LVDS; The enable circuit includes: the EN pin is connected to resistor R136, and resistor R136 is connected to DGND.

9. The conversion device for interferometer data acquisition as described in claim 1, characterized in that, The complete output circuit of one of the BiSS-C channels of the back-end protocol output unit includes: Power inputs include: 3V3P_PREPHERY_BISS, which is the FPGA-side power supply; 3V3P_PREPHERY_BISS is directly connected to the VDD1 pin of chip U7 to power the internal logic of chip U7; 3V3P_PREPHERY_BISS is also connected to the DE pin of chip U7 via resistor R55. Control and enable signals include: the DE pin, which is pulled up to 3V3P_PREPHERY_BISS through resistor R55, active high, enabling the chip to operate in transmit mode; the RE pin is pulled down to digital ground DGND through resistor R59, enabling low, and together with the DE pin, enabling the chip to enter transmit mode; the GND1 pin, GND1_1 pin, and GND1_2 pin are all connected to digital ground DGND; The data input signals include: BISS_CLK, which is connected to the RO pin of chip U7 after being current-limited by resistor R57, as a single-ended clock input; and BISS_DATA, which is connected to the DI pin of chip U7 after being current-limited by resistor R58. The VDD2 pin is connected to the isolation power supply V5P_ISO_BISS to power the differential output; the GND2_2 pin, GND2_1 pin, and GND2 pin are all connected to the isolation digital ground DGND_ISO. The differential output pins include: pin A, which is the positive differential output terminal of the clock signal; pin B, which is the inverted differential output terminal of the clock signal; pin Z, which is the inverted differential output terminal of the data signal; and pin Y, which is the positive differential output terminal of the data signal. Termination matching resistors include: resistor R56, which is connected between pins A and B to provide termination impedance matching for the clock differential pair; and resistor R60, which is connected between pins Y and Z to provide termination impedance matching for the data differential pair. The clock signal output link includes: pin A via fuse F9, outputting CLK_IN_P; pin B via fuse F10, outputting CLK_IN_N; The data signal output link includes: the Z pin outputs DATA_OUT_N via fuse F11; The Y pin outputs DATA_OUT_P via fuse F12; Overcurrent protection components, including fuses F9, F10, F11 and F12, are connected in series in the differential output path.

10. A method for converting data acquired by an interferometer, characterized in that, The method, employing the conversion apparatus for interferometer data acquisition as described in any one of claims 1 to 9, comprises: When the conversion device for interferometer data acquisition is powered on, the power management unit converts the external DC voltage into a multi-channel isolated regulated voltage via DC / DC converter to power each unit; the core processing unit completes system initialization, FPGA logic loading, and peripheral configuration. The front-end signal input unit acquires the triaxial raw LVDS differential signal output by the laser interferometer through the 26-pin SDR interface. After impedance matching, DC blocking filtering and level conversion, the three LVDS differential receiving circuits are converted into three single-axis digital signals and output to the core processing unit. The core processing unit performs interferometer connection verification on the three-axis stable digital signal to determine whether the laser interferometer is effectively connected and whether the signal link is normal. If the connection verification passes, the core processing unit continues to perform identification and obtains the identification results, including: channel number identification, output type identification, measurement resolution identification, and obtains the current working channel, data output mode, and physical measurement resolution of the interferometer; if the connection is abnormal, it enters a fault prompt state and waits for the connection to be restored before re-performing the verification; the data output mode includes: absolute and incremental output modes; The core processing unit automatically completes the matching of working parameters based on the recognition results, including configuring the BiSS-C output bit width, communication rate, data format and resolution mapping parameters; The core processing unit listens for configuration commands from the host computer. If it receives new working parameters from the user through the host computer, the core processing unit will overwrite the automatically matched working parameters with the new parameters; otherwise, it will continue to use the automatically matched default working parameters. The core processing unit performs parallel decoding of the three single-axis digital signals based on the matched working parameters, completes protocol encoding according to the BiSS-C standard timing, and generates a three-axis standard BiSS-C protocol signal, wherein the three-axis standard BiSS-C protocol signal includes: a three-axis BiSS-C clock signal and a data signal; The back-end protocol output unit receives the three-axis standard BiSS-C protocol signal, converts the single-axis BiSS-C clock signal and data signal into RS422 differential signals, and synchronously outputs them to the external motion controller through the HDB15 interface to provide high-precision reference position feedback for displacement sensor calibration; wherein, the RS422 differential signal of each axis includes: differential clock signal and differential data signal; The debugging and monitoring unit obtains triaxial position data that is sourced, synchronized, and of the same value as the triaxial standard BiSS-C protocol signal from the core processing unit, calculates the relative distance between axes, and uploads it to the host computer via gigabit Ethernet in combination with the operating status and waveform data, so as to realize real-time monitoring and debugging of the calibration process.

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