Low-power analog front-end circuit applied to animal tag and control method

Abstract

This invention discloses a low-power analog front-end circuit and control method for animal tags. The circuit includes: a radio frequency (RF) unit, a power management unit, and an antenna. The power management unit includes a rectifier and a low-power power management circuit. The rectifier is connected to the antenna. The low-power power management circuit supplies power to the RF unit and digital circuits. The RF unit includes a load modulation and limiting circuit, a demodulation circuit, and a clock generation circuit. The demodulation circuit receives the demodulated envelope signal sent by the rectifier and outputs digital demodulated data to the digital circuits. The clock generation circuit extracts a clock signal from the antenna signal generated by the antenna and outputs the clock signal to the digital circuits. The load modulation and limiting circuit receives the limiting reference voltage sent by the rectifier and the uplink data output by the digital circuits. In this embodiment, an animal identification tag adapted for wireless communication achieves a balance between low power consumption and small area while ensuring communication reliability.

Description

Technical Field

[0001] This invention relates to the field of analog circuit technology, and in particular to a low-power analog front-end circuit and control method for animal tagging. Background Technology

[0002] In the fields of modern livestock management, wildlife protection, and pet traceability, electronic animal tags have become a key carrier for achieving automatic identification of individuals; depending on the application form, they are mainly divided into ear tags, collar tags, and injectable glass tube tags.

[0003] To ensure that the tag signal can penetrate the animal's water-rich biological tissues, fur, and even overcome some of the shielding of metal fences, these tags typically operate in low-frequency bands (such as 134.2 kHz). The magnetic field in this band has extremely strong penetrating power and is currently the internationally accepted standard in the field of animal identification.

[0004] However, the design of analog front-end circuits for such passive animal tags faces extremely stringent challenges in terms of power consumption and energy maintenance: Power outage issues caused by communication characteristics: Passive animal tags do not have internal batteries and rely entirely on the magnetic field of an external reader coupled with an induction coil for power. However, in order to transmit data or perform synchronization, the reader intermittently shuts off the magnetic field when sending signals (i.e., "field stop"). During this period, the tag completely loses its power source, and the chip must rely on a tiny on-chip energy storage capacitor to "survive". If the circuit power consumption is too high, the capacitor will be depleted instantly, causing the tag to lose power and reset during data transmission, resulting in identification failure.

[0005] Static power consumption issues in traditional circuits: Most existing tag chips use a common analog circuit architecture, and their power consumption mainly comes from the static DC path that cannot be turned off: operational amplifier bias consumption: In order to maintain high accuracy, traditional voltage regulators and demodulators integrate operational amplifiers and comparators; these devices must have a constant static current flowing through them to maintain their working state, which usually consumes several microamps (μA) of power without generating any actual power gain; continuous leakage of resistor networks: In order to set the voltage ratio, traditional circuits widely use resistor voltage divider networks; this forms a path from the positive terminal of the power supply to ground (GND), and the current is continuously lost regardless of whether the tag is communicating.

[0006] For injectable animal tags with limited size (which prevents the energy storage capacitor from being made large), the aforementioned static power consumption is a fatal bottleneck restricting its communication distance and stability. Therefore, developing a low-power analog front-end circuit that eliminates high-power operational amplifiers and cuts off the leakage path of resistors is a core technical requirement for achieving high-performance animal tags. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a low-power analog front-end circuit and control method for animal tags, which is suitable for animal identification tags with wireless communication, ensuring communication reliability while achieving a balance between low power consumption and small area.

[0008] To address the aforementioned technical problems, embodiments of the present invention provide a low-power analog front-end circuit for animal tags, the low-power analog front-end circuit comprising: a radio frequency unit, a power management unit, and an antenna; The power management unit includes a rectifier and a low-power power management circuit. The input terminal of the rectifier is connected to the antenna and is used to convert the radio frequency AC signal received by the reader from the antenna into a DC power supply voltage, a limiting reference voltage, and a demodulated envelope signal. The limiting reference voltage and the demodulated envelope signal are input to the radio frequency unit, and the DC power supply voltage is input to the low-power power management circuit. The low-power power management circuit converts the input DC power supply voltage into a stable digital power supply voltage and supplies power to the radio frequency unit and the digital circuit. The radio frequency unit includes a load modulation and limiting circuit, a demodulation circuit, and a clock generation circuit. The demodulation circuit receives the demodulated envelope signal sent by the rectifier, demodulates the demodulated envelope signal to the ASK modulated signal sent by the reader, and outputs digital demodulated data to the digital circuit. The clock generation circuit extracts a clock signal from the antenna signal generated by the antenna and outputs the clock signal to the digital circuit. The load modulation and limiting circuit receives the limiting reference voltage sent by the rectifier and the uplink data output by the digital circuit.

[0009] Optionally, the rectifier is a multi-output rectifier bridge based on an NMDS cross-coupled gate structure; the ANTA and ANTB of the antenna are respectively connected to the drains of cross-coupled transistor pairs N7 and N8; the gate of cross-coupled transistor N7 is connected to ANTB; the gate of cross-coupled transistor N8 is connected to ANTA; and the sources of cross-coupled transistors N7 and N8 are both grounded.

[0010] Optionally, the rectifier includes a first rectifier branch, a second rectifier branch, and a third rectifier branch; The first rectifier branch is used to generate a DC power supply voltage, the second rectifier branch is used to generate a limiting reference voltage, and the third rectifier branch is used to generate a demodulation envelope signal. The first rectifier branch, the second rectifier branch, and the third rectifier branch are connected in parallel at the rectifier input terminal and isolated from each other at the output terminal. The NMOS transistors in the rectifier are configured to simultaneously perform electrostatic discharge protection functions.

[0011] Optionally, the low-power power management circuit includes a reference circuit, a low-dropout linear regulator, and a reset circuit. The reference circuit receives the DC power supply voltage output by the rectifier and converts the DC power supply voltage into a bias voltage. The reference circuit will use the bias voltage In the input low-dropout linear regulator, the low-dropout linear regulator is biased by the input voltage. After voltage regulation, a stable digital power supply voltage is output to the radio frequency unit, digital circuit, and reset circuit; the reset circuit is used to output a reset signal to the digital circuit.

[0012] Optionally, the low-dropout linear regulator is an operational amplifier-free architecture, including a startup circuit, a reference current generation circuit, a common-source cascode current mirror, and a resistor-free feedback adjustment loop; In the startup circuit, one end of resistor R1 is connected to the input high voltage. The other end is connected to the gate of PMOS transistor P1; the source of PMOS transistor P1 is connected to a high voltage. The drain of NMOS transistor N10 is connected to the drain of NMOS transistor N9; the gate of NMOS transistor N9 is connected to the drain of P1, and the drain of NMOS transistor N9 is connected to the bias voltage of the bias node. The source of NMOS transistor N9 is grounded; the reference current generation circuit uses a MOS transistor operating in the subthreshold region to generate a reference current independent of the power supply; the common-source common-gate current mirror is used to provide a bias current with high output impedance; the resistorless feedback adjustment loop directly controls the gate of the adjustment transistor by sampling the output voltage.

[0013] Optionally, the resistanceless feedback adjustment circuit utilizes a PMOS feedback transistor to sense the output voltage. The source of the PMOS feedback transistor is connected to the output terminal, and the gate is connected to the bias node. When the output voltage increases, the current flowing through the PMOS feedback transistor increases, which changes the current distribution of the common source and common gate current mirror, thereby adjusting the gate voltage of the power transistor to reduce the output voltage and form a negative feedback loop.

[0014] Optionally, the demodulation circuit includes an active RC low-wave filter circuit and an inverter shaping circuit; the active RC low-wave filter circuit is used to perform carrier frequency filtering on the received demodulated envelope signal and retain the baseband envelope signal in the demodulated envelope signal, wherein the resistor part in the active RC low-wave filter circuit is implemented by a current mirror active resistor composed of MOS transistors, and the capacitor part is implemented by MOS capacitors. The inverter shaping circuit is used to connect to the output of the active RC low-wave filter circuit. The baseband envelope signal is directly judged and shaped using the flip threshold of the inverter shaping circuit. The first-stage inverter of the inverter shaping circuit adopts an asymmetrical size design, so that its falling edge flip speed is slower than its rising edge, in order to adapt to the discharge characteristics of the baseband envelope signal.

[0015] Optionally, the clock generation circuit includes a current-limiting resistor, a switching transistor connected to the antenna, and a latch comparator consisting of two inverters connected end to end; the latch comparator uses a positive feedback mechanism to convert the sine wave signal on the antenna into a square wave clock signal.

[0016] Optionally, the energy storage capacitor and the filter capacitor in the low-power analog front-end circuit are both MOS capacitors.

[0017] In addition, embodiments of the present invention also provide a control method for a low-power analog front-end circuit, using the low-power analog front-end circuit as described above, the method comprising: When the reader approaches the low-power analog front-end circuit, the antenna on the low-power analog front-end circuit receives the radio frequency AC signal from the reader. The antenna on the low-power analog front-end circuit transmits the received radio frequency AC signal to the power management unit. In the power management unit, the rectifier converts the radio frequency AC signal into DC power supply voltage, limiting reference voltage, and demodulation envelope signal. The rectifier inputs the DC power supply voltage into the low-power power management circuit in the power management unit so that the low-power power management circuit can provide a stable digital power supply voltage to the low-power analog front-end circuit and the digital circuit connected to the low-power analog front-end circuit. The rectifier inputs the limiting reference voltage and the demodulated envelope signal into the RF unit, so that the RF unit can use the uplink and downlink control digital circuits to control the data interaction between the digital circuit and the reader based on the limiting reference voltage and the demodulated envelope signal.

[0018] In this embodiment of the invention, to address the issues of high quiescent power consumption and large resistor area in the LDO, a power management unit without op-amps and resistor feedback is designed, reducing the area and power consumption of the power management unit. To address the issues of large RC filter area and high quiescent power consumption in the demodulator, an RF interface circuit without op-amps and replacing them with MOS capacitors is designed, reducing the area and power consumption of the RF interface circuit. This enables the power management unit to convert unstable AC power induced by the antenna into DC power and provide ESD protection for the chip. Its input is connected to both ends of the induction coil of the animal tag, receiving the high-voltage AC signal generated by magnetic field coupling. Its output generates a high-voltage DC voltage for energy storage and a low-voltage constant power supply for the digital logic circuit. Simultaneously, it eliminates the main quiescent DC path in the analog circuit, significantly reducing the circuit's quiescent power consumption, thereby ensuring that the animal tag can still operate reliably in weak magnetic fields or during field pauses. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of a low-power analog front-end circuit applied to animal tags in an embodiment of the present invention; Figure 2 This is a circuit structure diagram of the rectifier in an embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit structure of the low-power power management circuit in an embodiment of the present invention; Figure 4 This is a schematic diagram of the circuit structure of the load modulation and limiting circuit in an embodiment of the present invention; Figure 5 This is a schematic diagram of the demodulation circuit in an embodiment of the present invention; Figure 6 This is a schematic diagram of the circuit structure of the clock generation circuit in an embodiment of the present invention; Figure 7 This is a flowchart illustrating the control method for a low-power analog front-end circuit in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example 1, please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a low-power analog front-end circuit applied to animal tags in an embodiment of the present invention.

[0023] like Figure 1 As shown, a low-power analog front-end circuit for animal tags includes: a radio frequency (RF) unit, a power management unit, and an antenna; the power management unit includes a rectifier and a low-power power management circuit; the input terminal of the rectifier is connected to the antenna, and is used to convert the RF AC signal received by the antenna from the reader into a DC power supply voltage, a limiting reference voltage, and a demodulated envelope signal, and input the limiting reference voltage and the demodulated envelope signal to the RF unit, and input the DC power supply voltage to the low-power power management circuit; the low-power power management circuit converts the input DC power supply voltage into a stable digital power supply. The voltage is supplied to the RF unit and the digital circuit; the RF unit includes a load modulation and limiting circuit, a demodulation circuit, and a clock generation circuit; the demodulation circuit receives the demodulated envelope signal sent by the rectifier, demodulates the demodulated envelope signal to the ASK modulated signal sent by the reader, and outputs digital demodulated data to the digital circuit; the clock generation circuit extracts the clock signal from the antenna signal generated by the antenna and outputs the clock signal to the digital circuit; the load modulation and limiting circuit receives the limiting reference voltage sent by the rectifier and the uplink data output by the digital circuit.

[0024] Specifically, the low-power analog front-end circuit serves as a bridge between the digital circuitry and the reader, converting the unstable AC power sensed by the antenna into DC power and providing ESD protection for the chip. Its input is connected to both ends of the induction coil of the animal tag, receiving the high-voltage AC signal generated by magnetic field coupling. Its output generates a high-voltage DC voltage for energy storage and a low-voltage constant power supply for the digital logic circuitry.

[0025] The power management unit receives the RF AC signal from the antenna through the ANTA and ANTB pins. Then, the rectifier and low-power power management circuit in the power management unit identify the RF AC signal from the antenna and convert it into DC power supply voltage, limiting reference voltage, and demodulation envelope signal. The DC power supply voltage is transmitted to the low-power power management circuit to generate a stable digital voltage to power the RF unit and digital circuit, so that the low-power analog front-end circuit can still work reliably in weak magnetic fields or during field pauses.

[0026] This rectifier is a multi-output rectifier, serving as the primary interface for energy exchange. It employs an NMOS cross-coupled structure in the signal flow direction. The RF AC signals from both ends of the antenna directly enter this rectifier, and after rectification, are split into three isolated independent output branches: the first branch generates a DC power supply voltage. Used to charge the energy storage capacitor; the second channel generates a limiting reference voltage. The first channel supplies the limiting circuit; the second channel generates a demodulation envelope signal which is supplied to the demodulation circuit, wherein the demodulation envelope signal is used to demodulate the reference voltage. It exists in the form of a rectifier; in addition, the large-sized rectifier tube in the rectifier is directly connected between the antenna pin and ground, and also serves as an electrostatic discharge (ESD) protection device.

[0027] In low-power power management circuits, an operational amplifier-free LDO (low dropout linear regulator) architecture is proposed for precise voltage regulation. The reference current source is generated by a voltage-independent reference current source. In the signal flow, the circuit receives the fluctuating DC power supply voltage from the rectifier output. As input, it is processed based on common-source cascode current mirror and resistorless feedback technology; the control loop uses the threshold voltage of the MOSFET and the mirror ratio of the current mirror to output the digital power supply voltage. Set at 1.5V; when the output digital power supply voltage... When fluctuations occur, a PMOS transistor is used as a voltage sensing device to directly convert the change in output voltage into a current signal and feed it back to the control loop, thereby driving the power adjustment transistor for compensation. This design cuts off the ground discharge path brought about by the traditional resistor voltage divider network, and achieves extremely low quiescent current while providing a stable voltage (1.5V).

[0028] The radio frequency (RF) unit is used for data interaction between the digital circuitry and the reader. Its input receives the amplitude-shift keying (ASK) modulated waveform from the coil, and its output outputs the demodulated digital signal and the recovered system clock. To reduce power consumption and chip area at low data rates, this RF unit circuit employs the following architecture and signal processing flow: The demodulation circuit is a comparator-free regulator designed for 100% ASK modulated signals. Its signal processing flow is as follows: First, the RF signal enters a low-pass filter composed of an active resistor and a MOS capacitor, which utilizes the high output impedance of the MOS transistor to filter out the carrier and extract the low-frequency envelope signal. Then, the envelope signal drives an asymmetric inverter for preliminary threshold decision. Finally, the signal undergoes further shaping by two stages of shaping inverters to recover the steeply edged digital baseband signal. This design avoids the chip area occupation and ground leakage current caused by passive resistors, significantly reducing demodulation power consumption.

[0029] The clock generation circuit adopts a hysteresis comparison structure based on a positive feedback latch, eliminating the need for a local oscillator. In the signal flow direction, the input of this circuit is directly connected across the differential signals at both ends of the antenna. The induced voltage directly drives the latch to flip, extracting the 134.2kHz square wave clock signal CLK from the carrier wave. Since energy is consumed only at the moment of signal flipping, the power consumption of this circuit is only in the nanoampere range.

[0030] The low-power analog front-end circuit employs an op-amp-free current-mode architecture, a resistor-free feedback mechanism, and threshold decision technology in the RF unit and power management unit. This eliminates the main static DC path in the analog circuit, significantly reducing the static power consumption of the circuit, thereby ensuring that the animal tag can still work reliably in weak magnetic fields or during field pauses.

[0031] Furthermore, the rectifier is a multi-output rectifier bridge based on an NMDS cross-coupled gate structure; the ANTA and ANTB of the antenna are respectively connected to the drains of cross-coupled transistor pairs N7 and N8; the gate of cross-coupled transistor N7 is connected to ANTB; the gate of cross-coupled transistor N8 is connected to ANTA; and the sources of cross-coupled transistors N7 and N8 are both grounded.

[0032] Furthermore, the rectifier includes a first rectifier branch, a second rectifier branch, and a third rectifier branch; wherein the first rectifier branch is used to generate a DC power supply voltage, the second rectifier branch is used to generate a limiting reference voltage, and the third rectifier branch is used to generate a demodulation envelope signal; the first rectifier branch, the second rectifier branch, and the third rectifier branch are connected in parallel at the rectifier input terminal and isolated from each other at the output terminal; the NMOS transistors in the rectifier are configured to simultaneously provide electrostatic discharge protection.

[0033] For details, please refer to Figure 2To achieve power isolation between functional modules and optimize layout area, the rectifier in this embodiment adopts a multi-output rectifier bridge based on an NMOS cross-coupled gate structure. The specific connection relationships are as follows: RF input terminals ANTA and ANTB are connected to the drains of cross-coupled transistor pairs N7 and N8, respectively. The gate of transistor N7 is connected to ANTB, and the gate of N8 is connected to ANTA. The sources of both N7 and N8 are grounded (VSS). This cross-connection method allows N7 and N8 to conduct alternately during the negative half-cycle of the RF signal, providing a low-impedance ground loop. Figure 2 As shown, transistors N7 and N8 form a cross-coupled pair, utilizing the comparator principle to reduce the turn-on voltage of the rectifier diodes, thereby reducing voltage loss. To accommodate different load requirements, the rectifier is configured with three independent outputs. Assume the peak value of the antenna input voltage is... The on-state voltage drop of the rectifier diode is The main power supply branch outputs DC power voltage. It can be approximated as: ; In the formula: This is the NMOS threshold voltage; To mitigate overdrive voltage; by optimizing the width-to-length ratio of N7 and N8, for example, making them not only rectifiers but also ESD discharge channels, additional ESD protection circuit area is saved.

[0034] Furthermore, the low-power power management circuit includes a reference circuit, a low-dropout linear regulator, and a reset circuit; the reference circuit receives the DC power supply voltage output by the rectifier and converts the DC power supply voltage into a bias voltage. The reference circuit will use the bias voltage In the input low-dropout linear regulator, the low-dropout linear regulator is biased by the input voltage. After voltage regulation, a stable digital power supply voltage is output to the radio frequency unit, digital circuit, and reset circuit; the reset circuit is used to output a reset signal to the digital circuit.

[0035] Furthermore, the low-dropout linear regulator is an operational amplifier-less architecture, wherein the low-power power management circuit includes a startup circuit, a reference current generation circuit, a common-source cascode current mirror, and a resistorless feedback adjustment loop; in the startup circuit, one end of resistor R1 is connected to the input high voltage. The other end is connected to the gate of PMOS transistor P1; the source of PMOS transistor P1 is connected to a high voltage. The drain of NMOS transistor N10 is connected to the drain of NMOS transistor N9; the gate of NMOS transistor N9 is connected to the drain of P1, and the drain of NMOS transistor N9 is connected to the bias voltage of the bias node. The source of NMOS transistor N9 is grounded; the reference current generation circuit uses a MOS transistor operating in the subthreshold region to generate a reference current independent of the power supply; the common-source common-gate current mirror is used to provide a bias current with high output impedance; the resistorless feedback adjustment loop directly controls the gate of the adjustment transistor by sampling the output voltage.

[0036] The resistanceless feedback adjustment circuit uses a PMOS feedback transistor to sense the output voltage. The source of the PMOS feedback transistor is connected to the output terminal, and the gate is connected to the bias node. When the output voltage increases, the current flowing through the PMOS feedback transistor increases, which changes the current distribution of the common source and common gate current mirror, thereby adjusting the gate voltage of the power transistor to reduce the output voltage and form a negative feedback loop.

[0037] Specifically, the core of the low-power power management circuit is a low-dropout linear regulator (LDO) without operational amplifiers or resistor feedback. Traditional LDOs rely on resistor divider networks and error amplifiers, resulting in relatively high static power consumption. In this embodiment, the output voltage is set using a common-source cascode current mirror and the threshold voltage characteristics of a MOSFET. The specific voltage regulation principle and formula derivation of the LDO in this embodiment are explained below. Figure 3 As shown, in the startup circuit, one end of resistor R1 is connected to the input high voltage. The other end is connected to the gate of PMOS transistor P1; the source of P1 is connected to... The drain of N9 is connected to the drain of NMOS transistor N10. The gate of N9 is connected to the drain of P1, and the drain of N9 is connected to the bias voltage of the bias node. The source of N9 is grounded; the reference current generation circuit generates a reference current independent of the power supply. The voltage-independent reference current source consists of P7, P8, N17, N18, and Q1; transistors N16, P6, and P7 form a feedback voltage regulation loop; among which... The current flowing through N16 is set to 4. In the reference current source and LDO core circuit, the sources of PMOS transistors P2, P3, P4, and P5 are all connected to... The gate interconnects form a current mirror; the drain output of the regulating transistor P5 provides a stable digital voltage. Regarding the feedback regulation loop: transistors N13, N14, N15, and N16 form a common-source, common-gate current mirror structure; the gate of N16 is connected to the feedback node (typically...). (or a node after level shifting), the source of N16 is grounded; P6 and P7 are PMOS transistors connected in series in the feedback loop, and the source of P6 is connected to... The source of P7 is connected to the drain of P6, and the drain of P7 is connected to the drain of N16; to achieve the adjustment between the gate and drain of the regulating transistor, the width-to-length ratio of P2-P5 is equal. = = The width-to-length ratio of N13 and N14 is equal, not a multiple, because the current flowing through N14 is I4, not... The aspect ratio of the N16 is designed to be four times that of the N15. =4 The current flowing through the feedback loop is clamped, and the current If in P6 and P7 is determined. = - =3 In the circuit, (W / L)P6 = (W / L)P7. Once the width-to-length ratio of N16, P6, and P7 is determined, VgsN16, VgsP6, and VgsP7 can be written accordingly. The expression for: When the circuit is in a closed-loop steady state, the output voltage The gate-source voltage of the transistor Decision. Once the aspect ratios of N16, P6, and P7 are determined, Vgs can be written accordingly. N16 Vgs P6 Vgs P7 and The expression: ; ; ; in, and These are the mobilities of electrons and holes, respectively. The gate oxide capacitance per unit area; as can be seen from the formula, a reasonable design of I1 and aspect ratio (W / L) is crucial. N22 (W / L) P21 It can be determined The DC voltage. Unlike the MOSFETs in the previous startup circuit and reference current source, P6-P7 and N13-N26 use 1.5V NMOS transistors with a lower threshold voltage, ensuring that P7 and N16 are in the saturation region when the LDO is working normally.

[0038] In the LDO architecture of the embodiment, the quiescent current can be obtained from the following formula: (5); By properly designing the reference current By determining the aspect ratio of transistors N16 and P6, precise settings can be achieved without resistive feedback. It is 1.5V.

[0039] Furthermore, the demodulation circuit includes an active RC low-wave filter circuit and an inverter shaping circuit. The active RC low-wave filter circuit is used to filter out the carrier frequency of the received demodulated envelope signal, retaining the baseband envelope signal in the demodulated envelope signal. The resistor part in the active RC low-wave filter circuit is implemented by a current mirror active resistor composed of MOS transistors, and the capacitor part is implemented by MOS capacitors. The inverter shaping circuit is used to connect to the output of the active RC low-wave filter circuit, and directly judges and shapes the baseband envelope signal using the flip threshold of the inverter shaping circuit. The first-stage inverter of the inverter shaping circuit adopts an asymmetrical size design, so that its falling edge flip speed is slower than its rising edge, in order to adapt to the discharge characteristics of the baseband envelope signal.

[0040] Furthermore, the clock generation circuit includes a current-limiting resistor, a switching transistor connected to the antenna, and a latch comparator consisting of two inverters connected end to end; the latch comparator uses a positive feedback mechanism to convert the sine wave signal on the antenna into a square wave clock signal.

[0041] Furthermore, the energy storage capacitor and filter capacitor in the low-power analog front-end circuit are both MOS capacitors.

[0042] like Figure 4 As shown, in this embodiment, a load modulation and limiting circuit, a demodulation circuit, and a clock generation circuit are provided; the limiting circuit is used to prevent the antenna induced voltage from being too high and damaging the chip; the circuit uses NMOS bleeder diodes N17 and N18 and a PMOS string (P7, P8, P9) connected by diodes as threshold detection. When the rectified output voltage... When rising, its limit threshold is activated. Determined by the following formula: ; When load modulation (uplink communication) is required, the digital signal Data_m controls the switch P9 to turn on, shorting P7. At this time, the new limiting threshold is lowered, forcing the limiter to turn on earlier and draw more current, thereby changing the antenna load impedance and achieving an ASK modulation effect with an amplitude modulation depth greater than 30%.

[0043] like Figure 5 As shown in the figure, this embodiment of the invention provides a comparator-free low-power demodulation circuit diagram. This modulation circuit aims to recover data from a 100% ASK signal, using a low-pass filter composed of "active resistor + MOS capacitor" to replace traditional large-area passive components; in order to correctly filter out the carrier frequency... (134.2 kHz) and retain data rate (4.194 kbps), the RC time constant of the filter must satisfy: ; In a specific embodiment of the present invention, an active resistor It is implemented by MOSFETs (P13, N24, etc.) operating in the subthreshold region; its equivalent resistance can be approximated as: ; By adjusting the width-to-length ratio of transistors such as N24, a very large equivalent resistance can be obtained, allowing for the use of smaller capacitors to meet the filtering requirements and significantly saving chip area. The filtered signal directly drives an asymmetric inverter for threshold decision, eliminating the static power consumption of the comparator. As shown in the figure, the demodulated signal... After envelope extraction and low-pass filtering, the signal first enters a three-stage inverter composed of 3.3V MOS transistors for pre-shaping. Since the discharge speed on the antenna is slower than the charging speed, the size of the NMOS transistors in the inverter is increased to accommodate the characteristic that the falling edge of the envelope is slower than the rising edge. Finally, the signal enters a buffer in the 1.5V voltage domain for final shaping, and the high level is converted into a digital operating voltage. The three-stage inverter also acts as a buffer stage to enhance the load capacity of the demodulation circuit and improve the speed and stability of the demodulation output.

[0044] like Figure 6 The clock generation circuit shown is connected as follows: Input terminals ANTA and ANTB are connected to the gates of input transistors N25 and N26 respectively through current-limiting resistors (or directly); the sources of N25 and N26 are connected to the two input nodes of the latch respectively; the latch comparator is composed of cross-coupled inverter pairs: transistors N27 and P12 form the first inverter, and N28 and P13 form the second inverter; the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter, forming a positive feedback loop; when Potential higher than At this time, N25 has a stronger conduction capability than N26, breaking the latch balance, and the positive feedback loop quickly pulls the output node to a high level; the output clock signal It is taken from the output node of the latch and output after passing through the subsequent shaping buffer.

[0045] In this embodiment of the invention, to address the issues of high quiescent power consumption and large resistor area in the LDO, a power management unit without op-amps and resistor feedback is designed, reducing the area and power consumption of the power management unit. To address the issues of large RC filter area and high quiescent power consumption in the demodulator, an RF interface circuit without op-amps and replacing them with MOS capacitors is designed, reducing the area and power consumption of the RF interface circuit. This enables the power management unit to convert unstable AC power induced by the antenna into DC power and provide ESD protection for the chip. Its input is connected to both ends of the induction coil of the animal tag, receiving the high-voltage AC signal generated by magnetic field coupling. Its output generates a high-voltage DC voltage for energy storage and a low-voltage constant power supply for the digital logic circuit. Simultaneously, it eliminates the main quiescent DC path in the analog circuit, significantly reducing the circuit's quiescent power consumption, thereby ensuring that the animal tag can still operate reliably in weak magnetic fields or during field pauses.

[0046] Example 2, please refer to Figure 7 , Figure 7 This is a flowchart illustrating the control method for a low-power analog front-end circuit in an embodiment of the present invention.

[0047] like Figure 7 As shown, a control method for a low-power analog front-end circuit, using the low-power analog front-end circuit as described above, includes: S701: When the reader approaches the low-power analog front-end circuit, the antenna provided on the low-power analog front-end circuit receives the radio frequency AC signal from the reader; S702: The antenna on the low-power analog front-end circuit transmits the received radio frequency AC signal to the power management unit. In the power management unit, the rectifier converts the radio frequency AC signal into DC power supply voltage, limiting reference voltage and demodulation envelope signal. S703: The rectifier inputs the DC power supply voltage into the low-power power management circuit in the power management unit so that the low-power power management circuit provides a stable digital power supply voltage to the low-power analog front-end circuit and the digital circuit connected to the low-power analog front-end circuit. The S704 rectifier inputs the limiting reference voltage and demodulated envelope signal into the RF unit, enabling the RF unit to use uplink / downlink control digital circuitry to control data interaction between the digital circuitry and the reader based on the limiting reference voltage and demodulated envelope signal.

[0048] Specifically, the control method for the low-power analog front-end circuit requires that when the reader approaches the low-power analog front-end circuit, since the low-power analog front-end circuit is a passive circuit, it needs to convert the radio frequency AC signal into a stable power supply voltage to power the digital circuit and the low-power analog front-end circuit. Therefore, it needs to receive the radio frequency AC signal from the reader through an antenna set on the low-power analog front-end circuit. Then, the received radio frequency AC signal is transmitted to the power management unit. In the power management unit, a rectifier converts the radio frequency AC signal into a DC power supply voltage, a limiting reference voltage, and a demodulation envelope signal. Then, the DC power supply voltage is input into the low-power power management circuit in the power management unit so that the low-power power management circuit can provide a stable digital power supply voltage to the low-power analog front-end circuit and the digital circuit connected to the low-power analog front-end circuit. Finally, the rectifier inputs the limiting reference voltage and the demodulation envelope signal into the radio frequency unit so that the radio frequency unit can use uplink and downlink control to control the data interaction between the digital circuit and the reader based on the limiting reference voltage and the demodulation envelope signal.

[0049] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0050] Furthermore, the above provides a detailed description of a low-power analog front-end circuit and control method for animal tags provided by the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A low-power analog front-end circuit for animal tagging, characterized in that, The low-power analog front-end circuit includes: a radio frequency unit, a power management unit, and an antenna; The power management unit includes a rectifier and a low-power power management circuit. The input terminal of the rectifier is connected to the antenna and is used to convert the radio frequency AC signal received by the reader from the antenna into a DC power supply voltage, a limiting reference voltage, and a demodulated envelope signal. The limiting reference voltage and the demodulated envelope signal are input to the radio frequency unit, and the DC power supply voltage is input to the low-power power management circuit. The low-power power management circuit converts the input DC power supply voltage into a stable digital power supply voltage and supplies power to the radio frequency unit and the digital circuit. The radio frequency unit includes a load modulation and limiting circuit, a demodulation circuit, and a clock generation circuit. The demodulation circuit receives the demodulated envelope signal sent by the rectifier, demodulates the demodulated envelope signal to the ASK modulated signal sent by the reader, and outputs digital demodulated data to the digital circuit. The clock generation circuit extracts a clock signal from the antenna signal generated by the antenna and outputs the clock signal to the digital circuit. The load modulation and limiting circuit receives the limiting reference voltage sent by the rectifier and the uplink data output by the digital circuit.

2. The low-power analog front-end circuit according to claim 1, characterized in that, The rectifier is a multi-output rectifier bridge based on an NMDS cross-coupled gate structure; the antenna's ANTA and ANTB are respectively connected to the drains of cross-coupled transistor pairs N7 and N8; the gate of cross-coupled transistor N7 is connected to ANTB; the gate of cross-coupled transistor N8 is connected to ANTA; and the sources of both cross-coupled transistor N7 and cross-coupled transistor N8 are grounded.

3. The low-power analog front-end circuit according to claim 2, characterized in that, The rectifier includes a first rectifier branch, a second rectifier branch, and a third rectifier branch; The first rectifier branch is used to generate a DC power supply voltage, the second rectifier branch is used to generate a limiting reference voltage, and the third rectifier branch is used to generate a demodulation envelope signal. The first rectifier branch, the second rectifier branch, and the third rectifier branch are connected in parallel at the rectifier input terminal and isolated from each other at the output terminal. The NMOS transistors in the rectifier are configured to simultaneously perform electrostatic discharge protection functions.

4. The low-power analog front-end circuit according to claim 1, characterized in that, The low-power power management circuit includes a reference circuit, a low-dropout linear regulator, and a reset circuit. The reference circuit receives the DC power supply voltage output by the rectifier and converts the DC power supply voltage into a bias voltage. The reference circuit inputs the bias voltage into the low dropout linear regulator. After the low dropout linear regulator performs voltage regulation on the input bias voltage, it outputs a stable digital power supply voltage to the RF unit, digital circuit, and reset circuit. The reset circuit is used to output a reset signal to the digital circuit.

5. The low-power analog front-end circuit according to claim 4, characterized in that, The low dropout linear regulator is an operational amplifier-free architecture, wherein the low power management circuit includes a startup circuit, a reference current generation circuit, a common source cascode current mirror, and a resistor-free feedback adjustment loop. In the startup circuit, one end of resistor R1 is connected to the input high voltage, and the other end is connected to the gate of PMOS transistor P1; the source of PMOS transistor P1 is connected to the high voltage, and the drain is connected to the drain of NMOS transistor N10; the gate of NMOS transistor N9 is connected to the drain of P1, the drain of NMOS transistor N9 is connected to the bias voltage of the bias node, and the source of NMOS transistor N9 is grounded; the reference current generation circuit uses a MOS transistor operating in the subthreshold region to generate a reference current independent of the power supply; the common-source common-gate current mirror is used to provide a bias current with high output impedance; the resistorless feedback adjustment loop directly controls the gate of the adjustment transistor by sampling the output voltage.

6. The low-power analog front-end circuit according to claim 5, characterized in that, The resistanceless feedback adjustment circuit uses a PMOS feedback transistor to sense changes in the output voltage. The source of the PMOS feedback transistor is connected to the output terminal, and the gate is connected to the bias node. When the output voltage increases, the current flowing through the PMOS feedback transistor increases, changing the current distribution of the common-source cascode current mirror, thereby adjusting the gate voltage of the power transistor to reduce the output voltage and forming a negative feedback loop.

7. The low-power analog front-end circuit according to claim 1, characterized in that, The demodulation circuit includes an active RC low-wave filter circuit and an inverter shaping circuit; the active RC low-wave filter circuit is used to perform carrier frequency filtering on the received demodulated envelope signal and retain the baseband envelope signal in the demodulated envelope signal, wherein the resistor part in the active RC low-wave filter circuit is implemented by a current mirror active resistor composed of MOS transistors, and the capacitor part is implemented by MOS capacitors. The inverter shaping circuit is used to connect to the output of the active RC low-wave filter circuit, and the baseband envelope signal is directly judged and shaped using the flip threshold of the inverter shaping circuit. The first-stage inverter of the inverter shaping circuit adopts an asymmetrical size design, making its falling edge flipping speed slower than its rising edge, in order to adapt to the discharge characteristics of the baseband envelope signal.

8. The low-power analog front-end circuit according to claim 1, characterized in that, The clock generation circuit includes a current-limiting resistor, a switching transistor connected to the antenna, and a latch comparator consisting of two inverters connected end to end; the latch comparator uses a positive feedback mechanism to convert the sine wave signal on the antenna into a square wave clock signal.

9. The low-power analog front-end circuit according to any one of claims 1-8, characterized in that, The energy storage capacitor and filter capacitor in the low-power analog front-end circuit are both MOS capacitors.

10. A control method for a low-power analog front-end circuit, characterized in that, The method, which utilizes the low-power analog front-end circuit as described in claim 1, comprises: When the reader approaches the low-power analog front-end circuit, the antenna on the low-power analog front-end circuit receives the radio frequency AC signal from the reader. The antenna on the low-power analog front-end circuit transmits the received radio frequency AC signal to the power management unit. In the power management unit, the rectifier converts the radio frequency AC signal into DC power supply voltage, limiting reference voltage, and demodulation envelope signal. The rectifier inputs the DC power supply voltage into the low-power power management circuit in the power management unit so that the low-power power management circuit can provide a stable digital power supply voltage to the low-power analog front-end circuit and the digital circuit connected to the low-power analog front-end circuit. The rectifier inputs the limiting reference voltage and the demodulated envelope signal into the RF unit, so that the RF unit can use the uplink and downlink control digital circuits to control the data interaction between the digital circuit and the reader based on the limiting reference voltage and the demodulated envelope signal.

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