LDO circuit with improved loop stability

By setting a buffer stage and an internal ESR compensation module in the LDO circuit, the gate impedance of the power transistor is dynamically adjusted, solving the problem of loop instability under high load current and achieving stability and output voltage accuracy across the entire load range.

CN122363443APending Publication Date: 2026-07-10SOUTH CHINA UNIV OF TECH
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-02-26
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

Under high load current conditions, the loop stability of existing LDO circuits is affected by changes in parasitic capacitance and ESR resistance. Traditional compensation methods are difficult to control accurately, resulting in output voltage fluctuations and loop instability.

Method used

A buffer stage is set between the error amplifier and the gate of the power transistor, and an internal ESR compensation module is used to generate a zero point. The secondary pole is canceled by negative feedback, and the gate impedance of the power transistor is dynamically adjusted according to the load current using an adaptive load.

Benefits of technology

It achieves improved loop stability across the entire load range, reduces component specification limitations, improves output voltage accuracy, avoids DC offset, and enhances circuit stability.

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Abstract

This invention discloses an LDO circuit for improving loop stability, relating to electronic circuits, and proposes a solution to address the loop instability problem in existing technologies. An internal ESR compensation module is set up to generate a zero to compensate for the secondary pole of the power transistor's gate, and the output signal is input to the inverting input of the error amplifier through negative feedback. The buffer stage is configured with an adaptive load, which dynamically changes the gate impedance of the power transistor according to the load current. Its advantages include not requiring an external capacitor to provide a specific ESR value, and the output capacitor can be a low-cost, small-size low-ESR ceramic capacitor, reducing component specification limitations. Before the compensation zero appears, negative feedback ensures that the voltage across the added compensation resistor is equal, preventing current flow and thus avoiding DC offset, resulting in a more accurate output voltage. The power transistor gate impedance can be dynamically adjusted according to changes in load current, which is beneficial for achieving loop stability across the entire load range.
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