A start-up circuit for a bandgap reference circuit

Abstract

This invention discloses a startup circuit for a bandgap reference circuit. The startup circuit includes: a first NMOS transistor, the control terminal of which receives the reference voltage generated by the bandgap reference circuit; a pull-up module connected between the power supply voltage and the first line; a Schmitt trigger; a second NMOS transistor; and a charging control module, which conducts when the startup control line is at a low potential pulled down, providing charging current to the first line, and cuts off when the startup control line returns to a high potential. This utilizes a diode structure formed by PMOS transistors in series and a series current mirror to reduce the overall power consumption of the startup circuit to the nA level. Furthermore, through the flexible configuration of the series diodes and the Schmitt trigger shaping circuit, the circuit can reliably operate over a wide power supply voltage range, breaking the degeneracy point and completing the startup of the reference circuit regardless of the power-on time (e.g., from microseconds to milliseconds).

Description

Technical Field

[0001] This invention relates to integrated circuit design, and more particularly to a startup circuit for a bandgap reference circuit. Background Technology

[0002] Bandgap reference circuits are crucial modules in power management integrated circuits, widely used in LDOs (Low Dropout Linear Regulators), DC-DC converters, RF circuits, and high-precision A / D and D / A converters. Their basic function is to provide a reference voltage that is almost independent of the chip's input voltage and temperature for use by other modules. A bandgap reference circuit mainly includes a startup circuit, an operational amplifier circuit, and a core circuit. The startup circuit is a critical component, directly impacting the normal functioning of the reference circuit. Its role is to break the degeneracy point of the original circuit structure, allowing for smooth startup and preventing the circuit from entering a degenerate state, while maintaining the original functionality. Furthermore, the lower the power consumption of the startup circuit, the better. Existing startup circuits suffer from drawbacks such as high power consumption and a limited applicable power supply voltage range, exhibiting certain limitations. The startup circuit structure of this invention features low power consumption and a wide applicable power supply voltage range, overcoming some of these limitations.

[0003] In order to solve the above problems, existing technologies, such as patent technology CN 106055011A, disclose a self-starting power supply circuit, which designs the traditional error amplifier as a bandgap reference operational amplifier and combines the bandgap reference circuit and the error amplifier. On the one hand, it simplifies the circuit, and on the other hand, the power supply of the bandgap reference operational amplifier is its own power supply output, which reduces the use of high-voltage devices and reduces power consumption to a certain extent. However, the power consumption is still in the uA level, and the applicable power supply range is still limited. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a startup circuit for a bandgap reference circuit. The power consumption of the startup circuit structure is reduced to the nA level and it is applicable to a wide range of power supplies. The voltage signal generated by the reference circuit composed of an operational amplifier and a transistor controls the gate of the NMOS transistor to generate a level signal.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] In a first aspect, this application discloses a startup circuit for a bandgap reference circuit, the bandgap reference circuit including an operational amplifier and an output current mirror controlled by the output terminal of the operational amplifier. The startup circuit includes: a first NMOS transistor, the control terminal of which is used to receive a reference voltage generated by the bandgap reference circuit, the first path terminal of the first NMOS transistor being grounded and the second path terminal being connected to a first line; a pull-up module connected between the power supply voltage and the first line, the pull-up module including at least one PMOS transistor in diode configuration for pulling up the potential of the first line to near the power supply voltage; a Schmitt trigger, the input terminal of which is connected to the first line and the output terminal of which is connected to the control terminal of a second NMOS transistor; a second NMOS transistor, the first path terminal of which is grounded and the second path terminal being connected to a startup control line, the startup control line being used to connect to the control terminal of the output current mirror; and a charging control module connected between the power supply voltage and the first line and controlled by the potential of the startup control line, the charging control module being turned on when the startup control line is at a low potential pulled down, providing charging current to the first line, and being turned off when the startup control line returns to a high potential.

[0007] Furthermore, the pull-up module includes multiple PMOS transistors connected in series in the form of diodes, wherein the gate and drain of each PMOS transistor are connected, the source of the previous PMOS transistor is connected to the drain of the next PMOS transistor, the source of the first PMOS transistor is connected to the power supply voltage, and the drain of the last PMOS transistor is connected to the first line.

[0008] Furthermore, the charging control module includes a first charging PMOS transistor and a second charging PMOS transistor connected in series between the power supply voltage and the first line. The source of the first charging PMOS transistor is connected to the power supply voltage, and the drain is connected to the source of the second charging PMOS transistor. The drain of the second charging PMOS transistor is connected to the first line, and the gates of both the first charging PMOS transistor and the second charging PMOS transistor are connected to the startup control line.

[0009] Furthermore, it also includes a capacitor connected between the power supply voltage and the first line.

[0010] Furthermore, the bandgap reference circuit includes: a first bipolar transistor and a second bipolar transistor, whose bases and collectors are connected, and whose emitters are both grounded; a first resistor, one end of which is grounded, and the other end of which is connected to the base of the first bipolar transistor; a second resistor, one end of which is connected to the collector of the second bipolar transistor, and the other end of which is grounded through a fourth resistor, and the connection line between the fourth resistor and the second resistor serves as the positive input terminal of the operational amplifier; the negative input terminal of the operational amplifier is connected to the collector of the first bipolar transistor; the output current mirror includes a first PMOS current mirror transistor, a second PMOS current mirror transistor, and a third PMOS current mirror transistor, whose gates are all connected to the output terminal of the operational amplifier and the startup control circuit, and whose sources are all connected to the power supply voltage; the drain of the first PMOS current mirror transistor is grounded through a third resistor and a fifth resistor connected in series, and the intermediate line between the third resistor and the fifth resistor provides the reference voltage.

[0011] Furthermore, the emitter area of ​​the second bipolar transistor is n times the emitter area of ​​the first bipolar transistor, where n is an integer greater than 1; and the resistance value of the first resistor is equal to the resistance value of the fourth resistor.

[0012] Furthermore, after the bandgap reference circuit outputs the reference voltage, the quiescent current of the startup circuit is no greater than 10nA.

[0013] Furthermore, the number of PMOS transistors in the pull-up module in the form of diodes is configured such that the startup circuit can complete startup within a power supply voltage range of 1.8V to 5.5V.

[0014] Furthermore, the startup circuit also includes an enable control terminal, which is used to control the connection and disconnection of the pull-up module or the charging control module to support externally enabled power-on startup.

[0015] The beneficial effects of this invention are:

[0016] This application embodiment utilizes a diode structure composed of PMOS transistors connected in series and a series current mirror to reduce the overall power consumption of the startup circuit to the nA level; and through the flexible configuration of the diodes connected in series and the Schmitt trigger shaping circuit, the circuit can operate reliably within a wide power supply voltage range. Regardless of the power-on time (e.g., from microseconds to milliseconds), it can break the degeneracy point and complete the startup of the reference circuit. After startup, the startup branch is automatically shut off through reference voltage feedback without affecting the core function. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of a bandgap reference circuit according to some embodiments of this application. Detailed Implementation

[0018] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] According to an embodiment of this application, a startup circuit for a bandgap reference circuit reduces power consumption to the nA level and is applicable to a wide power supply range. A voltage signal generated by a reference circuit composed of an operational amplifier and a bipolar transistor controls the gate of a first NMOS transistor, generating a level signal. By pulling down the gate of a PMOS transistor current mirror, current is injected into the core circuit structure and the operational amplifier circuit structure, thereby breaking the circuit's degeneracy point and generating a reference voltage signal. This voltage signal is then fed back to the startup circuit, turning off the pull-down current mirror circuit within the startup circuit, thus completing the startup of the reference circuit. This startup circuit structure features low power consumption and is applicable to a wide power supply voltage range.

[0020] The bandgap reference circuit will now be described with reference to an embodiment. Figure 1 , Figure 1The circuit on the right side includes a first bipolar transistor Q1, a second bipolar transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, an operational amplifier, and current mirror PMOS transistors: a first PMOS current mirror MP1, a second PMOS current mirror MP2, and a third PMOS current mirror MP3. The base and collector of the first bipolar transistor Q1 are connected together, and its emitter is grounded. Similarly, the base and collector of the second bipolar transistor Q2 are connected together, and its emitter is grounded. One end of the first resistor R1 is grounded, and the other end is connected to the base of the first bipolar transistor Q1. One end of the second resistor R2 is connected to the collector of the second bipolar transistor Q2, and the other end is connected to the fourth resistor R4, the other end of which is grounded. The negative input terminal of the operational amplifier OPA is connected to the collector of the first bipolar transistor Q1. The non-inverting input of the operational amplifier (OPA) is connected between the second resistor R2 and the fourth resistor R4. The output of the operational amplifier is connected to the current mirror PMOS transistors; as mentioned above, the gates of the first PMOS current mirror transistor MP1, the second PMOS current mirror transistor MP2, and the third PMOS current mirror transistor MP3 are connected. The drain of the first PMOS current mirror transistor MP1 is connected to the third resistor R3, and its source is connected to the power supply. One end of the fifth resistor R5 is connected to the third resistor R3, and the other end is grounded. The drain of the second PMOS current mirror transistor MP2 is connected to the non-inverting input of the operational amplifier, and its source is connected to the power supply voltage. The drain of the third PMOS current mirror transistor MP3 is connected to the negative input of the operational amplifier, and its source is connected to the power supply. The reference circuit module constructed by the above structure is mainly used to generate a reference voltage that is independent of the power supply voltage and temperature. In this way, a temperature-independent current can be generated by clamping the operational amplifier, and then mirrored by the current mirror circuit to form a reference voltage independent of the power supply voltage and temperature together with the third resistor R3 and the fifth resistor R5. However, the core circuit structure has a degenerate state, which may lead to abnormal circuit function. Therefore, an additional startup circuit is needed to break the degenerate state and make it work in a normal state.

[0021] In the bandgap reference circuit, two bipolar transistors Q1 and Q2, used to generate a positive temperature coefficient voltage, operate at essentially the same current. The first resistor R1 and the fourth resistor R4 are equal. The emitter area of ​​the second bipolar transistor Q2 is n times the emitter area of ​​the first bipolar transistor Q1, where n is an integer greater than 1. The bases of both the first bipolar transistor Q1 and the second bipolar transistor Q2 are connected to their collectors, forming a diode connection. The emitters of both the first bipolar transistor Q1 and the second bipolar transistor Q2 are connected to ground. This bandgap reference circuit primarily generates two currents: one positively correlated with temperature and the other negatively correlated with temperature. The current flowing through the second resistor R2 has a positive temperature coefficient, while the current flowing through the first resistor R1 has a negative temperature coefficient. By appropriately adjusting the circuit parameters, a current essentially independent of temperature can be generated.

[0022] In this embodiment, Figure 1 The circuit on the right is the core reference generation module, and the part on the left is the startup circuit module.

[0023] The startup circuit includes a first NMOS transistor MN1, whose control terminal (gate) is connected to the reference voltage Vref generated by the core circuit module, its second path terminal (drain) is connected to the first line S2, and its first path terminal (source) is connected to ground. A pull-up module is connected between the power supply voltage and the first line S2, and the pull-up module includes at least one PMOS transistor in the form of a diode connection.

[0024] Specifically, in this embodiment, the pull-up module consists of PMOS transistors MP4, MP5, MP6, and MP7 connected in series as diodes and then connected to the first line S2. The number of diodes connected in series can vary depending on the specific application scenario. The gate and drain of each PMOS transistor are connected, and the source of the preceding PMOS transistor is connected to the drain of the following PMOS transistor: the source of MP4 is connected to the power supply voltage, and its drain is connected to its gate and also to the source of MP5; the drain of MP5 is connected to its gate, forming a diode connected to the source of MP6; the drain of MP6 is connected to its gate, forming a diode connected to the source of MP7; the drain of MP7 is connected to its gate and the drain of the first NMOS transistor MN1, i.e., the first line S2. This pull-up module is used to pull the potential of the first line S2 up to near the power supply voltage.

[0025] Furthermore, the startup circuit also includes a Schmitt trigger ST, whose input is connected to the first line S2 and whose output is connected to the control terminal (gate) of the second NMOS transistor MN2. The first path terminal (source) of the second NMOS transistor MN2 is connected to ground, and the second path terminal (drain) is connected to the startup control line S1. This startup control line S1 is used to connect to the control terminal of the output current mirror, which is the gate of the first PMOS current mirror transistor MP1, the second PMOS current mirror transistor MP2, and the third PMOS current mirror transistor MP3.

[0026] like Figure 1 The startup circuit also includes a charging control module connected between the power supply voltage and the first line S2, and controlled by the potential of the startup control line S1. In this embodiment, the charging control module includes a first charging PMOS transistor MP8 and a second charging PMOS transistor MP9 connected in series between the power supply voltage and the first line S2: the source of the first charging PMOS transistor MP8 is connected to the power supply voltage, and its gate is connected to the startup control line S1; the drain of the first charging PMOS transistor MP8 is connected to the source of the second charging PMOS transistor MP9, and the gate of the second charging PMOS transistor MP9 is also connected to the startup control line S1; the drain of the second charging PMOS transistor MP9 is connected to the first line S2. The charging control module is turned on when the startup control line S1 is at a low potential, providing charging current to the first line S2, and is turned off when the startup control line S1 returns to a high potential.

[0027] In addition, the startup circuit also includes a capacitor C1, which is connected between the power supply voltage and the first line S2.

[0028] It is understandable that the circuit structure described above mainly adjusts the power consumption of the startup circuit and expands the range of the power supply voltage, enabling it to start normally within a wider power supply range and breaking the degeneracy of the circuit. The startup circuit and the bandgap reference circuit are powered by the supply voltage. The gate of the first NMOS transistor MN1 serves as the input terminal of the startup circuit in this embodiment, connected to the output reference voltage Vref of the bandgap core circuit. The startup control line S1 serves as an output terminal of the startup circuit in this embodiment, connected to the output port of the operational amplifier circuit in the bandgap reference core circuit, that is, the gate of the current mirror PMOS transistors MP1, MP2, and MP3.

[0029] Based on the above circuit, when the power supply is turned on, the initial state of the reference voltage Vref is 0, which is fed back to the gate of the first NMOS transistor MN1. At this time, the gate potential is 0, and the first NMOS transistor is in the off state. Due to the pull-up effect of the diodes connected in series (MP4 to MP7) in the pull-up module, the voltage signal of the first line S2 is close to the power supply voltage. After being shaped by a Schmitt trigger, it reaches the output port S3 voltage signal. At this time, the S3 voltage signal is connected to the gate of the second NMOS transistor MN2, and the second NMOS transistor is in the on state, pulling the start-up control line S1 voltage signal to a lower potential. Then, the difference between the gate and source voltages of the current mirror PMOS transistors (i.e., the first, second, and third PMOS current mirror transistors) reaches the turn-on threshold voltage of the PMOS transistors. The current mirrors begin to inject current into the core circuit module and the operational amplifier, breaking the degeneracy state of the core circuit, and the operational amplifier circuit begins to work. Simultaneously, because the second NMOS transistor MN2 turns on, pulling down the voltage of the startup control circuit S1 to a relatively low level, the current mirror formed by the first charging PMOS transistor MP8 and the second charging PMOS transistor MP9 in series in the charging control module conducts, charging capacitor C1. When the voltage across the first resistor R1 and the fourth resistor R4 is greater than the turn-on voltage VBE of the first bipolar transistor Q1 and the second bipolar transistor Q2, Q1 and Q2 can be turned on. Since the first resistor R1 is equal to the fourth resistor R4, due to the virtual short principle at the input of the operational amplifier, the voltage at the positive input terminal is equal to the voltage at the negative input terminal, the current in the first resistor R1 is equal to the current in the second resistor R2, and the emitter area of ​​the second bipolar transistor Q2 is n times that of the first bipolar transistor Q1, a current with a positive temperature coefficient will be generated. The VBE voltage of the bipolar transistor is a negative temperature coefficient voltage. Finally, a temperature-independent reference current is generated through the current mirror of the PMOS transistor, thus obtaining the reference voltage Vref. After the core circuit and operational amplifier are operating normally, the output reference voltage rises from zero to a relatively high voltage. When it reaches a certain voltage, the voltage fed back to the gate of the first NMOS transistor MN1 reaches the turn-on threshold voltage of MN1, and the first NMOS transistor will turn on, pulling down the voltage potential of the first line S2. This voltage signal is then shaped by the Schmitt trigger circuit, resulting in a low-level voltage signal at the output port S3. At this time, the second NMOS transistor MN2 is turned off, ending the pull-down state of the start-up control line S1. The start-up control line S1 voltage signal is generated by the core circuit and operational amplifier themselves. After the start-up circuit breaks the degeneracy state of the core circuit, it is turned off by the feedback signal, without affecting the normal state of the circuit itself. Therefore, by adding a start-up circuit to the bandgap reference circuit, the circuit can move away from the degeneracy point and enter a normal operating state during power-up. The output reference voltage continuously rises until it reaches the set bandgap reference voltage value and stabilizes at this reference voltage.

[0030] Once the circuit is operating normally, the current flowing through the current mirror of the first charging PMOS transistor MP8 and the second charging PMOS transistor MP9 connected in series in the charging control module is very small, ensuring minimal power consumption in the startup circuit. The minimum power consumption of the startup circuit can be around 1nA. The power consumption of the startup circuit is mainly determined by the number of diodes connected in series and the current mirror of the series-connected PMOS transistors. After the bandgap reference circuit outputs the reference voltage, the quiescent current of the startup circuit is no greater than 10nA. For example, by reasonably configuring the number of PMOS transistors connected in diode configuration in the pull-up module, the startup circuit can complete startup within a power supply voltage range of 1.8V to 5.5V. In this embodiment, four PMOS transistors connected in series, namely MP4, MP5, MP6, and MP7, are used, but their number can be increased or decreased according to the power supply voltage range. Similarly, enabling the switch to power on also applies to this startup circuit. The startup circuit also includes an enable control terminal, which is used to control the connection and disconnection of the pull-up module or the charging control module to support external enable power-on startup.

[0031] For a better understanding, please refer to [link / reference]. Figure 1In detail, the startup circuit mainly consists of a first NMOS transistor MN1, a second NMOS transistor MN2, a Schmitt trigger ST, a diode (i.e., a pull-up module) formed by PMOS transistors, a series-connected PMOS transistor (i.e., a charging control module), and a capacitor C1. The circuit connection structure is consistent with the aforementioned. During circuit startup, when the bandgap reference voltage Vref has not yet been properly established, the first NMOS transistor MN1 is in the off state. The voltage at the drain of the first NMOS transistor, i.e., the voltage of the first line S2, will approach the power supply voltage. After being shaped by the Schmitt trigger, the power supply voltage signal will be output. At this time, the second NMOS transistor MN2 turns on, and the voltage signal of the startup control line S1 will be pulled down. Current will be injected into the first resistor R1 and the fourth resistor R4 through the PMOS current mirrors, i.e., the first, second, and third PMOS current mirrors. When the voltage across the first resistor R1 and the fourth resistor R4 is greater than the turn-on voltage VBE of the first bipolar transistor Q1 and the second bipolar transistor Q2, Q1 and Q2 can be turned on. Since the first resistor R1 equals the fourth resistor R4, and due to the virtual short principle at the operational amplifier input, the voltage at the positive input terminal equals the voltage at the negative input terminal, the current in the first resistor R1 equals the current in the second resistor R2. The emitter area of ​​the second bipolar transistor Q2 is n times that of the first bipolar transistor Q1, where n is an integer greater than 1. This results in a current with a positive temperature coefficient. The VBE voltage of the bipolar transistor is a negative temperature coefficient voltage. Finally, the current mirrored by the PMOS transistor becomes a temperature-independent reference voltage. When the reference voltage Vref reaches a predetermined value, voltage feedback turns on the first NMOS transistor MN1. The drain of the first NMOS transistor, i.e., the first circuit S2, is pulled low, and the Schmitt trigger outputs ground potential, turning off the second NMOS transistor MN2 and stopping the pull-down of the startup control circuit S1. At this point, the startup circuit has completed its startup process. This startup circuit's advantages allow for very low power consumption, covering a wide power supply voltage range, and is applicable to different power-up times from microseconds to milliseconds.

[0032] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A startup circuit for a bandgap reference circuit, the bandgap reference circuit comprising an operational amplifier and an output current mirror controlled by the output of the operational amplifier, characterized in that, The startup circuit includes: The first NMOS transistor has a control terminal used to receive the reference voltage generated by the bandgap reference circuit. The first path terminal of the first NMOS transistor is grounded, and the second path terminal is connected to the first line. A pull-up module is connected between the power supply voltage and the first line. The pull-up module includes at least one PMOS transistor in the form of a diode connection, which is used to pull up the potential of the first line to close to the power supply voltage. A Schmitt trigger, whose input is connected to the first line and whose output is connected to the control terminal of the second NMOS transistor; The second NMOS transistor has its first path terminal grounded and its second path terminal connected to a startup control line, which is used to connect to the control terminal of the output current mirror. The charging control module is connected between the power supply voltage and the first line and is controlled by the potential of the start control line. The charging control module is turned on when the start control line is at a low potential and provides charging current to the first line, and is turned off when the start control line returns to a high potential.

2. The startup circuit for a bandgap reference circuit according to claim 1, characterized in that, The pull-up module includes multiple PMOS transistors connected in series in the form of diodes, wherein the gate and drain of each PMOS transistor are connected, the source of the previous PMOS transistor is connected to the drain of the next PMOS transistor, the source of the first PMOS transistor is connected to the power supply voltage, and the drain of the last PMOS transistor is connected to the first line.

3. The startup circuit for a bandgap reference circuit according to claim 1, characterized in that, The charging control module includes a first charging PMOS transistor and a second charging PMOS transistor connected in series between the power supply voltage and the first line. The source of the first charging PMOS transistor is connected to the power supply voltage, and the drain is connected to the source of the second charging PMOS transistor. The drain of the second charging PMOS transistor is connected to the first line, and the gates of both the first charging PMOS transistor and the second charging PMOS transistor are connected to the startup control line.

4. The startup circuit for a bandgap reference circuit according to claim 1, characterized in that... Also includes: A capacitor is connected between the power supply voltage and the first line.

5. The startup circuit for a bandgap reference circuit according to any one of claims 1-4, characterized in that, The bandgap reference circuit includes: The first bipolar transistor and the second bipolar transistor have their bases and collectors connected, and their emitters grounded. The first resistor has one end grounded and the other end connected to the base of the first bipolar transistor; The second resistor has one end connected to the collector of the second bipolar transistor and the other end grounded through the fourth resistor. The connection line between the fourth resistor and the second resistor serves as the non-inverting input terminal of the operational amplifier. The negative inverting input terminal of the operational amplifier is connected to the collector of the first bipolar transistor; The output current mirror includes a first PMOS current mirror transistor, a second PMOS current mirror transistor, and a third PMOS current mirror transistor. Their gates are all connected to the output terminal of the operational amplifier and the startup control circuit, and their sources are all connected to the power supply voltage. The drain of the first PMOS current mirror is grounded through a third resistor and a fifth resistor connected in series, with the reference voltage provided by the intermediate line of the third resistor and the fifth resistor.

6. The startup circuit for a bandgap reference circuit according to claim 5, characterized in that, The emitter area of ​​the second bipolar transistor is n times the emitter area of ​​the first bipolar transistor, where n is an integer greater than 1; and the resistance value of the first resistor is equal to the resistance value of the fourth resistor.

7. The startup circuit for a bandgap reference circuit according to any one of claims 1-4, characterized in that, After the bandgap reference circuit outputs the reference voltage, the quiescent current of the startup circuit is no greater than 10nA.

8. The startup circuit for a bandgap reference circuit according to any one of claims 1-4, characterized in that, The number of PMOS transistors in the pull-up module in diode configuration is configured such that the startup circuit can be started within a power supply voltage range of 1.8V to 5.5V.

9. The startup circuit for a bandgap reference circuit according to any one of claims 1-4, characterized in that, The startup circuit also includes an enable control terminal, which is used to control the connection and disconnection of the pull-up module or the charging control module to support externally enabled power-on startup.

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