An adaptive window-based variable step-size automatic gain control method

Abstract

This invention discloses a variable-step automatic gain control method based on an adaptive window, applicable to signal automatic gain control in data acquisition systems. The method preprocesses the input signal and samples it using an ADC to obtain a digital signal, which is then fed into an FPGA. A zero-crossing detection method based on a hysteresis comparator is used to estimate the signal frequency, and the window length is calculated based on this adaptive amplitude matching. The average signal amplitude within the window is then calculated and compared with a preset automatic gain threshold range. The gain step value is dynamically matched and updated to the variable gain amplifier to complete closed-loop control. Finally, the gain value is used to perform an amplitude inverse calculation to restore the signal. This invention improves the detection accuracy and dynamic response speed of the system over a wide bandwidth and dynamic range, eliminates the hardware resource consumption of floating-point division operations, and accurately outputs a distortion-free original proportional signal stream.

Description

Technical Field

[0001] This invention relates to the field of data acquisition, specifically to a variable step size automatic gain control method based on an adaptive window. Background Technology

[0002] In high-speed data acquisition and digital signal processing systems, the dynamic range of the input signal is large. If the amplitude of the input signal is not dynamically adjusted when the front-end ADC samples the signal, it is easy for small signals to have insufficient measurement accuracy and be submerged in quantization noise, resulting in a decrease in signal-to-noise ratio, or for large signals to exceed the range and cause peak clipping distortion. Therefore, it is necessary to perform automatic gain control on the input signal to ensure that the amplitude of the signal entering the high-speed ADC is always kept within the optimal range.

[0003] Data acquisition systems often rely on fixed-gain analog front-end circuits or purely analog hardware structures for gain control. Although such devices are simple in structure and have a relatively direct response in steady-state continuous wave signal acquisition, they often struggle to simultaneously handle weak and large signals when faced with wide dynamic range signals. Due to the lack of dynamic adaptive conditioning mechanisms, traditional fixed-gain data acquisition systems suffer from signal distortion and poor signal-to-noise ratio when faced with sudden large or weak signals, making it difficult to achieve lossless acquisition across the entire dynamic range.

[0004] Automatic gain control (AGB) first requires detecting the amplitude of the input signal, and then controlling the signal gain based on the amplitude. Traditional gain control includes a gain amplifier and an analog detector. The detector obtains the signal amplitude, and then the corresponding gain control word is calculated and updated in the gain amplifier to complete one gain control cycle. With the development of digital signal processing technology, various signal processing operations in the digital domain and amplitude detection have gradually become the mainstream. In addition, traditional gain control methods usually use fixed step values ​​for adjustment, which makes it difficult for the system to achieve the fastest adjustment when faced with sudden changes in signals, easily causing oscillations in the gain control process or resulting in slow response.

[0005] Therefore, designing a suitable automatic gain control method for data acquisition systems to achieve fast, adaptive, and precise gain control of signals with different frequencies and amplitudes, thereby improving the acquisition accuracy of data acquisition systems across the entire dynamic range and accurately reproducing signal amplitudes, is a crucial technical problem that urgently needs to be solved. Summary of the Invention

[0006] This invention addresses the shortcomings of automatic gain control (AGC) technology by proposing a variable-step AGC method based on an adaptive window. The method first estimates the frequency of the input signal and automatically matches a corresponding amplitude calculation window based on the frequency. Next, it calculates the average amplitude of the signal within this window. Then, it dynamically selects a gain step value based on the threshold range of this amplitude, superimposes it with the current gain to obtain an updated gain value for closed-loop adjustment. Finally, it uses the updated gain value to perform a reverse amplitude reconstruction calculation. This method has promising application prospects and commercial development value.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] S1: The input signal is preprocessed by the front-end hardware circuit, converted from single-ended to differential, and then initially conditioned by the variable gain amplifier. The signal is then sampled by the ADC to obtain a discrete digital signal y(n), and the digital signal is input to the FPGA for subsequent automatic gain control calculation.

[0009] S2: A zero-crossing detection method based on a hysteresis comparator is used to quickly estimate the frequency of y(n) to obtain the estimated frequency f of the current signal. est .

[0010] S3: According to f est Select the amplitude calculation window length N that matches the current signal frequency from the preset window table.

[0011] S4: Within the window length N, perform absolute value calculation on y(n) and calculate the average value to obtain the average amplitude A of the current signal. avg .

[0012] S5: Average amplitude A avg The signal amplitude is compared with a pre-set automatic gain control threshold range, and the corresponding gain control step value ΔG is dynamically matched according to the range in which the amplitude is located, so that the signal amplitude approaches and falls into the stable range.

[0013] S6: Add the current gain value to the gain step value ΔG to obtain the updated target gain control value, and write it into the variable gain amplifier via the SPI bus to complete one closed-loop automatic gain control.

[0014] S7: Before performing digital signal processing on the FPGA, the amplitude of the discrete digital signal y(n) acquired by the ADC needs to be reversed using the updated gain control value to output the original proportional digital signal stream without gain control.

[0015] In step S1, the preprocessing of the front-end hardware specifically includes input impedance matching, passive attenuation network, AC coupling, impedance transformation, and single-ended to differential conversion using a fully differential amplifier. During system reset, a variable gain amplifier provides a fixed initial gain control value, and the input signal frequency range is f. min ~f max The sampling frequency f of the high-speed ADC s It should be configured to be greater than the highest frequency f of the input signal. max twice, that is, f s >2f max .

[0016] In step S2, a zero-crossing detection method based on a hysteresis comparator is used for frequency estimation. First, a positive noise threshold V is set based on the full-scale value of the ADC. H and a negative noise threshold V L These two thresholds are symmetrically distributed around zero, thus creating a hysteresis dead zone in the digital domain, with a positive noise threshold V. H The negative noise threshold V is set to b% of the ADC full-scale value. L Set to -b% of the ADC full-scale value, with b limited to a range of 2~12. Set the current system status identifier as S[n]∈{0,1}. When the sampled value y(n)>V H When this occurs, it indicates that the signal has indeed entered the positive half-cycle, and the system state S[n] flips to 1, when the sampled value y(n) <V L When V indicates that the signal has indeed entered the negative half-cycle, the system state S[n] flips to 0, and when V L <y(n)<V H When the sampled value is within the hysteresis dead zone, the system state S[n] remains unchanged from the previous sampling time. In the FPGA, edge detection logic and a counter are used to monitor the changes in state S[n] in real time, recording the clock interval between an adjacent falling edge changing from 1 to 0 and the next rising edge changing from 0 to 1, denoted as N. CLK The time between a falling edge and a rising edge is one complete half-cycle of the input signal, combined with the system sampling rate f. s The estimated frequency f can be calculated quickly. est The calculation formula is as follows:

[0017]

[0018] In step S3, the preset frequency-window length mapping relationship divides the overall measurement frequency band of the system into multiple sub-frequency band intervals, and the estimated frequency f... estTo reduce the frequency of detection, the selected window length N increases exponentially to ensure that the selected window completely covers at least several half-cycles of the input signal waveform in the time domain, thereby improving detection accuracy. The window length N is strictly limited to 2. m , where m is a positive integer, and the range of values ​​for m is determined by the system's minimum and maximum measurement frequencies.

[0019] In step S4, within the window length N, the absolute values ​​of N signals are taken, and then the average value is calculated by summing them to obtain the average amplitude A. avg The specific formula is as follows:

[0020]

[0021] Since N is 2 m When this step is performed inside the FPGA, the arithmetic operation of dividing by N is equivalently replaced by a pure combinational logic operation of shifting the sum register to the right by m bits, thereby completely eliminating the hardware multiply-accumulator resource consumption and multi-cycle calculation delay caused by the floating-point divider IP core.

[0022] In step S5, the system stability interval is set between a first percentage and a second percentage of the ADC full-scale amplitude. The preset threshold interval is a multi-level asymmetric threshold interval formed by expanding outwards from the stability interval. When the average amplitude A is detected... avg When the signal significantly exceeds the upper threshold range, set the negative gain step value with the largest absolute value to achieve the fastest signal attenuation. When A is detected... avg Within a very small threshold range, a rapid amplification is achieved by setting the positive gain step value with the largest absolute value. When the signal approaches the boundary of the stable range, a smooth fine-tuning is performed by setting the gain step value equal to the minimum gain step value of the variable gain amplifier. avg When the system falls into the stable range, the output gain step value ΔG is set to 0, and the system maintains the current physical gain state unchanged.

[0023] In step S6, the current gain value is added to the gain step value ΔG to obtain the updated target gain control value, which is then written into the variable gain amplifier via the SPI bus to complete one closed-loop automatic gain control. At the same time, gain boundary protection is performed. If the updated target gain control value exceeds the physical boundary of the maximum or minimum gain of the variable gain amplifier, the target gain control value is set to the physical boundary value to prevent overflow.

[0024] In step S7, the formula for amplitude inverse restoration is:

[0025]

[0026] Where, x raw(n) represents the original digital amplitude of the restored distortion-free signal, and G represents the updated target gain control value.

[0027] Compared with the prior art, the present invention has the following beneficial technical effects and significant technical progress:

[0028] High-precision frequency estimation is achieved by effectively filtering out zero-point noise interference through a hysteresis comparator. The amplitude calculation window length is automatically matched according to the frequency to ensure the accuracy of wideband detection. Furthermore, the shift operation saves FPGA underlying hardware resources and reduces computational latency. In addition, the multi-level threshold variable step size control strategy perfectly balances the system's rapid response to sudden signals and smooth fine-tuning when stabilizing, avoiding gain oscillation. Finally, the original proportional signal stream without gain distortion is restored in the digital domain for subsequent digital signal processing, which has high practical value. Attached Figure Description

[0029] Figure 1 This is a system flowchart of the present invention;

[0030] Figure 2 This is a window length division table diagram of the first embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of gain adjustment according to the first embodiment of the present invention;

[0032] Figure 4 This is a comparison table of amplitude range and gain step in the first embodiment of the present invention; Detailed Implementation

[0033] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

[0034] Example 1

[0035] See Figure 1 In this embodiment, the data acquisition system uses a 14-bit wide ADS4249 as the ADC, sampling digital code values ​​ranging from -8192 to 8191, with a sampling frequency f. s The configuration is 200MSPS, the input signal frequency range is 30KHz~30MHz, the variable gain amplifier is selected as LMH6401, the gain adjustment range of this device is -6dB~+26dB, and the fully differential amplifier is selected as LMH5401.

[0036] This embodiment specifically includes the following steps:

[0037] Step 1: After the system starts running, the externally input analog signal x(n) first passes through the input impedance matching circuit to prevent signal reflection, and then enters the ten-fold passive attenuation network to ensure that sudden large signals are limited to the safe input range of the subsequent active devices. The attenuated signal is filtered by the AC coupling circuit to remove DC bias, and then input to the fully differential amplifier LMH5401. This amplifier performs impedance transformation and completes the conversion of the signal from single-ended to differential form. Subsequently, the differential analog signal is input to the variable gain amplifier LMH6401. In the initial state of the system, the FPGA writes the initial gain control word to the gain amplifier through the SPI bus. The signal after being conditioned by the variable gain amplifier is finally sent to the ADC for sampling, and the output digital signal sequence y(n) is sent to the FPGA for automatic gain control algorithm calculation and subsequent digital signal processing.

[0038] Step 2: After the FPGA receives the digital signal y(n) acquired by the ADC, it enters the frequency estimation stage. The frequency estimation is performed using a zero-crossing detection method based on a hysteresis comparator. First, a positive noise threshold V is set based on the full-scale value of the ADC. H and a negative noise threshold V L These two thresholds are symmetrically distributed around zero, thus creating a hysteresis dead zone in the digital domain, with a positive noise threshold V. H The negative noise threshold V is set to 5% of the ADC full-scale value. L Set to -5% of the ADC full-scale value, and set the current system status flag as S[n]∈{0,1}. When the sampled value y(n)>V H When this occurs, it indicates that the signal has indeed entered the positive half-cycle, and the system state S[n] flips to 1, when the sampled value y(n) <V L When V indicates that the signal has indeed entered the negative half-cycle, the system state S[n] flips to 0, and when V L <y(n)<V H When the sampled value is within the hysteresis dead zone, the system state S[n] remains unchanged from the previous sampling time. In the FPGA, edge detection logic and a counter are used to monitor the changes in state S[n] in real time, recording the clock interval between an adjacent falling edge changing from 1 to 0 and the next rising edge changing from 0 to 1, denoted as N. CLK The time between a falling edge and a rising edge is one complete half-cycle of the input signal, combined with the system sampling rate f. s The estimated frequency f can be calculated quickly. est The calculation formula is as follows:

[0039]

[0040] Step 3: After obtaining the estimated frequency, perform amplitude calculation window matching, based on... Figure 2 The window length partitioning table shown adaptively sets the window length N. This table finely divides the frequency band. When the frequency is between 20MHz and 30MHz, the window length N=16, and the calculation time is approximately 0.08μs; when the frequency is between 10MHz and 20MHz, the window length is N=32, and the calculation time is approximately 0.16μs; when the frequency is between 4MHz and 10MHz, the window length is N=64, and the calculation time is approximately 0.32μs; when the frequency is between 2MHz and 4MHz, the window length is N=128, and the calculation time is approximately 0.64μs; when the frequency is between 1MHz and 2MHz, the window length is N=256, and the calculation time is approximately 0.08μs. The computation time is approximately 1.28 μs; when the frequency is between 500 kHz and 1 MHz, the window length is N=512, and the computation time is approximately 2.56 μs; when the frequency is between 200 kHz and 500 kHz, the window length is N=1024, and the computation time is approximately 5.12 μs; when the frequency is between 100 kHz and 200 kHz, the window length is N=2048, and the computation time is approximately 10.24 μs; when the frequency is between 50 kHz and 100 kHz, the window length is N=4096, and the computation time is approximately 20.48 μs; when the frequency is between 30 kHz and 50 kHz, the window length is N=8192, and the computation time is approximately 40.96 μs. As the estimated frequency f... est To reduce the frequency of detection, the selected window length N increases exponentially to ensure that the selected window completely covers at least several half-cycles of the input signal in the time domain, thereby improving detection accuracy. The window length N is strictly limited to 2. m , where m is a positive integer, and the range of values ​​for m is determined by the system's minimum and maximum measurement frequencies.

[0041] Step 4: Within the selected window length N, take the absolute value of each of the N signals, then sum them to calculate the average value, and finally calculate the average amplitude A. avg The specific formula is as follows:

[0042]

[0043] Since N is strictly limited to 2 m When this step is performed inside the FPGA, the arithmetic operation of dividing by N is equivalently replaced by a pure combinational logic operation of shifting the sum register to the right by m bits, thereby completely eliminating the hardware multiply-accumulator resource consumption and multi-cycle calculation delay caused by the floating-point divider IP core.

[0044] Step 5: Calculate the average amplitude A avgCompare with the preset automatic gain control threshold range. Figure 3 This is a schematic diagram of gain adjustment. In this embodiment, the target threshold A is... target The ADC is set to 90% of its full scale, and the surrounding gray shaded area (80%–95% of full scale) is defined as the stable range. If the current average amplitude is within this stable threshold range, no gain adjustment is needed; the gain calculation is skipped, and the next round of ADC acquisition proceeds. Conversely, if the current average amplitude deviates from the stable range, the system will select a gain step ΔG based on the average amplitude. Outside the stable range, there are multiple levels of asymmetric thresholds, i.e., THR. H1 ~THR Hk and THR L1 ~THR Lk In this embodiment, k is set to 7. The control logic will adjust the value based on the degree to which the amplitude deviates from the dead zone. Figure 4 The amplitude range and gain step correspondence table is used to set an appropriate gain step, where the signal peak value A peak The mathematical relationship between the average amplitude and the mean amplitude is as follows:

[0045]

[0046] The only criterion the system relies on is the average amplitude A. avg The signal peak values ​​listed in the table are only theoretical equivalent references based on the characteristics of sinusoidal waves, used to illustrate the rationality of the interval division. When a sudden large input signal exceeds the ADC range, the signal will experience severe clipping distortion, at which point the average amplitude A will be affected. avgThe signal will approach the full-scale extreme value of 8191. The signal peak value in the table specifically refers to the theoretical equivalent peak value of the input signal without clipping, thus reflecting the severity of signal overflow and setting a corresponding large step attenuation. When the input signal experiences severe clipping overflow, and the signal peak value is greater than 81910, the average amplitude range is between 7923 and 8191, and the gain step ΔG is set to -20dB; when the signal peak value is between 40955 and 81910, the average amplitude range is between 7661 and 7923, and the gain step ΔG is set to -15dB; when the signal peak value is between 24573 and 40955, the average amplitude range is between 7307 and 7661, and the gain step ΔG is set to -10dB; when the signal peak value is between 16382 and 24573, the average amplitude range is... Between 6851 and 7307, set the gain step ΔG to -8dB; when the signal peak value is between 12287 and 16382, and the average amplitude range is between 6372 and 6851, set the gain step ΔG to -6dB; when the signal peak value is between 8184 and 12287, and the average amplitude range is between 5210 and 6372, set the gain step ΔG to -2dB; when the signal peak value is between 7781 and 8184, and the average amplitude range is between 4954 and 5210, set the gain step ΔG to -1dB; when the signal peak value is between 6553 and 77... When the signal peak value is between 81 and 4954, the average amplitude range is between 4172 and 4954, which is within the stable range, and the gain step ΔG is set to 0dB; when the signal peak value is between 5734 and 6553, the average amplitude range is between 3650 and 4172, and the gain step ΔG is set to 1dB; when the signal peak value is between 4915 and 5734, the average amplitude range is between 3129 and 3650, and the gain step ΔG is set to 2dB; when the signal peak value is between 3276 and 4915, the average amplitude range is between 2086 and 3129, and the gain step ΔG is set to 4dB. When the signal peak value is between 1638 and 3276, the average amplitude range is between 1043 and 2086, and the gain step ΔG is set to 6dB; when the signal peak value is between 819 and 1638, the average amplitude range is between 521 and 1043, and the gain step ΔG is set to 8dB; when the signal peak value is between 5 and 819, the average amplitude range is between 3 and 521, and the gain step ΔG is set to 10dB; based on the amplitude range, the corresponding gain control step value ΔG is dynamically matched to make the signal amplitude fall into the stable range, while maintaining the current physical gain state unchanged.

[0047] Step 6: After obtaining the current gain step ΔG, execute the normal gain update formula G=G old +ΔG,G oldThe system first sets the current gain value and then performs gain boundary protection checks. If the average amplitude is too large, it checks whether the calculated theoretical target gain has reached the hardware device's minimum value of -6dB. If it has, to prevent control word overflow, the target gain is set to the minimum value of -6dB. If it has not, the calculated gain G is output. If the average amplitude is too small, it checks whether the calculated theoretical target gain has reached the hardware device's maximum value of 26dB. If it has, the target gain is set to the maximum value of 26dB. If it has not, the normal gain G is output. After the gain update is complete, the gain word is written to the internal register of the variable gain amplifier LMH6401 via the SPI bus, completing one closed-loop automatic gain control cycle. Afterward, the system enters a short waiting state, outputs a stable signal, and then continues with a new round of AD sampling.

[0048] Step 7: Because the physical gain of the front end is constantly and dynamically adjusted, the signal entering the ADC is no longer the original true ratio. Therefore, before the FPGA sends data to the back-end module, amplitude inversion restoration is required. Using the current gain value G, the data acquired by the ADC after gain control is inverted and calculated. The formula is as follows:

[0049]

[0050] Where, x raw (n) represents the original digital amplitude of the restored distortion-free signal, and G represents the updated target gain control value.

[0051] This step allows the high-precision digital signal processing module at the back end, which is extremely sensitive to amplitude distortion, to be completely unaware of the complex dynamic changes in the physical gain at the front end. It always captures and processes a raw wide dynamic range digital signal sequence that is perfectly reproduced in terms of proportional structure and achieves an excellent signal-to-noise ratio.

[0052] The method provided in this embodiment, through close collaboration between hardware and software, perfectly balances the requirements for rapid convergence during large-scale signal abrupt changes and the requirements for steady-state measurement accuracy during stable operation, significantly improving the reliability and accuracy of the data acquisition system over a wide dynamic range.

[0053] The above description is merely a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A variable step-size automatic gain control method based on adaptive window, characterized in that, The method includes the following steps: S1: After the input signal is preprocessed by the front-end hardware circuit and the initial amplitude conditioning of the variable gain amplifier, it is input to the high-speed analog-to-digital converter (ADC) for sampling to obtain the discrete digital signal y(n), and the digital signal is input to the field programmable gate array (FPGA) for subsequent automatic gain control calculation. S2: A zero-crossing detection method based on a hysteresis comparator is used to quickly estimate the frequency of y(n) to obtain the estimated frequency f of the current signal. est ; S3: According to f est A calculation window of length N is selected that matches the current signal frequency. Within the window of length N, the absolute value of y(n) is taken and the average value is calculated to obtain the average amplitude A of the current signal. avg ; S4: Average amplitude A avg The signal amplitude is compared with the preset automatic gain control threshold range. Based on the range in which the amplitude is located, the corresponding gain step value ΔG is dynamically matched to make the signal amplitude approach and fall into the preset stable range. The current gain value of the variable gain amplifier is added to the gain step value ΔG to obtain the updated target gain control value. This updated target gain control value is written into the variable gain amplifier through the serial peripheral interface (SPI) bus to complete one closed-loop automatic gain control. Then, the updated target gain control value is used to perform the inverse amplitude restoration operation on the discrete digital signal y(n) acquired by the ADC to output the original proportional digital signal stream without gain control.

2. The variable step size automatic gain control method based on adaptive window according to claim 1, characterized in that, In step S2, the positive noise threshold V is set according to the full-scale value of the ADC. H and negative noise threshold V L Positive noise threshold V H Set to b% of the ADC full-scale value and the negative noise threshold V. L Set to -b% of the ADC full-scale value, where the value of parameter b is limited to 2≤b≤12, and the current system state is set to S[n]∈{0,1}. When the sampled value y(n)>V H When the sampled value y(n) is sampled, the system state S[n] flips to 1. <V L When V, the system state S[n] flips to 0. L <y(n)<V H At this time, the system state S[n] remains unchanged from the state at the previous sampling moment, and the clock interval N between the next falling edge that changes from 1 to 0 and the next rising edge that changes from 0 to 1 is recorded. CLK Combined with ADC sampling rate f s The estimated frequency f is calculated. est The calculation formula is: 。 3. The variable step size automatic gain control method based on adaptive window according to claim 1, characterized in that, In step S3, the preset frequency-window length mapping relationship divides the overall measurement frequency band of the system into multiple sub-frequency band intervals, and the estimated frequency f... est As the value decreases, the selected window length N increases exponentially, and the window length N is strictly limited to 2. m Where m is a positive integer, and the range of m is determined by the system's lowest and highest measurement frequencies. Within the window length N, the absolute value of y(n) is taken and the average value is calculated to obtain the average amplitude A of the current signal. avg The step of calculating the average value is achieved by arithmetically right-shifting the accumulated result by m bits. The specific mathematical formula is as follows: 。 4. The variable step size automatic gain control method based on adaptive window according to claim 1, characterized in that, In step S4, the automatic gain control threshold range includes a stable range, and upper and lower threshold ranges located on either side of the stable range. The stable range is set between a first and second proportion of the ADC full-scale amplitude. A multi-level asymmetric threshold range is formed by extending outwards from the stable range. When the average amplitude A is detected... avg Within the upper threshold range, a negative gain step value is set to achieve signal attenuation. When A is detected... avg Within the lower threshold range, a positive gain step value is set for signal amplification. When the signal approaches the boundary of the stable range, a smooth fine-tuning is performed by setting a value equal to the minimum gain step value of the variable gain amplifier. avg When the signal falls into the stable range, the output gain step value ΔG is set to 0, and the system maintains the current physical gain state. The current gain value of the variable gain amplifier is added to the gain step value ΔG to obtain the updated target gain control value, which is written into the variable gain amplifier via the SPI bus to complete one closed-loop automatic gain control. The gain update requires boundary protection. If the updated target gain control value exceeds the maximum or minimum gain value of the variable gain amplifier, the target gain control value is set to the maximum or minimum gain value. Before digital signal processing at the FPGA, the updated target gain control value is used to perform an inverse amplitude restoration operation on the discrete digital signal y(n) acquired by the ADC, outputting the original proportional digital signal stream without gain control. The restoration operation formula is: ， Where, x raw (n) represents the original digital amplitude of the restored distortion-free signal, and G represents the updated target gain control value.

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