SiC mosfet active driving system and method integrating crosstalk suppression and online gate oxide degradation monitoring

Abstract

This application provides a SiC MOSFET active drive system and method integrating crosstalk suppression and online gate oxide degradation monitoring, addressing the problem that existing SiC MOSFET active drive circuits cannot simultaneously achieve crosstalk suppression and gate oxide degradation monitoring. It includes a crosstalk suppression circuit and an online gate oxide degradation monitoring circuit; the crosstalk suppression circuit comprises a push-pull and charge pump unit and a negative voltage delay and self-attenuation unit; the online gate oxide degradation monitoring circuit includes an analog signal processing unit and a digital logic unit. This application adaptively adjusts the negative turn-off voltage online to suppress positive crosstalk and eliminates the risk of negative crosstalk breakdown through a self-attenuation mechanism. Simultaneously, the monitoring function extracts degradation parameters using the gate voltage discharge characteristics during normal turn-off, exhibiting extremely low temperature dependence and non-intrusive characteristics, without interfering with the normal power transmission of the converter.

Description

Technical Field

[0001] This invention relates to the field of SiC MOSFET gate driving, and in particular to a SiC MOSFET active driving system and method that integrates crosstalk suppression and online gate oxide degradation monitoring. Background Technology

[0002] In bridge arm topologies, the extremely fast switching speed of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) generates extremely high [efficiencies / high performance]. and This can cause displacement current through Miller capacitance, leading to positive or negative crosstalk voltages at the gate and source of the synchronous transistor, posing a risk of false turn-on or gate breakdown. Due to material defects in the SiC manufacturing process, the device is highly susceptible to gate oxide degradation during long-term operation. This can lead to a lower threshold voltage. Drift occurs, making the device more susceptible to being misactivated by positive crosstalk voltage.

[0003] Currently, crosstalk voltage suppression methods can be divided into passive and active methods. Passive methods reduce crosstalk voltage peaks through passive device parameter design (including drive voltage, resistance, etc.) and device selection, minimizing parasitic parameters on the printed circuit board (PCB) layout optimization, and optimal matching of drive and power circuit parameters. However, passive methods may introduce other negative impacts while suppressing crosstalk voltage; for example, increasing the drive resistance may reduce the switching speed of the device when suppressing crosstalk. Furthermore, in the field of electrified transportation, power devices operate under complex conditions and harsh service environments, placing extremely high reliability requirements on SiC MOSFETs. Passive methods may struggle to meet the reliability demands of power devices in electrified transportation. Active methods, building upon passive methods, further suppress crosstalk voltage on the drive side by controlling active devices, thereby improving the reliability of power devices. This method has the advantage of targeted crosstalk voltage suppression without affecting other performance characteristics of the power device. Moreover, active methods can integrate multiple functions such as crosstalk voltage suppression, switching speed improvement, and gate oxide aging monitoring on the drive side, thereby fully utilizing and maximizing the performance of SiC MOSFETs. It is important to note that both passive and active methods require accurate crosstalk models and safe operating domains as theoretical guidance and design foundations. Besides the reliability issues caused by crosstalk voltage, the threshold voltage of SiC MOSFETs also increases due to fabrication process and material defects, resulting in gate oxide aging. Drift makes it more susceptible to crosstalk voltage, further exacerbating the reliability issues of SiC MOSFETs.

[0004] Most existing active gate drivers (AGDs) only focus on generating self-decaying negative voltages to suppress crosstalk, without adequately considering online monitoring of gate oxide aging. Furthermore, closed-loop AGDs are complex and costly, often requiring additional high-bandwidth sampling circuitry and multiple power supply options. Crosstalk voltages significantly reduce the reliability of SiC MOSFET applications. Summary of the Invention

[0005] The purpose of this invention is to provide a SiC MOSFET active driving system and method that integrates crosstalk suppression and online gate oxide degradation monitoring. This addresses the technical problem that existing SiC MOSFET active driving circuits cannot simultaneously achieve crosstalk suppression and gate oxide degradation monitoring.

[0006] First, this application provides a SiC MOSFET active drive system that integrates crosstalk suppression and online gate oxide degradation monitoring, including a crosstalk suppression circuit and an online gate oxide degradation monitoring circuit;

[0007] The crosstalk suppression circuit includes a push-pull and charge pump unit for providing an amplitude-adjustable negative bias voltage to the device during the SiC MOSFET turn-off dead zone, and a negative voltage delay and self-attenuation unit for ensuring that the gate-source capacitance is fully discharged during the maximum duty cycle.

[0008] The gate oxide degradation monitoring circuit includes an analog signal processing unit for acquiring the lower and upper limits of the highly sensitive voltage range of gate oxide aging of SiC MOSFET, and a digital logic unit for accurately characterizing the discharge time of the gate voltage within the range and conditioning the analog value of the pulse signal into a readable time length.

[0009] Optionally, the push-pull and charge pump unit includes a P-type MOS transistor. N-type MOSFET Second diode First resistor and the first capacitor ;

[0010] The P-type MOS transistor The drain and the first resistor One end is connected to the P-type MOS transistor. The source of the N-type MOS transistor The drain and the first capacitor One end is connected to the second diode. The positive terminal and the first capacitor The other end is connected to the second diode. The negative electrode and the driver source of the SiC MOSFET and the N-type MOSFET The source connection.

[0011] Optionally, the negative voltage delay and self-attenuation unit includes a second resistor. Third diode Second capacitor and PNP transistors ;

[0012] The second resistor One end is connected to the gate of the SiC MOSFET, and the second resistor The other end is connected to the third diode The negative terminal of the third diode is connected. Positive electrode, PNP transistor The base and the second capacitor One end is connected to the PNP transistor. The collector and emitter are respectively connected to the second diode. The positive and negative terminals are connected, and the PNP transistor is... emitter and second capacitor The other end is connected to an N-type MOSFET. The source connection.

[0013] Optionally, the gate of the SiC MOSFET is also connected to the output of the driver IC, and one input of the driver IC is connected to the first diode. The positive terminal is connected to the first diode. The negative terminal and the first capacitor The other end is connected, and the other input terminal of the driver IC is connected to the drive power supply. and the first resistor The other end is connected.

[0014] Optionally, the microprocessor (MCU) adjusts the low-level time of the drive pulse in an online closed-loop manner based on the load current to control the first capacitor. The charging voltage, in the first capacitor of the SiC MOSFET turn-off dead zone. Provides an adjustable negative bias voltage for the device;

[0015] The first capacitor satisfy: ;in: For the maximum gate-source charge, For the maximum Miller charge, The first capacitor gate capacitance Maximum voltage during discharge , This is the maximum transient withstand negative voltage for SiC MOSFETs.

[0016] Optionally, after the crosstalk ends, the second capacitor Discharge PNP transistor When the circuit is turned on, the gate-source negative bias voltage is discharged and attenuated to 0V;

[0017] To ensure that the gate-source capacitance is at its maximum duty cycle After the discharge is complete, the second resistor The values ​​of satisfy:

[0018] ;in: Switching cycle of power devices.

[0019] Optionally, the analog signal processing unit includes a voltage inverting amplifier. Comparator Sum comparator ;

[0020] The voltage inverting amplifier The comparator is used to acquire the gate voltage of a SiC MOSFET and invert and scale it to a scaling voltage. and The input terminals of the comparator are respectively input with scaling values ​​for the lower and upper limits of the high-sensitivity voltage range for gate oxide aging. and Used to compare the scaled values ​​of the lower and upper limits with the scaled voltage.

[0021] Optionally, the digital logic unit includes a digital isolator. Digital isolators AND logic XOR gate ;

[0022] The digital isolator and The input terminals are respectively connected to the comparator and The output terminal is connected to the digital isolator. and Output terminal and logic XOR gate Connection, the comparator and The outputs are respectively passed through digital isolators and After isolation processing, a logic signal is obtained, and the logic signal is input into a logic XOR gate. Logic XOR gate The output is a high-level pulse used to characterize the discharge time of the gate voltage within the specified interval.

[0023] Secondly, this application provides a method for monitoring gate oxide degradation in a SiC MOSFET active driving system, characterized in that it monitors the aforementioned SiC MOSFET active driving system with integrated crosstalk suppression and online gate oxide degradation monitoring, and the specific method is as follows:

[0024] S1: Acquire the gate voltage of the SiC MOSFET, invert and scale it to a scaling voltage, compare the scaling voltage with the scaling values ​​of the lower and upper limits of the gate oxide aging high-sensitivity voltage range, and output them.

[0025] S2: After isolating and processing the output of step S1, obtain the logic signal and input the logic signal into the logic XOR gate. It outputs a high-level pulse to characterize the discharge time of the gate voltage within the range;

[0026] S3: The microprocessor acquires the count values ​​of the falling and rising edges of the high-level pulse and calculates the discharge time;

[0027] S4: The gate oxide degradation of SiCMOSFET is judged by the trend of the discharge time at the current moment relative to the discharge time in the initial healthy state.

[0028] Optionally, the specific method in step S4 is as follows:

[0029] Determine whether the discharge time at the current moment is equal to the discharge time in the initial healthy state:

[0030] If they are equal, then the gate oxide of the SiC MOSFET has not degraded;

[0031] If the discharge time at the current moment is shortened, the SiC MOSFET will experience negative bias temperature instability aging, and the shorter the discharge time, the deeper the degradation. If the discharge time at the current moment is extended, the SiC MOSFET will experience positive bias temperature instability aging, and the longer the discharge time, the deeper the degradation.

[0032] Because of the adoption of the above technical solution, the present invention has the following advantages:

[0033] 1. This application uses online adaptive adjustment of the negative turn-off voltage to suppress positive crosstalk and eliminates the risk of negative crosstalk breakdown through a self-attenuation mechanism. Simultaneously, the monitoring function extracts degradation parameters using the gate voltage discharge characteristics during normal turn-off, exhibiting extremely low temperature dependence and non-intrusive characteristics, without interfering with the normal power transmission of the converter.

[0034] 2. This application does not require additional dual-rail isolated power supply and microcontroller hardware costs, and can be seamlessly integrated into existing converter controllers, providing a solution with great engineering application value for the safe operation and health management of wide bandgap semiconductor devices throughout their entire life cycle.

[0035] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0036] The accompanying drawings of this invention are described below.

[0037] Figure 1 This is a circuit diagram of the crosstalk suppression circuit of the present invention.

[0038] Figure 2 This is a circuit diagram of the SiC MOSFET active drive system of the present invention.

[0039] Figure 3 This is a circuit diagram of the half-bridge converter of the present invention.

[0040] Figure 4 This is a timing diagram of the gate drive operation for crosstalk voltage suppression according to the present invention.

[0041] Figure 5 This is a diagram showing the operating modes of the SiC MOSFET active drive system of the present invention.

[0042] Figure 6 The different gate bias voltages of the present invention affect the device The effect diagram of the curve.

[0043] Figure 7 This is a flowchart illustrating the operation of the active gate drive circuit of the present invention during one switching cycle.

[0044] Figure 8 This is a timing diagram for monitoring the gate oxide aging state of the SiC MOSFET of the present invention.

[0045] Figure 9 This is a graph showing the monitoring results of the grid oxide aging state under a 600V bus voltage according to the present invention.

[0046] Figure 10 The graph shows the discharge time measurement results of the present invention at different gate oxide aging levels. Detailed Implementation

[0047] The present invention will be further described below with reference to the accompanying drawings and embodiments. The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. In the description of the embodiments of the present invention, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" or "linked" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0048] Example 1:

[0049] like Figure 1 and Figure 2 The SiC MOSFET active drive system shown includes a crosstalk suppression circuit and an online gate oxide degradation monitoring circuit.

[0050] like Figure 1 As shown, the crosstalk suppression circuit includes features for use in SiC MOSFETs The turn-off dead zone provides the device with an amplitude-adjustable negative bias voltage push-pull and charge pump unit, as well as a negative voltage delay and self-attenuation unit to ensure that the gate-source capacitance is discharged during the maximum duty cycle.

[0051] The push-pull and charge pump unit includes a P-type MOS transistor. N-type MOSFET Second diode First resistor and the first capacitor The P-type MOS transistor The drain and the first resistor One end is connected to the P-type MOS transistor. The source of the N-type MOS transistor The drain and the first capacitor One end is connected to the second diode. The positive terminal and the first capacitor The other end is connected to the second diode. The negative electrode and SiC MOSFET The driver source and N-type MOS transistor The source connection.

[0052] The negative voltage delay and self-attenuation unit includes a second resistor. Third diode Second capacitor and PNP transistors The second resistor One end is connected to the SiC MOSFET The gate connection, the second resistor The other end is connected to the third diode The negative terminal of the third diode is connected. Positive electrode, PNP transistor The base and the second capacitor One end is connected to the PNP transistor. The collector and emitter are respectively connected to the second diode. The positive and negative terminals are connected, and the PNP transistor is... emitter and second capacitor The other end is connected to an N-type MOSFET. The source connection.

[0053] The SiC MOSFET The gate is also connected to the output of the driver IC, and one input of the driver IC is connected to the first diode. The positive terminal is connected to the first diode. The negative terminal and the first capacitor The other end is connected, and the other input terminal of the driver IC is connected to the drive power supply. and the first resistor The other end is connected.

[0054] In this embodiment, the crosstalk suppression circuit realizes the generation, closed-loop adaptive adjustment, and self-attenuation of the negative turn-off voltage. The microprocessor (MCU) adjusts the voltage based on the load current. The low-level time of the drive pulse is adjusted online in a closed loop to control the first capacitor. The charging voltage in SiC MOSFET Turn off the first capacitor of the dead zone Provides an adjustable negative bias voltage for the device; achieves optimal suppression of positive crosstalk across the entire current range.

[0055] exist During the turn-off process, the first capacitor for gate capacitance Discharge and pull it down to To ensure that the gate of the silicon carbide MOSFET is not damaged, It should meet the following requirements:

[0056]

[0057] in, SiC MOSFET The transient maximum withstand negative pressure is selected to achieve good crosstalk suppression and grid oxide aging status monitoring functions. The voltage is 7.5V. During the turn-off process, the total gate charge is:

[0058]

[0059] in, The charge stored in the gate-source capacitance. The charge stored in the Miller capacitor. During the turn-off process, The voltage across the terminals is Descending to Within this interval Integrating yields the maximum gate-source charge:

[0060]

[0061] For Miller capacitance Its voltage self-current during the turn-off process Rise to For this interval Integrating, we obtain the maximum Miller charge as:

[0062]

[0063] To ensure that the turn-off speed of the silicon carbide MOSFET is not affected, the first capacitor... Able to Provide sufficient charge. Assume the first capacitor before turn-off... Voltage Maximum value reached And in achieve hour The voltage should not drop to The following, Represented as:

[0064] .

[0065] In this embodiment, after the crosstalk ends, the second capacitor Discharge causes the PNP transistor to... Turning on the circuit attenuates the gate-source negative bias voltage to 0V to prevent exacerbating negative crosstalk spikes. This ensures the gate-source capacitance operates at its maximum duty cycle. After the discharge is complete, the second resistor The values ​​of satisfy:

[0066] ;

[0067] in: Switching cycle of power devices.

[0068] like Figure 2As shown, the gate oxide degradation monitoring circuit includes an analog signal processing unit for acquiring the lower and upper limits of the highly sensitive voltage range of gate oxide aging of SiC MOSFET, and a digital logic unit for accurately characterizing the discharge time of the gate voltage within the range and conditioning the analog value of the pulse signal into a readable time length.

[0069] The analog signal processing unit includes a voltage inverting amplifier. Comparator Sum comparator The voltage inverting amplifier The comparator is used to acquire the gate voltage of a SiC MOSFET and invert and scale it to a scaling voltage. and The input terminals of the comparator are respectively input with scaling values ​​for the lower and upper limits of the high-sensitivity voltage range for gate oxide aging. and Used to compare the scaled values ​​of the lower and upper limits with the scaled voltage.

[0070] The digital logic unit includes a digital isolator. Digital isolators AND logic XOR gate The digital isolator and The input terminals are respectively connected to the comparator and The output terminal is connected to the digital isolator. and Output terminal and logic XOR gate Connection, the comparator and The outputs are respectively passed through digital isolators and After isolation processing, a logic signal is obtained, and the logic signal is input into a logic XOR gate. Logic XOR gate The output is a high-level pulse used to characterize the discharge time of the gate voltage within the specified interval.

[0071] In this embodiment, in the SiC MOSFET During the gate-source capacitor discharge period, the gate circuit can be approximately equivalent to a first-order RC circuit, and its charge is the integral of the discharge current over time. This is achieved by monitoring the input capacitance. The gate charge can be extracted by measuring the discharge current and discharge time within the specified range. However, direct current measurement requires methods such as current transformers (CTs) or sampling resistors, which have low bandwidth and are somewhat intrusive. Conversely, a window comparator can be used to measure the gate-source capacitance more simply. The method of monitoring the discharge time within a specific range is easy to implement and has low intrusion, as it only requires sampling the gate voltage. Based on the above analysis, this application selects monitoring the discharge time of the gate-source capacitance within a specific range as a characteristic quantity of the gate oxide aging state to realize SiC MOSFETs. Monitoring of the aging status of the grid oxide.

[0072] Example 2:

[0073] like Figure 3 The half-bridge converter shown includes active devices SiC MOSFETs. Passive device SiCMOSFET and bus voltage source , For load inductance The sensory energy within provides a pathway. When the upper tube When turned on, the load inductance current Approximately increasing linearly, when the upper pipe When turned off, the load inductance via the lower pipe Continuous flow. For ease of comparison, in this embodiment, the upper pipe... The driving circuit is a traditional gate drive, while the lower transistor... The proposed active gate drive (AGD) is then used. Figure 3 Medium resistance and The upper pipe is respectively and lower pipe The sum of the drive resistor and the gate internal resistance. The timing diagram of the half-bridge converter is as follows: Figure 4 As shown, the operating modes of the gate drive circuit are as follows: Figure 5 As shown.

[0074] Depend on Figure 4 It can be seen that, compared with the zero-turn-off gate voltage driving method, the negative voltage self-decaying gate driving method proposed in this application can make the lower transistor... gate voltage The voltage does not exceed its threshold voltage, thus avoiding false turn-on phenomena in the device. Due to the use of negative voltage turn-off, the proposed gate drive circuit has a faster turn-off speed and lower turn-off loss than the zero-turn-off gate voltage drive method. When negative crosstalk occurs, compared to the fixed negative turn-off gate voltage drive method, the negative turn-off gate voltage of the proposed gate drive has decayed to 0V, thus protecting the lower transistor. The gate voltage does not exceed its maximum gate withstand negative voltage threshold. Furthermore, the proposed drive circuit can generate a self-decaying negative turn-off gate voltage, eliminating the need for a negative rail power supply and allowing for a small, simple single-rail output. Isolated power supply. The fixed negative turn-off gate voltage drive method requires dual-rail output (…). and Isolated power supplies are bulky and have a more complex structure. Therefore, the proposed negative voltage self-attenuation gate drive circuit has greater advantages and potential in crosstalk suppression than traditional zero-voltage or fixed negative voltage drive methods.

[0075] like Figure 5 As shown in (a), Before the moment, the upper pipe In the dead zone stage, the upper pipe Drain-source voltage Bus voltage Lower pipe Drain-source voltage Approximately 0V, load current via the lower pipe The body diode freewheels. In At the moment, the dead time ends, and the pipe is lowered. drive signal When set high, the subsequent driver chip outputs a positive voltage. Gate-source voltage It rises rapidly. Simultaneously, the second resistor... With the second capacitor Third diode junction capacitance Forming an RC circuit, through For the second capacitor Junction capacitance Charging, second capacitor voltage It gradually increases. The time constant of the RC circuit is:

[0076]

[0077] because ,and Therefore, the second capacitor The charging process has a negligible impact on the turn-on process of the SiCMOSFET. After a period of time, the gate-source voltage... Achieving positive driving pressure And remain stable, lower pipe It operates in the fully conductive state in the third quadrant. Simultaneously, the second capacitor... The voltage across the two ends tends to stabilize. According to the capacitor voltage divider theorem, the voltage across the stabilized capacitor is the voltage across the second capacitor. Represented as:

[0078]

[0079] like Figure 5 As shown in (b), if the second diode Choosing a Schottky diode with a low forward voltage drop (typically 0.23 V) will result in a better driving voltage compared to a higher forward voltage. (Typically above 15V), its on-state voltage drop It can be ignored. Therefore, at the end of this stage, the first capacitor... The potential on the left side is The potential on the right side is 0 V. (From...) Figure 5 (b) It can be seen that the first capacitor The charging process begins at The moment ended At this moment, the management at this stage It is fully powered on, and its gate voltage is stable. Therefore, the first capacitor The charging process will not affect the lower tube. Normal operation.

[0080] like Figure 5 As shown in (c), At that moment, due to the driving signal It was placed on a high level again. Turn off, Activation, first capacitor The potential on the left side is rapidly pulled down to 0 V. Since the capacitor voltage cannot change abruptly, the potential on the right side drops to... First diode Second diode Shutdown due to negative pressure. For example... Figure 5 As shown in (c), the first capacitor The flow path is completely blocked. If the internal leakage current is ignored, then the first capacitor... The potential on the right side is "held" in this mode. .exist At that moment, the pipe was lowered. drive signal Set to low, and working mode III ends.

[0081] like Figure 5 As shown in (d), At any time, the upper management and lower pipe Upon entering the dead zone phase, to avoid straight-through of the bridge arm, the pipe is lowered. Should be on the upper pipe It was shut down before it was opened. Therefore, the pipeline was lowered. The drive signal is first set low, and the driver chip begins to output a low level. For example... Figure 5 As shown in (d), the lower pipe gate capacitance drive resistor First diode First capacitor and N-type MOSFET Forming a discharge circuit The negative charge in the middle is transferred to In the middle, gate voltage Self-driven positive pressure It begins to decrease, diode junction capacitance Second capacitor It decreases synchronously at a lower discharge rate. Because... Positive voltage, PNP transistor Turn off. As negative charges transfer, the first capacitor... The voltage gradually decreased. At time, gate capacitance and the first capacitor The charges between them tend to reach equilibrium, and this operating mode ends. At this moment, the gate capacitance... and the first capacitor The voltage at both ends is That is, gate voltage .

[0082] like Figure 5 As shown in (e), At that moment, the pipe was lowered. Completely shut down, dead zone ended, pipe connected. The driver chip begins to output positive drive voltage. Gate voltage It begins to rise. When Greater than the threshold voltage of SiC MOSFET At that time, the upper pipe When the circuit starts conducting, the load current... From the lower pipe Forced commutation to upper tube .when Rise to Miller voltage At that time, the load current is fully switched to the upper transistor. Its drain-source voltage It drops rapidly. Due to the fixed bus voltage. Lower pipe Drain-source voltage It rises at the same rate. This is due to the high drain-source voltage change rate of SiC MOSFETs. Lower pipe Miller capacitor A large displacement current is generated on it. The current flows into the lower tube. The gate node, so that its gate voltage The voltage is forcibly pulled high, causing a positive crosstalk voltage spike. For example... Figure 5 As shown in (e), the gate voltage is obtained through the proposed gate drive circuit. It was pulled down before crosstalk occurred. It will not be affected by positive crosstalk voltage spikes, thus avoiding false conduction. Therefore, through proper configuration... This ensures that the SiC MOSFET operates within a safe operating range. At any time, the upper management Drain-source voltage The voltage drops to approximately 0 V, at which point the crosstalk process and operating mode V cease. Because... , and There is a large time constant, and the voltage of the second capacitor is high during this stage. Still under positive voltage, PNP transistor Keep it off. Adjust the second capacitor. This phase can be extended or shortened. and The discharge time is adjusted to allow the proposed drive circuit to adapt to different dead time lengths.

[0083] like Figure 5 As shown in (f), At time , the voltage of the second capacitor When the voltage drops below 0V, the PNP transistor The gate current begins to gradually form. The first capacitor... pass and Discharge, first capacitor Right side voltage self Rapidly decreasing. Gate capacitance. Then through the PNP transistor PN junction, , and Discharge, due to its large time constant, The discharge rate is much lower than that of the first capacitor. The discharge rate of the first diode Negative pressure shut-off. At that moment, the first capacitor Discharge ends, voltage of the first capacitor The decay reaches 0 V. At the end of this phase, It has exceeded However, it has not yet decayed to 0V, so adjust the second resistor. Can be extended or shortened The discharge time during this stage.

[0084] like Figure 5As shown in (g), in this stage, the gate capacitance Continue discharging at a lower discharge rate. time, Attenuation to 0 V, PNP transistor Shut down, on the upper pipe Before the drive signal arrives, both the drive circuit and the power circuit are in a steady state. At that moment, this phase ends, and the proposed gate-driven negative turn-off gate voltage self-decay function is fully realized.

[0085] like Figure 5 As shown in (h), At that time, SiC MOSFETs and Entering the dead zone phase, the upper pipe It was shut down first. With... Gate-source voltage Its drain-source voltage gradually decreases. The drain-source voltage rises rapidly. Then it decreases accordingly. Similar to the turn-on process, a high drain-source voltage change rate... In the lower pipe Miller capacitor Displacement current induced on the upper Displacement current in the lower tube A large negative voltage drop is generated across the gate resistor, which in turn leads to a decrease in the gate voltage. The voltage is pulled low, i.e., a negative crosstalk voltage spike. This is due to the lower transistor. The gate voltage decays to 0V during the VI phase of operation, so the proposed active gate drive will not affect the negative crosstalk voltage spike, thus protecting the lower transistor. The gate voltage does not exceed its maximum gate negative voltage tolerance threshold. With the gate-source voltage... The drain-source voltage continues to decrease. Rise to bus voltage Meanwhile, load current Start commutation to lower tube And it freewheels through its body diode. When Drop to threshold voltage Below, upper pipe Fully shut off and load current All converters are directed to the lower tube. The crosstalk process and operating mode VIII end. Afterwards, in At any time, the upper management and lower pipe When the dead time ends, the drive circuit re-enters working mode I.

[0086] Example 3:

[0087] like Figure 7 and 8 The method shown is an active driving method for SiC MOSFETs used to control the half-bridge converter described in Example 2. The specific steps are as follows:

[0088] S1: Acquires the converter output voltage, and the microprocessor (MCU) calculates the voltage across the upper transistor. and lower pipe Duty cycle and Initial control of the converter is performed.

[0089] S2: Real-time acquisition of load current According to the load current Update the lower tube duty cycle ;

[0090] S3: The microprocessor (MCU) performs an update of the duty cycle. ;

[0091] S4: Determine whether gate oxide aging monitoring is required. If required, obtain the discharge time and determine the gate oxide aging. If not required, end the control.

[0092] The specific method for obtaining the discharge time and determining the gate oxide aging in step S4 is as follows:

[0093] S4.1: Data Acquisition Tube The gate voltage is calculated and scaled inverted to a scaling voltage. The scaling voltage is then compared with the scaling values ​​of the lower and upper limits of the gate oxide aging high-sensitivity voltage range and output.

[0094] S4.2: After isolating and processing the output of step S1, obtain the logic signal and input the logic signal into the logic XOR gate. It outputs a high-level pulse to characterize the discharge time of the gate voltage within the range;

[0095] S4.3: The microprocessor acquires the count values ​​of the falling and rising edges of the high-level pulse and calculates the discharge time;

[0096] In this embodiment, the discharge time measured in the microprocessor The microprocessor obtains the falling edge of the high-level pulse. and rising edge The relationship between the count values ​​is as follows:

[0097]

[0098] in, This is the scaling factor updated after module self-calibration. This is the system master clock cycle.

[0099] S4.4: Based on the trend of the discharge time at the current moment relative to the discharge time in the initial healthy state, the lower tube is... The gate oxide degradation is determined by the following method:

[0100] Determine whether the discharge time at the current moment is equal to the discharge time in the initial healthy state:

[0101] If they are equal, then the lower pipe is used. The gate oxide did not degrade;

[0102] If the discharge time at the current moment is shortened, then the lower tube... Negative bias temperature instability aging occurred, and the shorter the discharge time, the deeper the degradation; if the discharge time at the current moment is extended, the lower tube... It exhibits positive bias temperature instability aging, and the longer the discharge time, the deeper the degradation.

[0103] In this embodiment, as Figure 6 As shown in (a), when the SiC MOSFET undergoes PBTI aging, and The shift to the right ultimately results in The curve shifts to the right overall. For example... Figure 6 (b) When SiC MOSFETs undergo NBTI aging, and The final result of shifting to the left is The curve shifts to the left as a whole. The deviation of the curve will result in different amounts of charge stored or released by the gate-source capacitance in that region. Therefore, monitoring... Figure 6 The charge level of the gate-source capacitor in the aging-sensitive region is an effective way to monitor the aging state of the gate oxide.

[0104] like Figure 9 and Figure 10 As shown, Figure 10 In order to be in The graph shows the discharge time measurement results for different gate oxide aging levels within the gate-source voltage range. As the NBTI aging level increases, the SiC MOSFET's... The curve shifts to the left, and its discharge time gradually shortens. Device B underwent accelerated aging for 75 hours, and its discharge time was 9.1 ns shorter than that of the unaged device C. Device A, accelerated aging for 150 hours, had a discharge time 14.1 ns shorter than that of device C. Devices D and E underwent simulated PBTI positive gate bias accelerated aging experiments. After PBTI aging occurred, the SiC MOSFET's... As the curve shifts to the right, the discharge time gradually increases. Devices D and E underwent 75 and 150 hours of PBTI accelerated aging experiments, respectively, and their discharge times were significantly longer than those of device C. Meanwhile, the discharge time of device E was 5.1 ns longer than that of device D, indicating that the discharge time gradually increases with the degree of aging. In actual operation of SiC MOSFETs, the gate of the SiC MOSFET is subjected to alternating PBTI and NBTI stresses, and its aging type depends on the superposition of the two stresses. However, in the driving circuit of this application, once the gate oxide aging of the SiC MOSFET occurs, its CV curve will shift, resulting in different discharge times for the gate capacitance within the characteristic range. The proposed online monitoring circuit for gate oxide aging allows for effective monitoring of the aged gate oxide aging state. For trench gate SiC MOSFETs, the aging trend is roughly the same as that of planar gates, and the proposed method is also universally applicable to the online monitoring of the gate oxide aging state of trench gate SiC MOSFETs.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A SiC MOSFET active drive system integrating crosstalk suppression and online gate oxide degradation monitoring, characterized in that, Includes crosstalk suppression circuitry and online gate oxide degradation monitoring circuitry; The crosstalk suppression circuit includes a push-pull and charge pump unit for providing an amplitude-adjustable negative bias voltage to the device during the SiC MOSFET turn-off dead zone, and a negative voltage delay and self-attenuation unit for ensuring that the gate-source capacitance is fully discharged during the maximum duty cycle. The gate oxide degradation monitoring circuit includes an analog signal processing unit for acquiring the lower and upper limits of the highly sensitive voltage range of gate oxide aging of SiC MOSFET, and a digital logic unit for accurately characterizing the discharge time of the gate voltage within the range and conditioning the analog value of the pulse signal into a readable time length.

2. The SiC MOSFET active drive system integrating crosstalk suppression and online gate oxide degradation monitoring according to claim 1, characterized in that, The push-pull and charge pump unit includes a P-type MOS transistor. N-type MOSFET Second diode First resistor and the first capacitor ; The P-type MOS transistor The drain and the first resistor One end is connected to the P-type MOS transistor. The source of the N-type MOS transistor The drain and the first capacitor One end is connected to the second diode. The positive terminal and the first capacitor The other end is connected to the second diode. The negative electrode and the driver source of the SiC MOSFET and the N-type MOSFET The source connection.

3. The SiC MOSFET active drive system integrating crosstalk suppression and online gate oxide degradation monitoring according to claim 2, characterized in that, The negative voltage delay and self-attenuation unit includes a second resistor. Third diode Second capacitor and PNP transistors ; The second resistor One end is connected to the gate of the SiC MOSFET, and the second resistor The other end is connected to the third diode The negative terminal of the third diode is connected. Positive electrode, PNP transistor The base and the second capacitor One end is connected to the PNP transistor. The collector and emitter are respectively connected to the second diode. The positive and negative terminals are connected, and the PNP transistor is... emitter and second capacitor The other end is connected to an N-type MOSFET. The source connection.

4. The SiC MOSFET active drive system integrating crosstalk suppression and online gate oxide degradation monitoring according to claim 3, characterized in that, The gate of the SiC MOSFET is also connected to the output of the driver IC, and one input of the driver IC is connected to the first diode. The positive terminal is connected to the first diode. The negative terminal and the first capacitor The other end is connected, and the other input terminal of the driver IC is connected to the drive power supply. and the first resistor The other end is connected.

5. The SiC MOSFET active drive system integrating crosstalk suppression and online gate oxide degradation monitoring according to claim 2, characterized in that, The microprocessor (MCU) adjusts the low-level time of the drive pulse in an online closed-loop manner based on the load current to control the first capacitor. The charging voltage, in the first capacitor of the SiC MOSFET turn-off dead zone. Provides an adjustable negative bias voltage for the device; The first capacitor satisfy: ;in: For the maximum gate-source charge, For the maximum Miller charge, The first capacitor gate capacitance Maximum voltage during discharge , This is the maximum transient withstand negative voltage for SiC MOSFETs.

6. The SiC MOSFET active drive system integrating crosstalk suppression and online gate oxide degradation monitoring according to claim 3, characterized in that, After the crosstalk ends, the second capacitor Discharge causes the PNP transistor to... When the circuit is turned on, the gate-source negative bias voltage is discharged and attenuated to 0V; To ensure that the gate-source capacitance is at its maximum duty cycle After the discharge is complete, the second resistor The values ​​of satisfy: ;in: Switching cycle of power devices.

7. The SiC MOSFET active drive system integrating crosstalk suppression and online gate oxide degradation monitoring according to claim 1, characterized in that, The analog signal processing unit includes a voltage inverting amplifier. Comparator Sum comparator ; The voltage inverting amplifier The comparator is used to acquire the gate voltage of a SiC MOSFET and invert and scale it to a scaling voltage. and The input terminals of the comparator are respectively input with scaling values ​​for the lower and upper limits of the high-sensitivity voltage range for gate oxide aging. and Used to compare the scaled values ​​of the lower and upper limits with the scaled voltage.

8. A SiC MOSFET active drive system integrating crosstalk suppression and online gate oxide degradation monitoring according to claim 7, characterized in that, The digital logic unit includes a digital isolator. Digital isolators AND logic XOR gate ; The digital isolator and The input terminals are respectively connected to the comparator and The output terminal is connected to the digital isolator. and Output terminal and logic XOR gate Connection, the comparator and The outputs are respectively passed through digital isolators and After isolation processing, a logic signal is obtained, and the logic signal is input into a logic XOR gate. Logic XOR gate The output is a high-level pulse used to characterize the discharge time of the gate voltage within the specified interval.

9. A method for monitoring gate oxide degradation in a SiC MOSFET active drive system, characterized in that, The method for monitoring the SiC MOSFET active drive system with integrated crosstalk suppression and online gate oxide degradation monitoring as described in any one of claims 1-8 is as follows: S1: Acquire the gate voltage of the SiC MOSFET, invert and scale it to a scaling voltage, compare the scaling voltage with the scaling values ​​of the lower and upper limits of the gate oxide aging high-sensitivity voltage range, and output them. S2: After isolating and processing the output of step S1, obtain the logic signal and input the logic signal into the logic XOR gate. It outputs a high-level pulse to characterize the discharge time of the gate voltage within the range; S3: The microprocessor acquires the count values ​​of the falling and rising edges of the high-level pulse and calculates the discharge time; S4: The gate oxide degradation of SiCMOSFET is judged by the trend of the discharge time at the current moment relative to the discharge time in the initial healthy state.

10. The method for monitoring gate oxide degradation in a SiC MOSFET active drive system according to claim 9, characterized in that, The specific method in step S4 is as follows: Determine whether the discharge time at the current moment is equal to the discharge time in the initial healthy state: If they are equal, then the gate oxide of the SiC MOSFET has not degraded; If the discharge time at the current moment is shortened, the SiC MOSFET will experience negative bias temperature instability aging, and the shorter the discharge time, the deeper the degradation. If the discharge time at the current moment is extended, the SiC MOSFET will experience positive bias temperature instability aging, and the longer the discharge time, the deeper the degradation.

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