A SiC planar mosfet device
By optimizing the structure and process of SiC planar MOSFET devices, the problems of electric field concentration and easy degradation of the gate oxide layer have been solved, resulting in lower on-resistance, switching loss and improved radiation resistance, making them suitable for high-voltage, high-frequency and high-radiation environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JINAN JINGHENG ELECTRONICS
- Filing Date
- 2026-04-27
- Publication Date
- 2026-07-10
AI Technical Summary
Traditional SiC planar MOSFET devices suffer from problems such as electric field concentration, easy degradation of the gate oxide layer, and large gate-drain capacitance under high voltage, high frequency, and high radiation environments, which limit the improvement of their on-resistance, switching loss, and radiation resistance.
The SiC planar MOSFET device with a bottom-up structure includes an N+ substrate layer, an N-doped buffer layer, an N-epitaxial layer, a JFET region, a P-base region, a source N+ region, and a source trench. The P+ region is injected through the source trench and distributed vertically along the channel. Combining dual-channel and single-channel structures, the gate polysilicon and ILD dielectric design are optimized.
Significantly reduces cell size, increases switching speed, reduces switching losses, improves radiation resistance, is compatible with existing planar MOSFET processes, and enhances device conduction characteristics and high-temperature stability.
Smart Images
Figure CN122373410A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of power semiconductor manufacturing technology, specifically relating to a SiC planar MOSFET device. Background Technology
[0002] Against the backdrop of the power electronics industry's continuous development towards high efficiency and high power density, power semiconductor devices, as the core of power electronic devices, directly determine the system's cost and efficiency. Although silicon-based power device technology is quite mature, as applications extend towards high voltage, high frequency, high temperature, and high reliability, the inherent physical limitations of silicon materials, such as their relatively low bandgap and thermal conductivity, make it difficult to meet increasingly stringent requirements. Therefore, wide-bandgap semiconductor materials, represented by silicon carbide (SiC), have gradually become a research hotspot in the field of power devices due to their excellent electrical and thermal properties.
[0003] Silicon carbide (SiC) materials possess advantages such as high thermal conductivity, wide bandgap, and high critical breakdown field strength. This allows SiC MOSFETs to exhibit lower characteristic on-resistance and switching losses at the same voltage level, enabling higher operating frequencies and significantly improved high-temperature stability. Furthermore, the wide bandgap endows SiC devices with excellent radiation resistance, exhibiting lower threshold voltage drift and leakage current increase under high-energy particle radiation environments, making them suitable for high-radiation applications such as aerospace and nuclear energy. At the device structure level, miniaturization of the cell size is one of the key ways to improve power density and frequency characteristics: reducing the cell size effectively reduces the on-resistance per unit area, while shortening the channel length and optimizing switching characteristics, thereby further reducing switching losses.
[0004] SiC planar MOSFETs, as a typical structure of power MOSFETs, have smaller cell sizes compared to laterally diffused MOSFETs (LDMOSFETs), which is beneficial for improving integration density and frequency response. However, the electric field of traditional SiC planar MOSFETs is concentrated in the middle of the gate oxide layer, which can easily lead to reliability issues under long-term stress, and the gate oxide layer degradation is more significant in radiation-resistant environments. At the same time, their gate-drain capacitance is relatively large, limiting further improvements in switching speed. How to achieve superior on-resistance, switching losses, and radiation resistance in SiC MOSFETs remains a technical challenge. Summary of the Invention
[0005] To solve the above problems, the technical solution adopted in this application is: This application provides a SiC planar MOSFET device, comprising, from bottom to top, N... + Substrate layer, N-doped buffer layer, N - Epitaxial layer, JFET region, P-base region, source N-type electrode +Region, source trench; The N-doped buffer layers include a high-doped SiC buffer1 layer, a medium-high doped SiC buffer2 layer, and a low-doped SiC buffer3 layer. The upper surface of the source trench extends to the SiC surface, and the lower surface extends to the N. - The epitaxial layer contains source metal within the source trench, and source P is injected around and at the bottom of the source trench. + The region contains source metal covering the source trench and part of the source N. + The region extends to the source P on the other side. + The edge of the area; Gate oxide layer covers the source N + On the P-base region and JFET region, the gate oxide layer is covered by gate polysilicon, the width of which is smaller than the width of the gate oxide layer, and the source metal and the gate polysilicon are separated by an ILD dielectric.
[0006] Furthermore, the SiC planar MOSFET device has a strip-shaped cell structure, and the source trenches are periodically distributed between the gate polysilicon along a direction perpendicular to the trench. The source metal extends along a direction perpendicular to the channel, and one side is cut off from the source P. + At the edge of the region, the source metal near the P-based region can cover the source P. + The region ends at the source pole N. + district.
[0007] Furthermore, the source trench extends longitudinally to N. - Epitaxial layer, source P-type source trench injection + The region partially overlaps with the P-base region and the source N-base region. + The sections may overlap or not overlap.
[0008] Furthermore, the source P + The region is located at the bottom and around the source trench, and is achieved by changing the injection process conditions. The material deposited inside the source trench is conductive material.
[0009] Furthermore, the source trench is a single-channel cell, and the gate polysilicon covers a portion of the source N-cell. + The cell gate polysilicon interconnects in the non-source trench regions, including the P-base region and part of the JFET region, cover the JFET region, P-base region, and source N-base region. + The region forms a double-channel cell.
[0010] Furthermore, the source P + A JFET region exists between the left boundary of the source region and the right boundary of the P-base region, and the width of the JFET region is 0.5 μm to 4.5 μm; the source P +The right boundary of the region overlaps with the left boundary of the P-based region, with an overlap length of 0.2 μm to 0.5 μm, and the source P... + The right boundary of the region does not cover the source N. + The area or the coverage source N + The left boundary of the region is 0.1μm to 0.2μm.
[0011] Furthermore, the source metal is connected to the source trench and the source P through the source contact hole. + Region and part of the source pole N + Region contact; along the cell direction, the source metal is in the source N + The extension length above the region is greater than that at the source P. + The extension length above the region is used to reduce the source contact resistance.
[0012] Furthermore, the N + The substrate doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 ; The doping concentration of the SiC buffer 1 layer is 4 × 10⁻⁶. 17 cm -3 ~8×10 17 cm -3 ; The doping concentration of the SiC buffer 2 layer is 2×10⁻⁶. 17 cm -3 ~6×10 17 cm -3 ; The doping concentration of the SiC buffer 3 layer is 1×10⁻⁶. 17 cm -3 ~5×10 17 cm -3 ; The N - The doping concentration of the epitaxial layer is 1×10 15 cm -3 ~2×10 16 cm -3 ; The doping concentration of the JFET region is 1×10⁻⁶. 16 cm -3 ~6×10 16 cm -3 ; The surface doping concentration of the P-based region is 5 × 10⁻⁶. 16 cm -3 ~5×10 17 cm -3 ; The source N + The doping concentration of the region is 5×10 18 cm -3 ~5×10 19 cm -3 ; The source P + The doping concentration of the region is 5×10 18 cm -3 ~5×10 19 cm -3 .
[0013] Furthermore, the depth of the source trench exceeds the lower boundary of the P-base region by 0.5 μm to 2 μm; the width of the source trench is 2 μm to 10 μm; the spacing between adjacent source trenches is 5 μm to 10 μm; and the distance between the source trench and the P-base region is 1 μm to 5 μm.
[0014] A second aspect of this application provides a method for fabricating a SiC planar MOSFET device, comprising the following steps: Step S1, provide N + SiC substrate; Step S2, in N + A SiC buffer 1 layer with a high doping concentration, a SiC buffer 2 layer with a medium-high doping concentration, a SiC buffer 3 layer with a low doping concentration, and an N-doped layer are sequentially epitaxially grown on a SiC substrate. - Epitaxial layer; Step S3: Form the JFET region, P-based region, and source N-type region through ion implantation. + district; Step S4: Etch SiC to form source trenches, the lower surface of which extends to N. - Epitaxial layer; Step S5: Form source P by angle injection around and at the bottom of the source trench. + district; Step S6: Perform high-temperature annealing to activate the implanted ions; Step S7: Grow or deposit a gate oxide layer and deposit gate polysilicon; Step S8: Etch the gate polysilicon to completely remove the polysilicon at the source trench, while retaining the polysilicon at the non-source trench. Step S9: Deposit ILD dielectric and etch to form source contact holes and gate contact holes; Step S10: Deposit source metal and gate metal to form ohmic contacts and electrodes.
[0015] Compared with the prior art, the beneficial effects of this application are as follows: 1. This application involves injecting source trenches into P +The region enables shorting of the P-base region, unlike the lateral P-base of a planar MOSFET. + In this method, the source trench and polysilicon are arranged periodically along the vertical direction of the channel to avoid the source metal being too far apart along the channel direction. This method can significantly reduce the cell size.
[0016] 2. In this application, the cells at non-source trench locations adopt a dual-channel path, while the cells at source trench locations adopt a single-channel path. Combined with the JFET region, this can significantly improve the switching speed and reduce switching losses of the device while ensuring conduction characteristics.
[0017] 3. The local source trench structure of this application, combined with the bottom three-layer buffer layer structure, can improve the radiation resistance of the device. The source trench can quickly extract hole carriers generated by single-particle collisions, alleviate the high electric field problem caused by the Kirk effect, and avoid single-particle burn-out and single-ion leakage phenomena.
[0018] 4. The fabrication process of this application is compatible with the existing planar MOSFET process and belongs to planar channel devices. By only adding source trench etching and source P+ region injection process steps, the device's conduction characteristics, switching characteristics and radiation resistance can be improved. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the three-dimensional structure of the source trench of the SiC planar MOSFET device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the three-dimensional structure of the SiC planar MOSFET device at the non-source trench provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the source metal and gate polysilicon layout of two SiC planar MOSFETs provided in the embodiments of the present invention; Figure 4 This is a schematic diagram of the substrate / buffer layer / epipolar layer structure in an embodiment of the present invention; Figure 5 This is the implantation of the JFET region / P base region / N in the embodiments of the present invention. + A schematic diagram of the area's structure; Figure 6 This is a schematic diagram of the structure of the source trench etched at the cross section in an embodiment of the present invention; Figure 7 In this embodiment of the invention, the source P is injected at the cross-section of the source trench. + A schematic diagram of the area's structure; Figure 8 This is a schematic diagram of the gate oxide layer and polysilicon structure at the source trench cross section in an embodiment of the present invention; Figure 9 This is a schematic diagram of the ILD structure at the source trench in an embodiment of the present invention; Figure 10 This is a schematic diagram of the cross-sectional etching of the ILD and the deposition of the source metal structure at the source trench in an embodiment of the present invention; Figure 11 This is a schematic diagram of the gate oxide layer structure at the non-source trench section in an embodiment of the present invention; Figure 12 This is a schematic diagram of the gate polysilicon structure at the non-source trench section in an embodiment of the present invention; Figure 13 This is a schematic diagram of the ILD structure at the non-source trench section in an embodiment of the present invention.
[0020] In the diagram: 1. SiC substrate; 2. High-doped SiC buffer layer 1; 3. Medium-doped SiC buffer layer 2; 4. Low-doped SiC buffer layer 3; 5. Buffer layer; 6. N - Epitaxial layers 6, 7, JFET region, 8, P-base region, 9, source N-type electrode + Area 10, Source Trench 10, 11, Source P + 12. Gate oxide layer, 13. Gate polysilicon, 14. ILD dielectric, 15. Source metal. Detailed Implementation
[0021] The present application will be further described in detail below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present application.
[0022] like Figures 1 to 13 As shown, this application provides a SiC planar MOSFET device, comprising, from bottom to top, N... + Substrate layer 1, N-doped buffer layer 5, N - Epitaxial layer 6, JFET region 7, P-base region 8, source N + Area 9, Source Trench 10; The N-doped buffer layer 5 includes a high-doped SiC buffer 1 layer 2, a medium-high doped SiC buffer 2 layer 3, and a low-doped SiC buffer 3 layer 4. The upper surface of the source trench 10 extends to the SiC surface, and the lower surface extends to the N. - Epitaxial layer 6, source metal 15 is disposed in the source trench 10, and source P is injected around the perimeter and bottom of the source trench 10. + Region 11, in which source metal 15 covers source trench 10 and part of source N. +Section 9, extending to the source P on the other side. + The edge of zone 11; Gate oxide layer 12 covers the source N + On region 9, P-base region 8 and JFET region 7, above the gate oxide layer 12 is a gate polysilicon 13, the width of the gate polysilicon 13 is smaller than the width of the gate oxide layer 12, and the source metal 15 and the gate polysilicon are separated by an ILD dielectric 14.
[0023] The SiC planar MOSFET device has a strip-shaped cell structure, and the source trenches 10 are periodically distributed between the gate polysilicon 13 along a direction perpendicular to the trench. The source metal 15 extends along a direction perpendicular to the channel and is cut off from the source P on one side. + At the edge of region 11, the source metal 15 near the P-based region 8 can cover the source P. + Region 11 and ends at source pole N + District 9.
[0024] The source trench 10 extends longitudinally to N. - Epitaxial layer 6, source P injected in source trench 10 + Region 11 overlaps with part of P-base region 8, and is adjacent to source N. + The nine sections may or may not overlap.
[0025] The source P + Region 11 is located at the bottom and around the source trench 10, and is achieved by changing the injection process conditions. The material deposited inside the source trench 10 is conductive material.
[0026] The source trench 10 is a single-channel cell, and the gate polysilicon 13 covers part of the source N. + Region 9, P-base region 8, and part of JFET region 7 are interconnected with the cell gate polysilicon 13 at the non-source trench, covering JFET region 7, P-base region 8, and source N. + Zone 9 forms a double-channel cell.
[0027] The source P + A JFET region 7 exists between the left boundary of region 11 and the right boundary of the P-base region 8, and the width of the JFET region 7 is 0.5 μm to 4.5 μm; the source P + The right boundary of region 11 overlaps with the left boundary of P-based region 8, with an overlap length of 0.2 μm to 0.5 μm, and the source P... + The right boundary of region 11 does not cover source N. + Zone 9 or covering source pole N + The left boundary of zone 9 is 0.1μm to 0.2μm.
[0028] The source metal 15 is connected to the source trench 10 and the source P through the source contact hole. +Region 11 and part of the source pole N + Region 9 contact; along the cell direction, source metal 15 is at source N + The extension length above region 9 is greater than that at source P. + The extension length above region 11 is used to reduce the source contact resistance.
[0029] The N + The doping concentration of substrate layer 1 is 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 ; The doping concentration of the SiC buffer 1 layer 2 is 4 × 10⁻⁶. 17 cm -3 ~8×10 17 cm -3 ; The doping concentration of the SiC buffer 2 layer 3 is 2×10⁻⁶. 17 cm -3 ~6×10 17 cm -3 ; The doping concentration of the SiC buffer 3 layer 4 is 1×10⁴. 17 cm -3 ~5×10 17 cm -3 ; The N - The doping concentration of epitaxial layer 6 is 1×10⁻⁶. 15 cm -3 ~2×10 16 cm -3 ; The doping concentration of the JFET region 7 is 1×10⁻⁶. 16 cm -3 ~6×10 16 cm -3 ; The surface doping concentration of the P-base region 8 is 5 × 10⁸. 16 cm -3 ~5×10 17 cm -3 ; The source N + The doping concentration in zone 9 is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 ; The source P + The doping concentration of region 11 is 5 × 10⁻⁶. 18 cm -3 ~5×1019 cm -3 .
[0030] The depth of the source trench 10 exceeds the lower boundary of the P-base region 8 by 0.5 μm to 2 μm; the width of the source trench 10 is 2 μm to 10 μm; the spacing between adjacent source trenches is 5 μm to 10 μm; and the distance between the source trench 10 and the P-base region 8 is 1 μm to 5 μm.
[0031] This application also provides a method for fabricating a SiC planar MOSFET device, comprising the following steps: Step S1, provide N + SiC substrate 1; its doping element is N (nitrogen) forming an N-type semiconductor, and the doping concentration can be 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 Its thickness can be selected from 200μm to 350μm.
[0032] Step S2, in N + On a SiC substrate 1, a highly doped SiC buffer 1 layer 2, a medium-to-high doped SiC buffer 2 layer 3, a low doped SiC buffer 3 layer 4, and an N-doped SiC buffer 4 are sequentially epitaxially grown. - Epitaxial layer 6; wherein the thickness of the N-doped buffer layer 5 can be selected from 2μm to 5μm, and an N-type semiconductor is epitaxially mounted on the buffer layer 5 to form an N-type semiconductor. - Epitaxial layer 6, with a doping concentration of 1×10⁶. 15 cm -3 ~2×10 16 cm -3 The thickness of this N-type doped drift region is determined by the device's voltage rating. For example, for a typical 1200V device, N... - The preferred doping concentration of epitaxial layer 6 is 6 × 10⁻⁶. 15 cm -3 The thickness is 9um, such as Figure 4 As shown.
[0033] Step S3: Form JFET region 7, P-based region 8 and source N by ion implantation. + Region 9; Regarding Region 7 of the JFET, the upper half of the semiconductor is N-type doped to form a current-conducting layer, using multiple ion implantations of N (nitrogen) elements, with a doping concentration of 1×10⁻⁶. 16 cm -3 ~6×10 16 cm -3Regarding the P-based region 8, a P-type semiconductor is formed by high-temperature Al (aluminum) ion implantation. Multiple ion implantations are performed, with implantation energies decreasing from high to low, ranging from 100keV to 700keV. The implantation junction depth is 0.5μm to 1μm. The doping concentration at the SiC surface can be selected as 5×10⁻⁶. 16 cm -3 ~5×10 17 cm -3 ,like Figure 5 As shown. Regarding source N + In region 9, relying on the oxide shielding layer formed in step S3 (P-based region 8), an oxide layer is deposited, controlling the sidewall oxide layer thickness to be between 0.2 μm and 0.8 μm to ensure controllable channel length. The oxide layer is anisotropically etched until the SiC interface is exposed at the bottom. The etching rate is strictly controlled to avoid SiC steps. Low-energy, high-temperature, multiple implantation of N (nitrogen) elements is used to form the source N. + Zone 9, doping concentration can be selected at 5×10 18 cm -3 ~5×10 19 cm -3 .
[0034] Step S4: Etch SiC to form source trench 10, the lower surface of the source trench 10 extending to N. - Epitaxial layer 6; Regarding the source trench 10, SiC is etched to form the source trench 10. The left boundary of the source trench 10 is the JFET region 7, and the distance between it and the P-base region 8 is 1μm to 5μm. The right boundary can be selected to be 0.2μm to 0.5μm away from the P-base region 8, or cover the left boundary of the P-base region 8 by 0.1μm to 0.4μm, or cover the N-base region 8. + The left boundary of region 9 is 0.1μm to 0.2μm; the length of the polysilicon trench along the cell direction can be selected from 2μm to 10μm, and the spacing of the source trenches 10 can be selected from 5μm to 10μm; the depth of the source trenches 10 needs to extend beyond the lower boundary of the P-based region 8 by 0.5μm to 2μm, such as... Figure 6 As shown; it should be noted that the width, depth and distribution density of the source trench 10 are not explicitly defined in this embodiment of the application, and can be determined through simulation optimization in practice.
[0035] Step S5: Form source P around and at the bottom of source trench 10 by angle injection. + Section 11; Regarding source P + Zone 11, such as Figure 7 As shown, a highly doped P-type semiconductor is formed by multiple high-temperature implantation of Al (aluminum) ions. The doping concentration can be selected as 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3The implantation sites are located around the perimeter and bottom of the source trench 10. Ion implantation is achieved by adjusting the implantation angle to the sidewalls of the trench. + The left boundary of region 11 needs to be a certain distance from the right boundary of the P-based region 8. The width of the middle JFET region 7 can be selected from 0.5 μm to 4.5 μm. (Source P...) + The right junction of region 11 needs to overlap with the left boundary of the P-base region, ensuring an overlap length of 0.2 μm to 0.5 μm. The N-type source can be optionally covered. + Region 9 has a range of 0.1 μm to 0.2 μm, or may not cover the source N. + District 9.
[0036] Step S6: Perform high-temperature annealing to activate implanted ions; a carbon film sputtering method is used to grow a graphite protective layer at the source trench 10 and the SiC surface, and high-temperature annealing is used to activate the implanted N (nitrogen) ions and Al (aluminum) ions. The annealing temperature can be selected from 1400℃ to 1600℃, and then the residual adhesive on the surface is removed.
[0037] Step S7: Grow or deposit gate oxide layer 12 and deposit gate polysilicon 13; Regarding gate dielectric oxide layer 12, grow an oxide layer with a thickness of 30nm to 60nm on the silicon carbide surface by thermal oxidation or deposition.
[0038] Step S8: Etch the gate polysilicon 13 to completely remove the polysilicon at the source trench 10, while retaining the polysilicon at the non-source trench locations; regarding the gate polysilicon 13, as... Figure 8 As shown, the gate polysilicon is formed using a deposition process. Cells near the source trench are etched with gate polysilicon 13 to ensure that the polysilicon completely covers the channel region formed by the P-base region and that the right boundary covers the source N-base region. + The length of region 9 can be selected from 0.05 μm to 0.1 μm, and the length of the right boundary covering JFET region 7 can be selected from 0.05 μm to 0.1 μm. Furthermore, the distance between the polysilicon and the source P along the channel direction is... + The boundary can be selected from 0.5μm to 1μm. The polysilicon inside the source trench is completely etched away; the polysilicon in the cells near the non-source trench does not need to be etched, and can completely cover the JFET region 7, the P-base region 8, and the source N. + District 9.
[0039] Step S9: Deposit ILD dielectric 14 and etch to form source contact holes and gate contact holes; regarding the deposition of interlayer dielectric ILD14, as follows... Figure 9 As shown, an ILD14 layer is deposited on the surface of SiC as an electrical isolation between the gate polysilicon and the source metal.
[0040] Step S10: Deposit source metal 15 and gate metal to form ohmic contacts and electrodes. Regarding the source metal 15 electrode, dry etching ILD14 forms source metal 15 contact holes. These contact holes completely cover the source trench 10 and also cover the left-side source P. + Region 11 does not exceed the source pole P + The width of region 11 must be half of the source metal contact hole along the cell, and it must not exceed the source P on both sides. + Half of area 11, the right side of the source metal contact hole needs to cover the source N. + Region 9, and the lateral distance between it and the gate polysilicon 13 shall not be less than 0.3μm, to ensure electrical isolation between the gate polysilicon and the metal; sputter nickel metal and perform rapid thermal annealing, the source N inside the source trench 10 + Ti (titanium) / TiN (titanium nitride) / Al (aluminum) metal is deposited above region 9, such as Figure 10 As shown.
[0041] This resulted in two types of cross-sectional structures, such as Figure 1 As shown, the source contact hole shorts the P-base region 8, and the cells at the source trench 10 are single-channel cells. Due to the high concentration of JFET region 7, the decrease in conduction capability caused by the reduction in the number of channels can be significantly alleviated. At the same time, the gate polysilicon 13 covers a small area of JFET region 7, ensuring a small gate-drain coupling capacitance, which can improve the switching speed of the device and reduce switching losses. The cell structure at the non-source contact hole location is as follows. Figure 2 As shown, the upper gate polysilicon 13 completely covers the area, which can significantly reduce the resistance of the gate polysilicon and improve the gate switching speed; the area between the P-base regions 8 is the JFET region 7, which is a dual-channel cell, and the high doping concentration of the JFET region can achieve high conduction capability of the device.
[0042] To further reduce the source contact resistance of the device, this application also proposes another layout structure for the source metal, such as... Figure 3 As shown, the left figure is the layout structure of the aforementioned source metal with a rectangular structure, where the right half of the source metal is completely located at the source P along the cell direction. + Inside region 11, the source N is covered. + The source metal above region 9 also did not exceed source P. + Section 11, this structure has low requirements for linewidth and a high degree of process feasibility; because the source metal is located on the lower right side of the N source. + The structure of region 9 and P-based region 8 can avoid the source metal from reacting with N. - The direct contact of epitaxial layer 6, and the current conduction of the non-dual-channel cell structure, are all conducted from the N+ region to the source metal here. Therefore, the source N... +The larger current in region 9 appears on both sides of the source trench along the cell direction. Therefore, the length of the source metal at this location can be appropriately increased. The right figure shows a cell structure with low source contact resistance. Increasing the length of the source metal on the right half of this location can significantly reduce the on-resistance. After etching the source contact hole, ILD dry etching is required to form the gate contact hole. Ti / TiN / Al is sputtered simultaneously with the source contact hole to form the gate pad and source pad. SiN is deposited and dry etching is used to form the passivation layer. The back side is thinned, the back side metal is evaporated, and laser annealing is used to form the ohmic contact.
[0043] Of course, the above embodiments are not intended to limit this application, and this application is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of this application should also fall within the protection scope of this application.
Claims
1. A SiC planar MOSFET device, characterized in that: Including the following settings from bottom to top: N + Substrate layer (1), N-doped buffer layer (5), N - Epitaxial layer (6), JFET region (7), P-base region (8), source N + Area (9), source trench (10); The N-doped buffer layer (5) includes a high-doped SiC buffer1 layer (2), a medium-high doped SiC buffer2 layer (3), and a low-doped SiC buffer3 layer (4). The upper surface of the source trench (10) extends to the SiC surface, and the lower surface extends to the N. - Epitaxial layer (6), source metal (15) is disposed in the source trench (10), and source P is injected around the periphery and bottom of the source trench (10). + Region (11), in which source metal (15) covers source trench (10) and part of source N + Region (9), extending to the source P on the other side. + The edge of zone (11); Gate oxide layer (12) covers the source N + On region (9), P-base region (8) and JFET region (7), above the gate oxide layer (12) is gate polysilicon (13), the width of gate polysilicon (13) is smaller than the width of gate oxide layer (12), and there is an ILD dielectric (14) between the source metal (15) and the gate polysilicon.
2. The SiC planar MOSFET device according to claim 1, characterized in that: The SiC planar MOSFET device has a strip cell structure, and the source trench (10) is periodically distributed between the gate polysilicon (13) along the direction perpendicular to the trench. The source metal (15) extends along the direction perpendicular to the channel and is cut off at the source P on one side. + The edge of region (11), near the source metal (15) of the P-based region (8), can cover the source P. + Region (11) and terminates at source N. + District (9).
3. A SiC planar MOSFET device according to claim 1, characterized in that: The source trench (10) extends longitudinally to N - Epitaxial layer (6), source P injected into source trench (10) + Region (11) partially overlaps with P-based region (8) and with source N. + Section (9) may or may not overlap.
4. A SiC planar MOSFET device according to claim 1, characterized in that: The source P + Region (11) is located at the bottom and around the source trench (10), and is achieved by changing the injection process conditions. The material deposited inside the source trench (10) is conductive material.
5. A SiC planar MOSFET device according to claim 1, characterized in that: The source trench (10) is a single-channel cell, and the gate polysilicon (13) covers part of the source N. + Region (9), P-base region (8) and part of JFET region (7), cell gate polysilicon (13) interconnects at non-source trench, covering JFET region (7), P-base region (8) and source N + Region (9) forms a double-channel cell.
6. A SiC planar MOSFET device according to claim 1, characterized in that: The source P + A JFET region (7) exists between the left boundary of region (11) and the right boundary of the P-base region (8), the width of which is 0.5 μm to 4.5 μm; the source P + The right boundary of region (11) overlaps with the left boundary of P-based region (8) by a length of 0.2 μm to 0.5 μm, and the source P + The right boundary of region (11) does not cover the source N. + Region (9) or covering source N + The left boundary of region (9) is 0.1μm to 0.2μm.
7. A SiC planar MOSFET device according to claim 1, characterized in that: The source metal (15) is connected to the source trench (10) and the source P through the source contact hole. + Region (11) and part of the source N + Area (9) contact; Along the cell direction, the source metal (15) is at the source N. + The extension length above region (9) is greater than that at source P. + The extension length above region (11) is used to reduce the source contact resistance.
8. A SiC planar MOSFET device according to claim 1, characterized in that: The N + The doping concentration of the substrate layer (1) is 1×10 19 cm -3 ~1×10 20 cm -3 ; The doping concentration of the SiC buffer 1 layer (2) is 4×10⁻⁶. 17 cm -3 ~8×10 17 cm -3 ; The doping concentration of the SiC buffer 2 layer (3) is 2×10⁻⁶. 17 cm -3 ~6×10 17 cm -3 ; The doping concentration of the SiC buffer 3 layer (4) is 1×10⁻⁶. 17 cm -3 ~5×10 17 cm -3 ; The N - The doping concentration of the epitaxial layer (6) is 1×10 15 cm -3 ~2×10 16 cm -3 ; The doping concentration of the JFET region (7) is 1×10⁻⁶. 16 cm -3 ~6×10 16 cm -3 ; The surface doping concentration of the P-base region (8) is 5 × 10⁻⁶. 16 cm -3 ~5×10 17 cm -3 ; The source N + The doping concentration of region (9) is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 ; The source P + The doping concentration of region (11) is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 .
9. A SiC planar MOSFET device according to claim 1, characterized in that: The depth of the source trench (10) exceeds the lower boundary of the P-base region (8) by 0.5 μm to 2 μm; the width of the source trench (10) is 2 μm to 10 μm; the spacing between adjacent source trenches is 5 μm to 10 μm; and the distance between the source trench (10) and the P-base region (8) is 1 μm to 5 μm.
10. A method for fabricating a SiC planar MOSFET device, characterized in that, Includes the following steps: Step S1, provide N + SiC substrate (1); Step S2, in N + A SiC buffer 1 layer (2) with high doping concentration, a SiC buffer 2 layer with medium to high doping concentration, a SiC buffer 3 layer with low doping concentration, and an N-doped SiC buffer 3 layer (4) are epitaxially grown sequentially on a SiC substrate (1). - Epitaxial layer (6); Step S3: Form the JFET region (7), P-based region (8), and source N-type electrode by ion implantation. + District (9); Step S4: Etch SiC to form a source trench (10), the lower surface of which extends to N. - Epitaxial layer (6); Step S5: Form source P by angle injection around and at the bottom of the source trench (10). + District (11); Step S6: Perform high-temperature annealing to activate the implanted ions; Step S7: Grow or deposit a gate oxide layer (12) and deposit gate polysilicon (13). Step S8: Etch the gate polysilicon (13) to completely remove the polysilicon at the source trench (10) and retain the polysilicon at the non-source trench. Step S9: Deposit ILD dielectric (14) and etch to form source contact holes and gate contact holes; Step S10: Deposit source metal (15) and gate metal to form ohmic contact and electrode.