Vertical double-diffused metal oxide semiconductor field effect transistor and method of fabrication
By using a self-built channel diode structure and an optimized VDMOS design, the problem of VDMOS's difficulty in achieving excellent switching performance at low cost was solved. This resulted in optimized reverse freewheeling characteristics and low on-resistance, reducing manufacturing difficulty and cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI JINGYUE ELECTRONICS CO LTD
- Filing Date
- 2026-04-08
- Publication Date
- 2026-07-10
Smart Images
Figure CN122373419A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a vertically double-diffused metal-oxide-semiconductor field-effect transistor and its fabrication method. Background Technology
[0002] In power electronic systems, power semiconductor devices play an increasingly important role in handling high voltage, high current, high frequency signals, and high power management. Vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOS) are widely used in high-voltage devices, such as ventilation ducts, due to their high voltage withstand capability and simple manufacturing process. With the development of ventilation ducts and other related fields, higher performance requirements are being placed on VDMOS, demanding excellent switching performance while maintaining low cost. To meet these requirements, the industry has conducted numerous optimizations of VDMOS. Currently, the mainstream optimization schemes mainly include electron irradiation and platinum diffusion technologies. However, electron irradiation suffers from performance degradation over time, while platinum diffusion technology requires consideration of metal contamination issues and necessitates the establishment of a separate production line, resulting in higher costs. Summary of the Invention
[0003] The purpose of this invention is to overcome the problems of the prior art and provide a vertical double-diffused metal-oxide-semiconductor field-effect transistor and its fabrication method.
[0004] The objective of this invention is achieved through the following technical solution: a vertically double-diffused metal-oxide-semiconductor field-effect transistor, comprising: Substrate; Epitaxial layer, located on the front side of the substrate; The base region is formed in the epitaxial layer; The source region is formed within the base region; Gate polysilicon and source polysilicon are located above the epitaxial layer. The gate polysilicon and source polysilicon form a four-polysilicon structure on the front side of the device. The four-polysilicon structure includes gate polysilicon on both sides and source polysilicon in the middle. The source oxide layer is located beneath the source polycrystalline silicon. The gate oxide layer is located below the gate polysilicon, and the thickness of the source oxide layer is smaller than that of the gate oxide layer. A shielding oxide layer is formed above the epitaxial layer, and the gate polysilicon and source polysilicon are located within the shielding oxide layer; The gate metal is connected to the gate polysilicon through a contact hole; The source metal is connected to the source polysilicon and the source region through contact holes; The back metal layer is located on the back side of the substrate.
[0005] In one embodiment, the gate polysilicon has a U-shaped structure.
[0006] In one embodiment, the width of the gate polysilicon in the Y direction is greater than the width of the polysilicon in the X direction.
[0007] In one embodiment, the polysilicon spacing in the Y direction of the gate polysilicon is twice the smallest cell size.
[0008] In one embodiment, the source polysilicon has an intermittent strip structure.
[0009] In one embodiment, the length and width of the source polysilicon can be adjusted.
[0010] In one embodiment, a JFET region is formed on top of the epitaxial layer, the JFET region being located between two adjacent base regions and below the gate polysilicon.
[0011] It should be further noted that the technical features corresponding to the above examples can be combined or substituted to form new technical solutions.
[0012] This invention also includes a method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor, the method comprising the following steps: An epitaxial layer is grown on the front side of the substrate; Growth source oxide layer; Deposition source polycrystalline silicon; A gate oxide layer is grown, and the thickness of the source oxide layer is smaller than the thickness of the gate oxide layer. A gate polysilicon is deposited, and the gate polysilicon and source polysilicon form a quad polysilicon structure on the front side of the device. The quad polysilicon structure includes gate polysilicon on both sides and source polysilicon in the middle. A second conductivity type implantation is performed to form a base region in the epitaxial layer; Perform first conductivity type injection to form a source region located in the base region; A shielding oxide layer is grown, and the gate polysilicon and source polysilicon are located within the shielding oxide layer; Deposit the front and back metal layers.
[0013] In one embodiment, after growing the epitaxial layer on the front side of the substrate, the method further includes: JFET implantation is performed to form a JFET region on top of the epitaxial layer.
[0014] In one embodiment, the thickness of the source oxide layer is 20nm-100nm, and the thickness of the gate oxide layer is 50nm-1.2μm.
[0015] It should be further noted that the technical features corresponding to the above examples can be combined or replaced to form new technical solutions.
[0016] Compared with the prior art, the beneficial effects of the present invention are: 1. In this invention, the thickness of the source oxide layer beneath the source polysilicon is less than the thickness of the gate oxide layer beneath the gate polysilicon. Under reverse bias, the source polysilicon is connected to a positive potential, inducing a conductive channel beneath it, thus forming a built-in channel diode structure. The forward voltage of this built-in channel diode structure is significantly lower than that of a conventional MOSFET diode, optimizing the device's reverse freewheeling characteristics. Furthermore, compared to traditional VDMOS, this application introduces a built-in channel diode structure in the VDMOS, forming only four polysilicon structures on the front side of the device and ensuring the source oxide layer thickness is less than the gate oxide layer thickness. This requires only an additional source polysilicon mask to achieve the aforementioned device performance improvement, balancing the needs for low cost and superior switching performance.
[0017] 2. The gate polysilicon adopts a U-shaped structure, and the width of the gate polysilicon in the Y direction is greater than the width in the X direction. It can utilize the channel formed by the gate polysilicon in the lateral region (X direction) to compensate for the reduced channel density due to the presence of source polysilicon, thereby optimizing switching performance while maintaining a low on-resistance.
[0018] 3. The Y-direction spacing of the gate polysilicon is twice the smallest cell size, which facilitates matching with the cell layout and reduces manufacturing difficulty.
[0019] 4. Setting the layout of the source polysilicon as an intermittent strip structure can provide a larger process window for contact hole etching and improve manufacturing yield.
[0020] 5. The length and width of the source polysilicon are adjustable. By adjusting the length and width of the source polysilicon and its spacing with the gate polysilicon, the capacitance between the source and gate of the device can be adjusted, thereby adjusting the charging and discharging time of the gate and improving Miller charge and switching time. Attached Figure Description
[0021] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The accompanying drawings are provided to provide a further understanding of the present application and constitute a part of the present application. The same reference numerals are used in these drawings to denote the same or similar parts. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application.
[0022] Figure 1 This is a schematic diagram of the front structure of a device according to an embodiment of the present invention; Figure 2This is a schematic diagram of the side structure of a device provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a device layout provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the device structure for fabricating the JFET region after step S1, as provided in an embodiment of the method of the present invention. Figure 5 This is a schematic diagram of the device structure obtained by step S2 in an embodiment of the method of the present invention; Figure 6 This is a schematic diagram of the device structure obtained by step S3 in an embodiment of the method of the present invention; Figure 7 This is a schematic diagram of the device structure obtained by step S4 in an embodiment of the method of the present invention; Figure 8 This is a schematic diagram of the device structure prepared in step S5 of an embodiment of the method of the present invention; Figure 9 This is a schematic diagram of the device structure obtained by step S6 in an embodiment of the method of the present invention; Figure 10 This is a schematic diagram of the device structure obtained by step S7 in an embodiment of the method of the present invention; Figure 11 This is a schematic diagram of the device structure obtained by step S8 in an embodiment of the method of the present invention; Figure 12 This is a schematic diagram of the device structure prepared in step S9 of an embodiment of the method of the present invention.
[0023] In the figure: 1-substrate; 2-epitaxy layer; 3-base region; 4-source region; 5-gate polysilicon; 6-source polysilicon; 7-shielding oxide layer; 8-front metal layer; 9-back metal layer; 10-JFET region; 11-source oxide layer; 12-gate oxide layer; 13-gate polysilicon mask; 14-source polysilicon mask. Detailed Implementation
[0024] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0025] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0026] In one embodiment, such as Figure 1-2As shown, a vertically double-diffused metal-oxide-semiconductor field-effect transistor includes: Substrate 1 is a semiconductor substrate of the first conductivity type, which can be silicon, silicon nitride, gallium nitride, etc. In this embodiment, an N-type single crystal silicon substrate is preferred.
[0027] Epitaxial layer 2 is located on the front side of the substrate; the epitaxial layer is a first conductivity type epitaxial layer, and in this embodiment it is an N-type epitaxial layer.
[0028] Base region 3, formed in the epitaxial layer, is of the second conductivity type; in this embodiment, it is a P-type base region. It is formed by ion implantation, with boron as the implanting element and an implantation dose of 1 × 10⁻⁶. 13 cm -2 -1×10 14 cm -2 .
[0029] Source region 4, formed within the base region, is a highly doped N-type region of the first conductivity type in this embodiment. Element P is implanted at a dose of 1 × 10⁻⁶. 15 cm -2 -1×10 16 cm -2 .
[0030] Gate polysilicon 5 and source polysilicon 6 are located above the epitaxial layer, forming a quad polysilicon structure on the front side of the device. The quad polysilicon structure includes two gate polysilicon layers on both sides and two source polysilicon layers in the middle. The gate polysilicon layer and the source polysilicon layer are heavily N-type doped, with a thickness of 0.5 μm-1 μm, and can be formed by chemical vapor deposition.
[0031] The source oxide layer 11, located beneath the source polycrystalline silicon, can be silicon dioxide, silicon nitride, or a high-k dielectric (such as aluminum oxide), preferably silicon dioxide. The thickness of the source oxide layer is 20nm-100nm, for example, 20nm, 50nm, 80nm, or 100nm.
[0032] The gate oxide layer 12, located beneath the gate polysilicon, can be silicon dioxide or a high-k dielectric, preferably silicon dioxide. The gate oxide layer thickness is 50 nm to 1.2 μm, for example, 50 nm, 100 nm, 300 nm, 600 nm, 1.0 μm, or 1.2 μm. The source oxide layer is thinner than the gate oxide layer. In the reverse state, the source polysilicon is connected to a positive potential, and a conductive channel is induced beneath the source polysilicon, making its forward voltage much lower than that of a conventional MOSFET diode, thus optimizing the device's reverse freewheeling characteristics.
[0033] A shielding oxide layer 7 is formed above the epitaxial layer and is made of silicon dioxide or silicon nitride. It is a silicon dioxide layer grown by chemical vapor deposition. Preferably, the shielding oxide layer is made of the same material as the source oxide layer and the gate oxide layer. Both the gate polysilicon and the source polysilicon are located inside the shielding oxide layer; that is, the shielding oxide layer covers the sides and top of the gate polysilicon and the source polysilicon and extends to the surface of the epitaxial layer. The shielding oxide layer is used to isolate the front metal layer from the polysilicon and the epitaxial layer to prevent short circuits.
[0034] The gate metal is connected to the gate polysilicon through contact holes. The gate metal is formed using one or more metal materials selected from aluminum, copper, titanium, titanium nitride, and tungsten, and is formed by sputtering or evaporation.
[0035] The source metal is connected to the source polysilicon and the source region through contact holes. The source metal is formed using one or more metal materials selected from aluminum, copper, titanium, titanium nitride, and tungsten, and is formed by sputtering or evaporation. It should be noted that the front metal layer 8 is first formed by sputtering or evaporation, and then the front metal layer is photolithographically and etched to form the gate metal and source metal that are isolated from each other.
[0036] The back metal layer 9 is located on the back side of the substrate. The back metal is formed by a combination of one or more metal materials selected from aluminum, copper, titanium, titanium nitride, and tungsten, and is formed by sputtering or evaporation to form the drain ohmic contact.
[0037] This embodiment forms a quad polysilicon structure on the front side of the device, with the source oxide layer thickness being less than the gate oxide layer thickness. When the source polysilicon is connected to a positive potential in the reverse state, an N-type conductive channel is induced beneath it. This conductive channel, together with the source region and epitaxial layer, constitutes a built-in channel diode. The forward voltage of this diode is significantly lower than that of a conventional VDMOS body diode, thereby significantly optimizing the reverse freewheeling characteristics and reducing reverse recovery losses. Furthermore, compared to traditional VDMOS, this embodiment only requires an additional source polysilicon mask, balancing low cost with superior switching performance.
[0038] In one embodiment, such as Figure 3 As shown, the gate polysilicon mask 13 has a square-shaped structure (rectangular ring structure). The gate polysilicon has the same structure as the gate polysilicon mask, that is, the gate polysilicon is also a closed square shape.
[0039] In one embodiment, such as Figure 3 As shown, the width of the gate polysilicon in the Y direction is greater than that in the X direction. This design results in a longer channel length in the Y direction (vertical) and a shorter channel length in the X direction (lateral). The channel formed by the gate polysilicon in the lateral region (X direction) can compensate for the reduced channel density due to the presence of source polysilicon, thereby optimizing switching performance while maintaining a low on-resistance.
[0040] In one embodiment, the polysilicon spacing in the Y direction of the gate polysilicon is twice the smallest cell size, which facilitates matching with the cell layout, reduces manufacturing difficulty, and improves yield.
[0041] In one embodiment, such as Figure 3 As shown, the source polysilicon mask 14 has an intermittent elongated structure. The source polysilicon itself has the same structure as the source polysilicon mask, that is, the source polysilicon is an intermittent elongated structure, specifically appearing as multiple parallel elongated strips located in the middle region of the four polysilicon structures, with each source polysilicon strip being interrupted. Utilizing this intermittent elongated polysilicon structure provides a larger process window for contact hole etching, improving manufacturing yield.
[0042] In one embodiment, the length and width of the source polysilicon can be adjusted according to application requirements. By adjusting the width of the source polysilicon, the spacing between the source polysilicon and the gate polysilicon can be changed, thereby adjusting the gate-source capacitance of the device, and consequently adjusting the gate charge-discharge time to improve Miller charge and switching time. By adjusting the length of the source polysilicon and the width of the discontinuity interval, the total area of the source polysilicon per unit area can be adjusted. Therefore, this embodiment, by adjusting the length and width of the source polysilicon, can meet the differentiated needs of different application scenarios.
[0043] In one embodiment, a JFET region is formed on top of the epitaxial layer, located between two adjacent base regions and below the gate polysilicon. The JFET region is formed by ion implantation, with phosphorus as the implanting element and an implantation dose of 1×10⁻⁶. 12 cm -2 -1×10 13 cm -2 The injection energy is 50keV-150keV. The doping concentration of the JFET region is higher than that of the epitaxial layer. The JFET region is used to reduce the resistance between adjacent base regions, thereby reducing the on-resistance of the device.
[0044] This invention also includes a method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor, comprising the following steps: S1: An epitaxial layer is grown on the front side of the substrate.
[0045] In step S1, a first conductivity type epitaxial layer, namely an N-type epitaxial layer, is grown on the front side of the substrate by chemical vapor deposition.
[0046] Preferably, such as Figure 4 As shown, after the epitaxial layer 2 is grown on the front side of substrate 1, the following steps are also included: JFET implantation is performed to form a JFET region 10 on top of the epitaxial layer.
[0047] Specifically, the JFET region is formed by ion implantation, with phosphorus as the implanted element and an implantation dose of 1×10⁻⁶. 12 cm -2 -1×10 13 cm -2 The injection energy is 50keV-150keV. This JFET region is located between two adjacent base regions formed in subsequent steps and below the gate polysilicon to reduce on-resistance.
[0048] S2: As Figure 5 As shown, the source oxide layer 11 is grown.
[0049] In step S2, this source oxide layer will subsequently serve as an insulating layer beneath the source polysilicon. It can be silicon dioxide, silicon nitride, or a high-k dielectric (such as aluminum oxide), preferably silicon dioxide. This silicon dioxide layer can be grown by thermal oxidation or chemical vapor deposition. The thickness of the source oxide layer is 20nm-100nm, for example, 20nm, 50nm, 80nm, or 100nm.
[0050] S3: As Figure 6 As shown, the deposition source is polycrystalline silicon 6.
[0051] In step S3, source polysilicon is formed by chemical vapor deposition and N-type doping is performed. Then, photolithography and etching are performed using a source polysilicon mask to form a discontinuous elongated source polysilicon structure. In this embodiment, the thickness of the source polysilicon is 0.5μm-1μm, and can be 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, or 1.0μm.
[0052] S4: As Figure 7 As shown, a gate oxide layer 12 is grown.
[0053] In step S4, the gate oxide layer can be silicon dioxide or a high-k dielectric, preferably silicon dioxide, which can be grown by thermal oxidation or chemical vapor deposition. Preferably, the gate oxide layer and the source oxide layer are made of the same material. Further, before growing the gate oxide layer, the source oxide layer not covered by the source polysilicon is first etched away, and then the gate oxide layer is grown by thermal oxidation with a thickness of 50nm-1.2μm, for example 50nm, 100nm, 300nm, 600nm, 1.0μm or 1.2μm.
[0054] S5: As Figure 8 As shown, a gate polysilicon 5 is deposited.
[0055] In step S5, gate polysilicon is deposited by chemical vapor deposition to a thickness of 0.5 μm-1 μm and then heavily N-type doped. A U-shaped gate polysilicon pattern is formed by photolithography and etching, with the polysilicon width in the Y direction being greater than the width in the X direction. The spacing between the polysilicon cells in the Y direction is twice the smallest cell size. The gate polysilicon and source polysilicon together constitute a quad polysilicon structure.
[0056] S6: As Figure 9 As shown, a second conductivity type implantation is performed to form base region 3.
[0057] In step S6, a second conductivity type (P-type) implantation is performed, with boron as the implanted element and a dose of 1×10⁻⁶. 13 cm -2 -1×10 14 cm -2 After annealing, a P-type base region is formed.
[0058] S7: As Figure 10 As shown, a first conductivity type injection is performed to form source region 4 located in the base region.
[0059] In step S7, the first conductivity type (N-type) implantation is performed, with phosphorus (P) implanted at a dose of 1 × 10⁻⁶. 15 cm -2 -1×10 16 cm -2 After annealing, an N-type source region is formed within the base region.
[0060] S8: As Figure 11 As shown, a shielding oxide layer 7 is grown.
[0061] In step S8, the shielding oxide layer can be silicon dioxide or a high-k dielectric, preferably a silicon dioxide layer. Preferably, the shielding oxide layer is made of the same material as the source oxide layer and the gate oxide layer. Before growing the shielding oxide layer, the gate oxide layer not covered by the gate polysilicon and the source oxide layer not covered by the source polysilicon are etched away. Then, a silicon dioxide layer is grown by chemical vapor deposition, completely encapsulating the gate polysilicon and the source polysilicon. After the shielding oxide layer is grown, P... + Heavy doping implantation, implantation dose of 1×10 15 cm -2 -1×10 16 cm -2 Used to form P at the bottom of subsequent contact holes + The body contact region is used to reduce the contact resistance between the source metal and the base region.
[0062] S9: such as Figure 12 As shown, a front metal layer 8 and a back metal layer 9 are deposited.
[0063] In step S9, each metal layer can be formed using one or more metal materials selected from aluminum, copper, titanium, titanium nitride, and tungsten, through sputtering or evaporation. Preferably, the front metal layer is first formed by sputtering or evaporation, and the gate metal and source metal that are isolated from each other are formed by photolithography and etching. Then, the back metal layer is sputtered to form an ohmic contact.
[0064] The preparation method of this invention only requires adding a source polysilicon mask to the traditional VDMOS process. The remaining process steps are compatible with the traditional process, with limited cost increase, making it suitable for large-scale production.
[0065] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.
Claims
1. A vertically double-diffused metal-oxide-semiconductor field-effect transistor, characterized in that, include: Substrate; Epitaxial layer, located on the front side of the substrate; The base region is formed in the epitaxial layer; The source region is formed within the base region; Gate polysilicon and source polysilicon are located above the epitaxial layer. The gate polysilicon and source polysilicon form a four-polysilicon structure on the front side of the device. The four-polysilicon structure includes gate polysilicon on both sides and source polysilicon in the middle. The source oxide layer is located beneath the source polycrystalline silicon. The gate oxide layer is located below the gate polysilicon, and the thickness of the source oxide layer is smaller than that of the gate oxide layer. A shielding oxide layer is formed above the epitaxial layer, and the gate polysilicon and source polysilicon are located within the shielding oxide layer; The gate metal is connected to the gate polysilicon through a contact hole; The source metal is connected to the source polysilicon and the source region through contact holes; The back metal layer is located on the back side of the substrate.
2. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The gate polysilicon has a square-shaped structure.
3. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The width of the gate polysilicon in the Y direction is greater than the width of the polysilicon in the X direction.
4. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The polysilicon spacing in the Y direction of the gate polysilicon is twice the smallest cell size.
5. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The source polycrystalline silicon has an intermittent elongated structure.
6. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The length and width of the source polycrystalline silicon can be adjusted.
7. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, A JFET region is formed on the top of the epitaxial layer. The JFET region is located between two adjacent base regions and below the gate polysilicon.
8. A method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor, characterized in that, Includes the following steps: An epitaxial layer is grown on the front side of the substrate; Growth source oxide layer; Deposition source polycrystalline silicon; A gate oxide layer is grown, and the thickness of the source oxide layer is smaller than the thickness of the gate oxide layer. A gate polysilicon is deposited, and the gate polysilicon and source polysilicon form a quad polysilicon structure on the front side of the device. The quad polysilicon structure includes gate polysilicon on both sides and source polysilicon in the middle. A second conductivity type implantation is performed to form a base region in the epitaxial layer; Perform first conductivity type injection to form a source region located in the base region; A shielding oxide layer is grown, and the gate polysilicon and source polysilicon are located within the shielding oxide layer; Deposit the front and back metal layers.
9. The method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 8, characterized in that, After growing the epitaxial layer on the front side of the substrate, the following steps are also included: JFET implantation is performed to form a JFET region on top of the epitaxial layer.
10. The method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 8, characterized in that, The thickness of the source oxide layer is 20nm-100nm, and the thickness of the gate oxide layer is 50nm-1.2μm.