Fabrication method of dummy gate process link in semiconductor chip
By forming an ONO layer in the semiconductor chip to control the width of the shallow trench isolation structure and the etching process window, the device short-circuiting problem caused by the increase in shallow trench width is solved, and the device reliability is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU HFC SEMICONDUCTOR CO
- Filing Date
- 2026-04-16
- Publication Date
- 2026-07-10
AI Technical Summary
During the fabrication of semiconductor devices, an increase in the width of shallow trenches can alter the process window, affecting device fabrication and potentially leading to device short circuits and failures.
An ONO layer is formed in the semiconductor chip to cover the upper sidewall of the shallow trench isolation structure. The process window when etching the substrate on both sides of the dummy gate pattern is controlled by controlling the thickness of the ONO layer, which avoids the widening of the shallow trench isolation structure, protects the source/drain regions from being etched simultaneously, and ensures that the metal gate is not lost.
By controlling the process window and protecting the topographic integrity of the source/drain regions, device short circuits are avoided, thus improving device reliability.
Smart Images
Figure CN122373436A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a pseudo-gate process in a semiconductor chip. Background Technology
[0002] In the design phase of semiconductor devices, the device layout is first designed, including the device structure, dimensions, and arrangement. Then, the fabrication phase is carried out according to the design requirements. In the fabrication of one type of semiconductor device, a shallow trench isolation structure is first formed, and then a dummy gate pattern is formed on the shallow trench isolation structure. The dimensions of the shallow trench and dummy gate pattern have been designed in the design phase. However, during fabrication, process variations can cause the width of the shallow trench to increase. This increased width leads to changes in the process window during subsequent fabrication, affecting device fabrication and causing problems such as device short circuits, ultimately leading to device failure. Summary of the Invention
[0003] The purpose of this invention is to provide a method for fabricating a pseudo-gate process in a semiconductor chip, thereby avoiding device failure caused by short circuits and improving device reliability.
[0004] To achieve the above objectives, the present invention provides a method for fabricating a dummy gate process in a semiconductor chip, comprising:
[0005] A substrate is provided in which a plurality of shallow trench isolation structures are formed, and the insulating medium filled in the shallow trench isolation structures is etched back so that the top surface of the insulating medium is lower than the surface of the substrate.
[0006] An ONO layer is formed on the surface of the substrate on which the shallow trench isolation structure is formed;
[0007] A photoresist is formed at the position corresponding to the shallow trench isolation structure of the pseudo gate pattern, and the top silicon oxide layer in the ONO layer that does not cover the photoresist is removed by wet etching.
[0008] After removing the photoresist, the silicon nitride layer and silicon oxide layer in the ONO layer are removed by wet etching;
[0009] A gate oxide layer is formed, and a pseudo gate pattern is formed on the substrate surface on which the gate oxide layer is formed;
[0010] A sidewall layer is formed on the surface of the pseudo-gate pattern, and the sidewall layer is etched without obstruction to form the sidewalls;
[0011] The substrates on both sides of the dummy gate pattern are etched, and the source / drain regions are formed in the substrates corresponding to the etched positions on both sides of the dummy gate pattern by epitaxy.
[0012] After filling the source / drain region with an intermediate dielectric layer, the dummy gate pattern is removed.
[0013] Optionally, the ONO layer may be formed using an ALD process.
[0014] Optionally, the ONO layer covers the upper sidewall of the shallow trench of the shallow trench isolation structure and the isolation medium.
[0015] Optionally, the thickness of the bottom silicon oxide layer, the silicon nitride layer, and the top silicon oxide layer in the ONO layer is 2nm~3nm.
[0016] Optionally, the gate oxide layer may be formed using a thermal oxidation process.
[0017] Optionally, the thickness of the gate oxide layer is 3nm to 5nm.
[0018] Optionally, after etching the substrate on both sides of the dummy gate pattern, the thickness of the substrate between the etching positions on both sides of the dummy gate pattern and the shallow trench isolation structure is 1nm~2nm.
[0019] Optionally, after etching the substrate on both sides of the dummy gate pattern, the etching positions on both sides of the dummy gate pattern are further cleaned.
[0020] Optionally, during wet etching to remove the dummy gate pattern, the remaining bottom silicon oxide layer and silicon nitride layer in the ONO layer prevent the etchant from contacting the source / drain regions during the etching process.
[0021] Optionally, after removing the pseudo-gate pattern, the method further includes:
[0022] A metal oxide layer and a metal gate are formed at the corresponding positions where the dummy gate pattern is removed;
[0023] Contact holes are formed in the intermediate dielectric layer, and the contact holes are cleaned.
[0024] The contact hole is filled with metallic material.
[0025] In the method for fabricating a dummy gate process in a semiconductor chip provided by this invention, an ONO layer is formed on the surface of a substrate with a shallow trench isolation structure, thus avoiding widening of the shallow trench isolation structure. Furthermore, by controlling the thickness of the ONO layer, the process window during etching the substrate on both sides of the dummy gate pattern can be controlled, preventing the complete removal of the substrate on both sides of the shallow trench isolation structure. During the etching process to remove the dummy gate pattern, the portion of the ONO layer retains an isolation function, protecting the source / drain regions from simultaneous etching and maintaining the integrity of their morphology. After the subsequent formation of the metal gate, the portion of the ONO layer isolates the source / drain regions and the metal gate, preventing the loss of the metal gate and short circuits during contact hole formation and cleaning. Therefore, the method of this invention can avoid device failure caused by device short circuits, thereby improving device reliability. Attached Figure Description
[0026] Figures 1-16 This is a schematic diagram of the corresponding steps in a method for fabricating a dummy gate process in a semiconductor chip.
[0027] Figure 17 This is a flowchart illustrating a method for fabricating a pseudo-gate process in a semiconductor chip according to an embodiment of the present invention.
[0028] Figures 18-37 This is a schematic diagram of the corresponding steps in the fabrication method of the pseudo-gate process in a semiconductor chip according to an embodiment of the present invention.
[0029] in, Figures 1-16 The attached figures are labeled as follows:
[0030] 10-Substrate; 12-Pad oxide layer; 14-Pad silicon nitride layer; 20-Shallow trench; 22-Insulating dielectric; 30-Gate oxide layer; 40-Dummy gate pattern; 41-First opening; 42-Second opening; 51-Sidewall layer; 51a-Sidewall; 52-Intermediate dielectric layer; 61-Epiaxial trench; 62-Epiaxial layer; 71-Metal oxide layer; 72-Metal gate; 81-Contact hole; 82-Metal material.
[0031] Figures 18-37 The attached figures are labeled as follows:
[0032] 100 - Substrate; 120 - Pad oxide layer; 140 - Pad silicon nitride layer; 200 - Shallow trench; 220 - Insulating dielectric; 310 - Bottom silicon oxide layer; 320 - Silicon nitride layer; 330 - Top silicon oxide layer; 340 - Gate oxide layer; 400 - Photoresist; 500 - Pseudo-gate pattern; 510 - First opening; 520 - Second opening; 610 - Sidewall layer; 610a - Sidewall; 620 - Intermediate dielectric layer; 710 - Epitaxial trench; 720 - Epitaxial layer; 810 - Metal oxide layer; 820 - Metal gate; 910 - Contact hole; 920 - Metal material. Detailed Implementation
[0033] Figures 1-16 This is a schematic diagram illustrating the corresponding steps in a method for fabricating a dummy gate process in a semiconductor chip. Please refer to it. Figure 1 A substrate 10 is provided, on which a pad oxide layer 12 and a pad silicon nitride layer 14 are formed. Several shallow trenches 20 are formed in the substrate 10 using a photolithography process (only one shallow trench 20 is shown in the figure).
[0034] Please refer to Figure 2 The shallow trench 20 is filled with an insulating medium 22, and the insulating medium 22 covers the silicon nitride layer 14. At this time, the width of the shallow trench 20 is CD1 (initial width).
[0035] Please refer to Figure 3 After filling, the insulating medium 22 in the shallow trench 20 is annealed. Annealing can increase the density of the insulating medium 22, and annealing will increase the width of the shallow trench 20. At this time, the width of the shallow trench 20 is CD2, CD2 > CD1.
[0036] Please refer to Figure 4 The insulating medium 22 on the surface of the substrate 10 and the insulating medium 22 on the upper part of the shallow trench 20 are etched away, and the remaining insulating medium 22 fills the lower part of the shallow trench 20 to form a shallow trench isolation structure; and the pad oxide layer 12 and the pad silicon nitride layer 14 are removed to expose the surface of the substrate 10.
[0037] Please refer to Figure 5 A thermal oxidation process is used to oxidize the substrate 10 to form a gate oxide layer 30 on the surface of the substrate 10 and the upper sidewall of the shallow trench 2. Since the thermal oxidation process will lose part of the substrate 10, the width of the shallow trench 20 (specifically the upper width of the shallow trench 20) will be further increased. At this time, the width of the shallow trench 20 is CD3, CD3 > CD2; the thickness of the gate oxide layer 30 can be 3nm~5nm. After this step, the shallow trench 20 is widened by about 20nm compared with the width design value.
[0038] Please refer to Figure 6 Several pseudo gate patterns 40 are formed. Some pseudo gate patterns 40 fill the upper part of the shallow trench 20 and are higher than the surface of the gate oxide layer 30. Some pseudo gate patterns 40 are located on the gate oxide layer 30. Several pseudo gate patterns 40 have the same height and there is a first opening 41 between adjacent pseudo gate patterns 40. The first opening 41 exposes part of the surface of the gate oxide layer 30. The material of the pseudo gate pattern 40 can be polycrystalline silicon.
[0039] Please refer to Figure 7 The sidewall layer 51 is formed to conformally cover the surface of the pseudo-gate pattern 40 and the surface of the exposed gate oxide layer 30.
[0040] Please refer to Figure 8 Unobstructed etching is performed on the sidewall layer 51 to remove the top surface of the dummy gate pattern 40 and the exposed surface of the gate oxide layer 30, thereby forming a sidewall 51a on the side of the dummy gate pattern 40. Then, the gate oxide layer 30 and the substrate 10 are etched downward along the first opening 41 to form an epitaxial trench 61. Since the width of the shallow trench 20 is widened, the process window becomes smaller during this etching step. Some lateral etching will occur when etching the substrate downward. The smaller process window means that there is no substrate 10 to isolate the epitaxial trench 61 and the dummy gate pattern 40 in the shallow trench 20. The epitaxial trench 61 exposes the gate oxide layer 30 on the upper sidewall of the shallow trench 20.
[0041] Please refer to Figure 9 Before epitaxial growth, the epitaxial groove 61 needs to be cleaned to remove the oxide on the inner wall of the epitaxial groove 61 to avoid affecting the epitaxial growth. The gate oxide layer 30 on the upper sidewall of the shallow trench 20 exposed by the epitaxial groove 61 will be removed during cleaning, exposing the pseudo gate pattern 40 in the shallow trench 20.
[0042] Please refer to Figure 10 An epitaxial layer 62 is epitaxially grown in the epitaxial groove 61 to serve as the source / drain region of the device. The epitaxial layer 62 is in direct contact with the pseudo-gate pattern 40, and the morphology of the epitaxial layer 62 is relatively poor (not shown in the figure). The material of the epitaxial layer 62 can be germanium silicon.
[0043] Please refer to Figure 11 An intermediate dielectric layer 52 is formed by filling the first opening, and the top of the intermediate dielectric layer 52 is flush with the top of the pseudo-gate pattern 40.
[0044] Please refer to Figure 12 The dummy gate pattern 40 is removed by wet etching. Since the epitaxial layer 62 is in contact with the dummy gate pattern 40 and the materials of the epitaxial layer 62 and the dummy gate pattern 40 are similar, the epitaxial layer 62 will be removed simultaneously during wet etching with an etchant (i.e., source / drain region loss). The etchant used for wet etching can be a TMAH solution. After removing the dummy gate pattern 40, a second opening 42 is formed, that is, the area where the dummy gate pattern 40 was originally located is used as the second opening 42.
[0045] Please refer to Figure 13First, a metal oxide layer 71 is formed to cover the sidewalls and bottom of the second opening 42. Since the epitaxial layer is removed, the epitaxial groove 61 is blocked by the sidewall 51a and the intermediate dielectric layer 52, making it difficult to form the metal oxide layer 71 in the epitaxial groove 61. Then, a metal gate 72 is formed to fill the second opening 42. Since the epitaxial layer is removed, part of the metal gate 72 will fill the epitaxial groove 61. However, the epitaxial groove 61 is blocked by the sidewall 51a and the intermediate dielectric layer 52, making it difficult to completely fill the epitaxial groove 61 (the figure shows the general morphology). The material of the metal gate 72 can be titanium nitride, etc.
[0046] Please refer to Figure 14 The intermediate dielectric layer 52 is etched to form a contact hole 81, which penetrates the intermediate dielectric layer 52.
[0047] Please refer to Figure 15 After forming contact hole 81, contact hole 81 is cleaned. The cleaning agent can be a mixture of dilute sulfuric acid and hydrogen peroxide or hydrofluoric acid solution. During cleaning, the metal gate 72 in the epitaxial groove 61 will be removed. An interlayer dielectric layer (not shown in the figure) is formed on the intermediate dielectric layer 52 and the metal gate 72. Contact hole 81 is formed through the interlayer dielectric layer. While retaining the interlayer dielectric layer, contact hole 81 is cleaned. Normally, the metal gate 72 is covered with the interlayer dielectric layer, and the cleaning agent will not contact the metal gate 72 during cleaning. However, since the metal gate 72 above the shallow trench 20 is connected to the metal gate 72 in the epitaxial groove 61, the metal gate 72 above the shallow trench 20 may be removed simultaneously, resulting in the loss of metal gate 72.
[0048] Please refer to Figure 16 The contact hole 81 is filled with metal material 82, which fills the epitaxial groove 61 and extends to the insulating medium 22 in the shallow trench 20. Due to the loss of the metal gate 72, a short circuit will occur in the device, leading to device failure. Therefore, the fabrication method needs to be improved to ensure device reliability.
[0049] Based on this, in the method for fabricating a dummy gate process in a semiconductor chip provided by this invention, an ONO layer is formed on the surface of a substrate with a shallow trench isolation structure, thus avoiding widening of the shallow trench isolation structure. Furthermore, by controlling the thickness of the ONO layer, the process window during etching the substrate on both sides of the dummy gate pattern can be controlled, preventing the complete removal of the substrate on both sides of the shallow trench isolation structure. During the etching process of removing the dummy gate pattern, the portion of the ONO layer retains an isolation function, protecting the source / drain regions from simultaneous etching and maintaining the integrity of their morphology. After the subsequent formation of the metal gate, the portion of the ONO layer isolates the source / drain regions and the metal gate, preventing the loss of the metal gate and short circuits during contact hole formation and cleaning. Therefore, the method of this invention can avoid device failure caused by device short circuits, thereby improving device reliability.
[0050] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. The accompanying drawings are all in a very simplified form and are not drawn to scale, only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structures; in particular, different proportions are sometimes used because different drawings need to show different focuses.
[0051] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0052] In the description of this application, it should be understood that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are used only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the equipment or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0053] Furthermore, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.
[0054] Figure 17 This is a flowchart illustrating the fabrication method of the dummy gate process in a semiconductor chip provided in this embodiment. Please refer to... Figure 17 This invention provides a method for fabricating a pseudo-gate process in a semiconductor chip, comprising:
[0055] Step S1: Provide a substrate in which several shallow trench isolation structures are formed, and etch back the insulating medium filling the shallow trench isolation structures so that the top surface of the insulating medium is lower than the surface of the substrate.
[0056] Step S2: Form an ONO layer on the surface of the substrate with the shallow trench isolation structure;
[0057] Step S3: Form photoresist at the position corresponding to the shallow trench isolation structure of the pseudo gate pattern, and remove the top silicon oxide layer in the ONO layer that does not cover the photoresist by wet etching.
[0058] Step S4: After removing the photoresist, wet etching is used to remove the silicon nitride layer and silicon oxide layer in the ONO layer;
[0059] Step S5: Form a gate oxide layer and form a pseudo gate pattern on the substrate surface on which the gate oxide layer is formed;
[0060] Step S6: Form a sidewall layer on the surface of the pseudo-gate pattern, and perform unobstructed etching on the sidewall layer to form the sidewalls;
[0061] Step S7: Etch the substrate on both sides of the dummy gate pattern, and form the source / drain regions in the substrate corresponding to the etching positions on both sides of the dummy gate pattern using epitaxy.
[0062] Step S8: After filling the source / drain region with an intermediate dielectric layer, remove the pseudo gate pattern.
[0063] Figures 18-37This is a schematic diagram illustrating the corresponding steps in the fabrication method of the dummy gate process in the semiconductor chip provided in this embodiment. The following is in conjunction with... Figures 18-37 The method for fabricating the dummy gate process in the semiconductor chip provided in this embodiment will be described in detail.
[0064] Execution step S1: Please refer to Figure 18 A substrate 100 is provided, which can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate, and is not limited thereto. The substrate 100 includes an active region (not shown in the figure), which is located on the surface of the substrate 100; a pad oxide layer 120 and a pad silicon nitride layer 140 are formed on the substrate 100, and a plurality of shallow trenches 200 are formed in the substrate 100 using a photolithography process (only one shallow trench 200 is shown in the figure).
[0065] Please refer to Figure 19 An insulating medium 220 is filled in the shallow trench 200, and the insulating medium 220 covers the silicon nitride layer 140. At this time, the width of the shallow trench 200 is CD1 (initial width), and the material of the insulating medium 220 can be silicon oxide.
[0066] Please refer to Figure 20 After filling, the insulating medium 220 in the shallow trench 200 is annealed. Annealing can increase the density of the insulating medium 220, and annealing will cause the width of the shallow trench 200 to increase. At this time, the width of the shallow trench 200 is CD2, CD2>CD1. For example, the shallow trench 200 increases by about 15nm.
[0067] Please refer to Figure 21 The insulating medium 220 is etched back so that the top surface of the insulating medium 220 is lower than the surface of the substrate 100. Specifically, the insulating medium 220 on the surface of the substrate 100 and the insulating medium 220 on the upper part of the shallow trench 200 are etched away. The remaining insulating medium 220 fills the lower part of the shallow trench 200 and exposes the upper sidewall of the shallow trench 200, so as to form a shallow trench isolation structure in the substrate 100. The pad oxide layer 120 and the pad silicon nitride layer 140 are removed to expose the surface of the substrate 100.
[0068] Execution step S2: Please refer to Figure 22An ONO layer is formed on the surface of the substrate 100 with the shallow trench isolation structure. Specifically, the ONO layer is formed on the upper sidewall of the shallow trench 200 and the surface of the substrate 100. The ONO layer also covers the top surface of the insulating dielectric 220. The ONO layer includes a bottom silicon oxide layer 310, a silicon nitride layer 320, and a top silicon oxide layer 330 stacked sequentially from bottom to top. In this embodiment, the ONO layer is formed using an ALD (Atomic Layer Deposition) process. The ALD process does not cause loss of the substrate 100, that is, it does not further increase the width of the shallow trench 200. The thickness of the bottom silicon oxide layer 310, the silicon nitride layer 320, and the top silicon oxide layer 330 in the ONO layer can all be 2nm to 3nm, and is not limited to this.
[0069] Execution step S3: Please refer to Figure 23 and Figure 24 , Figure 24 Design layout for pseudo-grating pattern 500 and photoresist 400. Figure 23 for Figure 24 A schematic diagram showing the formation of photoresist 400 at the mid-section line A1A2. Photoresist 400 is formed on a shallow trench isolation structure corresponding to the dummy gate pattern 500 (the design position of the dummy gate pattern 500 is known during fabrication). Photoresist 400 is located above the shallow trench 200 and extends to cover the ONO layer on the substrate 100 at the top edge of the shallow trench 200. The width of photoresist 400 is greater than the width of the dummy gate pattern 500 (width is...). Figure 24 (Horizontal dimensions in the text). Please refer to... Figure 25 Using photoresist 400 as a mask, wet etching is used to remove the top silicon oxide layer 330 in the ONO layer that does not cover photoresist 400.
[0070] Execution step S4: Please refer to Figure 25 After etching away the top silicon oxide layer 330 in the ONO layer that does not cover the photoresist 400, the photoresist 400 is removed to expose the remaining top silicon oxide layer 330. Please refer to... Figure 26 and Figure 27The silicon nitride layer 320 and silicon oxide layer in the ONO layer are removed by wet etching. Specifically, the silicon nitride layer 320 corresponding to the position of the removed top silicon oxide layer 330 in the ONO layer is first removed by wet etching. The etchant is preferably H3PO4. The silicon nitride layer 320 and silicon oxide layer have a high etch selectivity, and the effect on the silicon oxide layer is slight during etching. Then, the bottom silicon oxide layer 310 corresponding to the position of the removed top silicon oxide layer 330 in the ONO layer and the remaining top silicon oxide layer 330 are removed by wet etching, exposing part of the surface of the substrate 100. The etchant is preferably DHF solution or BHF solution, and the effect on the silicon nitride layer 320 is slight during etching. The retained portion of the ONO layer (i.e., the retained ON layer, which includes the bottom silicon oxide layer 310 and the silicon nitride layer 320) covers the upper sidewall of the shallow trench 200 and the top edge of the shallow trench 200 of the substrate 100, and also covers the top surface of the insulating medium 220.
[0071] Execution step S5: Please refer to Figure 28 A gate oxide layer 340 is formed on the exposed surface of the substrate 100 using a thermal oxidation process. The thickness of the gate oxide layer 340 can be 3nm to 5nm, and is not limited thereto. This step of forming the gate oxide layer 340 does not oxidize the sidewalls of the shallow trench 200, so it does not lead to an increase in the width of the shallow trench 200.
[0072] Please refer to Figure 29 A dummy gate pattern 500 is formed on the surface of the substrate 100 on which the gate oxide layer 340 is formed, and a dummy gate pattern 500 is formed on the shallow trench isolation structure (three dummy gate patterns 500 are shown in the figure). Part of the dummy gate pattern 500 is located on the upper part of the shallow trench 200 and covers the ONO layer (retained ON layer) retained on the top edge of the shallow trench 200. The width of the dummy gate pattern 500 is approximately the same as the width of the shallow trench 200. Part of the dummy gate pattern 500 is located on the gate oxide layer 340, and there is a first opening 510 between adjacent dummy gate patterns 500 to expose the gate oxide layer 340. The first opening 510 can also expose the ONO layer retained on the top edge of the shallow trench 200. The material of the dummy gate pattern 500 can be polysilicon.
[0073] Execution step S6: Please refer to Figure 30 A sidewall layer 610 is formed on the surface of the dummy gate pattern 500. Specifically, the sidewall layer 610 conformally covers the top and sides of the dummy gate pattern 500 and the exposed surface of the gate oxide layer 340 (i.e., the sidewalls and bottom of the first opening 510 and the top surface of the dummy gate pattern 500). The sidewall layer 610 can be made of silicon nitride. Please refer to [reference needed]. Figure 31The sidewall layer 610 is etched without obstruction to form the sidewall 610a. Specifically, the sidewall layer 610 of the top surface of the pseudo gate pattern 500 and the exposed surface of the gate oxide layer 340 (bottom of the first opening 510) is etched away to form the sidewall 610a on the side of the pseudo gate pattern 500.
[0074] Execution step S7: Please continue to refer to Figure 31 The substrates 100 on both sides of the dummy gate pattern 500 are etched. Specifically, the gate oxide layer 340 and part of the substrate 100 are etched downward along the first opening 510 to form an epitaxial groove 710. Since the width of the shallow trench 200 is not further widened, the process window is relatively large during this etching step. Some lateral etching will occur when the substrate 100 is etched downward. There is a part of the substrate 100 between the epitaxial groove 710 and the sidewall of the shallow trench 200 (shown by the dashed box in the figure). The thickness of the substrate 100 between the epitaxial groove 710 and the sidewall of the shallow trench 200 is the same as the thickness of the substrate 100 between the etched positions on both sides of the dummy gate pattern 500 and the shallow trench isolation structure. The thickness of the substrate 100 between the epitaxial groove 710 and the sidewall of the shallow trench 200 can be 1nm~2nm.
[0075] After etching the substrates 100 on both sides of the dummy gate pattern 500, the etching positions on both sides of the dummy gate pattern 500 are cleaned to remove oxides from the inner wall of the epitaxial trench 710 (the etching positions on both sides of the dummy gate pattern 500) to avoid affecting the formation of the source / drain region during epitaxial growth. There is a portion of substrate 100 between the ON layer of the epitaxial trench 710 and the upper sidewall of the shallow trench 200, which will not affect the ON layer of the upper sidewall of the shallow trench 200, and the morphology of the epitaxial layer is better during subsequent epitaxial growth.
[0076] Please refer to Figure 32 The source / drain regions are formed in the substrate 100 corresponding to the etching positions on both sides of the pseudo gate pattern 500 by epitaxial growth. Specifically, an epitaxial layer 720 is formed in the epitaxial groove 710 to serve as the source / drain region of the device. The material of the epitaxial layer 720 can be germanium silicon.
[0077] Execution step S8: Please refer to Figure 33 An intermediate dielectric layer 620 is filled on the source / drain region (epitaxy layer 720). The top of the intermediate dielectric layer 620 is flush with the top of the dummy gate pattern 500. The intermediate dielectric layer 620 can be made of silicon oxide, silicon oxynitride, etc. Please refer to [reference needed]. Figure 34The dummy gate pattern 500 is removed by wet etching, and the etchant used for wet etching can be a TMAH solution. The remaining bottom silicon oxide layer 310 and silicon nitride layer 320 (the part of the ONO layer retained) in the ONO layer isolate the etchant from the source / drain region (epitaxial layer 720) when the dummy gate pattern 500 is removed, thereby protecting the source / drain region (epitaxial layer 720). After the dummy gate pattern 500 is removed, a second opening 520 is formed, that is, the area where the dummy gate pattern 500 was originally located is used as the second opening 520.
[0078] Further, please refer to Figure 35 A metal oxide layer 810 and a metal gate 820 are formed at the corresponding positions where the dummy gate pattern 500 is removed. Specifically, the metal oxide layer 810 is first formed to cover the sidewalls and bottom of the second opening 520. Then, the metal gate 820 is formed by filling the second opening 520. Due to the isolation of the portion of the ONO layer (ON layer), the metal gate 820 will only be located in the second opening 520. The material of the metal gate 820 can be titanium nitride, etc.
[0079] Please refer to Figure 36 The intermediate dielectric layer 620 is etched to form a contact hole 910 that penetrates the intermediate dielectric layer 620 and extends into the epitaxial layer 720 (source / drain region). After forming the contact hole 910, it is cleaned. The cleaning agent can be a mixture of dilute sulfuric acid and hydrogen peroxide or a hydrofluoric acid solution. Due to the isolation between the substrate 100 and the sidewalls of the epitaxial trench 710 and the shallow trench 200, and the portion of the retained ONO layer (ON layer), the cleaning will not affect the metal gate 820 and will not cause the metal gate 820 to be lost. An interlayer dielectric layer (not shown in the figure) is formed on the intermediate dielectric layer 620 and the metal gate 820. The contact hole 910 penetrates the interlayer dielectric layer. The contact hole 910 is cleaned while retaining the interlayer dielectric layer. Please refer to [reference needed]. Figure 37 The contact hole 910 is filled with metal material 920 to form a contact element, and the epitaxial layer 720 serves as the source / drain region of the device. The source and drain electrodes are brought out through the contact element.
[0080] In summary, in the method for fabricating a dummy gate process in a semiconductor chip provided by this invention, an ONO layer is formed on the substrate surface where a shallow trench isolation structure is formed, thus avoiding widening of the shallow trench isolation structure. Furthermore, by controlling the thickness of the ONO layer, the process window during etching the substrate on both sides of the dummy gate pattern can be controlled, preventing the complete removal of the substrate on both sides of the shallow trench isolation structure. During the etching process to remove the dummy gate pattern, the portion of the ONO layer retains an isolation function, protecting the source / drain regions from simultaneous etching and maintaining the integrity of their morphology. After the subsequent formation of the metal gate, the portion of the ONO layer isolates the source / drain regions and the metal gate, preventing the loss of the metal gate and short circuits during contact hole formation and cleaning. Therefore, the method of this invention can avoid device failure caused by device short circuits, thereby improving device reliability.
[0081] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A method for fabricating a dummy gate process in a semiconductor chip, characterized in that, include: A substrate is provided in which a plurality of shallow trench isolation structures are formed, and the insulating medium filled in the shallow trench isolation structures is etched back so that the top surface of the insulating medium is lower than the surface of the substrate. An ONO layer is formed on the surface of the substrate on which the shallow trench isolation structure is formed; A photoresist is formed at the position corresponding to the shallow trench isolation structure of the pseudo gate pattern, and the top silicon oxide layer in the ONO layer that does not cover the photoresist is removed by wet etching. After removing the photoresist, the silicon nitride layer and silicon oxide layer in the ONO layer are removed by wet etching; A gate oxide layer is formed, and a pseudo gate pattern is formed on the substrate surface on which the gate oxide layer is formed; A sidewall layer is formed on the surface of the pseudo-gate pattern, and the sidewall layer is etched without obstruction to form the sidewalls; The substrates on both sides of the dummy gate pattern are etched, and the source / drain regions are formed in the substrates corresponding to the etched positions on both sides of the dummy gate pattern by epitaxy. After filling the source / drain region with an intermediate dielectric layer, the dummy gate pattern is removed.
2. The method for fabricating the dummy gate process in a semiconductor chip as described in claim 1, characterized in that, The ONO layer is formed using the ALD process.
3. The method for fabricating the dummy gate process in a semiconductor chip as described in claim 2, characterized in that, The ONO layer covers the upper sidewall of the shallow trench of the shallow trench isolation structure and the isolation medium.
4. The method for fabricating the dummy gate process in a semiconductor chip as described in claim 2, characterized in that, The thickness of the bottom silicon oxide layer, silicon nitride layer, and top silicon oxide layer in the ONO layer is 2nm~3nm.
5. The method for fabricating the dummy gate process in a semiconductor chip as described in claim 1, characterized in that, The gate oxide layer is formed using a thermal oxidation process.
6. The method for fabricating a dummy gate process in a semiconductor chip as described in claim 5, characterized in that, The thickness of the gate oxide layer is 3nm~5nm.
7. The method for fabricating a dummy gate process in a semiconductor chip as described in claim 1, characterized in that, After etching the substrate on both sides of the dummy gate pattern, the thickness of the substrate between the etching positions on both sides of the dummy gate pattern and the shallow trench isolation structure is 1nm~2nm.
8. The method for fabricating a pseudo-gate process in a semiconductor chip as described in claim 1, characterized in that, After etching the substrates on both sides of the dummy gate pattern, the etching positions on both sides of the dummy gate pattern are cleaned.
9. The method for fabricating a dummy gate process in a semiconductor chip as described in claim 1, characterized in that, During wet etching to remove the dummy gate pattern, the remaining bottom silicon oxide layer and silicon nitride layer in the ONO layer prevent the etchant from contacting the source / drain regions during the etching process.
10. The method for fabricating a dummy gate process in a semiconductor chip as described in claim 1, characterized in that, After removing the pseudo-gate pattern, the process also includes: A metal oxide layer and a metal gate are formed at the corresponding positions where the dummy gate pattern is removed; Contact holes are formed in the intermediate dielectric layer, and the contact holes are cleaned. The contact hole is filled with metallic material.