Radio frequency transistor based on aligned semiconducting carbon nanotube array and method of fabrication

Abstract

This invention discloses a radio frequency (RF) transistor based on a carbon nanotube array and its fabrication method. The RF transistor includes a substrate with an insulating surface, an active region formed by an oriented array of semiconductor-type carbon nanotubes, a gate dielectric layer, a gate metal layer, and source and drain electrodes. The active region is a channel functional region surrounded by a continuous carbon nanotube-free region, retaining only the carbon nanotube strips required for channel conductivity and the necessary source-drain contact overlap region; the carbon nanotube-free region has a clearance margin δ around the perimeter of the channel functional region. This method thoroughly removes all carbon nanotubes outside the active region through plasma etching, physically cutting off parasitic conduction paths and eliminating capacitive coupling effects. Compared to traditional local line isolation methods, this invention can improve transconductance by ≥35%, cutoff frequency by ≥20%, maximum oscillation frequency by ≥15%, and reduce gate-source parasitic capacitance by ≥25%, while significantly improving device consistency, making it suitable for large-scale RF array integration.

Description

Technical Field

[0001] This invention relates to the field of carbon-based integrated circuits and radio frequency devices, and in particular to a radio frequency field-effect transistor based on a directional semiconductor carbon nanotube array and its fabrication method. Background Technology

[0002] As wireless communication technology evolves towards sixth generation (6G), higher frequency and bandwidth requirements are being placed on radio frequency (RF) front-end devices. For communication bands above 90 GHz, RF transistors with high transconductance and low parasitic capacitance are needed. Carbon nanotubes (CNTs) are particularly suitable due to their ultra-high carrier mobility (up to 2000 cm²V⁻¹s⁻¹ and above) and high saturation velocity (up to 3.5 × 10⁻¹). 7 With its excellent current carrying capacity (cm / s) and high purity oriented semiconductor carbon nanotube arrays, it is considered an important candidate for the next generation of radio frequency transistor channel materials. In recent years, top-gate metal-oxide-semiconductor field-effect transistors (MOS FETs) based on high purity oriented semiconductor carbon nanotube arrays have shown the potential for cutoff frequencies exceeding 500 GHz and maximum oscillation frequencies exceeding 1 THz.

[0003] In the fabrication of carbon nanotube radio frequency transistors, defining the active area (AA) is one of the key process steps that determines the RF performance of the device. The definition of the active area refers to clearly defining the boundary between the channel region and the non-channel region through patterning and etching processes, retaining the carbon nanotube strips required for the channel, and removing non-functional carbon nanotubes.

[0004] However, the commonly used method for defining the active region in existing technologies is the "local line isolation" scheme. This scheme only uses fine lines or narrow frames to create isolation trenches with limited width through plasma etching around the channel. Although this method can physically sever carbon nanotubes at the channel edge, a large area of ​​redundant carbon nanotube arrays is still retained outside the active region. These residual carbon nanotubes cause several problems: First, the residual carbon nanotubes form parallel conductive paths, increasing the off-state leakage current and reducing the on / off ratio. Second, the large area of ​​carbon nanotubes retained outside the active region creates significant capacitive coupling between the carbon nanotubes and the gate metal, RF pads, and interconnects, increasing the gate-source parasitic capacitance (C0). gs ) and gate-drain parasitic capacitance (C gd This severely limits the device's cutoff frequency (f). T ) and maximum oscillation frequency (f maxThe improvement of the active region; third, when relying solely on fine-line isolation, lithographic alignment errors and etching tolerances can cause the actual boundary of the active region to shift, which in turn can lead to large fluctuations in device performance (such as transconductance and cutoff frequency), affecting the consistency and yield of large-scale array integration.

[0005] Therefore, how to significantly reduce parasitic effects and improve the frequency characteristics of carbon nanotube radio frequency transistors without changing the core material system by optimizing the definition process of the active region is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] The purpose of this invention is to provide a method and device for improving the performance of carbon nanotube radio frequency transistors by optimizing the active region definition, so as to solve the problems of significant parasitic effects, limited radio frequency performance and poor device consistency caused by local line isolation schemes in the prior art.

[0007] To achieve the above objectives, the present invention provides a radio frequency transistor based on a directional semiconductor carbon nanotube array, comprising: Substrate, the substrate having an insulating layer; An array of semiconductor carbon nanotubes is oriented on an insulating layer of the substrate, the array of carbon nanotubes forming an active region; The gate dielectric layer located on the active region; The gate metal layer located on the gate dielectric layer; The source and drain electrodes respectively form electrical contacts with the carbon nanotube array; The active region is a channel functional region surrounded by a continuous carbon nanotube-free region. The channel functional region retains the carbon nanotube strips required to form the channel conductivity, as well as the contact overlap area between the carbon nanotube strips and the source and drain electrodes. The carbon nanotube-free region is provided with a clearance margin δ around the channel functional region to suppress parasitic conduction and capacitive coupling between the carbon nanotubes outside the active region and the gate, source, drain electrodes, and pads.

[0008] In an optional embodiment, the clear margin δ is 0.45 to 10 μm; or, the clear margin δ is 2 to 20 times the gate length Lg.

[0009] In an optional embodiment, the carbon nanotube array has a semiconductor purity ≥99.99%, an array density of 60–200 nanotubes / μm, and the array orientation is parallel to the width direction of the device. The substrate is a high resistivity silicon substrate, and the insulating layer is a SiO2 layer thermally grown on the silicon substrate, with a thickness of 100–1000 nm.

[0010] The gate dielectric layer is an HfO2 layer with a thickness of 3–8 nm; the gate metal layer is a Pd / Au stack or a Ti / Au stack. The contact metal between the source and drain electrodes is a Pd / Au stack with a total thickness of ≤40 nm.

[0011] In an optional embodiment, the RF transistor further includes a bridge structure located on the drain side, the bridge structure causing the gate metal to cross over to form an air gap on the drain side, thereby reducing gate-source parasitic capacitance and gate resistance.

[0012] In an optional embodiment, the channel is designed as a multi-finger parallel structure with an exponent N≥2, the total channel width is the sum of the widths of each finger, and the carbon-free nanotube region surrounds the periphery of the entire multi-finger structure.

[0013] In an optional embodiment, the source and drain are connected to the RF pads of the coplanar waveguide structure.

[0014] Another aspect of the present invention provides a method for fabricating the above-mentioned radio frequency transistor based on a oriented semiconductor carbon nanotube array, comprising the following steps: A directionally aligned semiconductor carbon nanotube array thin film is formed on a substrate with an insulating layer; The active region pattern is defined on the carbon nanotube array film by photolithography, and the carbon nanotubes outside the active region are removed by plasma etching to form a channel functional region surrounded by a continuous carbon nanotube-free region. The carbon nanotube-free region has a removal margin δ around the channel functional region. A gate dielectric layer is deposited on the channel functional region; A source and a drain are formed, and the source and drain respectively form electrical contacts with the carbon nanotube array; Forming a gate metal layer; and forming radio frequency pads and interconnect structures.

[0015] In an optional embodiment, the plasma etching is inductively coupled plasma etching, the etching gas includes O2 with a flow rate of 10–40 sccm, the ICP source power is 200–600 W, the RF bias power is 0–100 W, the cavity pressure is 5–50 mTorr, and the etching time is 10–120 s; the etching gas includes Ar with a flow rate of 5–20 sccm.

[0016] In an optional embodiment, the method further includes the step of forming a sacrificial layer bridge structure on the drain side, such that the formed gate metal crosses the sacrificial layer bridge structure on the drain side, and forming an air bridge gap after removing the sacrificial layer.

[0017] In an optional embodiment, the sacrificial bridge structure is made of polymethyl methacrylate and is formed by spin coating and photolithography patterning, with a thickness of 200–600 nm.

[0018] The present invention has the following beneficial effects: (1) Completely eliminate parasitic conduction path: By removing all carbon nanotubes outside the active region over a large area, the parallel conduction path formed by the residual carbon nanotubes is physically cut off, which effectively reduces the off-state leakage current of the device and improves the switching ratio.

[0019] (2) Significantly reduced parasitic capacitance: The carbon nanotube-free region eliminates the capacitive coupling between the carbon nanotubes and the gate, pads, and interconnects, thus reducing the gate-source parasitic capacitance (C0). gs This reduces the cutoff frequency by more than 25%, thereby significantly improving the cutoff frequency (f). T ) and maximum oscillation frequency (f max Actual measurement data shows that, compared with the control device using a local line isolation scheme, the present invention can increase the transconductance (gm) by ≥35% and the on-state current (I). on ) Improvement of ≥32%, cutoff frequency (f T Increase by ≥20%, maximum oscillation frequency (f) max Increase by ≥15%.

[0020] (3) Improve device consistency: The large-area continuous removal scheme provides more stable control over the active region boundary, reduces the impact of photolithography alignment and etching tolerance on device performance, and is conducive to improving the yield of large-scale RF array integration.

[0021] (4) Good process compatibility: The present invention is fully compatible with the existing carbon nanotube radio frequency transistor fabrication process, without changing the core material system or introducing additional complex processes.

[0022] (5) Superimposed optimization effect: The solution of the present invention can be superimposed with the drain side air bridge structure to achieve three-dimensional parasitic suppression in the substrate plane and vertical direction, and further improve the radio frequency performance. Attached Figure Description

[0023] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several specific embodiments of this disclosure are illustrated in the drawings by way of example and not limitation.

[0024] Figure 1 This is a schematic diagram of the cross-sectional structure of the radio frequency transistor before and after the removal of the active region, according to an embodiment of the present invention.

[0025] Figure 2 This is an enlarged schematic diagram of the structure in which the active region is defined using a large-area removal method in an embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram showing the positional relationship between the RF pads and the active region in an embodiment of the present invention.

[0027] Figure 4 This is a comparison diagram of the overall layout structure of the radio frequency transistor in the embodiments of the present invention and the prior art; the left side is the prior art device using a local line isolation scheme, and the right side is the device of the present invention using a large area removal of the active region scheme.

[0028] Figure 5 This is an enlarged schematic diagram of the structure in the prior art that uses local line isolation to define the active region.

[0029] Figure 6 This is a normalized comparison chart of key radio frequency performance parameters between the embodiments of the present invention and existing technical solutions.

[0030] Figure 7 The trend curves show the effects of different clearance margins δ on gate-source parasitic capacitance and cutoff frequency. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.

[0032] Example 1

[0033] This embodiment provides a radio frequency transistor based on a carbon nanotube array. Figure 1 This is a schematic diagram of the cross-sectional structure of the device in this embodiment. From bottom to top, they are: a high resistivity Si substrate 101, an insulating SiO2 layer 102, a carbon nanotube channel layer 103, an HfO2 top gate dielectric layer (4.8 nm) 104, and a gate metal (Ti / Au) 105.

[0034] The substrate is a high-resistivity (>20 kΩ·cm) single-crystal silicon substrate. The substrate has an insulating layer, which is a SiO2 layer thermally grown on the silicon substrate. In this embodiment, the SiO2 layer has a thickness of 500 nm. The choice of a high-resistivity silicon substrate effectively reduces the loss and parasitic coupling of the substrate to radio frequency signals. The thickness of the SiO2 layer can be selected in the range of 100–1000 nm, preferably 300–600 nm. The SiO2 insulating layer electrically isolates the carbon nanotube channels from the silicon substrate and provides a flat deposition surface. It should be noted that the substrate is not limited to a silicon substrate. In other embodiments, the substrate can also be a quartz substrate, a sapphire substrate, or other substrate materials with high resistivity and insulating surfaces, as long as their surfaces have a suitable insulating layer.

[0035] A directional array of semiconductor carbon nanotubes sits atop the SiO2 insulating layer. This carbon nanotube array forms the active area (AA). In this embodiment, the carbon nanotube array has a semiconductor purity ≥99.99%, a density of approximately 100 nanotubes / μm, and is oriented parallel to the device width direction (i.e., the direction perpendicular to the source-to-drain line). The average diameter of the carbon nanotubes is approximately 1.5 nm, and they are single-walled carbon nanotubes. The density of the carbon nanotube array can be selected in the range of 60–200 nanotubes / μm. Higher densities provide greater channel current and transconductance, but also increase inter-tube shielding effects; lower densities help reduce inter-tube coupling, but may lead to insufficient current density. In radio frequency applications, a density range of 60–200 nanotubes / μm achieves a good balance between current drive capability and inter-tube coupling. Figure 1 As shown, in the cross-sectional structure, the carbon nanotube channel layer exists only within the active region boundary. In the region outside the active region boundary, the carbon nanotubes have been completely removed, leaving only the exposed SiO2 surface.

[0036] A gate dielectric layer is formed on top of the carbon nanotube array. In this embodiment, the gate dielectric layer is an HfO2 (hafnium oxide) film, grown at a low temperature of 105°C using atomic layer deposition (ALD). The ALD growth was performed for 40 cycles, resulting in a physical thickness of 4.8 nm and an equivalent oxide thickness (EOT) of approximately 1.44 nm. The thickness of the HfO2 layer can be selected within the range of 3–8 nm. The low-temperature ALD process (deposition temperature ≤110°C) was chosen to avoid thermal damage to the carbon nanotube channels and disruption of the ordered arrangement of the deposited carbon nanotube array caused by the high-temperature process.

[0037] like Figure 1 As shown, the HfO2 gate dielectric layer not only covers the carbon nanotube channel region within the active region, but also extends to cover part of the SiO2 surface outside the active region, playing a role in protecting the edge of the active region and passivating the etched surface.

[0038] The source and drain electrodes form electrical contacts with the carbon nanotube array. In this embodiment, the contact metals for both the source and drain electrodes are Pd / Au stacks, with a Pd layer thickness of 20 nm and an Au layer thickness of 10 nm, for a total thickness of 30 nm (≤40 nm). A low-barrier ohmic contact can be formed between the Pd metal and the carbon nanotubes, with a measured contact resistance below 150 Ω·μm. The purpose of controlling the total source / drain metal thickness to below 40 nm is to reduce the parasitic capacitance generated in the overlap region between the gate metal and the source / drain electrodes.

[0039] like Figure 2 As shown, in the magnified structure of the active region (AA), it can be clearly seen that the source and drain are located at the two ends of the carbon nanotube strip, and the carbon nanotube strip forms a continuous conductive channel between the source and drain.

[0040] In this embodiment, the gate metal layer is located above the gate dielectric layer, disposed above the channel region between the source and drain. In this embodiment, the gate metal layer is a Ti / Au stack (5 nm / 150 nm). Ti acts as an adhesion layer, improving the adhesion between Au and HfO2. The gate length Lg is 90 nm in this embodiment. In other embodiments, the gate metal layer can also be a Pd / Au stack. Figure 1 As shown, the gate is located between the source and drain, and below it are the HfO2 gate dielectric layer and the carbon nanotube channel layer, forming a complete top-gate metal-oxide-semiconductor (MOS) structure.

[0041] The core innovation of this invention lies in the way the active region is defined. For example... Figure 2 As shown, the active region is a channel functional region surrounded by a continuous area without carbon nanotubes. This channel functional region retains only the carbon nanotube strips required to form channel conductivity and the overlapping contact areas between the carbon nanotube strips and the source and drain electrodes. The carbon nanotubes outside the active region have been completely removed, forming a large-area continuous insulating region.

[0042] like Figure 2 As further shown, the carbon nanotube-free region is provided with a clearance margin δ around the perimeter of the channel functional area. In this embodiment, the clearance margin δ is set to 5 × Lg = 5 × 90 nm = 450 nm (i.e., 0.45 μm). The purpose of setting the clearance margin δ is to suppress parasitic conduction and capacitive coupling between the external carbon nanotubes (if any remain) of the active region and the gate, source, drain, and RF pads with sufficient physical distance. The value of the clearance margin δ can be selected in the range of 0.45 to 10 μm, or characterized as 2 to 20 times the gate length Lg. In a preferred embodiment, the clearance margin δ is 5 to 10 times the gate length Lg, within which the best balance between chip area and parasitic suppression effect can be achieved.

[0043] like Figure 3 As shown, the source and drain are connected to the RF pads of the ground-signal-ground (GSG) waveguide structure. The gate lead extends outward from the gate within the active region and connects to a separate gate pad. In this invention, the area below the lead is also a carbon nanotube-free region; that is, the carbon nanotubes below the lead path have been removed. This design effectively avoids parasitic capacitive coupling between the gate lead and the carbon nanotubes on the substrate surface, further reducing the total parasitic capacitance of the device.

[0044] Figure 4 An embodiment of the present invention is shown ( Figure 4 (right side) and existing technology ( Figure 4 A comparison of the overall layout structure on the left side. In existing technical solutions ( Figure 4 In the left-hand section, the active region is defined using local line isolation. For example... Figure 5 As shown in the magnified image, this scheme uses only fine lines or narrow frames for plasma etching to create isolation trenches with limited width around the channel. The large area outside the isolation trenches retains the carbon nanotube array. These residual carbon nanotubes form parallel parasitic conductive paths and also generate significant capacitive coupling with the gate metal, GSG pads, and interconnect traces.

[0045] In contrast, in the present invention ( Figure 4 (On the right) The area outside the active region is a large area free of carbon nanotubes. The active region is distributed in an island-like pattern at the center of the chip, with the surrounding carbon nanotubes completely removed. The GSG pad area, lead area, and chip edge area are all clean insulating surfaces, without any carbon nanotube residue. This structure fundamentally eliminates parasitic conduction and capacitive coupling paths between the carbon nanotubes outside the active region and the electrodes and pads of the device.

[0046] Example 2

[0047] This embodiment provides a method for fabricating the above-mentioned radio frequency transistor, and the specific process flow includes the following steps: Step 1: Form a oriented semiconductor carbon nanotube array thin film on a substrate with an insulating layer.

[0048] A high-resistivity (>20 kΩ·cm) silicon substrate with a thermally grown 500 nm thick SiO2 insulating layer was selected. A conjugated polymer dispersion-dip coating method was used to form an array of oriented carbon nanotubes on this substrate. Specifically, commercially available arc-discharged carbon nanotube powder (2 mg / mL concentration) and the conjugated polymer PCz (2 mg / mL concentration) were first dissolved in 500 mL of toluene, dispersed using a 650 W ultrasonic probe for 30 min, and then purified by centrifugation at 50,000 g for 2 h. The purified carbon nanotube solution was redispersed in 1,1,2-trichloroethane as the target solvent. A 4-inch wafer was immersed in the carbon nanotube solution and pulled at a constant speed of 10 μm / s, utilizing the binary liquid interface effect at the liquid surface to oriented and deposit the carbon nanotubes onto the wafer surface. After deposition, the surface was sequentially cleaned with toluene, tetrahydrofuran, and N,N-dimethylformamide for at least 20 minutes each to remove residual polymer coatings and impurity molecules. Finally, it was cured by baking at 170°C for 30 minutes. The resulting carbon nanotube array had an arrangement density of approximately 100 nanotubes / μm, a semiconductor purity of ≥99.99%, and the carbon nanotube array orientation was parallel to the width direction of the device.

[0049] Step 2: Define the active region pattern using photolithography, and remove the carbon nanotubes outside the active region using plasma etching.

[0050] Photoresist S1813 was spin-coated onto a carbon nanotube array film at a spin speed of 4000 rpm, resulting in a photoresist thickness of approximately 1.4 μm. A pre-baking process was performed at 100–115 °C for 60–90 s. The active region pattern was defined using a laser direct-write lithography machine or an electron beam lithography machine, with an exposure dose of 100–150 mJ / cm², and development was performed using MF-319 developer. After the above lithography process, the photoresist remained within the active region pattern (i.e., the channel functional region), covering and protecting the carbon nanotubes in the channel region; the photoresist outside the active region pattern was removed, exposing the carbon nanotube regions to be etched. The design of the active region pattern must ensure sufficient clearance margin δ around the channel functional region. In this embodiment, the gate length Lg is 90 nm, and the clearance margin δ is set to 5 × Lg = 450 nm, meaning the minimum distance from the boundary of the active region lithography pattern to the outermost edge of the channel functional region is 450 nm.

[0051] Subsequently, inductively coupled plasma (ICP) etching was used to remove the carbon nanotubes outside the active region. The ICP etching parameters in this embodiment are as follows: Main etching gas: O2, flow rate 20 sccm; Assist gas: Ar, flow rate 10 sccm (introduces physical bombardment component to improve etching anisotropy and edge neatness); ICP source power: 400 W; RF bias power: 50 W (low bias to reduce physical damage to the substrate); Cavity pressure: 20 mTorr; Substrate temperature: 25℃; Etching time: 60 s.

[0052] The parameters were selected based on the following: the O2 plasma exhibits a highly selective chemical reaction (carbon oxidation reaction) with carbon nanotubes, which removes carbon nanotubes without damaging the SiO2 substrate and the subsequently deposited HfO2 gate dielectric; the introduction of an appropriate amount of Ar gas increases the physical bombardment component, improving the etching uniformity at the active region edges. The O2 flow rate can be selected within the range of 10–40 sccm, and the Ar flow rate within the range of 5–20 sccm. The ICP source power can be selected within the range of 200–600 W, and the RF bias power within the range of 0–100 W. The cavity pressure can be selected within the range of 5–50 mTorr. The etching time can be selected within the range of 10–120 s, adjusted according to the density and thickness of the carbon nanotube array.

[0053] After etching, residual photoresist is removed using an organic solvent. This step creates a channel functional region surrounded by continuous carbon nanotube-free regions, such as... Figure 2 As shown.

[0054] Step 3: Deposit a grid dielectric layer on the channel functional area.

[0055] Atomic layer deposition (ALD) was used to deposit the HfO2 gate dielectric layer. The ALD precursors were tetrakis(dimethylamido)hafnium (TDMAH) and H2O. The deposition temperature was 105 °C. A total of 40 deposition cycles were performed to obtain an HfO2 film with a thickness of approximately 4.8 nm. The HfO2 film covered the entire channel region and the edge region of the active region, providing passivation protection to the etched surface.

[0056] Step 4: Form the source and drain.

[0057] Source / drain electrode patterns were defined using electron beam lithography. A Pd / Au bilayer metal was deposited using electron beam evaporation, with a Pd layer thickness of 20 nm and an Au layer thickness of 10 nm. The source and drain electrodes were then formed using a lift-off process. A low-resistance ohmic contact was formed between the Pd metal and the carbon nanotube array; the measured contact resistance was less than 150 Ω·μm.

[0058] Step 5: Form the gate metal layer.

[0059] The gate pattern was defined using electron beam lithography. A Ti / Au multilayer metal (5 nm / 150 nm) was deposited using electron beam evaporation, with Ti serving as the adhesion layer. The gate was then formed via a lift-off process. The gate length Lg = 90 nm.

[0060] Step 6: Form RF pads and interconnect structures.

[0061] GSG coplanar waveguide RF pads and interlayer interconnects are formed using photolithography and metal evaporation / lifting processes. The pads and interconnect metals utilize a Ti / Au stack (5 nm / 400 nm). The final result is as follows: Figure 3 The complete RF transistor layout shown has the source and drain connected to the signal terminals of the GSG pads via interconnect traces.

[0062] Example 3

[0063] The RF transistor of this embodiment, based on the structure described in Embodiment 1, further includes a bridge structure located on the drain side. This bridge structure allows the gate metal to cross over to form an air gap on the drain side, thereby reducing the gate-source parasitic capacitance (C). gs ) and gate resistance (R g In terms of the preparation method, this embodiment adds a step of forming a sacrificial layer bridge structure on the drain side between step four (forming the source and drain) and step five (forming the gate metal layer) as described in embodiment 2.

[0064] Specifically, after source / drain metal deposition, polymethyl methacrylate (PMMA) is spin-coated onto the drain side as a sacrificial layer. A PMMA film with a thickness of 400 nm is formed by spin-coating. Subsequently, a bridge window pattern is defined in the target area above the drain using electron beam lithography, and after development, a PMMA bridge structure with a predetermined shape is formed. The bridge span (i.e., the distance the bridge structure spans along the channel length) is 200 nm. The thickness of the sacrificial layer bridge structure can be selected in the range of 200–600 nm, and the bridge span can be selected in the range of 100–300 nm.

[0065] In the subsequent step five, during gate metal evaporation, the Ti / Au gate metal is deposited normally on the HfO2 gate dielectric layer in the channel region, while on the drain side, it crosses the PMMA bridge structure, with the metal deposited on the top surface of the PMMA bridge. In the final stripping process, the PMMA sacrificial layer is dissolved and removed by an organic solvent (such as acetone), and the gate metal originally deposited on the top surface of the PMMA is stripped away along with the sacrificial layer, thus forming an air bridge gap on the drain side. The air bridge gap physically separates the gate metal from the carbon nanotubes and HfO2 gate dielectric on the drain side in the vertical direction, replacing HfO2 (dielectric constant κ≈13) with air (dielectric constant κ≈13) as the equivalent dielectric in this region, thereby significantly reducing the parasitic capacitance between the gate and drain.

[0066] When this air-bridge structure is combined with a large-area active region removal scheme, a three-dimensional parasitic suppression effect is achieved: within the substrate plane, the large-area removal scheme cuts off the horizontal parasitic conduction path of carbon nanotubes and eliminates in-plane capacitive coupling; in the vertical direction, the air-bridge structure reduces the vertical parasitic capacitance between the gate and drain. Simultaneously, the air-bridge structure allows for increased gate metal thickness in non-channel regions (i.e., employing a Tall Gate design), reducing the gate line resistance (R0) without increasing the parasitic capacitance in the channel region. g ), thereby further increasing the maximum oscillation frequency (f max ).

[0067] Example 4

[0068] This embodiment provides a multi-finger parallel structure radio frequency transistor. The radio frequency transistor in this embodiment employs a multi-finger parallel channel design, with an index N=10 (i.e., 10 fingers in parallel). Each finger has a channel width of 10 μm, and the total channel width W=N×10 μm=100 μm. Except for the multi-finger parallel channel design, the other structural parameters (including the substrate, carbon nanotube array parameters, gate dielectric layer, metal electrodes, etc.) are the same as in Embodiment 1.

[0069] In the active region definition step, the photolithographic pattern defines the 10-finger channel region as a whole. That is, the carbon nanotube-free region surrounds the entire periphery of the multi-finger structure, rather than defining the active region for each finger separately. This design ensures that there is no interference from redundant carbon nanotubes between the fingers within the multi-finger structure. The removal margin δ is also set to 5×Lg, that is, the minimum distance from the outer edge of the multi-finger structure to the nearest carbon nanotube removal boundary is 5×Lg.

[0070] The technical advantage of the multi-finger parallel structure lies in the increased total channel width, which provides larger on-state current and transconductance, thus benefiting the output power of the RF power amplifier. The multi-finger design also further reduces the normalized gate parasitic resistance. In this embodiment, the 10-finger parallel device can provide a total on-state current exceeding 150 mA and a total transconductance exceeding 150 mS under the drain-source voltage Vds = -0.8 V. The on-state current density and transconductance density, normalized to the channel width, are consistent with those of the single-finger device in Embodiment 1, indicating that the multi-finger structure has good uniformity and scalability.

[0071] To fully verify the technical effectiveness of the present invention, radio frequency transistors using a local line isolation scheme (Type A, control group) and a large-area active region removal scheme (Type B, the present invention scheme, δ=5×Lg) were fabricated on the same carbon nanotube array wafer. Except for the definition of the active region, the core parameters (gate length Lg=90nm, carbon nanotube array density ~100 lines / μm, HfO2 gate dielectric layer thickness 4.8 nm, Pd / Au source / drain contact metal, Ti / Au gate metal, etc.) were kept consistent between the two groups of devices.

[0072] The test conditions were the same as in Example 5. The normalized comparison results of various key RF performance parameters are shown in the table below:

[0073] like Figure 6 As shown, the above comparative data is presented in the form of a normalized bar chart. Hollow bars represent Type A scheme (normalized reference value 1.0x), and filled bars represent Type B scheme (this invention). From... Figure 6 As can be clearly seen, the present invention has achieved significant improvements in four performance indicators: transconductance, on-state current, cutoff frequency, and maximum oscillation frequency, while the gate-source parasitic capacitance has been greatly reduced.

[0074] The physical mechanisms underlying the aforementioned performance improvements can be understood from the following aspects: (1) After removing carbon nanotubes from the active region over a large area, the parallel conductive paths formed by the residual carbon nanotubes are eliminated, increasing the effective channel conductivity of the device and thus improving the transconductance gm and the on-state current Ion; (2) The carbon nanotube-free region eliminates the capacitive coupling between the carbon nanotubes and the gate and pads, reducing both the gate-source parasitic capacitance Cgs and the gate-drain parasitic capacitance Cgd; (3) Since the cutoff frequency fT is proportional to the transconductance gm and the total gate capacitance (Cgs), the performance improvement is significantly enhanced. gs +C gd The ratio of fT≈gm / [2π(C) gs +C gdThe increase in transconductance and the decrease in parasitic capacitance together led to a significant increase in fT; (4) the maximum oscillation frequency fmax is not only related to f T It is related to the gate resistance Rg and the output conductance gds. The reduction of parasitic capacitance and the elimination of parasitic conduction paths both contribute to the improvement of fmax.

[0075] Based on the structure described in Example 1, this embodiment investigates the effect of different clearance margins δ on device performance. Samples with different clearance margins δ were fabricated on a device with a gate length Lg = 90 nm, including: δ ≈ 0 (corresponding to the local line isolation scheme in the prior art, serving as a control group), δ = 2 × Lg = 180 nm, δ = 5 × Lg = 450 nm, δ = 10 × Lg = 900 nm, and δ = 20 × Lg = 1800 nm (i.e., 1.8 μm). Except for the clearance margin δ, all other structural parameters and fabrication processes remained consistent across the groups of samples.

[0076] RF S-parameter testing was conducted on a Lake Shore CRX-4K vacuum probe station (vacuum level <10). -5 The test was conducted at room temperature (300 K) using a Keysight N522x series vector network analyzer (VNA) with a frequency range of 100 MHz to 40 GHz. Standard GSG probes (100 / 150 μm pitch) were used, and SOLT calibration was performed using a standard calibration plate to align the reference plane to the probe tip. To obtain the intrinsic performance of the transistor, an open-short two-step unembedding method was used to subtract parasitic effects from the pads and leads. The DC bias conditions were: drain-source voltage Vds = -0.8 V, gate-source voltage V... gs Find the voltage point corresponding to the peak transconductance (gm,peak).

[0077] The cutoff frequency (fT) is obtained by calculating the current gain |h21| from the de-embedded S-parameters and taking the frequency intercept when |h21| = 0 dB (i.e., 1). The maximum oscillation frequency (fT) is... max The frequency intercept is obtained by extracting the Mason one-sided gain (U) function and taking the value when U=1.

[0078] The effects of different clear margins δ on the device's RF performance are shown in the table below:

[0079] like Figure 7 As shown, with the increase of the clearance margin δ, the gate-source parasitic capacitance C gs The cutoff frequency f continues to decrease. T and maximum oscillation frequency f maxContinuous improvement. When δ≥5×Lg, all three performance indicators tend to saturate: from δ=5×Lg to δ=20×Lg, C gs It only decreased from 185 fF / mm to 174 fF / mm (a decrease of about 6%), fT only increased from 106 GHz to 108 GHz (an increase of about 2%), and fmax only increased from 108 GHz to 110 GHz (an increase of about 2%).

[0080] This pattern aligns with the theoretical model of exponential decay of parasitic capacitance with distance (Cpar∝e^(-δ / λ)), where λ is the characteristic decay length, dependent on the substrate dielectric properties and device geometry. When δ is sufficiently large, the parasitic coupling contribution from carbon nanotubes outside the active region approaches zero. Considering both chip area utilization efficiency and performance gains, the optimal value for the clearance margin δ is recommended to be 5–10 times the gate length (i.e., 5×Lg–10×Lg). This range suppresses over 80% of parasitic coupling without wasting chip area due to an excessively large clearance region.

[0081] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. For those skilled in the art, various modifications, equivalent substitutions, and improvements can be made without departing from the spirit and scope of the present invention. For example, the substrate is not limited to silicon substrates, but can also be quartz substrates, sapphire substrates, etc.; the gate dielectric layer is not limited to HfO2, but can also be high-k dielectric materials such as Al2O3 and ZrO2; the source / drain metals are not limited to Pd / Au, but can also be Ti / Pd / Au stacked structures; plasma etching is not limited to ICP etching, but can also be dry etching processes such as reactive ion etching (RIE). Furthermore, the design concept of large-area removal of the active region of the present invention is not only applicable to carbon nanotube RF transistors, but also to RF field-effect transistors based on other low-dimensional materials (such as graphene nanoribbons, molybdenum disulfide, black phosphorus, etc.). All modifications made within the spirit and scope of the claims of the present invention should be included within the scope of protection of the present invention.

Claims

1. A radio frequency transistor based on an array of oriented semiconductor carbon nanotubes, characterized in that, include: Substrate, the substrate having an insulating layer; An array of semiconductor carbon nanotubes is oriented on an insulating layer of the substrate, the array of carbon nanotubes forming an active region; The gate dielectric layer located on the active region; The gate metal layer located on the gate dielectric layer; The source and drain electrodes respectively form electrical contacts with the carbon nanotube array; The active region is a channel functional region surrounded by a continuous carbon nanotube-free region. The channel functional region retains the carbon nanotube strips required to form the channel conductivity, as well as the contact overlap area between the carbon nanotube strips and the source and drain electrodes. The carbon nanotube-free region is provided with a clearance margin δ around the channel functional region to suppress parasitic conduction and capacitive coupling between the carbon nanotubes outside the active region and the gate, source, drain electrodes, and pads.

2. The radio frequency transistor based on a directional semiconductor carbon nanotube array according to claim 1, characterized in that, The clearance margin δ is 0.45 to 10 μm; or, the clearance margin δ is 2 to 20 times the gate length Lg.

3. The radio frequency transistor based on a directional semiconductor carbon nanotube array according to claim 1, characterized in that, The carbon nanotube array has a semiconductor purity ≥99.99%, a packing density of 60–200 nanotubes / μm, and the array orientation is parallel to the width direction of the device; and The substrate is a high resistivity silicon substrate, and the insulating layer is a SiO2 layer thermally grown on the silicon substrate, with a thickness of 100–1000 nm. The gate dielectric layer is an HfO2 layer with a thickness of 3–8 nm; the gate metal layer is a Pd / Au stack or a Ti / Au stack. The contact metal between the source and drain electrodes is a Pd / Au stack with a total thickness of ≤40 nm.

4. The radio frequency transistor based on a directional semiconductor carbon nanotube array according to claim 1, characterized in that, The radio frequency transistor also includes a bridge structure on the drain side, which allows the gate metal to cross over to form an air gap on the drain side, thereby reducing gate-source parasitic capacitance and gate resistance.

5. The radio frequency transistor based on a directional semiconductor carbon nanotube array according to claim 1, characterized in that, The channel is designed as a multi-finger parallel structure with an exponent N≥2. The total channel width is the sum of the widths of each finger, and the carbon-free nanotube region surrounds the periphery of the entire multi-finger structure.

6. The radio frequency transistor based on a directional semiconductor carbon nanotube array according to claim 1, characterized in that, The source and drain are connected to the RF pads of the coplanar waveguide structure.

7. A method for fabricating a radio frequency transistor based on an array of oriented semiconductor carbon nanotubes as described in any one of claims 1-6, characterized in that, Includes the following steps: A directionally aligned semiconductor carbon nanotube array thin film is formed on a substrate with an insulating layer; The active region pattern is defined on the carbon nanotube array film by photolithography, and the carbon nanotubes outside the active region are removed by plasma etching to form a channel functional region surrounded by a continuous carbon nanotube-free region. The carbon nanotube-free region has a removal margin δ around the channel functional region. A gate dielectric layer is deposited on the channel functional region; A source and a drain are formed, and the source and drain respectively form electrical contacts with the carbon nanotube array; Forming a gate metal layer; And to form RF pads and interconnect structures.

8. The method according to claim 7, characterized in that, The plasma etching is inductively coupled plasma etching, with the etching gas including O2 at a flow rate of 10–40 sccm, the ICP source power being 200–600 W, the RF bias power being 0–100 W, the cavity pressure being 5–50 mTorr, and the etching time being 10–120 s; the etching gas also includes Ar at a flow rate of 5–20 sccm.

9. The method according to claim 7, characterized in that, The method further includes the step of forming a sacrificial layer bridge structure on the drain side, such that the formed gate metal crosses the sacrificial layer bridge structure on the drain side, and forming an air bridge gap after removing the sacrificial layer.

10. The method according to claim 9, characterized in that, The sacrificial bridge structure is made of polymethyl methacrylate and is formed by spin coating and photolithography, with a thickness of 200–600 nm.

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