A semiconductor structure and a method of fabricating the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The semiconductor structure preparation method comprises the following steps: arranging a plurality of first components on a first carrier plate; arranging a plastic sealing film layer on the first carrier plate; the plastic sealing film layer is a pre-formed film layer, and the thickness of the plastic sealing film layer is smaller than that of the first component; the plastic sealing film layer covers the first component and the exposed area of the first carrier plate; and a metal layer is formed outside the plastic sealing film layer. The preparation method of the semiconductor structure is advantageous in improving the reliability of the semiconductor packaging structure by introducing the pre-formed plastic sealing film layer arranged on the first component, and the thickness of the plastic sealing film layer is smaller than that of the first component.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In semiconductor product packaging, leadframes or pre-installed PCB substrates are commonly used for chip lead-out. However, this type of packaging process suffers from a series of problems, including low package reliability and difficulties in product iteration (each product requires a corresponding leadframe design). Related technologies employ wiring to electrically lead out the chip. This method typically utilizes a carrier board. After the chip and other components are placed on the carrier board, molding compound is filled to form a relatively thick encapsulation layer covering the chip and other components, allowing for electrical lead-out via wiring. However, during the packaging process, a thick encapsulation layer can interfere with the placement of structural layers, such as wiring layers or shielding layers, on the side of the encapsulation layer facing away from the chip. Summary of the Invention

[0003] This application provides a method for fabricating a semiconductor structure, comprising:

[0004] Multiple first components are spaced apart on the first carrier board;

[0005] A molding compound layer is provided on the first carrier board; the molding compound layer is a pre-formed film layer and its thickness is less than that of the first component;

[0006] A metal layer is formed outside the plastic sealant layer.

[0007] In some embodiments, the first component has a front side and a back side, and the front side is provided with solder pads; the step of spacing the plurality of first components on the first carrier plate includes:

[0008] Multiple first components are disposed on the first carrier plate with their backs facing the first carrier plate at intervals.

[0009] In some embodiments, after forming a metal layer outside the molding compound layer, the method includes:

[0010] The metal layer is patterned to form a lead layer; the lead layer is electrically connected to the solder pad on the front side of the first component.

[0011] In some embodiments, after patterning the metal layer to form a lead layer, the method includes:

[0012] A first encapsulation layer is formed, which covers the lead layer and the exposed molding film layer;

[0013] Remove the first substrate to form a first intermediate semiconductor structure comprising a plurality of first components, a molding compound, a lead layer, and a first encapsulation layer.

[0014] In some embodiments, after removing the first carrier board, the method further includes:

[0015] The first intermediate semiconductor structure is flipped and disposed on the second carrier board;

[0016] A first wiring layer is provided, which is electrically connected to the lead layer.

[0017] In some embodiments, after the first intermediate semiconductor structure is flipped onto the second substrate and before the first wiring layer is formed, the method further includes:

[0018] The first intermediate semiconductor structure is thinned to expose the lead layer;

[0019] After the first wiring layer is set, the first wiring layer is directly connected to the lead layer;

[0020] Remove the second carrier plate.

[0021] In some embodiments, after forming the first encapsulation layer, the method further includes:

[0022] A through-hole is formed in the first encapsulation layer, through which the lead layer is exposed;

[0023] An electrical connection layer is provided on the side of the through hole and the first encapsulation layer opposite to each of the first components;

[0024] A second component is disposed on the side of the first encapsulation layer opposite to the plurality of first components, and the second component is connected to at least a portion of the plurality of first components through the electrical connection layer.

[0025] In some embodiments, the first component has a front side and a back side, and the front side is provided with solder pads; the step of spacing the plurality of first components on the first carrier plate includes:

[0026] Multiple first components are disposed on the first carrier plate with their front faces facing the first carrier plate at intervals; the metal layer serves as a shielding layer.

[0027] In some embodiments, after forming a metal layer outside the molding compound layer, the method includes:

[0028] A second encapsulation layer is formed, which covers the plastic sealant layer.

[0029] In some embodiments, after forming the second encapsulation layer, the method includes:

[0030] Remove the first substrate to form a second intermediate semiconductor structure comprising multiple first components, a molding film layer, a metal layer, and a second encapsulation layer;

[0031] The second intermediate semiconductor structure is flipped and placed on the third substrate;

[0032] A second wiring layer is provided, which is electrically connected to the solder pads on the front side of the first component.

[0033] This application also provides a semiconductor structure comprising:

[0034] The first package seal has a groove with an opening facing one side.

[0035] A first component; at least a portion of the first component is disposed within the groove; the first component has a front side and a back side, the front side being provided with solder pads; the front side of the first component faces the bottom of the groove.

[0036] A molding compound layer is at least partially located in the groove, and the portion located in the groove is located between the first component and the first encapsulation layer; the molding compound layer is a pre-formed film layer, and its thickness is less than the thickness of the first component;

[0037] A lead layer is disposed in the groove and on the side of the first encapsulation layer where the groove is located, and the lead layer is electrically connected to the solder pad on the front side of the first component.

[0038] A first wiring layer is disposed on the side of the first encapsulation layer where a groove is provided, and the first wiring layer is electrically connected to the lead layer.

[0039] This application also provides a semiconductor structure comprising:

[0040] The first package seal has a groove with an opening facing one side.

[0041] A first component; at least a portion of the first component is disposed within the groove; the first component has a front side and a back side, the front side being provided with solder pads; the front side of the first component faces the bottom of the groove.

[0042] A molding compound layer is at least partially located in the groove, and the portion located in the groove is located between the first component and the first encapsulation layer; the molding compound layer is a pre-formed film layer, and its thickness is less than the thickness of the first component;

[0043] A lead layer is disposed in the groove and on the side of the first encapsulation layer where the groove is located, and the lead layer is electrically connected to the solder pad on the front side of the first component.

[0044] A through-hole is located on one side of the front of the first component, and the lead layer is exposed through the through-hole;

[0045] An electrical connection layer is disposed in the through-hole and on the side of the first encapsulation layer opposite to each of the first components;

[0046] A second component is disposed on the side of the first encapsulation layer opposite to the plurality of first components, and the second component is connected to at least a portion of the plurality of first components through the electrical connection layer.

[0047] This application also provides a semiconductor structure comprising:

[0048] The second sealing layer has a groove with an opening facing one side;

[0049] At least one first component; at least a portion of each first component is disposed within one of the grooves; the first component has a front side and a back side, the front side being provided with solder pads; the back side of each first component faces the bottom of the groove.

[0050] A molding compound is located in the groove and on the surface of the second encapsulation layer on the side where the groove is located. The portion located in the groove is between the first component and the second encapsulation layer. The molding compound is a pre-formed film layer and its thickness is less than that of the first component.

[0051] A metal layer is disposed between the plastic sealant layer and the second encapsulation layer;

[0052] The second wiring layer is located on the front side of the first component and on the side of the molding compound layer opposite to the second encapsulation layer. The second wiring layer is electrically connected to the solder pads on the front side of the first component.

[0053] In some embodiments, the first component includes a chip; when the semiconductor structure includes a second component, the second component includes a passive component.

[0054] The main technical effects achieved by the embodiments of this application are:

[0055] The semiconductor structure and its fabrication method provided in this application introduce a pre-formed molding compound layer disposed on multiple first components, with the thickness of the molding compound layer being less than the thickness of the first components. This allows the multiple first components to be fixed to a carrier substrate as a whole by the thinner molding compound layer, facilitating the metal layer process on the molding compound layer. For components requiring wiring outside the molding compound layer, the thinner molding compound layer makes the opening process easier and more reliable in achieving electrical connection between the wiring and the chip. For components requiring a shielding layer outside the molding compound layer, the shielding layer can be well positioned on the bottom and outer sides of the chip, achieving better shielding performance. This also facilitates the placement of structural layers such as wiring layers or shielding layers, thereby improving the performance of the semiconductor packaging structure. Attached Figure Description

[0056] Figure 1 This is a flowchart of a semiconductor structure fabrication method provided in an exemplary embodiment of this application;

[0057] Figures 2 to 12 These are structural diagrams corresponding to different steps in the semiconductor structure fabrication process using an exemplary embodiment of this application.

[0058] Figures 13 to 16 These are structural diagrams corresponding to different steps in the process of preparing another semiconductor structure using a semiconductor structure fabrication method provided in an exemplary embodiment of this application;

[0059] Figures 17 to 18 These are structural diagrams corresponding to different steps in the process of preparing another semiconductor structure using a semiconductor structure preparation method provided in an exemplary embodiment of this application;

[0060] Figures 19 to 21 These are structural diagrams corresponding to different steps in the process of preparing another semiconductor structure using a semiconductor structure fabrication method provided in an exemplary embodiment of this application. Detailed Implementation

[0061] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0062] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0063] The following is in conjunction with the appendix Figures 1 to 21 The following describes some embodiments of this application in detail. Unless otherwise specified, the embodiments and features described below can be combined with each other.

[0064] Reference Figure 1 This application provides a method for fabricating a semiconductor structure, which includes the following steps S10 to S30:

[0065] In step S10, multiple first components are spaced apart on the first carrier board;

[0066] In step S20, a molding compound is applied to the first carrier board; the molding compound is a pre-formed film layer with a thickness less than that of the first component; the molding compound covers the first component and the exposed area of ​​the first carrier board.

[0067] In step S30, a metal layer is formed outside the plastic sealant layer.

[0068] The aforementioned semiconductor structure fabrication method introduces a pre-formed molding compound layer disposed on multiple first components, with the thickness of the molding compound layer being less than the thickness of the first components. This allows the multiple first components to be fixed to a carrier substrate as a whole by the thinner molding compound layer, facilitating the metal layer process on the molding compound layer. For components requiring wiring outside the molding compound layer, the thinner molding compound layer makes the opening process easier and more reliable in achieving electrical connections between the wiring and the chip. For components requiring a shielding layer outside the molding compound layer, the shielding layer can be positioned well on the bottom and outer sides of the chip, achieving better shielding performance. This also facilitates the placement of structural layers such as wiring layers or shielding layers, thereby improving the performance of the semiconductor packaging structure.

[0069] First, please combine Figures 2 to 16 The method for preparing semiconductor structures using the aforementioned semiconductor structure is described in detail.

[0070] like Figure 2 As shown, in step S10, a plurality of first components 10 are spaced apart on the first carrier board 1001.

[0071] The plurality of first components 10 are spaced apart on the first carrier plate 1001 by means of an adhesive layer 2001. The adhesive layer 2001 is a temporary bonding adhesive and is removed at the same time as or after the removal of the first carrier plate 1001.

[0072] The first component 10 has a front side 11 and a back side 12, and the front side 11 is provided with solder pads 111. In this embodiment, the step of arranging a plurality of first components 10 at intervals on the first carrier board 1001 includes:

[0073] Multiple first components 10 are disposed on the first carrier plate 1001 with their back surfaces 12 facing the first carrier plate 1001 at intervals.

[0074] like Figure 3 As shown, in step S20, a molding compound layer 20 is formed on the first carrier board 1001. The molding compound layer 20 is a pre-formed film layer, and its thickness is less than the thickness of the first component 10. The molding compound layer 20 covers the exposed areas of the first component 10 and the first carrier board 1001.

[0075] The molding compound layer 20 can be an epoxy resin molding compound. It can be laminated onto the first component 10 and the first carrier board 1001 by vacuum lamination.

[0076] The thickness of the molding film layer 20 can be 200mm-25μm.

[0077] This step S20 can form different first components 10 into a whole through the plastic encapsulation film layer 20 to ensure the subsequent process.

[0078] like Figure 5 As shown, in step S30, a metal layer 3 is formed outside the molding compound 20. The metal layer can be formed using methods including metal layer growth processes.

[0079] like Figure 6 As shown, in some embodiments, after forming a metal layer outside the molding compound 20 in step S30, the method includes the following step S40:

[0080] In S40, the metal layer is patterned to form a lead layer 30; the lead layer 30 is electrically connected to the solder pad 111 on the front side 11 of the first component 10.

[0081] The metal layer can be patterned using an exposure and development method.

[0082] like Figure 4As shown, before the metal layer is formed, openings 201 can be created in the molding compound 20 using processes such as laser encapsulation to expose the solder pads 111. When the metal layer 3 is formed, a portion of the metal layer 3 fills the openings 201 to electrically connect with the solder pads 111.

[0083] The opening 201 can be a square hole with a length and width of 15um, or it can be an opening of any shape or size.

[0084] like Figure 7 and Figure 8 As shown, after patterning the metal layer to form the lead layer 30, the method includes steps S50 and S60:

[0085] In step S50, a first encapsulation layer 40 is formed. The first encapsulation layer 40 covers the lead layer 30 and the exposed molding compound layer 20, as shown below. Figure 7 As shown.

[0086] In step S60, the first carrier board 1001 is removed to form a first intermediate semiconductor structure including a plurality of first components 10, a molding compound layer 20, a lead layer 30, and a first encapsulation layer 40, i.e. Figure 8 The first intermediate semiconductor structure is shown.

[0087] like Figures 9 to 11 As shown, in some embodiments, after removing the first carrier plate 1001 in step S60, the method further includes steps S70 and S90.

[0088] like Figure 9 As shown, in step S70, the first intermediate semiconductor structure is flipped and disposed on the second carrier plate 1002.

[0089] The adhesive layer 2002 can be used to bond the following: Figure 8 The first intermediate semiconductor structure shown is disposed on the second carrier 1002.

[0090] like Figure 11 As shown, in step S90, a first wiring layer 50 is provided, and the first wiring layer 50 is electrically connected to the lead layer 30.

[0091] like Figure 10 As shown, in some embodiments, after the first intermediate semiconductor structure is flipped onto the second substrate 1002 and before the first wiring layer 50 is formed, the method further includes the following step S80:

[0092] In step S80, the first intermediate semiconductor structure is thinned to expose the lead layer 30.

[0093] Accordingly, after the first wiring layer 50 is set, the first wiring layer 50 is directly connected to the lead layer 30.

[0094] like Figure 12 As shown, after setting the first wiring layer 50, the method includes the following step S100: removing the second carrier board 1002 to form as shown. Figure 12 The semiconductor structure 100 shown.

[0095] The semiconductor structure 100 can be a diced semiconductor product.

[0096] It should be noted that, when fabricating the semiconductor structure 100, multiple first components 10 corresponding to one semiconductor structure 100 can be disposed on the carrier plate, or multiple first components 10 included in multiple semiconductor structures 100 can be disposed. Accordingly, after removing the second carrier plate, the method may further include slicing the structure after removing the second carrier plate to form one or more semiconductor structures 100.

[0097] Figure 12 The semiconductor structure 100 shown includes two first components 10. In practice, the semiconductor structure may also include one or more first components 10.

[0098] It should be noted that, in some other embodiments, the semiconductor structure 100 may also be part of an intermediate component of the entire board formed after packaging and wiring. Accordingly, it can be further divided to form corresponding semiconductor products.

[0099] This application also provides a semiconductor structure, combined with Figure 12 As shown, the semiconductor structure 100 may include a first encapsulation layer 40, a plurality of first components 10, a molding compound layer 20, a lead layer 30, and a first wiring layer 50.

[0100] The first package seal 40 has a groove 401 with an opening facing one side.

[0101] At least a portion of the first component 10 is disposed within the groove 401. The first component 10 has a front side 11 and a back side 12, and the front side 11 is provided with solder pads 111. The front side 11 of the first component 10 faces the bottom of the groove 401.

[0102] The molding compound 20 is at least partially located in the groove 401, and the portion located in the groove 401 is between the first component 10 and the first encapsulation layer 40. The molding compound 20 is a pre-formed film layer, and its thickness is less than the thickness of the first component 10.

[0103] In the formed semiconductor structure 100, the thickness direction of the first component 10 is consistent with the thickness direction T1 of the semiconductor structure 100.

[0104] It should be noted that during the fabrication of the semiconductor structure 100, a molding compound 20 is actually used to encapsulate the first component 10. The thickness direction of this molding compound 20 is not always consistent with the thickness direction T1 of the semiconductor structure 100. For example… Figure 12 As shown, the thickness direction of the plastic encapsulation layer 20 covering the peripheral portion of the first component 10 is the direction indicated by t1. This thickness direction t1 is not consistent with the thickness direction T1 of the semiconductor structure 100.

[0105] The lead layer 30 is disposed in the groove 401 and on the side of the first encapsulation layer 40 where the groove 401 is disposed. The lead layer 30 is electrically connected to the solder pad 111 on the front side 11 of the first component 10.

[0106] The first wiring layer 50 is disposed on the side of the first encapsulation layer 40 where the groove 401 is provided, and the first wiring layer 50 is electrically connected to the lead layer 30.

[0107] It should be noted that the first component 10 can be a chip, such as a chip with MOS or an IC chip.

[0108] A first wiring layer 50 may also be provided on the back side of the first component 10. For chips with MOS, solder pads may also be provided on the back side of the first component 10. Accordingly, the first wiring layer 50 can directly electrically lead out the solder pads on this side. For first wiring layers that do not have solder pads on the back side of the first component and have heat dissipation requirements, they may include a heat dissipation portion that does not have electrical leads out and is in direct contact with the back side of the first component. Of course, for first components where the back side cannot directly contact the first wiring layer 50, after the corresponding intermediate semiconductor structure is flipped, an insulating material layer such as a dielectric layer may be provided on the back side of the first component, and then the corresponding first wiring layer 50 may be provided.

[0109] The semiconductor structure 100 can be a diced semiconductor product. The semiconductor structure 100 can also be part of a complete board intermediate assembly formed after packaging and wiring. If the semiconductor structure is a diced semiconductor product, the semiconductor structure may also include one or more first components.

[0110] like Figures 13 to 16 As shown, in some other embodiments, the thinning operation of step S80 may not be performed between steps S70 and S90.

[0111] Accordingly, such as Figure 13As shown, through-holes 202 are formed in the molding compound layer 20, and then step S90 is performed to set the first wiring layer 50. After removing the second carrier board 1002, a structure as shown can be formed. Figure 16 The semiconductor structure 200 shown is different from the semiconductor structure 100 described above in that the first wiring layer 50 of the semiconductor structure 200 is partially disposed in the via 202 to connect with the lead layer 30.

[0112] It should be noted that the semiconductor structure 200 can be a diced semiconductor product. In fact, the semiconductor structure can also include one or more first components 10. The semiconductor structure 200 can also be part of an intermediate assembly of a complete board formed after packaging and wiring.

[0113] The following combination Figures 2 to 7 as well as Figure 17 and Figure 18 The method for fabricating other semiconductor structures using the described semiconductor structure is described in detail. After forming the first encapsulation layer 40, the method further includes steps S110, S120, and S130.

[0114] In step S110, a through hole 402 is formed in the first encapsulation layer 40, and the lead layer 30 is exposed through the through hole 402.

[0115] In step S120, an electrical connection layer 60 is provided on the side of the through hole 402 and the first encapsulation layer 40 facing away from each of the first components 10.

[0116] In step S130, a second component 70 is disposed on the side of the first encapsulation layer 40 away from the plurality of first components 10, and the second component 70 is connected to at least a portion of the plurality of first components 10 through the electrical connection layer 60.

[0117] The second component 70 can be a passive component, such as a resistor, capacitor, or inductor.

[0118] Accordingly, after removing the first carrier plate 1001, a structure such as Figure 18 The semiconductor structure 300 is shown.

[0119] It should be noted that after the first encapsulation layer 40 is formed, but before step S110, the first encapsulation layer 40 can be thinned to 50 μm or less from the surface of the first component 10, and then through holes can be formed by laser drilling.

[0120] The through hole can be a square hole with a length and width of 15μm, or it can be an opening of other shapes or sizes.

[0121] The semiconductor structure 300 can be a diced semiconductor product.

[0122] It should be noted that, when fabricating the semiconductor structure 300, multiple first components 10 corresponding to one semiconductor structure 300 can be disposed on the carrier plate, or multiple first components 10 included in multiple semiconductor structures 300 can be disposed. Accordingly, after removing the first carrier plate, the method may further include slicing the structure after removing the first carrier plate to form one or more semiconductor structures 300.

[0123] Figure 18 The semiconductor structure 300 shown includes two first components 10. In practice, the semiconductor structure may also include one or more first components 10.

[0124] In some other embodiments, the semiconductor structure 300 may also be part of an intermediate component of the entire board formed after packaging and wiring. Accordingly, it can be further divided to form corresponding semiconductor products.

[0125] This application also provides a semiconductor structure, which is suitable for... Figure 18 As shown, the semiconductor structure 300 may include a first encapsulation layer 40, a plurality of first components 10, a molding compound layer 20, a lead layer 30, and an electrical connection layer 60.

[0126] The first package seal 40 has a groove 403 with an opening facing one side.

[0127] At least a portion of the first component 10 is disposed within one of the recesses 403. The first component 10 has a front side 11 and a back side 12, the front side 11 having solder pads 111. The front side 11 of the first component 10 faces the bottom of the recess 403.

[0128] The molding compound 20 is at least partially located in the groove 403, and the portion located in the groove 403 is between the first component 10 and the first encapsulation layer 40. The molding compound 20 is a pre-formed film layer, and its thickness is less than the thickness of the first component 10.

[0129] In the formed semiconductor product 300, the thickness direction of the first component 10 is consistent with the thickness direction T2 of the semiconductor product 300.

[0130] It should be noted that during the fabrication of the semiconductor structure 300, a molding compound 20 is actually used to encapsulate the first component 10. The thickness direction of this molding compound 20 is not always consistent with the thickness direction T2 of the semiconductor structure 300. For example… Figure 18As shown, the thickness direction of the plastic encapsulation layer 20 covering the peripheral portion of the first component 10 is the direction indicated by t2. This thickness direction t2 is not consistent with the thickness direction T2 of the semiconductor product 300.

[0131] The lead layer 30 is disposed in the groove 403 and on the side of the first encapsulation layer 40 where the groove 403 is disposed. The lead layer 30 is electrically connected to the solder pad 111 on the front side 11 of the first component 10.

[0132] The first encapsulation layer 40 has a through hole 402 located on one side of the front side 11 of the first component 10, through which the lead layer 30 is exposed.

[0133] An electrical connection layer 60 is disposed in the through hole 402 and on the side of the first encapsulation layer 40 opposite to each of the first components 10.

[0134] The second component 70 is disposed on the side of the first encapsulation layer 40 opposite to the plurality of first components 10, and the second component 70 is connected to at least a portion of the plurality of first components 10 through the electrical connection layer 60.

[0135] It should be noted that the semiconductor structure 300 can be a diced semiconductor product. The semiconductor structure 300 can also be part of an intermediate component of a complete board formed after packaging and wiring. If the semiconductor structure is a diced semiconductor product, the semiconductor structure may also include one or more first components.

[0136] Please refer to the following: Figure 2 , Figure 3 as well as Figures 19 to 21 The preparation of some other semiconductor structures using the aforementioned semiconductor structure preparation method is described in detail.

[0137] In some embodiments, the first component 10 has a front side 11 and a back side 12, the front side 11 being provided with solder pads 111. Step S10, spacing the plurality of first components 10 on the first carrier board 1001, includes:

[0138] Multiple first components 10 are disposed on the first carrier plate 1001 with their front faces 11 facing the first carrier plate 1001 at intervals; the metal layer 3 serves as a shielding layer.

[0139] In some embodiments, after forming the metal layer 3 outside the molding compound 20 in step S30, the method includes the following step S140.

[0140] In step S140, a second encapsulation layer 80 is formed, which covers the plastic sealant layer 20.

[0141] In some embodiments, after forming the second encapsulation layer 80, the method includes steps S150 to S180.

[0142] In step S150, the first carrier plate 1001 is removed to form a second intermediate semiconductor structure including a plurality of first components 10, a molding compound 20, a metal layer 3 and a second encapsulation layer 80.

[0143] In step S160, the second intermediate semiconductor structure is flipped and disposed on the third carrier plate 1003. The second intermediate semiconductor structure can be disposed on the third carrier plate 1003 through the adhesive layer 2003.

[0144] In step S170, a second wiring layer 90 is provided, which is electrically connected to the pad 111 on the front side 11 of the first component 10.

[0145] In step S180, the third carrier plate 1003 is removed.

[0146] like Figure 21 As shown, accordingly, after removing the carrier plate, a structure can be formed as follows: Figure 21 The semiconductor structure shown is 400.

[0147] The semiconductor structure 400 can be a diced semiconductor product.

[0148] It should be noted that the semiconductor structure 400 may include one or more first components 10. Figure 21 An exemplary schematic diagram includes a semiconductor structure comprising a first component 10. When fabricating the semiconductor structure 400, one first component 10 corresponding to one semiconductor structure 400 can be disposed on a first carrier plate, or multiple first components 10 included in multiple semiconductor structures 400 can be disposed. Accordingly, after removing the third carrier plate 1003, the method may further include slicing the structure after removing the third carrier plate 1003 to form one or more corresponding semiconductor structures 400. The fabrication method for a semiconductor structure 400 comprising multiple first components 10 is similar.

[0149] It should be noted that, in some other embodiments, the semiconductor structure 400 may also be part of the intermediate component of the entire board formed after packaging and wiring. Accordingly, it can be further divided to form the corresponding semiconductor product.

[0150] This application also provides a semiconductor structure 400, combined with... Figure 21 As shown, the semiconductor structure 400 includes a second encapsulation layer 80, a first component 10, a molding compound 20, a metal layer 3, and a second wiring layer 90.

[0151] The second package seal 80 has a groove 801 with an opening facing one side.

[0152] At least a portion of the first component 10 is disposed within one of the grooves 801; the first component 10 has a front side 11 and a back side 12, the front side 11 being provided with solder pads 111; the back side 12 of the first component 10 faces the bottom of the groove 801.

[0153] The molding film layer 20 is located in the groove 801 and on the surface of the second encapsulation layer 80 on the side where the groove 801 is located. The portion located in the groove 801 is located between the first component 10 and the second encapsulation layer 80. The molding film layer 20 is a pre-formed film layer and its thickness is less than that of the first component 10.

[0154] In the formed semiconductor product 400, the thickness direction of the first component 10 is consistent with the thickness direction T3 of the semiconductor product 300.

[0155] It should be noted that during the fabrication of the semiconductor structure 400, a molding compound 20 is actually used to encapsulate the first component 10. The thickness direction of this molding compound 20 is not always consistent with the thickness direction T3 of the semiconductor structure 400. For example… Figure 18 As shown, the thickness direction of the plastic encapsulation layer 20 covering the peripheral portion of the first component 10 is the direction indicated by t3. This thickness direction t3 is not consistent with the thickness direction T3 of the semiconductor product 400.

[0156] The metal layer 3 is disposed between the plastic sealing film layer 20 and the second encapsulation layer 80.

[0157] The second wiring layer 90 is located on the front side 11 of the first component 10 and on the side of the molding compound 20 opposite to the second encapsulation layer 80. The second wiring layer 90 is electrically connected to the solder pads 111 on the front side 11 of the first component 10.

[0158] For a semiconductor structure comprising multiple first components 10, the second encapsulation layer of the semiconductor structure may include multiple recesses 801 with openings facing the same side, and correspondingly, at least a portion of each first component 10 is disposed within one of the recesses 801. The second wiring layer 90 may electrically lead out each first component individually, or may interconnect portions of the multiple first components 10, thereby providing electrical leads out.

[0159] The semiconductor structure 400 can be a diced semiconductor product. The semiconductor structure 400 can also be part of an intermediate component of a complete board formed after packaging and wiring. If the semiconductor structure is a diced semiconductor product, the semiconductor structure may also include one or more first components.

[0160] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0161] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Multiple first components are spaced apart on the first carrier board; A molding compound is disposed on the first carrier plate; the molding compound is a pre-formed film layer and its thickness is less than that of the first component; the molding compound covers the first component and the exposed area of ​​the first carrier plate; A metal layer is formed outside the plastic sealant layer.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The first component has a front and a back, and the front is provided with solder pads; the step of arranging a plurality of first components spaced apart on a first carrier plate includes: Multiple first components are disposed on the first carrier plate with their backs facing the first carrier plate at intervals.

3. The method for preparing the semiconductor structure as described in claim 2, characterized in that, After forming a metal layer outside the molding compound film layer, the method includes: The metal layer is patterned to form a lead layer; the lead layer is electrically connected to the solder pad on the front side of the first component.

4. The method for preparing the semiconductor structure as described in claim 3, characterized in that, After patterning the metal layer to form a lead layer, the method includes: A first encapsulation layer is formed, which covers the lead layer and the exposed molding film layer; Remove the first substrate to form a first intermediate semiconductor structure comprising a plurality of first components, a molding compound, a lead layer, and a first encapsulation layer.

5. The method for preparing the semiconductor structure as described in claim 4, characterized in that, After removing the first carrier plate, the method further includes: The first intermediate semiconductor structure is flipped and disposed on the second carrier board; A first wiring layer is provided, which is electrically connected to the lead layer.

6. The method for preparing a semiconductor structure as described in claim 5, characterized in that, After the first intermediate semiconductor structure is flipped onto the second substrate and before the first wiring layer is formed, the method further includes: The first intermediate semiconductor structure is thinned to expose the lead layer; After the first wiring layer is set, the first wiring layer is directly connected to the lead layer; Remove the second carrier plate.

7. The method for preparing a semiconductor structure as described in claim 4, characterized in that, After forming the first encapsulation layer, the method further includes: A through-hole is formed in the first encapsulation layer, through which the lead layer is exposed; An electrical connection layer is provided on the side of the through hole and the first encapsulation layer opposite to each of the first components; A second component is disposed on the side of the first encapsulation layer opposite to the plurality of first components, and the second component is connected to at least a portion of the plurality of first components through the electrical connection layer.

8. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The first component has a front and a back, and the front is provided with solder pads; the step of arranging a plurality of first components spaced apart on a first carrier plate includes: Multiple first components are disposed on the first carrier plate with their front faces facing the first carrier plate at intervals; the metal layer serves as a shielding layer.

9. The method for preparing a semiconductor structure as described in claim 8, characterized in that, After forming a metal layer outside the molding compound film layer, the method includes: A second encapsulation layer is formed, which covers the plastic sealant layer.

10. The method for preparing the semiconductor structure according to claim 9, characterized in that, After forming the second encapsulation layer, the method includes: Remove the first substrate to form a second intermediate semiconductor structure comprising multiple first components, a molding film layer, a metal layer, and a second encapsulation layer; The second intermediate semiconductor structure is flipped and placed on the third substrate; A second wiring layer is provided, which is electrically connected to the solder pads on the front side of the first component.

11. A semiconductor structure, characterized in that, include: First pack sealing layer; It has a groove with an opening facing one side; First component; At least a portion of the first component is disposed within the groove; the first component has a front side and a back side, the front side being provided with solder pads; the front side of the first component faces the bottom of the groove. A molding compound layer is at least partially located in the groove, and the portion located in the groove is located between the first component and the first encapsulation layer; the molding compound layer is a pre-formed film layer, and its thickness is less than the thickness of the first component; A lead layer is disposed in the groove and on the side of the first encapsulation layer where the groove is located, and the lead layer is electrically connected to the solder pad on the front side of the first component. A first wiring layer is disposed on the side of the first encapsulation layer where a groove is provided, and the first wiring layer is electrically connected to the lead layer.

12. A semiconductor structure, characterized in that, include: First pack sealing layer; It has a groove with an opening facing one side; First component; At least a portion of the first component is disposed within the groove; the first component has a front side and a back side, the front side being provided with solder pads; the front side of the first component faces the bottom of the groove. A molding compound layer is at least partially located in the groove, and the portion located in the groove is located between the first component and the first encapsulation layer; the molding compound layer is a pre-formed film layer, and its thickness is less than the thickness of the first component; A lead layer is disposed in the groove and on the side of the first encapsulation layer where the groove is located, and the lead layer is electrically connected to the solder pad on the front side of the first component. A through-hole is located on one side of the front of the first component, and the lead layer is exposed through the through-hole; An electrical connection layer is disposed in the through-hole and on the side of the first encapsulation layer opposite to each of the first components; A second component is disposed on the side of the first encapsulation layer opposite to the plurality of first components, and the second component is connected to at least a portion of the plurality of first components through the electrical connection layer.

13. A semiconductor structure, characterized in that, include: Second pack sealing layer; It has a groove with an opening facing one side; First component; At least a portion of the first component is disposed within the groove; the first component has a front side and a back side, the front side being provided with solder pads; the back side of the first component faces the bottom of the groove. A molding compound is located in the groove and on the surface of the second encapsulation layer on the side where the groove is located, wherein the portion located in the groove is between the first component and the second encapsulation layer; the molding compound is a pre-formed film layer and its thickness is less than the thickness of the first component; A metal layer is disposed between the plastic sealant layer and the second encapsulation layer; The second wiring layer is located on the front side of the first component and on the side of the molding compound layer opposite to the second encapsulation layer. The second wiring layer is electrically connected to the solder pads on the front side of the first component.

14. The semiconductor structure according to any one of claims 11 to 13, characterized in that, The first component includes a chip; when the semiconductor structure includes a second component, the second component includes a passive component.

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