Multiplication circuit, arithmetic circuit, and electronic device

Abstract

A multiplication circuit with reduced power consumption is provided. The multiplication circuit includes a first unit and a second unit. Both the first and second units are used as current source circuits. The first unit generates a first current based on the gate-source voltage of a first transistor, and the second unit generates a reference current based on the gate-source voltage of a second transistor. Furthermore, the multiplication circuit functions to change the reference current of the second unit to a second current, thereby amplifying the first current to a third current according to the ratio of the reference current to the second current. Additionally, to maintain the gate-source voltage of each of the first and second transistors, both the first and second units include switching sections. Each switching section includes a transistor connected in series and a capacitor connected between them.

Description

Technical Field

[0001] One aspect of the present invention relates to a multiplication circuit, an arithmetic circuit, and an electronic device.

[0002] Furthermore, one aspect of the present invention is not limited to the aforementioned technical fields. The technical fields of the invention disclosed in this specification relate to an object, a method of operation, or a method of manufacturing. Furthermore, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, specifically, examples of the technical fields of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, energy storage devices, imaging devices, storage devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for inspecting them. Background Technology

[0003] Currently, the development of integrated circuits modeled after the structure of the human brain is gaining momentum. These integrated circuits assemble electronic circuitry that mimics the brain's structure and include circuits that mimic "neurons" and "synapses." Therefore, such integrated circuits are sometimes referred to as "neuro-morphic," "brain-morphic," or "brain-inspired." These integrated circuits feature a non-von Neumann architecture, which, compared to the von Neumann architecture where power consumption increases with processing speed, promises to enable parallel processing with extremely low power consumption.

[0004] Data processing models that mimic neural networks, including "neurons" and "synapses," are called artificial neural networks (ANNs, sometimes simply referred to as neural networks in this specification). For example, Non-Patent Documents 1 and 2 disclose computing devices that use SRAM (Static Random Access Memory) to construct artificial neural networks.

[0005] In addition, there are studies that use computing devices constituting artificial neural networks, for example, for the correction of images displayed on display devices. For example, Patent Document 1 discloses a display device in which computing circuits constituting artificial neural networks are used to adjust the brightness, hue, etc. of the displayed image according to the preferences of the person viewing the image.

[0006] [Preliminary Technology Documents]

[0007] [Patent Literature]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2018-36639

[0009] [Non-patent literature]

[0010] [Non-Patent Literature 1] M. Kang et al., “IEEE Journal of Solid-State Circuits”, 2018, Volume 53, No.2, pp.642-655.

[0011] [Non-Patent Literature 2] J. Zhang et al., “IEEE Journal of Solid-State Circuits”, 2017, Volume 52, No.4, pp.915-924. Summary of the Invention

[0012] The technical problem that the invention aims to solve

[0013] The computational circuits constituting artificial neural networks mainly include circuits capable of performing product-sum operations. In particular, in multilayer artificial neural networks such as multilayer perceptrons, a large number of weight coefficients and neuron input data are multiplied, requiring numerous multiplication and addition circuits. Furthermore, in conventional computers, the results of multiplication or addition operations are temporarily written to storage devices and read back during subsequent operations; therefore, memory accesses occur frequently in artificial neural network operations. Thus, as an in-memory approach, the product-sum operation circuit preferably incorporates a storage circuit within the computational circuit to store the input data (multiplier, multiplicand, etc.) or the operation results.

[0014] As an example of this storage circuit, SRAM, with its high access speed, can be cited. However, since SRAM is volatile, the power consumption for holding data is high. Another example is a gain-cell type storage circuit, but since data is held by switching and capacitive elements, the data retention time depends on the characteristics of the switching elements. For example, the larger the off-state current of the switching elements, the faster the data degradation due to charge leakage. On the other hand, by reducing the off-state current of the switching elements, this data degradation can be suppressed. Therefore, in an in-memory product summation circuit, it is preferable to include a storage circuit with low power consumption and the ability to retain data for a long time.

[0015] One objective of this invention is to provide a multiplication circuit with reduced power consumption. Another objective of this invention is to provide a multiplication circuit with a small circuit area. Another objective of this invention is to provide a multiplication circuit capable of retaining data for extended periods. Another objective of this invention is to provide a novel multiplication circuit. Another objective of this invention is to provide an arithmetic circuit including the above-described multiplication circuit. Another objective of this invention is to provide an electronic device including the above-described arithmetic circuit.

[0016] Note that the purpose of one aspect of the present invention is not limited to the objectives described above. The above objectives do not preclude the existence of other objectives. Furthermore, other objectives are those not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract objectives not mentioned above from the description, drawings, etc. Moreover, one aspect of the present invention achieves at least one of the above and other objectives without necessarily achieving all of them.

[0017] means of solving technical problems (1)

[0019] One aspect of the present invention is a multiplication circuit comprising a first unit and a second unit. The first unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor element, and a second capacitor element. The second unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a third capacitor element, and a fourth capacitor element.

[0020] One of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor and the first terminal of the first capacitor element. The other of the source and drain of the second transistor is electrically connected to the gate of the third transistor and the first terminal of the second capacitor element. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the fourth transistor. One of the source and drain of the fifth transistor is electrically connected to one of the source and drain of the sixth transistor and the first terminal of the third capacitor element. The other of the source and drain of the sixth transistor is electrically connected to the gate of the seventh transistor and the first terminal of the fourth capacitor element. One of the source and drain of the seventh transistor is electrically connected to one of the source and drain of the eighth transistor. The other of the source and drain of the first transistor and the other of the source and drain of the fourth transistor are both electrically connected to the first wiring. The other of the source and drain of the fifth transistor, the other of the source and drain of the eighth transistor, the second terminal of the first capacitor element, the second terminal of the second capacitor element, the second terminal of the third capacitor element, and the second terminal of the fourth capacitor element are electrically connected to the second wiring. In addition, the gates of the first transistor, the second transistor, the fifth transistor, and the sixth transistor are electrically connected to the third wiring. (2)

[0022] One aspect of the present invention is a multiplication circuit that includes a first unit and a second unit, and is different from (1) described above. The first unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor element, and a second capacitor element. The second unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a third capacitor element, and a fourth capacitor element.

[0023] One of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor and the first terminal of the first capacitor element. The other of the source and drain of the second transistor is electrically connected to the gate of the third transistor and the first terminal of the second capacitor element. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the fourth transistor. One of the source and drain of the fifth transistor is electrically connected to one of the source and drain of the sixth transistor and the first terminal of the third capacitor element. The other of the source and drain of the sixth transistor is electrically connected to the gate of the seventh transistor and the first terminal of the fourth capacitor element. One of the source and drain of the seventh transistor is electrically connected to one of the source and drain of the eighth transistor. The other of the source and drain of the first transistor and the other of the source and drain of the fourth transistor are both electrically connected to the first wiring. The other of the source and drain of the fifth transistor, the other of the source and drain of the eighth transistor, the second terminal of the first capacitor element, the second terminal of the second capacitor element, the second terminal of the third capacitor element, and the second terminal of the fourth capacitor element are all electrically connected to the second wiring. Furthermore, the gates of the first transistor and the fifth transistor are electrically connected to the third wiring. Additionally, the gates of the second transistor and the sixth transistor are electrically connected to the fourth wiring. (3)

[0025] In (1) or (2) above, one aspect of the present invention may also have the following structure: the electrostatic capacitance value of the second capacitor element is greater than the electrostatic capacitance value of the first capacitor element, and the electrostatic capacitance value of the fourth capacitor element is greater than the electrostatic capacitance value of the third capacitor element. (4)

[0027] In the above (3), one aspect of the present invention may also have the following structure: the first transistor to the eighth transistor all contain oxide semiconductor in the channel forming region.

[0028] Furthermore, the oxide semiconductor preferably comprises one or more elements selected from indium, zinc, and element M. Element M is selected from one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. (5)

[0030] In (4) above, one embodiment of the present invention may also have the following structure: the second unit has the function of maintaining the gate potential of the seventh transistor by means of a reference current flowing through the source-drain of the seventh transistor, and the first unit has the function of maintaining the gate potential of the third transistor by means of a first current flowing through the source-drain of the third transistor. Particularly preferred is that the first unit has the following function: due to the capacitive coupling of the fourth capacitor element, the gate potential of the seventh transistor changes, causing the reference current flowing through the source-drain of the seventh transistor to change to a second current, thereby amplifying the first current flowing through the source-drain of the third transistor to a third current according to the ratio of the reference current to the second current. (6)

[0032] One aspect of the present invention is an operational circuit comprising multiple multiplication circuits, a first circuit, a second circuit, and a third circuit as described in (5) above. Each of the multiple multiplication circuits is electrically connected to the same first wiring, and each of the multiple multiplication circuits is electrically connected to different second wirings.

[0033] The first circuit has the function of generating a first current based on first data and inputting the first current through a first wiring into one of a plurality of multiplication circuits. The second circuit has the function of generating a second current based on second data and inputting the second current into a multiplication circuit electrically connected to one of a plurality of second wirings. The third circuit has the function of performing a nonlinear function operation on the sum of the third currents flowing through each of the plurality of multiplication circuits via the first wiring as input, thereby outputting the result. (7)

[0035] One aspect of the present invention is an electronic device comprising the computing circuit and the housing described in (6) above. (8)

[0037] One aspect of the present invention is a multiplication circuit that includes a first unit and a second unit, and is different from (1) and (2) above. The first unit includes K (K is an integer greater than or equal to 3) first transistors, second transistors, third transistors, K-1 first capacitor elements, and second capacitor elements. In addition, the second unit includes L (L is an integer greater than or equal to 3) fourth transistors, fifth transistors, sixth transistors, L-1 third capacitor elements, and fourth capacitor elements.

[0038] K first transistors are connected in series. Furthermore, in the K first transistors connected in series, the connection portion of any two consecutive first transistors is electrically connected to the first terminal of a first capacitor element.

[0039] One of the K first transistors connected in series is electrically connected to the gate of the second transistor and the first terminal of the second capacitor. Additionally, one of the source and drain of the second transistor is electrically connected to one of the source and drain of the third transistor. Furthermore, L fourth transistors are connected in series. In addition, the connection portion of any two consecutive fourth transistors in the series connection is electrically connected to the first terminal of a third capacitor. Furthermore, one of the L fourth transistors connected in series is electrically connected to the gate of the fifth transistor and the first terminal of the fourth capacitor. Additionally, one of the source and drain of the fifth transistor is electrically connected to one of the source and drain of the sixth transistor. Furthermore, the other of the K first transistors connected in series and the other of the source and drain of the third transistor are electrically connected to the first wiring. Furthermore, the other of the L fourth transistors connected in series, the other of the source and drain of the eighth transistor, each of the second terminals of the K-1 first capacitors, the second terminal of the second capacitor, each of the second terminals of the L-1 third capacitors, and the second terminal of the fourth capacitor are electrically connected to the second wiring. In addition, each of the gates of the K first transistors and each of the gates of the L fourth transistors are electrically connected to the third wiring. (9)

[0041] In the above (8), one aspect of the present invention may also have the following structure: the first transistor to the sixth transistor all contain oxide semiconductor in the channel forming region.

[0042] Furthermore, the oxide semiconductor preferably comprises one or more elements selected from indium, zinc, and element M. Element M is selected from one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. (10)

[0044] In the above (9), one embodiment of the present invention may also have the following structure: the second unit has the function of maintaining the gate potential of the fifth transistor by means of a reference current flowing through the source-drain of the fifth transistor, and the first unit has the function of maintaining the gate potential of the second transistor by means of a first current flowing through the source-drain of the second transistor. Particularly preferred is that the first unit has the following function: due to the capacitive coupling of the fourth capacitor element, the gate potential of the fifth transistor changes, causing the reference current flowing through the source-drain of the fifth transistor to change to a second current, thereby amplifying the first current flowing through the source-drain of the second transistor to a third current according to the ratio of the reference current to the second current. (11)

[0046] One aspect of the present invention is an operational circuit comprising a plurality of multiplication circuits, a first circuit, a second circuit, and a third circuit as described above (10). Each of the plurality of multiplication circuits is electrically connected to the same first wiring. In addition, each of the plurality of multiplication circuits is electrically connected to a plurality of different second wirings.

[0047] The first circuit has the function of generating a first current based on first data and inputting the first current through a first wiring into one of a plurality of multiplication circuits. The second circuit has the function of generating a second current based on second data and inputting the second current into a multiplication circuit electrically connected to one of a plurality of second wirings. The third circuit has the function of performing a nonlinear function operation on the sum of the third currents flowing through each of the plurality of multiplication circuits via the first wiring as input, thereby outputting the result. (12)

[0049] One aspect of the present invention is an electronic device comprising the computing circuit and the housing described in (11) above.

[0050] Invention Effects

[0051] According to one aspect of the present invention, a multiplication circuit with reduced power consumption can be provided. Additionally, according to one aspect of the present invention, a multiplication circuit with a small circuit area can be provided. Furthermore, according to one aspect of the present invention, a multiplication circuit capable of retaining data for a long period can be provided. Furthermore, according to one aspect of the present invention, a novel multiplication circuit can be provided. Furthermore, according to one aspect of the present invention, an arithmetic circuit including the above-described multiplication circuit can be provided. Furthermore, according to one aspect of the present invention, an electronic device including the above-described arithmetic circuit can be provided.

[0052] Note that the effects of one aspect of the present invention are not limited to those described above. The above-described effects do not preclude the existence of other effects. Furthermore, other effects are those not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract effects not mentioned above from the description, drawings, etc. Moreover, one aspect of the present invention has at least one of the above-described effects and other effects. Therefore, one aspect of the present invention may sometimes lack the effects listed above, depending on the circumstances.

[0053] Brief description of the attached figures

[0054] Figure 1A and Figure 1B This is a circuit diagram illustrating an example of the structure of a multiplication circuit.

[0055] Figure 2 This is a circuit diagram illustrating an example of the structure of a multiplication circuit.

[0056] Figure 3A and Figure 3B This is a circuit diagram illustrating an example of the structure of a multiplication circuit.

[0057] Figure 4A and Figure 4B This is a circuit diagram illustrating an example of the structure of a multiplication circuit.

[0058] Figure 5 This is a circuit diagram showing an example of the structure of an operational circuit.

[0059] Figures 6A to 6C This is a circuit diagram illustrating an example of the structure of the circuits included in an operational circuit.

[0060] Figures 7A to 7D This is a circuit diagram illustrating an example of the structure of the circuits included in an operational circuit.

[0061] Figures 8A to 8C This is a block diagram illustrating an example of the structure of the circuits included in an operational circuit.

[0062] Figures 9A to 9C This is a diagram illustrating a neural network.

[0063] Figure 10A and Figure 10B This is a block diagram illustrating an example of the structure of the circuits included in an operational circuit.

[0064] Figure 11 This is a block diagram illustrating an example of the structure of a computing device.

[0065] Figure 12A and Figure 12B This is a block diagram illustrating an example of the structure of the circuits included in an arithmetic unit.

[0066] Figure 13A and Figure 13B This is a block diagram illustrating an example of the structure of the circuits included in an arithmetic unit.

[0067] Figure 14A This is a block diagram illustrating an example of the structure of the circuits included in an arithmetic unit. Figure 14B and Figure 14C This is a circuit diagram illustrating an example of the structure of a memory cell.

[0068] Figures 15A to 15C This is a circuit diagram illustrating an example of the structure of the circuits included in an arithmetic unit.

[0069] Figure 16 This is a diagram illustrating an example of a convolutional neural network.

[0070] Figure 17 This is a diagram illustrating an example of convolution processing.

[0071] Figure 18This is a diagram illustrating an example of convolution processing.

[0072] Figure 19 This is a timing diagram illustrating a working example of convolution processing in a computing device.

[0073] Figure 20A and Figure 20B This is a diagram illustrating an example of pooling processing.

[0074] Figure 21A and Figure 21B This is a block diagram illustrating an example of the structure of the circuits included in an arithmetic unit.

[0075] Figure 22 This is a three-dimensional schematic diagram showing an example of the structure of a computing device.

[0076] Figure 23 This is a block diagram illustrating an example of the structure of a computing device.

[0077] Figure 24 This is a block diagram illustrating an example of the structure of a computing device.

[0078] Figure 25 This is a cross-sectional schematic diagram showing an example of the structure of a computing device.

[0079] Figure 26A and Figure 26B This is a three-dimensional schematic diagram showing an example of a transistor structure.

[0080] Figure 27A and Figure 27B This is a three-dimensional schematic diagram showing an example of a transistor structure.

[0081] Figure 28A This is a planar schematic diagram showing an example of a transistor structure. Figures 28B to 28D This is a cross-sectional schematic diagram showing an example of a transistor structure.

[0082] Figure 29A and Figure 29B This is a three-dimensional schematic diagram showing an example of a transistor structure.

[0083] Figures 30A to 30C This is a cross-sectional schematic diagram showing an example of a transistor structure.

[0084] Figure 31A This is a planar schematic diagram showing an example of a transistor structure. Figures 31B to 31D This is a cross-sectional schematic diagram showing an example of a transistor structure.

[0085] Figure 32A and Figure 32B This is a three-dimensional schematic diagram showing an example of a transistor structure.

[0086] Figure 33 This is a cross-sectional schematic diagram showing an example of the structure of a computing device.

[0087] Figure 34A This is a plan view illustrating an example of the structure of a computing device. Figure 34B This is a plan view illustrating an example of the structure of a computing device.

[0088] Figure 35 This is a cross-sectional schematic diagram showing an example of the structure of a computing device.

[0089] Figure 36 This is a three-dimensional schematic diagram showing an example of the structure of a computing device.

[0090] Figure 37A and Figure 37B It is a diagram showing the hierarchy of various storage devices.

[0091] Figures 38A to 38D This is a diagram showing an example of an electronic component.

[0092] Figure 39A and Figure 39B This is a diagram illustrating an example of an electronic device. Figure 39C This is a diagram illustrating an example of a large computer.

[0093] Figure 40 This is a diagram illustrating an example of a space device.

[0094] Figure 41 This is a diagram illustrating an example of a secondary storage system that can be applied to a data center.

[0095] Figure 42A and Figure 42B This is a circuit diagram illustrating the circuit model used for the simulation described in the embodiments.

[0096] Figure 43 This is a graph showing the holding time of the potentials in the simulation results illustrated in the embodiments.

[0097] Figure 44 This is a circuit diagram illustrating the circuit model used for the simulation described in the embodiments.

[0098] Figure 45A and Figure 45B This is a graph showing the holding time of the potentials in the simulation results illustrated in the embodiments.

[0099] Figures 46A1 to 46A7 and Figures 46B1 to 46B6 It is a circuit diagram used to illustrate electrical connections.

[0100] Methods of implementing the invention

[0101] In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as a circuit that includes semiconductor elements (e.g., transistors, diodes, and photodiodes) and a device that includes such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. An integrated circuit can be cited as an example of a semiconductor device. Furthermore, a chip incorporating an integrated circuit can also be cited as an example of a semiconductor device, as can an electronic component containing a chip in a package. Additionally, for example, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are sometimes semiconductor devices themselves, or sometimes include semiconductor devices.

[0102] In this specification, “connection” includes, for example, “electrical connection”.

[0103] When the connection relationship of circuit elements is represented as an "electrical connection" to define an object, "electrical connection" includes, for example, "direct connection" and "indirect connection". "Direct connection between A and B" means, for example, that A and B are connected without any circuit elements (such as transistors or switches, rather than wiring). On the other hand, "indirect connection between A and B" means, for example, that A and B are connected with one or more circuit elements.

[0104] Here, the definition of "A and B indirectly connected" refers to the following connection relationship: That is, when assuming the circuit is operating, if there is a sequence of events such as the exchange of electrical signals or the interaction of potentials between A and B during circuit operation, such a circuit can be defined as "A and B indirectly connected." Furthermore, even if there is no sequence of events where there is an exchange of electrical signals or the interaction of potentials between A and B, if there is an exchange of electrical signals or the interaction of potentials between A and B during circuit operation, it can still be defined as "A and B indirectly connected." Note that "A and B indirectly connected" defines the connection relationship of circuit elements as an object. Therefore, for example, even if the circuit is not operating because it is not supplied with a power supply voltage, the circuit can still be defined as "A and B indirectly connected" (note that, as an example, this is limited to the case where there is an exchange of electrical signals or the interaction of potentials between A and B during circuit operation when the circuit is supplied with a power supply voltage).

[0105] The following are specific examples of "indirect connection". First, as an example of "A and B are indirectly connected", there is the following... Figure 46A1 and Figure 46A2Examples of "indirect connection between A and B" include cases where A and B are connected via the source and drain of one or more transistors. Other examples of "indirect connection between A and B" include cases where A and B are connected via one or more switches. In the case of "indirect connection between A and B," assuming the circuit is operational, at least once a transistor between A and B is in an on-state, a conducting state, or a state where current can flow. Furthermore, the case of "indirect connection between A and B" also includes cases where one transistor between A and B is in a off-state or a non-conducting state. In the case of "indirect connection between A and B," when multiple transistors are connected between A and B, assuming the circuit is operational, at least once each of the multiple transistors between A and B is in an on-state, a conducting state, or a state where current can flow. That is, in the case of "indirect connection between A and B," multiple transistors do not necessarily need to be in an on-state, a conducting state, or a state where current can flow simultaneously. Therefore, the case of "indirect connection between A and B" includes cases where multiple transistors between A and B are in an off-state or a non-conducting state simultaneously or at different times. As another example, such as Figure 46A3 As shown, when A and C are connected through the source and drain of transistor TrP and B and C are connected through the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected", "B and C are indirectly connected", or "A and B are indirectly connected". Note that, as described below, when a fixed potential V is supplied to C from the power supply or GND, etc., although it can be said that "A and C are indirectly connected" or "B and C are indirectly connected", it is not possible to say that "A and B are indirectly connected".

[0106] The above examples illustrate situations where "indirect connection" can or cannot be described. However, the following examples show situations where "indirect connection" cannot be described. Even when electrical signals are exchanged or potentials interact between A and B during circuit operation, there are exceptions where "A and B are indirectly connected" cannot be described. An example of this exception is when A and B are connected through an insulator. That is, when A and B are connected through an insulator, "A and B are indirectly connected" cannot be described. Specific examples of A and B being connected through an insulator include... Figure 46A4 The example shown illustrates a capacitor connected between A and B. Other examples of A and B being connected via an insulator include... Figure 46A5 This refers to a situation where a gate insulating film of a transistor is sandwiched between A and B, as shown. In this case, it is not permissible to say that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected".

[0107] As another example where it's inappropriate to say "A and B are indirectly connected," cases where there is no exchange of electrical signals or interaction of electrical potentials between A and B can be cited. For example, the following situations exist: Figure 46A6 and Figure 46A7 As shown, along the path from A to B, multiple transistors are connected through their source and drain terminals, and the nodes between the transistors are supplied with a fixed potential V from the power supply or GND. In this case, although it cannot be said that "A and B are indirectly connected," it is possible to say that "A is indirectly connected to V" or "B is indirectly connected to V." Figure 46A3 In the case where A and C are connected through the source and drain of transistor TrP, and B and C are connected through the source and drain of transistor TrQ, and a fixed potential V is supplied to C from the power supply or GND, etc., it has the same characteristics as... Figure 46A6 and Figure 46A7 Since they are the same relationship, we cannot say "A is indirectly connected to B" but we can say "A is indirectly connected to C" or "B is indirectly connected to C".

[0108] Although the above examples of "indirect connection" are shown, the provisions of "indirect connection" are included in the provisions of "electrical connection", so in the case of "A and B are indirectly connected", it can be said that "A and B are electrically connected".

[0109] Next, specific examples of the "direct connection" case are shown. As an example of the case where "A and B are directly connected," such as... Figure 46B1 , Figure 46B2 and Figure 46B3 As shown, there are cases where A and B are not connected through circuit components. Furthermore, as... Figure 46B4 and Figure 46B5 As shown, when A and B are not connected to a power supply with a fixed potential V or GND via circuit components, it can be said that "A and B are directly connected", "A is directly connected to V", or "B is directly connected to V". Furthermore, as... Figure 46B6 As shown, even when A (or B) is connected to a fixed potential V through the source and drain of a transistor, it can be said that "A and B are directly connected". However, since A and V, or B and V, are connected through the source and drain of a transistor, it cannot be said that they are directly connected; instead, it can be said that "A and V are indirectly connected" or "B and V are indirectly connected".

[0110] Although the above examples show "direct connection", the definition of "direct connection" is included in the definition of "electrical connection", so in the case of "A and B are directly connected", it can be said that "A and B are electrically connected".

[0111] In this specification, the description of "multiple circuit elements connected in series" includes the case where multiple circuit elements are connected continuously by connecting the terminals of two adjacent circuit elements to each other. In addition, this connection also includes "electrical connection".

[0112] For example, the description of "K resistors (where K is an integer greater than or equal to 2) connected in series" includes the following cases: one terminal of the first resistor is connected to one terminal of the second resistor, another terminal of the kth resistor (where k is an integer greater than or equal to 2 and less than K-1) is connected to one terminal of the (k+1)th resistor, and the other terminal of the (K-1)th resistor is connected to one terminal of the Kth resistor. Similarly, the description of "K transistors (where K is an integer greater than or equal to 2) connected in series" includes the following cases: one of the source and drain of the first transistor is connected to one of the source and drain of the second transistor, the other of the source and drain of the kth transistor (where k is an integer greater than or equal to 2 and less than K-1) is connected to one of the source and drain of the (k+1)th transistor, and the other of the source and drain of the (K-1)th transistor is connected to one of the source and drain of the Kth transistor.

[0113] Furthermore, even when independent components are connected to each other in a circuit diagram, sometimes one component can function as multiple components. For example, when a portion of a wiring is used as an electrode, a conductive film functions as both a wiring and an electrode. Therefore, the term "connection" in this specification also includes such cases where a conductive film functions as multiple components.

[0114] In this specification, etc., a "resistive element" can be, for example, a circuit element having a resistance value greater than 0Ω or a wiring having a resistance value greater than 0Ω. Therefore, in this specification, a "resistive element" includes wiring having a resistance value, a transistor, a diode, or a coil through which current flows between the source and drain. Therefore, "resistive element" can sometimes be referred to as "resistor," "load," or "area having a resistance value." In contrast, "resistor," "load," or "area having a resistance value" can sometimes be referred to as "resistive element." As for the resistance value, it is preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Furthermore, it can also be 1Ω or more and 1×10⁻⁶. 9 Below Ω.

[0115] In this specification, etc., "capacitor element" can be, for example, a circuit element having an electrostatic capacitance value higher than 0F, a wiring area having an electrostatic capacitance value higher than 0F, a parasitic capacitance, or the gate capacitance of a transistor. Furthermore, "capacitor element," "parasitic capacitance," or "gate capacitance" can sometimes be referred to simply as "capacitor." In contrast, "capacitor" can sometimes be referred to simply as "capacitor element," "parasitic capacitance," or "gate capacitance." Furthermore, a "capacitor element" (including a "capacitor element" with three or more terminals) comprises an insulator and a pair of conductors holding the insulator. Thus, the "pair of conductors" of a "capacitor" can be referred to simply as a "pair of electrodes," a "pair of conductive regions," a "pair of regions," or a "pair of terminals." Furthermore, "one of the pair of terminals" and "the other of the pair of terminals" are sometimes referred to as the first terminal and the second terminal, respectively. Furthermore, the electrostatic capacitance value can be, for example, 0.05fF or more and 10pF or less. Furthermore, for example, it can also be 1pF or more and 10μF or less.

[0116] In addition, in this specification, a switch refers to a component that controls whether current flows by changing to an on or off state. Alternatively, a switch refers to a component that selects and switches the current path.

[0117] In this specification, "conducting state" refers to a state in which current may flow between the two input / output terminals, and "non-conducting state" refers to a state in which the two input / output terminals are electrically disconnected. Furthermore, in this specification, the open state of a switch falls within the category of "conducting state," and the closed state falls within the category of "non-conducting state." Therefore, in this specification, the "conducting state" and "open state" of the switch can be interchanged, as can the "non-conducting state" and "closed state."

[0118] Furthermore, switches sometimes include two or more terminals besides the control terminals, allowing current to flow through. As an example, electrical switches or mechanical switches can be used. In other words, a switch is not limited to a specific component as long as it has the function of controlling current.

[0119] Examples of electrical switches include transistors (such as bipolar transistors or MOS transistors), diodes (such as PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM) diodes, MIS (Metal-insulator-semiconductor) diodes, or diode-connected transistors), or logic circuits that combine these components. When a transistor is used as a switch, the "on state" or "turn-on state" of a transistor refers, for example, to the state where current can flow between the source and drain electrodes of the transistor. Conversely, the "off state" or "turn-off state" of a transistor refers to the state where the source and drain electrodes of the transistor are electrically disconnected. When a transistor is used solely as a switch, there are no particular restrictions on the transistor's polarity (conduction type).

[0120] As an example of a mechanical switch, a switch utilizing MEMS (microelectromechanical systems) technology can be cited. This switch has mechanically movable electrodes, and operates by controlling the on and off states through the movement of these electrodes.

[0121] In this specification, a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the switching between the transistor's on and off states. The two terminals used as the source or drain are the transistor's input and output terminals. Depending on the transistor's conductivity type (n-channel or p-channel) and the potential applied to the three terminals, one of the two input / output terminals is used as the source, and the other as the drain. Therefore, in this specification, the source and drain may sometimes be interchanged. In this specification, when describing the transistor's connection relationship, the terms "one of the source and drain" and "the other of the source and drain" are used. In this specification, sometimes one of the source and drain is referred to as the "first electrode of the transistor" or "first terminal of the transistor," and the other is referred to as the "second electrode of the transistor" or "second terminal of the transistor." Furthermore, depending on the transistor's structure, sometimes a back gate is included in addition to the three terminals mentioned above. In this case, in this specification, sometimes one of the transistor's gate and back gate is referred to as the first gate, and the other is referred to as the second gate. Furthermore, in the same transistor, the "gate" and "back gate" can sometimes be interchanged. In addition, when a transistor includes three or more gates, each gate is sometimes referred to as the first gate, the second gate, the third gate, etc. in this specification.

[0122] For example, as described in this specification, a multi-gate transistor with two or more gate electrodes can be used as an example of a transistor. When a multi-gate structure is used, since the channel forming regions are connected in series, it becomes a structure in which multiple transistors are connected in series. Therefore, by using a multi-gate structure, the off-state current can be reduced, and the transistor's voltage withstand capability (reliability) can be improved. Alternatively, by utilizing a multi-gate structure, when the transistor is operating in the saturation region, even if the voltage between the drain and source changes, the change in the drain and source current is not significant, thereby obtaining a voltage-current characteristic with a flat tilt angle. When utilizing a voltage-current characteristic with a flat tilt angle, an ideal current source circuit or an active load with extremely high resistance can be realized. As a result, differential circuits or current mirror circuits with good characteristics can be realized.

[0123] Furthermore, circuit diagrams illustrating a single circuit element sometimes include cases where that circuit element comprises multiple circuit elements. For example, a circuit diagram illustrating a resistor may include cases where two or more resistors are connected in series. Similarly, a circuit diagram illustrating a capacitor may include cases where two or more capacitors are connected in parallel. Likewise, a circuit diagram illustrating a transistor may include cases where two or more transistors are connected in series and their gates are connected to each other. Likewise, a circuit diagram illustrating a switch may include cases where the switch comprises two or more transistors connected in series or in parallel and their gates are connected to each other.

[0124] Furthermore, in this specification and other documents, the term "node" may also be referred to as terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit structure and device structure. Additionally, "terminal" and "wiring" may also be referred to as "node."

[0125] Furthermore, in this specification, etc., a selector sometimes refers to, for example, a circuit that includes multiple input terminals and one output terminal, and selects one from the multiple input terminals and establishes a conduction state between the selected input terminal and the output terminal. In other words, a selector sometimes refers to a circuit that selects one from each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, a selector sometimes refers to, for example, a circuit that includes multiple output terminals and one input terminal, and selects one from the multiple output terminals and establishes a conduction state between the selected output terminal and the input terminal. In other words, a selector sometimes refers to a circuit that selects one from multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. That is to say, a selector sometimes refers to a multiplexer or a multiplexer. In particular, in the case of inputting or outputting analog potentials or analog currents, a selector sometimes refers to an analog multiplexer or an analog multiplexer.

[0126] Furthermore, in this instruction manual and other documents, the terms "voltage" and "potential" may be interchanged as appropriate. "Voltage" refers to the potential difference between the reference potential and a reference potential. For example, when the reference potential is ground potential (grounding potential), "voltage" may also be referred to as "potential." Ground potential does not necessarily mean 0V. Furthermore, potential is relative; the potential supplied to wiring, the potential applied to circuits, and the potential output from circuits also change according to changes in the reference potential.

[0127] Furthermore, in this specification and other materials, "high-level potential" and "low-level potential" do not imply specific potentials. For example, if two wires are both labeled as "wires used to supply a high-level potential," the high-level potentials supplied to the two wires may be different. Similarly, if two wires are both labeled as "wires used to supply a low-level potential," the low-level potentials supplied to the two wires may be different.

[0128] Furthermore, "current" refers to the phenomenon of charge migration (conductivity). For example, the description "conductivity occurs in a positively charged body" can be replaced with the description "conductivity occurs in a negatively charged body in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge migration (conductivity) during charge carrier migration. Here, examples of charge carriers include electrons, holes, anions, cations, and complex ions, depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction of migration of positively charged charge carriers and is described as a positive current quantity. In other words, the direction of migration of negatively charged charge carriers is opposite to the direction of current and is described as a negative current quantity. Therefore, in this specification, unless otherwise specified, regarding the positive or negative (or direction) of the current, the description "current flows from element A to element B" can be replaced with the description "current flows from element B to element A." Furthermore, the description "current is input to element A" can be replaced with the description "current is output from element A."

[0129] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," and "third" are added to avoid confusion regarding the constituent elements. Therefore, these ordinal numbers do not limit the number of constituent elements. Furthermore, these ordinal numbers do not limit the order of the constituent elements. For example, in this specification and other documents, a "first" constituent element in one embodiment may be referred to as a "second" constituent element in other embodiments or claims. Furthermore, for example, in this specification and other documents, a constituent element referred to by "first" in one embodiment may be omitted in other embodiments or claims.

[0130] In this specification and other materials, for convenience, terms such as "upper" and "lower" are sometimes used to indicate the arrangement of components in conjunction with the accompanying drawings. Furthermore, the positional relationships of the components may be appropriately changed depending on the orientation in which each component is described. Therefore, the terminology used is not limited to that described in the specification and other materials, and may be appropriately replaced as needed. For example, if the description is "an insulator located on the top surface of a conductor," it can be changed to "an insulator located on the bottom surface of a conductor" by rotating the orientation of the shown drawings by 180°.

[0131] Furthermore, terms like "above" or "below" are not limited to situations where the constituent elements are directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed directly in contact with insulating layer A; it can also include situations where other constituent elements are included between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not necessarily mean that electrode B is formed directly in contact with insulating layer A; it can also include situations where other constituent elements are included between insulating layer A and electrode B. Likewise, the expression "electrode B below insulating layer A" does not necessarily mean that electrode B is formed directly in contact below insulating layer A; it can also include situations where other constituent elements are included between insulating layer A and electrode B.

[0132] Furthermore, in this specification and other materials, terms such as "row" and "column" are sometimes used to describe the matrix-like configuration of constituent elements and their positional relationships. Moreover, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to that described in the specification and other materials, and may be appropriately changed as needed. For example, by rotating the orientation of the accompanying drawings by 90°, the expression "row direction" may sometimes be replaced with "column direction."

[0133] Furthermore, in this specification and other materials, the terms "film" and "layer" may be interchanged depending on the context. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer." Additionally, depending on the situation, other terms may be used instead of "film" and "layer." For example, "conductive layer" or "conductive film" may sometimes be replaced with "conductor." Furthermore, "insulating layer" or "insulating film" may sometimes be replaced with "insulator."

[0134] Note that in this specification, the terms "electrode," "wiring," and "terminal" do not functionally limit their constituent elements. For example, sometimes "electrode" is used as part of "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as one unit. Additionally, for example, sometimes "terminal" is used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where one or more of "electrode," "wiring," and "terminal" are formed as one unit. Therefore, for example, an "electrode" can be part of "wiring" or "terminal," and vice versa. Furthermore, the terms "electrode," "wiring," or "terminal" are sometimes replaced with terms such as "area," depending on the context.

[0135] In this instruction manual and other documents, the terms "wiring," "signal line," or "power line" may be interchanged depending on the situation or circumstances. For example, sometimes "wiring" may be changed to "signal line." Similarly, sometimes "wiring" may be changed to "power line." Conversely, sometimes "signal line" or "power line" may be changed to "wiring." Sometimes "power line" may be changed to "signal line." Conversely, sometimes "signal line" may be changed to "power line." Furthermore, depending on the situation or circumstances, sometimes the "potential" applied to the wiring may be changed to "signal." Conversely, sometimes "signal" may be changed to "potential."

[0136] Furthermore, in this specification and the like, timing diagrams are sometimes used to describe the operation of semiconductor devices. Moreover, the timing diagrams used in this specification and the like show ideal operating examples, and unless otherwise specified, are not limited to the periods, signal (e.g., potential or current) magnitudes, and timing shown in the timing diagram. In the timing diagrams of this specification and the like, the magnitudes and timing of signals (e.g., potential or current) input to each wiring (including nodes) in the timing diagram can be changed according to the situation. For example, even if two periods are shown at equal intervals in the timing diagram, the lengths of the two periods may sometimes be different. Furthermore, for example, even if one period is shown to be longer than the other, the lengths of the two periods may sometimes be the same, or sometimes one period may be shorter than the other.

[0137] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when the channel formation region of a transistor contains a metal oxide, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide can form the channel formation region of a transistor that has at least one of amplification, rectification, and switching functions, the metal oxide can be called a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor.

[0138] Furthermore, in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Additionally, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0139] Furthermore, in this specification and the like, impurities in a semiconductor refer to substances other than the main components constituting the semiconductor layer. For example, elements with a concentration of less than 0.1 at.% are considered impurities. When impurities are present, one or more of the following may occur: increased defect state density, decreased carrier mobility, and decreased crystallinity in the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter the semiconductor properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, especially, for example, hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0140] In this specification, "parallel" means the angle between two straight lines is -10° or higher and less than 10°. Therefore, it also includes angles between -5° or higher and less than 5°. "Approximately parallel" means the angle between two straight lines is -30° or higher and less than 30°. Furthermore, "perpendicular" means the angle between two straight lines is 80° or higher and less than 100°. Therefore, it also includes angles between 85° or higher and less than 95°. "Approximately perpendicular" means the angle between two straight lines is 60° or higher and less than 120°.

[0141] Furthermore, the structures shown in each embodiment in this specification and the like can be appropriately combined with structures shown in other embodiments to constitute a mode of the present invention. Additionally, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0142] Furthermore, the content described in one embodiment (part or all of it) may be applied / combined / replaced with at least one of the other content described in that embodiment (part or all of it) and the content described in one or more other embodiments (part or all of it).

[0143] Note that the content described in the embodiments refers to the content illustrated using various accompanying drawings or the content described using the text in the specification.

[0144] Furthermore, more figures can be formed by combining the figures shown in one embodiment (part or all of them) with other parts of the figures, other figures shown in that embodiment (part or all of them), and at least one figure shown in one or more other embodiments (part or all of them).

[0145] The embodiments described in this specification are illustrated with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same symbols are sometimes used in different drawings to denote the same parts or parts having the same function, and repeated descriptions are omitted. In perspective views, etc., illustrations of some constituent elements are sometimes omitted for clarity.

[0146] In this specification and other materials, when multiple elements use the same symbol and it is necessary to distinguish them, symbols such as "_1", "[n]", and "[m,n]" are sometimes added to the symbol for identification. Furthermore, in the accompanying drawings and other materials, when symbols such as "_1", "[n]", and "[m,n]" are added to the symbol for identification, if it is not necessary to distinguish them in this specification or other materials, these symbols are sometimes omitted.

[0147] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate ideal examples and are not limited to the shapes or values ​​shown. For example, non-uniformity in signals, voltages, or currents caused by noise or timing deviations may be included.

[0148] (Implementation Method 1)

[0149] In this embodiment, a multiplication circuit of a semiconductor device as one aspect of the present invention is described.

[0150] <Existing multiplication circuit>

[0151] First, the multiplication circuit of the existing structure is explained.

[0152] Figure 2 The circuit structure shown is the structure of a multiplication circuit MP, which includes a multiplication unit IM and a driving unit IMD. The multiplication unit IM includes transistors F1, F2, and F5, and capacitor C5. The driving unit IMD includes transistors F1D, F2D, and F5D, and capacitor C5D.

[0153] In the multiplication unit IM, the first terminal of transistor F1 is connected to the gate of transistor F2 and the first terminal of capacitor C5. The gate of transistor F1 is connected to wiring WSL. Additionally, the first terminal of transistor F2 is connected to wiring VE0, and the second terminal of transistor F2 is connected to the first terminal of transistor F5. Furthermore, the second terminal of capacitor C5 is connected to wiring XCL. Additionally, the second terminals of transistors F1 and F5 are connected to wiring WCL. Finally, the gate of transistor F5 is connected to wiring VE1.

[0154] In the driving unit IMD, the first terminal of transistor F1D is connected to the gate of transistor F2D and the first terminal of capacitor C5D. The gate of transistor F1D is connected to wiring WSL. Additionally, the first terminal of transistor F2D is connected to wiring VE0, and the second terminal of transistor F2D is connected to the first terminal of transistor F5D. Furthermore, the second terminal of capacitor C5D is connected to wiring XCL. Additionally, the second terminals of transistors F1 and F5 are connected to wiring XCL. Finally, the gate of transistor F5 is connected to wiring VE1.

[0155] In addition, Figure 2 In the diagram, the connection between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 is denoted as node N, and the connection between the first terminal of transistor F1D, the gate of transistor F2D, and the first terminal of capacitor C5D is denoted as node ND.

[0156] In particular, transistors F1 and F1D function as switching transistors. Furthermore, transistor F1 is sometimes referred to as the write transistor in the multiplication unit IM, and transistor F1D as the write transistor in the drive unit IMD. Additionally, transistors F2 and F2D are transistors that operate in the subthreshold region.

[0157] Additionally, transistor F5 is used as a clamping transistor (sometimes called a clamping FET) to prevent drain-induced barrier lowering (DIBL) in transistor F2. Similarly, transistor F5D is used as a clamping transistor to prevent DIBL in transistor F2D. Therefore, the gates of transistors F5 and F5D are provided with a fixed potential for the range in which transistors F5 and F5D are used as clamping transistors. In other words, wiring VE1 is used as the wiring to supply this fixed potential.

[0158] The multiplication unit IM is used as a current generation circuit to generate a subthreshold current. For example, the fixed potential supplied to wiring VE0 is ground (GND). Furthermore, by supplying a high-level potential to wiring WSL, transistor F1 is turned on, and a subthreshold current flows through wiring WCL, which in turn flows through transistors F5 and F2 through wiring VE0. Since transistor F1 is turned on, the gate-source voltage of transistor F2 becomes the voltage corresponding to the amount I of the subthreshold current. Specifically, because the source potential of transistor F2 is ground, the gate potential is set to a value such that the amount of the source-drain current of transistor F2 is the amount I of the subthreshold current. Then, by supplying a low-level potential to wiring WSL, transistor F1 is turned off, and the gate potential of transistor F2 remains at the first terminal of capacitor C5. Since the gate-source voltage of transistor F2 is fixed, the multiplication unit IM becomes a current generation circuit that generates a subthreshold current of amount I flowing from wiring WCL to wiring VE0. Note that in this specification, this operation is referred to as "setting (programming) the current between the source and drain of transistor F2 flowing through the multiplication unit IM to I", etc.

[0159] Similar to the multiplication unit IM, the drive unit IMD is also used as a current generation circuit to generate the subthreshold current. For example, the fixed potential supplied to wiring VE0 is ground (GND). Furthermore, by supplying a high-level potential to wiring WSL, transistor F1D is turned on, and a subthreshold current flows through wiring XCL, which then flows through transistors F5D and F2D through wiring VE0. Since transistor F1D is turned on, the gate-source voltage of transistor F2D becomes the voltage corresponding to the amount I of the subthreshold current. Specifically, because the source potential of transistor F2D is ground, the gate potential is set to a value such that the amount of the source-drain current of transistor F2D is the amount I of the subthreshold current. Then, by supplying a low-level potential to wiring WSL, transistor F1D is turned off. The gate potential of transistor F2D is maintained at the first terminal of capacitor element C5D, and the gate-source voltage of transistor F2D is fixed. Therefore, in the driving unit IMD, the current I flowing through the source-drain of transistor F2D is set as the amount of current I. The driving unit IMD becomes a current generating circuit that allows the subthreshold current of amount I to flow. At this time, the potentials of nodes ND and wiring XCL are approximately equal.

[0160] Here, it is explained that Figure 2 The multiplication circuit MP shown performs the multiplication operation between w and x (both w and x are positive numbers including 0). First, consider the following case: I is set as the subthreshold current in the transistor F2D of the drive unit IMD. ref0 Next, in transistor F2 of the multiplication unit IM, wI is set as the amount of subthreshold current. ref0 Note that the "I" here... ref0 This refers to the amount of reference current flowing through transistors F2 and F2D when they operate in the subthreshold region. Here, this is determined by increasing or decreasing the reference current I flowing through wiring XCL. ref0 And make it xI ref0 The potential of the wiring XCL also changes accordingly, and the potential of node N also changes due to the capacitive coupling of the capacitor element C5 in the multiplication unit IM. At this time, the gate-source voltage of transistor F2 in the multiplication unit IM also changes, and the current flowing through the source-drain of transistor F2 becomes wxI. ref0 In other words, the multiplication unit IM will draw a current proportional to the product of w and x from wiring WCL to wiring VE0. Therefore, Figure 2 The multiplication circuit MP shown can perform multiplication of w and x.

[0161] In the multiplication unit IM, the first terminal (node ​​N) of capacitor C5 maintains a potential corresponding to the amount of subthreshold current flowing through the source-drain junction of transistor F2. Here, when transistor F1 is in the off state and its leakage current increases, the potential of the first terminal (node ​​N) of capacitor C5 changes, thus affecting the amount of subthreshold current flowing through the source-drain junction of transistor F2, which can sometimes influence the result of the multiplication operation. Furthermore, since leakage current flows through wiring WCL or wiring VE0, it can also sometimes affect the result of the multiplication operation.

[0162] Similarly, in the drive unit IMD, the first terminal (node ​​N) of capacitor C5D maintains a potential corresponding to the amount of subthreshold current flowing through the source-drain of transistor F2D. Here, when the leakage current of transistor F1D increases when F1D is in the off state, the potential of the first terminal (node ​​N) of capacitor C5D changes, so the potential of wiring XCL also changes, which may sometimes affect the result of the multiplication operation of multiplication unit IM.

[0163] <Multiplication circuit of the present invention>

[0164] One aspect of the semiconductor device of the present invention is a multiplication circuit that addresses the aforementioned issues and can prevent potential fluctuations at nodes N and ND due to charge leakage.

[0165] Figure 1A The multiplication circuit MPA shown is a semiconductor device according to one aspect of the present invention, which is to change... Figure 2 The circuit diagram shown in Figure 1 illustrates the structure of the multiplication circuit. The multiplication circuit MPA in Figure 1... Figure 2 The difference between the multiplication circuit MP and the multiplication circuit is that the multiplication unit IM has a switch SF1, and the drive unit IMD has a switch SF1D. Note that it can also be said that... Figure 1A The multiplication unit IM uses a switch SF1 instead of Figure 2 The structure of transistor F1 of the multiplication unit IM, and it can also be said that... Figure 1A The drive unit IMD uses a switch section SF1D instead of Figure 2 The structure of transistor F1D in the driving unit IMD.

[0166] exist Figure 1A In the multiplication unit IM, the switching section SF1 includes a capacitor C4, a transistor F1a, and a transistor F1b. Similarly, the switching section SF1D included in the drive unit IMD includes a capacitor C4D, a transistor F1Da, and a transistor F1Db. Therefore, in this specification, the switching section SF1 is sometimes referred to as the write switch in the multiplication unit IM, and the switching section SF1D is sometimes referred to as the write switch in the drive unit IMD.

[0167] The first terminal of transistor F1a is connected to the first terminal of transistor F1b and the first terminal of capacitor C4. The gates of transistors F1a and F1b are connected to wiring WSL. The second terminal of transistor F1a is connected to the second terminal of transistor F5 and wiring WCL. The second terminal of transistor F1b is connected to the gate of transistor F2 and the first terminal of capacitor C5. In other words, it is possible to... Figure 2 Replacing the second terminal of transistor F1 with the second terminal of transistor F1a can... Figure 2 Replacing the first terminal of transistor F1 with the second terminal of transistor F1b can... Figure 2 The gate of transistor F1 is replaced with the gates of transistors F1a and F1b.

[0168] Similar to the second terminal of capacitor C5, the second terminal of capacitor C4 is connected to wiring XCL.

[0169] The first terminal of transistor F1Da is connected to the first terminal of transistor F1Db and the first terminal of capacitor C4D. The gates of transistors F1Da and F1Db are connected to wiring WSL. The second terminal of transistor F1Da is connected to the second terminal of transistor F5D and wiring XCL. The second terminal of transistor F1Db is connected to the gate of transistor F2D and the first terminal of capacitor C5D. In other words, it is possible to... Figure 2 Replacing the second terminal of transistor F1D with the second terminal of transistor F1Da can... Figure 2 Replacing the first terminal of transistor F1D with the second terminal of transistor F1Db can... Figure 2 The gate of transistor F1D is replaced with the gates of transistors F1Da and F1Db.

[0170] Similar to the second terminal of capacitor element C5D, the second terminal of capacitor element C4D is connected to wiring XCL.

[0171] In addition, Figure 1A In this diagram, the connection between the first terminal of transistor F1a, the first terminal of transistor F1b, and the first terminal of capacitor C4 is described as node NS. Additionally, the connection between the first terminals of transistor F1Da, the first terminals of transistor F1Db, and the first terminal of capacitor C4D is described as node NSD.

[0172] Both switching units SF1 and SF1D have a structure in which two transistors are connected in series and their gates are connected to the same wiring. In other words, the two transistors included in each of switching units SF1 and SF1D are used as a single transistor. Furthermore, by connecting the two transistors in series, the channel length of the single transistor can be extended. By extending the channel length, the off-state current of the single transistor can be reduced, thus reducing the leakage current flowing through switching units SF1 and SF1D when they are in the off state.

[0173] As described above, the switching unit SF1 includes a capacitor element C4. Specifically, the first terminal of the capacitor element C4 is connected to the first terminals of both transistors F1a and F1b, so that when both transistors F1a and F1b are in the ON state, the potential of the second terminal of transistor F1a or the second terminal of transistor F1b can be written to the first terminal of the capacitor element C4. Furthermore, by switching each of transistors F1a and F1b from the ON state to the OFF state, this potential can be maintained in the first terminal of the capacitor element C4.

[0174] For example, by inputting a high-level potential from wiring WSL to the gate of each of transistors F1a and F1b, both transistors F1a and F1b can be turned on, allowing the potential of wiring WCL to be written to the first terminal (node ​​N) of capacitor C5 and the first terminal (node ​​NS) of capacitor C4. Furthermore, by maintaining a potential not only in the first terminal of capacitor C5 but also in the first terminal of capacitor C4, for example, even if the off-state current of transistor F1b increases due to a fault, fluctuations in the potential maintained at node N can be prevented. When the off-state current of transistor F1b increases, charge is distributed between the first and second terminals of transistor F1b, but the first terminal (node ​​NS) of capacitor C4 maintains almost the same potential as the first terminal (node ​​N) of capacitor C5, thus suppressing charge distribution as much as possible. As a result, the amount of potential fluctuation at node N can be reduced.

[0175] Similarly, in the switching section SF1D, the first terminal of the capacitor element C4D is connected to the first terminals of transistors F1Da and F1Db. Therefore, when both transistors F1Da and F1Db are in the ON state, the potential of the second terminal of transistor F1Da or the second terminal of transistor F1Db can be written to the first terminal of the capacitor element C4D. Furthermore, by switching each of transistors F1Da and F1Db from the ON state to the OFF state, this potential can be maintained in the first terminal of the capacitor element C4D.

[0176] Switching section SF1D has the same structure as switching section SF1, so switching section SF1D can achieve the same effect as switching section SF1. In switching section SF1D, by turning on both transistors F1Da and F1db, the potential of each write wiring XCL at the first terminal (node ​​N) of capacitor element C5 and the first terminal (node ​​NS) of capacitor element C4 can be controlled. In addition, the first terminal (node ​​NSD) of capacitor element C4D is maintained at approximately the same potential as the first terminal (node ​​ND) of capacitor element C5D, so even if the off-state current of transistor F1Db increases due to a fault, for example, the potential fluctuation maintained at node ND can be prevented.

[0177] In particular, transistors F1a and F1b included in the switching section SF1, and transistors F1Da and F1Db included in the switching section SF1D, are preferably OS transistors, for example. Specifically, the metal oxide included in the channel forming region of the OS transistor can be, for example, indium oxide, gallium oxide, and zinc oxide. Furthermore, the metal oxide preferably contains one or more selected from indium, element M, and zinc. Note that element M is selected from one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony. In particular, element M is preferably selected from one or more selected from aluminum, gallium, yttrium, and tin.

[0178] In particular, as the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also denoted as IGZO) is preferred. Alternatively, an oxide containing indium, tin, and zinc (also denoted as ITZO (registered trademark)) is preferred. Alternatively, an oxide containing indium, gallium, tin, and zinc is preferred. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also denoted as IAZO) is preferred. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also denoted as IAGZO) is preferred. The OS transistor will be described in detail in Embodiment 5.

[0179] Furthermore, the metal oxide contained in the channel formation region of the OS transistor preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider an oxide layer having a two-layer structure with a first layer and a second layer directly above the first layer. The atomic ratio of element M, relative to the main component metal element, in the metal oxide used in the first layer is preferably greater than the atomic ratio of element M, relative to the main component metal element, in the metal oxide used in the second layer. Furthermore, the atomic ratio of element M, relative to In, in the metal oxide used in the first layer is preferably greater than the atomic ratio of element M, relative to In, in the metal oxide used in the second layer. By employing this structure, the diffusion of impurities and oxygen from the structure formed beneath the first layer to the second layer can be suppressed.

[0180] Furthermore, the ratio of In atoms relative to element M in the metal oxide used in the second layer is preferably greater than the ratio of In atoms relative to element M in the metal oxide used in the first layer. By employing this structure, the OS transistor can achieve large on-state current and high-frequency characteristics.

[0181] Specifically, for example, as the metal oxide used for the first layer, a metal oxide with an In:M:Zn ratio of 1:3:2 or similar, an In:M:Zn ratio of 1:3:4 or similar, or an In:M:Zn ratio of 1:1:0.5 or similar can be used. Furthermore, as the metal oxide used for the second layer, a metal oxide with an In:M:Zn ratio of 1:1:1 or similar, an In:M:Zn ratio of 1:1:1.2 or similar, an In:M:Zn ratio of 1:1:2 or similar, or an In:M:Zn ratio of 4:2:3 or similar can be used. Note that "similar" includes a range of ±30% of the desired atomic ratio.

[0182] To reduce the off-state current of the transistor, an oxide containing In, Gallium (Ga), and Zinc (Zn) is preferably used as the metal oxide for the semiconductor layer. When the semiconductor layer of the transistor contains an oxide containing In, Gallium (Ga), and Zinc (Zn), the current flowing through each channel width of 1 μm between the source and drain when the gate-source voltage is 0V is 1 × 10⁻¹⁰ at room temperature (e.g., above 1°C and below 30°C). -20 Below A, at 85℃, it is 1×10 -18 A and below or at 125℃ is 1×10 -16Below A. Furthermore, as described above, in this specification, the condition where the current flowing through the source-drain junction is extremely small when the gate-source voltage of the transistor is 0V is referred to as normally off.

[0183] Thus, by using OS transistors for transistors F1a and F1b in the switching section SF1, the leakage current flowing through the switching section SF1 when it is in the off state can be reduced. In addition, even if the off-state current of transistor F1b increases, the potential fluctuation of the first terminal (node ​​N) of capacitor element C5 can be suppressed by the charge held in the first terminal (node ​​NS) of capacitor element C4.

[0184] Similarly, by using OS transistors for transistors F1Da and F1Db in the switching section SF1D, the leakage current flowing through the switching section SF1D when it is in the off state can be reduced. In addition, even if the off-state current of transistor F1Db increases, the potential fluctuation of the first terminal (node ​​ND) of capacitor element C5D can be suppressed by the charge held in the first terminal (node ​​NSD) of capacitor element C4D.

[0185] Furthermore, although the details are described in the embodiments, in the multiplication unit IM, by maintaining the potential of the first terminal (node ​​N) of capacitor C5 in the switching section SF1 including transistors F1a, F1b, and capacitor C4, when transistors F1a and F1b are simultaneously in the off state, the potential of node N can decrease more slowly than the potential of node NS. In other words, the potential of node N can be maintained for a longer period than the potential of node NS. Based on the results of the embodiments ( Figure 45A and Figure 45B It can be said that the larger the electrostatic capacitance of capacitor C4 is compared to that of capacitor C5, the longer the potential of node N is maintained. Therefore, by making the electrostatic capacitance of capacitor C4 greater than that of capacitor C5, a multiplication unit capable of maintaining the potential of node N for a long time can be manufactured. Note that the above describes the multiplication unit IM, but the driving unit IMD can achieve the same effect.

[0186] Furthermore, by reducing the leakage current of each of the switching sections SF1 and SF1D, the refresh operation required for the potentials of nodes N and ND can be reduced. Additionally, by reducing the refresh operation, the power consumption of the multiplication circuit can be reduced.

[0187] Furthermore, the higher the temperature of a transistor, the more easily its characteristics deteriorate. However, by using OS transistors for transistors F1a, F1b, F1Da, and F1Db, as described above, for example, it is possible to achieve a source-drain current of 1 × 10⁻⁶ when the transistor temperature is 125°C and the gate-source voltage is 0V. -16 Below A. In other words, it can be said that OS transistors are resistant to high temperatures, therefore multiplier circuits (MPAs) that include OS transistors can also operate stably at high temperatures.

[0188] Furthermore, transistors F2, F5, F2D, and F5D can also use the aforementioned OS transistors. By using OS transistors as transistors included in the multiplication circuit MPA, transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D can be manufactured simultaneously in the same process, thereby reducing the cycle time of the multiplication circuit MPA.

[0189] In particular, by using the OS transistor as one or both of transistors F2 and F2D, one or both of transistors F2 and F2D can operate over a wide current range in the subthreshold region, thereby reducing current consumption and expanding the range of values ​​of computable multiplication results.

[0190] Furthermore, transistors other than OS transistors can be used, selected from one or more of transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D. For example, transistors other than OS transistors can include transistors containing silicon in the channel formation region (hereinafter referred to as Si transistors). Additionally, examples of silicon include monocrystalline silicon, amorphous silicon, microcrystalline silicon, or polycrystalline silicon (including low-temperature polycrystalline silicon (LTPS)).

[0191] In addition, as transistors other than OS transistors and Si transistors, examples include transistors containing germanium in the channel formation region, transistors containing compound semiconductors such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in the channel formation region, transistors containing carbon nanotubes in the channel formation region, or transistors containing organic semiconductors in the channel formation region.

[0192] Note that although transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D shown in Figure 1 are all n-channel transistors, they can also be p-channel transistors depending on the situation. In other words, the polarities of the transistors listed above can be either n-channel or p-channel. Note that this specification describes each of transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D as an n-channel transistor, but when one or more of the transistors listed above are changed to p-channel transistors, the potential input to the multiplication circuit MPA needs to be appropriately changed in order for the multiplication circuit MPA to operate properly.

[0193] Note that variations in the polarity of the transistors described above are not limited to transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D. For example, the same applies to transistors described in other parts of the specification or those shown in other accompanying drawings.

[0194] <Example 1 of a variation of a multiplication circuit>

[0195] Alternatively, the operational circuit of one embodiment of the present invention may not employ [the aforementioned method]. Figure 1A The structure shown adopts Figure 1B The structure shown. Figure 1B The multiplication circuit MPA shown is Figure 1A The example of a variation of the multiplication circuit MPA shown includes wiring WSL, which includes wiring WSLa and wiring WSLb.

[0196] exist Figure 1B In the circuit, the gate of each of transistor F1a in switching unit SF1 and transistor F1Da in switching unit SF1D is connected to wiring WSLa. Additionally, the gate of each of transistor F1b in switching unit SF1 and transistor F1Db in switching unit SF1D is connected to wiring WSLb. Note that in... Figure 1B In this context, both WSLa and WSLb are collectively referred to as WSL.

[0197] By setting the wiring WSLa and wiring WSLb, the operating timing of the group of transistors F1a and F1Da can be made different from that of the group of transistors F1b and F1Db.

[0198] For example, in a room temperature environment with low off-state current, transistors F1b and F1Db are kept in the on state. Transistors F1a and F1Da are both switching transistors that switch between on and off states. This allows the potentials of nodes N and NS to be maintained in switching section SF1, and the potentials of nodes ND and NSD to be maintained in switching section SF1D. At this time, in switching section SF1, nodes N and NS are in a conducting state, combining the electrostatic capacitance values ​​of capacitors C4 and C5, thus maintaining the potentials of nodes N and NS for a longer period. The same applies to switching section SF1D.

[0199] For example, in high-temperature environments where the off-state current increases, as described above, by simultaneously switching the on and off states of transistors F1a and F1b in the switching section SF1, the off-state current of switch SF1 can be reduced. The same applies to switch SF1D.

[0200] <Example 2 of a variation of a multiplication circuit>

[0201] Alternatively, the operational circuit of one embodiment of the present invention may not employ [the aforementioned method]. Figure 1A The structure shown adopts Figure 3A The structure shown. Figure 3A The multiplication circuit MPA shown is Figure 1A The example of a variation of the multiplication circuit MPA shown includes transistors F1a, F1b, F1Da, and F1Db, all of which include a back gate.

[0202] Specifically, Figure 3A Transistors F1a, F1b, F1Da, and F1Db shown are, for example, transistors whose channels are located between two opposing gates. Each transistor includes a gate (sometimes referred to as a first gate) and a back gate (sometimes referred to as a second gate). Furthermore, the gate and back gate can be interchanged. Therefore, in this specification, "gate" can be referred to as "back gate." Similarly, "back gate" can be referred to as "gate." Specifically, the connection structure of "gate connected to the first wiring and back gate connected to the second wiring" can be replaced by the connection structure of "back gate connected to the first wiring and gate connected to the second wiring."

[0203] exist Figure 3AIn the multiplication circuit MPA, each of transistors F1a, F1b, F1Da, and F1Db has a structure in which the gate and back gate are connected to each other. In other words, the transistors listed above have a structure in which the potential input to the gate of the transistor is also input to the back gate of the transistor. Thus, by using transistors with the gate and back gate connected, the on-state current of the transistor can be increased, and the off-state current of the transistor can be decreased. For example, by increasing the on-state current of the transistor, the speed at which charge is stored in node N (node ​​ND) becomes faster, thereby increasing the write speed of the potential of the multiplication unit IM (driving unit IMD). Furthermore, for example, by decreasing the off-state current of the transistor, the leakage of charge from node N (node ​​ND) can be reduced, thus extending the potential holding time of the multiplication unit IM (driving unit IMD).

[0204] in addition, Figure 3A The structure of the multiplication circuit MPA can be changed to Figure 3B The structure of the multiplication circuit MPA is shown. Figure 3B The multiplication circuit MPA and Figure 3A The difference between the multiplication circuit MPA and the other circuit is that the back gate of each of transistors F1a, F1b, F1Da and F1Db is not connected to the gate of the transistor itself, but is connected to the wiring BGE.

[0205] By connecting wiring BGE to the back gate of each of transistors F1a, F1b, F1Da, and F1Db, a potential different from the potential supplied by wiring WSL can be supplied to the back gate of each of transistors F1a, F1b, F1Da, and F1Db via wiring BGE.

[0206] For example, by connecting an external circuit that outputs a specified potential to wiring BGE, that potential can be supplied to the back gate of each of transistors F1a, F1b, F1Da, and F1Db. Furthermore, by adjusting this potential, the threshold voltage of each of transistors F1a, F1b, F1Da, and F1Db can be varied. Specifically, by outputting a low-level potential, a negative potential, etc., from the external circuit to wiring BGE, the threshold voltage of each of transistors F1a, F1b, F1Da, and F1Db can be increased, and the on and off states of each of transistors F1a, F1b, F1Da, and F1Db can be switched by the potential supplied from wiring WSL. Alternatively, by outputting a high-level potential, a positive potential, etc., from the external circuit to wiring BGE, the threshold voltage of each of transistors F1a, F1b, F1Da, and F1Db can be reduced, and the on and off states of each of transistors F1a, F1b, F1Da, and F1Db can be switched by the potential supplied from wiring WSL.

[0207] Note that examples of changing a transistor to include a back gate structure are not limited to transistors F1a, F1b, F1Da, and F1Db. For example, it is also possible to... Figure 1A , Figure 1B , Figure 3A and Figure 3B Transistors F2, F5, F2D, and F5D shown may be modified to have transistors with back gates. Alternatively, transistors described in other parts of the specification or shown in other figures may also be modified to have back gates. Furthermore, transistors with back gates described in other parts of the specification may be modified to have transistors without back gates.

[0208] <Example 3 of a variation of a multiplication circuit>

[0209] Alternatively, the operational circuit of one embodiment of the present invention may not employ [the aforementioned method]. Figure 1A The structure shown adopts Figure 4A The structure shown. Figure 4A The multiplication circuit MPA shown has the following structure: Switching sections SF1 and SF1D do not include two transistors connected in series, but instead include k transistors connected in series (here, k is an integer of three or more). Furthermore, in Figure 4A In the switching sections SF1 and SF1D, a capacitor element is provided between two consecutively connected transistors. In other words, both the switching section SF1 and the switching section SF1D include k-1 capacitor elements.

[0210] Specifically, Figure 4A The switch unit SF1 shown includes transistors F1[1] to F1[k] and capacitor elements C4[1] to C4[k-1]. Additionally, Figure 4A The switch section SF1D shown includes transistors F1D[1] to F1D[k] and capacitor elements C4D[1] to C4D[k-1].

[0211] In the switching section SF1, transistors F1[1] to F1[k] are connected in series. Furthermore, the gates of each of transistors F1[1] to F1[k] are connected to wiring WSL. Additionally, the first terminal of capacitor C4[p] is connected between two consecutive transistors F1[p] (p being an integer greater than or equal to 1 and less than or equal to k-1) and transistor F1[p+1]. Furthermore, the second terminals of each of capacitors C4[1] to C4[k-1] are connected to wiring XCL.

[0212] Similarly, in the switching section SF1D, transistors F1D[1] to F1D[k] are connected in series. Furthermore, the gates of each of transistors F1D[1] to F1D[k] are connected to wiring WSL. Additionally, a capacitor C4D[p] is connected between two consecutive transistors F1D[p] and F1D[p+1]. Furthermore, the second terminals of each of capacitors C4D[1] to C4D[k-1] are connected to wiring XCL.

[0213] like Figure 4A As shown, in the switching section SF1, by having three or more transistors connected in series, the channel length can be substantially increased compared to... Figure 1A The switch section SF1 shown is long, which reduces leakage current in the off state. Furthermore, since a capacitor is provided between the two consecutive transistors, the first terminals of each capacitor can maintain approximately the same potential. Therefore, even if the off-state current of one or more transistors increases, almost no charge distribution occurs through that transistor, thus maintaining the potential of node N held by the switch section SF1 for a long time. Note that the same applies to the switch section SF1D.

[0214] exist Figure 4AIn the multiplication circuit MPA, the number of transistors in the switching section SF1 and the number of transistors in the switching section SF1D are equal. However, depending on the situation, the number of transistors in the switching section SF1 and the number of transistors in the switching section SF1D can be different. For example, when the multiplier held by the multiplication unit IM is frequently rewritten, in other words, when the multiplier does not need to be held at a potential for a long time in the multiplication unit IM, the number of transistors in the switching section SF1 of the multiplication unit IM can be less than the number of transistors in the switching section SF1D of the drive unit IMD. On the other hand, when the potential corresponding to the reference current does not need to be rewritten in the drive unit IMD, the drive unit IMD preferably holds that potential for a long time. Therefore, the number of transistors in the switching section SF1D of the drive unit IMD is preferably more than the number of transistors in the switching section SF1 of the multiplication unit IM.

[0215] Furthermore, the area occupied by the multiplication circuit MPA can be reduced by decreasing the number of transistors included in either the multiplication unit IM or the drive unit IMD.

[0216] in addition, Figure 4A The structure of the multiplication circuit MPA can be changed to Figure 4B The structure of the multiplication circuit MPA is shown. Figure 4B The multiplication circuit MPA and Figure 4A The difference in the multiplication circuit MPA is that: wiring WSL is provided with wiring WSLa and wiring WSLb; the gate of each of transistor F1[d] (d is an odd number greater than or equal to 1 and less than or equal to k) and transistor F1D[d] is connected to wiring WSLa; and the gate of each of transistor F1[e] (e is an even number greater than or equal to 2 and less than or equal to k) and transistor F1D[e] is connected to wiring WSLb. Additionally, in Figure 4B In this example, k is an even number.

[0217] and Figure 1B The multiplication circuit is the same. Figure 4B The multiplication circuit MPA can make the operating timing of the group of transistors F1[d] and F1D[d] different from that of the group of transistors F1[e] and F1D[e].

[0218] Therefore, for example, in a room temperature environment with low off-state current, transistors F1[e] and F1D[e] are kept in the on state. Since both transistors F1[d] and F1D[d] use switching transistors that switch between on and off states, the potential of node N can be maintained in the switching section SF1, and the potential of node ND can be maintained in the switching section SF1D.

[0219] For example, in high-temperature environments where the off-state current increases, as described above, by simultaneously switching the on and off states of transistors F1[d] and F1[e] in the switching section SF1, the off-state current of switch SF1 can be reduced. The same applies to switch SF1D.

[0220] Note that although a multiplication circuit has been described in this embodiment, it can also be applied to purposes other than multiplication. Examples of circuits other than multiplication include addition circuits and division circuits. Furthermore, as other examples, this multiplication circuit can also be applied to storage circuits, pixel circuits, amplification circuits, conversion circuits, and functional circuits.

[0221] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. In addition, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with configurations, structures, methods, etc. shown in other embodiments, etc.

[0222] (Implementation Method 2)

[0223] In this embodiment, an example of the structure of the operational circuit of the multiplication circuit MPA described in the above embodiment will be explained.

[0224] <Example of operational circuit structure>

[0225] Figure 5 The operational circuit ANP shown includes a cell array CA, circuit WSD, circuit WCS, circuit XCS, and circuit ITS. In particular, Figure 5 The circuit structures of the cell array CA, circuit WCS, circuit XCS, and circuit ITS are shown.

[0226] The cell array CA includes, for example, multiplication units IM[1,1] to IM[m,n] (where m and n are integers greater than or equal to 1) and driving units IMD_1 to IMD_m. The driving units IMD_1 to IMD_m and the multiplication units IM[1,1] to IM[m,n] are configured in a matrix within the cell array CA. Specifically, the driving units IMD_1 to IMD_m are arranged sequentially in the column direction, and the multiplication units IM[1,1] to IM[m,n] are configured as an m-row, n-column matrix.

[0227] In the i-th row (where i is an integer greater than or equal to 1 and less than or equal to m), any one of the driving unit IMD_i and multiplication units IM[i, 1] to IM[i, n] can be the multiplication circuit MPA described in Implementation 1. In the cell array CA, by using a driving unit IMD_i, a multiplication operation can be performed on each of the multiplication units IM[i, 1] to IM[i, n] arranged in the same i-th row.

[0228] In this embodiment, for simplicity, the structures of multiplication units IM[1,1] to IM[m,n] are identical. Therefore, sometimes the addresses of the same content in multiplication units IM[1,1] to IM[m,n] are omitted and referred to as multiplication unit IM. Similarly, the structures of driving units IMD_1 to IMD_m are identical, and sometimes the addresses of the same content in driving units IMD_1 to IMD_m are omitted and referred to as driving unit IMD.

[0229] exist Figure 5 In the arithmetic circuit ANP, the cell array CA, for example, has the function of performing a product sum operation on multiple first data written to multiple multiplication units IM and multiple second data sent from the circuit XCS to multiple arithmetic units. Note that in Figure 5 In the operational circuit ANP shown, each first data and each second data is a positive value or "0".

[0230] As an example, the multiplication unit IM is used as the unit for performing multiplication operations. Additionally, as an example, the driving unit IMD has the function of maintaining a potential corresponding to the reference data in order to perform operations in the multiplication unit IM. Note that the multiplication unit IM is the multiplication unit IM described in Embodiment 1, and the driving unit IMD is the driving unit IMD described in Embodiment 1. Furthermore, the reference data is the reference current I used to generate the reference current quantity I described in Embodiment 1. ref0 The data will be explained in detail later.

[0231] As an example, the multiplication unit IM includes a switch SF1, transistor F2, transistor F5, and capacitor C5. As another example, the drive unit IMD includes a switch SF1D, transistor F2D, transistor F5D, and capacitor C5D.

[0232] Regarding the switch section SF1 included in the multiplication unit IM and the switch section SF1D included in the drive unit IMD, please refer to the description of the switch section SF1 and the switch section SF1D described in Embodiment 1.

[0233] The structures (e.g., channel length, channel width, and shape) of transistors F2 included in each of the multiplication units IM[1,1] to IM[m,n] are preferably identical, and the structures of transistors F5 included in each of the multiplication units IM[1,1] to IM[m,n] are preferably identical. Furthermore, the structures of transistors F2D included in each of the driving units IMD_1 to IMD_m are preferably identical, and the structures of transistors F5D included in each of the driving units IMD_1 to IMD_m are preferably identical. Additionally, the structures of transistors F2 and F2D are preferably identical, and the structures of transistors F5 and F5D are preferably identical.

[0234] When transistors have identical structures, their electrical characteristics can be made approximately equal. Therefore, when the transistors F2 in multiplication units IM[1,1] to IM[m,n] each have identical structures, and the transistors F5 in multiplication units IM[1,1] to IM[m,n] each have identical structures, the multiplication units IM[1,1] to IM[m,n] can perform almost identical operations under the same conditions. Here, "identical conditions" refers, for example, to the potentials supplied to the source, drain, and gate of each transistor F2, the potentials supplied to the source, drain, and gate of each transistor F5, and the potentials input to multiplication units IM[1,1] to IM[m,n]. Similarly, when the transistors F2D in driving units IMD_1 to IMD_m each have identical structures, and the transistors F5D in driving units IMD_1 to IMD_m each have identical structures, the driving units IMD_1 to IMD_m can perform almost identical operations under the same conditions. Here, the same condition refers, for example, to the potentials supplied to the source, drain, and gate of each transistor F2D, the potentials supplied to the source, drain, and gate of each transistor F5D, and the voltages input to drive units IMD_1 to IMD_m.

[0235] Furthermore, unless otherwise specified, the cases where transistors F2 and F2D operate in the subthreshold region are included (in other words, in transistor F2 or F2D, the gate-source voltage is lower than the threshold voltage, and more preferably, the drain current increases exponentially with respect to the gate-source voltage). In other words, this includes cases where the gate, source, and drain voltages of each of the aforementioned transistors are appropriately biased so that the transistor operates in the subthreshold region. Therefore, this includes cases where transistors F2 and F2D operate with off-state current flowing between their source and drain.

[0236] Furthermore, transistors F5 and F5D are used, for example, as clamping transistors. Therefore, the gates of transistors F5 and F5D are preferably supplied with a fixed potential. Additionally, by providing transistor F5, DIBL in transistor F2 can be prevented, the details of which will be explained later. Similarly, by providing transistor F5D, DIBL in transistor F2D can be prevented.

[0237] On the other hand, if DIBL in transistor F2 can be ignored, transistor F5 can also be omitted in the multiplication unit IM. Similarly, if DIBL in transistor F2D can be ignored, transistor F5D can also be omitted in the drive unit IMD.

[0238] Regarding the transistors that can be used as transistors F2, F5, F2D, and F5D, refer to the description of transistors F2, F5, F2D, and F5D as described in Embodiment 1.

[0239] In the multiplication unit IM shown in Figure 1, the second terminal of transistor F1b is connected to the gate of transistor F2. The first terminal of transistor F2 is connected to wiring VE0. The first terminal of capacitor C5 is connected to the gate of transistor F2. The second terminal of transistor F2 is connected to the first terminal of transistor F5. Additionally, the second terminal of transistor F5 is connected to the second terminal of transistor F1a, and the gate of transistor F5 is connected to wiring VE1. Furthermore, the first terminals of transistors F1a and F1b are connected to the first terminal of capacitor C4.

[0240] Furthermore, in the multiplication unit IM shown in Figure 1, the second terminal of transistor F2 is connected in series with the wiring WCL through the first and second terminals of transistor F5. This prevents a high-level potential from being directly applied to the second terminal of transistor F2 from the wiring WCL. Therefore, DIBL in transistor F2 can be prevented.

[0241] In the multiplication unit IM, if the second terminal of transistor F2 is directly connected to wiring WCL (i.e., transistor F5 is not present), sometimes a high-level potential is directly applied to the second terminal of transistor F2 from wiring WCL, causing DIBL to occur in transistor F2. When DIBL occurs in transistor F2, the threshold voltage of transistor F2 decreases, thus sometimes changing the voltage range of the subthreshold region of transistor F2. Therefore, when transistor F5 is not present in the multiplication unit IM, the current flowing through the subthreshold region of transistor F2 sometimes fluctuates.

[0242] exist Figure 2In the driving unit IMD shown, the second terminal of transistor F1Db is connected to the gate of transistor F2D. The first terminal of transistor F2D is connected to wiring VE0. The first terminal of capacitor C5D is connected to the gate of transistor F2D. The second terminal of transistor F2D is connected to the first terminal of transistor F5D. Additionally, the second terminal of transistor F5D is connected to the second terminal of transistor F1Da, and the gate of transistor F5D is connected to wiring VE1. Furthermore, the first terminals of transistors F1Da and F1Db are connected to the first terminal of capacitor C4D.

[0243] Similar to transistor F5 in the multiplication unit IM, transistor F5D in the drive unit IMD also has the function of preventing DIBL in transistor F2D.

[0244] Wiring VE0 is used as the wiring between the first and second terminals of transistor F2 in the multiplication unit IM, allowing current to flow. Furthermore, wiring VE0 is used as the wiring between the first and second terminals of transistor F2D in the drive unit IMD, allowing current to flow. As an example, wiring VE0 is used as the wiring to supply a fixed potential. This fixed potential can be, for example, a low-level potential or a ground potential.

[0245] Wiring VE1 is used to apply potentials to the gate of transistor F5 in the multiplication unit IM and the gate of transistor F5D in the drive unit IMD, respectively. Note that this potential is preferably within the range where transistors F5 and F5D are used as clamping transistors.

[0246] exist Figure 5 In the cell array CA, in the Figure 1A When the multiplication unit IM is used as the multiplication unit IM[i,j] (not shown) located in the i-th row and j-th column, the second terminal of transistor F1a and the second terminal of transistor F5 are connected to wiring WCL_j, and the gates of transistor F1a and F1b are connected to wiring WSL_i. Additionally, the second terminal of capacitor C5 is connected to wiring XCL_i. Note that in Figure 5 In the multiplication unit IM[i,j], the switching part SF1 ( Figure 1A The connection between the second terminal of transistor F1b, the gate of transistor F2, and the first terminal of capacitor element C5 is node N[i,j].

[0247] In addition, in the Figure 1A The drive unit IMD is used as a drive unit located in Figure 5When driving cell IMD_i (not shown) in the i-th row of cell array CA, the second terminals of transistors F1Da and F5D are connected to wiring XCL_i, and the gate of transistor F1Da and transistor F1Db are connected to wiring WSL_i. Additionally, the second terminal of capacitor C5D is connected to wiring XCL_i. Note that in Figure 5 In the drive unit IMD_i, the switching section SF1 ( Figure 1A The connection between the second terminal of transistor F1Db, the gate of transistor F2D, and the first terminal of capacitor element C5D is node ND[i].

[0248] Nodes N[i, j] and ND[i] are used as hold nodes for each cell. Additionally, Figure 5 The abstract shows nodes N[1,1], N[1,n], N[m,1], N[m,n], ND[1], and ND[m].

[0249] [Circuit WSD]

[0250] The circuit WSD, for example, has the function of selecting a row of cell array CA that is configured with multiplication units IM as the object of writing when writing the first data. Additionally, when writing the first data, the drive unit IMD in the same row is selected, and reference data used to generate the reference current is written to the drive unit IMD.

[0251] Specifically, for example, in Figure 5 In this circuit, supplying a high-level potential to wiring WSL_1 and a low-level potential to wirings WSL_2 (not shown) to WSL_m via circuit WSD enables transistors F1a, F1b, F1Da, and F1Db, whose gates are connected to wiring WSL_1, to be turned on, while transistors F1a, F1b, F1Da, and F1Db, whose gates are connected to wirings WSL_2 to WSL_m, are turned off. In other words, it enables the write switches of the multiplication unit IM and the drive unit IMD, which are configured in the first row of the cell array CA1, to be turned on.

[0252] [Circuit WCS]

[0253] The circuit WCS, for example, has the following functions: it obtains first data as digital data from an external source, converts the first data into analog data (current quantity), and supplies the converted first data to the multiplication units IM included in the cell array CA. For example, when the circuit WCS writes the first data to the multiplication units IM[i,j] included in the cell array CA, after the circuit WSD selects the multiplication units IM[i,1] to IM[i,n] in the i-th row of the cell array CA, the circuit WCS supplies the first data to the arithmetic units in the first column of the cell array CA through wiring WCL_j.

[0254] The circuit WCS includes, for example, circuit SWCA and circuits WCSa_1 to WCSa_n.

[0255] For example, the circuit SWCA has the function of switching between the on and off states of the control wiring WCL_j (not shown) and the circuit WCSa_j (not shown).

[0256] The circuit SWCA includes, for example, switches SA_1 to SA_n.

[0257] The first terminal of switch SA_j (not shown) is connected to wiring WCL_j, the second terminal of switch SA_j is connected to circuit WCSa_j, and the control terminal of switch SA_j is connected to wiring SWLA.

[0258] For each of switches SA_1 to SA_n, an analog switch or an electrical switch such as a transistor can be used. In particular, it is preferable to use the aforementioned transistor as an electrical switch for each of switches SA_1 to SA_n, and even more preferably, an OS transistor. Note that when using an electrical switch for each of switches SA_1 to SA_n, a Si transistor, in addition to an OS transistor, can be used as the switch. Alternatively, each of switches SA_1 to SA_n can also be a mechanical switch.

[0259] Note that in this instruction manual, etc., Figure 5 Each of the switches SA_1 to SA_n shown is in the open state when a high-level potential is supplied to the control terminal and in the closed state when a low-level potential is supplied to the control terminal.

[0260] As an example, the wiring SWLA is used to switch the on and off states of switches SA_1 to SA_n. Therefore, the wiring SWLA is supplied with a high-level potential or a low-level potential.

[0261] In addition, circuit WCSa_1 is connected to wiring IWL_1, and circuit WCSa_n is connected to wiring IWL_n.

[0262] Circuit WCSa_j (not shown) has, for example, the function of obtaining first data from wiring IWL_j (not shown) and supplying a signal corresponding to that first data to wiring WCL_j. Specifically, circuit WCSa_j supplies the first data to be accommodated in any one of the multiplication units IM[1,j] to IM[m,j] arranged in the j-th column of the cell array CA when switch SA_j is in the open state. Note that in Figure 5 In the cell array CA, the signal is preferably analog data (current).

[0263] For example, circuit WCSa_j can have Figure 6A The structure shown. Note that in Figure 6A In order to show the connection between circuit WCSa_j and its surrounding circuits, circuit SWCA, switch SA_j, wiring SWLA and wiring WCL_j are also shown.

[0264] in addition, Figure 6A The switch SA_j shown is Figure 5 The circuit SWCA includes any one of switches SA_1 to SA_n. Similarly, wiring WCL_j is an extension set... Figure 5 Any one of the wirings WCL_1 to WCL_n in the cell array CA.

[0265] In other words, wiring WCL_j is connected to circuit WCSa_j through switch SA_j.

[0266] Figure 6A The circuit WCSa_j shown includes, for example, a switch SWW. The first terminal of switch SWW is connected to the second terminal of switch SA_j, and the second terminal of switch SWW is connected to wiring VINIL1. Wiring VINIL1 is used to supply an initialization potential to wiring WCL_j, which can be ground (GND), a low-level potential, or a high-level potential. Note that switch SWW is only in the on state when supplying an initialization potential to wiring WCL_j; otherwise, it is in the off state.

[0267] As a switch SWW, an electrical switch (e.g., an analog switch or a transistor) can be used. Alternatively, when using a transistor as a switch SWW, the transistor can be a transistor with the same structure as transistor F1 or transistor F2. In addition to electrical switches, mechanical switches can also be used.

[0268] Additionally, as an example, Figure 6A The circuit WCSa_j includes multiple current sources CS. Specifically, the circuit WCSa_j has M-bit (2 MThe first data output of the value (M is an integer greater than or equal to 1) is the function of current quantity. At this time, the circuit WCSa_j includes 2 M -1 current source CS. The circuit WCSa_j, for example, includes one current source CS that outputs the value of bit 0 as current, two current sources CS that output the value of bit 1 as current, and 2... M-1 A current source CS that outputs the value of the (M-1)th bit as current.

[0269] exist Figure 6A In the circuit, each current source CS includes a terminal U1 and a terminal U2. The terminal U1 of each current source CS is connected to the second terminal of the switch SA_j included in the circuit SWCA. In addition, the terminal U2 of one current source CS is connected to the wiring DW[0], and the terminals U2 of the two current sources CS are respectively connected to the wiring DW[1]. M-1 Terminal U2 of each current source CS is connected to wiring DW[M-1].

[0270] Multiple current sources CS in circuit WCSa_j have the same amount I Wut The function of outputting a constant current from terminal U1. Note that, in practice, during the manufacturing stage of the operational circuit ANP, errors sometimes occur due to fluctuations in the electrical characteristics of the transistors in each current source CS. Therefore, the amount of constant current I output from each of the multiple current sources CS at terminal U1 is different. Wut The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. Note that in this embodiment, it is assumed that the constant current I output from the terminal U1 of the plurality of current sources CS in the circuit WCSa_j is... Wut There is no error between them, so this is explained.

[0271] Wiring DW[0] to wiring DW[M-1] can be the aforementioned wiring IWL_j, used as wiring to obtain the first data as digital data from the outside. Specifically, wiring DW[0] to wiring DW[M-1] is used to transmit the output quantity I from the current source CS connected to them. Wut The wiring of a constant current signal. For example, when wiring DW[0] is supplied with a high-level potential, the current source CS connected to wiring DW[0] acts as a constant current, causing I to... Wut When the current flows through the second terminal of switch SA_j and the wiring DW[0] is supplied with a low-level potential, the current source CS connected to wiring DW[0] does not output I. Wut The constant current. For example, when wiring DW[1] is supplied with a high level potential, the two current sources CS connected to wiring DW[1] make a total of 2I Wut A constant current flows through the second terminal of switch SA_j. When wiring DW[1] is supplied with a low-level potential, the current source CS connected to wiring DW[1] does not output a total of 2I.Wut The constant current. For example, when wiring DW[M-1] is supplied with a high-level potential, the 2 connected to wiring DW[M-1]... M-1 The current source CS makes a total of 2 M-1 I Wut A constant current flows through the second terminal of switch SA_j. When wiring DW[M-1] is supplied with a low-level potential, the current source CS connected to wiring DW[M-1] does not output a total of 2 M-1 I Wut The constant current of the quantity.

[0272] A current source CS connected to wiring DW[0] functions as the value of current flowing through bit 0; two current sources CS connected to wiring DW[1] function as the value of current flowing through bit 1; and two current sources CS connected to wiring DW[M-1] function as the value of current flowing through bit 1. M-1 Each current source CS functions as the value of the current flowing through the (M-1)th bit. Here, consider the circuit WCSa_j when M is 2. For example, when the value of the 0th bit is "1" and the value of the 1st bit is "0", wiring DW[0] is supplied with a high level potential and wiring DW[1] is supplied with a low level potential. At this time, the quantity I Wut The constant current flows from circuit WCSa_j to the second terminal of switch SA_j in circuit SWCA. Additionally, for example, when the value of bit 0 is "0" and the value of bit 1 is "1", wiring DW[0] is supplied with a low-level potential and wiring DW[1] is supplied with a high-level potential. At this time, the quantity 2I... Wut The constant current flows from circuit WCSa_j to the second terminal of switch SA_j in circuit SWCA. Additionally, for example, when the value of bit 0 is "1" and the value of bit 1 is "1", wiring DW[0] and wiring DW[1] are supplied with a high-level potential. At this time, the amount 3I... Wut The constant current flows from circuit WCSa_j to the second terminal of switch SA_j in circuit SWCA. Additionally, for example, when the value of bit 0 is "0" and the value of bit 1 is "0", wiring DW[0] and wiring DW[1] are supplied with a low-level potential. In this case, the constant current does not flow from circuit WCSa_j to the second terminal of switch SA_j in circuit SWCA.

[0273] Notice, Figure 6A The circuit WCSa_j is shown when M is an integer greater than or equal to 3, but when M is 1... Figure 6A The circuit WCSa_j preferably adopts a structure that does not have a current source CS connected to wiring DW[1] to wiring DW[M-1]. Furthermore, when M is 2, Figure 6A The circuit WCSa_j preferably adopts a structure in which the current source CS is not connected to the wiring DW[2] (not shown) to the wiring DW[M-1].

[0274] Next, a specific structural example of the current source CS will be described.

[0275] Figure 7A The current source CS1 shown can be applied to Figure 6A The circuit of the current source CS in the circuit WCSa_j, the current source CS1 includes transistor Tr1 and transistor Tr2.

[0276] The first terminal of transistor Tr1 is connected to wiring VDDL. The second terminal of transistor Tr1 is connected to the gate and back gate of transistor Tr1, and the first terminal of transistor Tr2. The second terminal of transistor Tr2 is connected to terminal U1, and the gate of transistor Tr2 is connected to terminal U2. Additionally, terminal U2 is connected to wiring DW.

[0277] DW wiring is Figure 6A Any one of the wiring DW[0] to wiring DW[M-1].

[0278] The VDDL wiring is used as a wiring to supply a fixed potential. This fixed potential can be, for example, a high-level potential.

[0279] When the fixed potential supplied by the wiring VDDL is set to a high level, the first terminal of transistor Tr1 is input with a high level potential. Additionally, the potential of the second terminal of transistor Tr1 is set to a potential lower than this high level potential. At this time, the first terminal of transistor Tr1 is used as the drain, and the second terminal of transistor Tr1 is used as the source. Furthermore, the gate and the second terminal of transistor Tr1 are connected, so the voltage between the gate and source of transistor Tr1 is 0V. Therefore, when the threshold voltage of transistor Tr1 is within an appropriate range, a current (drain current) in the subthreshold region flows between the first and second terminals of transistor Tr1. In the case where transistor Tr1 is an OS transistor, this current is preferably, for example, 1.0 × 10⁻⁶. -8 A and below, preferably 1.0 × 10 -12 Below A, 1.0 × 10 is further preferred. -15 Below A. Furthermore, for example, this current is more preferably in a range that increases exponentially with respect to the gate-source voltage. That is, transistor Tr1 is used as a current source to allow current to flow through the current range when operating in the subthreshold region. This current can be the aforementioned I. Wut Or the following I Xut .

[0280] Transistor Tr2 is used as a switching element. Furthermore, when the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal, the first terminal of transistor Tr2 is used as the drain, and the second terminal is used as the source. Additionally, the back gate and the second terminal of transistor Tr2 are connected, so the voltage between the back gate and the source is 0V. Therefore, when the threshold voltage of transistor Tr2 is within an appropriate range, transistor Tr2 is in the on state when a high-level potential is input to its gate, and in the off state when a low-level potential is input to its gate. Specifically, when transistor Tr2 is in the on state, the current in the subthreshold current range flows from the second terminal of transistor Tr1 to terminal U1; when transistor Tr2 is in the off state, this current does not flow from the second terminal of transistor Tr1 to terminal U1.

[0281] Note that it can be used Figure 6A The circuit of the current source CS in the circuit WCSa_j is not limited to Figure 7A The current source CS1. For example, the current source CS1 has a structure that connects the back gate of transistor Tr2 and the second terminal of transistor Tr2, but it can also be a structure in which the back gate of transistor Tr2 is connected to other wiring. Figure 7B An example of this structure is shown. Figure 7B The current source CS2 shown has a structure in which the back gate of transistor Tr2 is connected to the wiring VTHL. In current source CS2, since the wiring VTHL is connected to external circuitry, a predetermined potential can be supplied to the back gate of transistor Tr2 by supplying a predetermined potential to the wiring VTHL using this external circuitry. This allows the threshold voltage of transistor Tr2 to be changed. In particular, by increasing the threshold voltage of transistor Tr2, the off-state current of transistor Tr2 can be reduced.

[0282] Alternatively, for example, current source CS1 has a structure that connects the back gate of transistor Tr1 and the second terminal of transistor Tr1, but it can also have a structure in which the voltage between the back gate and the second terminal of transistor Tr2 is maintained by a capacitor element. Figure 7C An example of this structure is shown. Figure 7CThe current source CS3 shown includes transistors Tr1 and Tr2, transistor Tr3, and capacitor C7. The difference between current source CS3 and current source CS1 is that the second terminal of transistor Tr1 is connected to its back gate via capacitor C7; and the back gate of transistor Tr1 is connected to the first terminal of transistor Tr3. Furthermore, current source CS3 has a structure where the second terminal of transistor Tr3 is connected to wiring VTL and the gate of transistor Tr3 is connected to wiring VWL. In current source CS3, supplying a high-level potential to wiring VWL turns transistor Tr3 on, thus conducting the connection between wiring VTL and the back gate of transistor Tr1. At this time, a predetermined potential can be input from wiring VTL to the back gate of transistor Tr1. Conversely, supplying a low-level potential to wiring VWL turns transistor Tr3 off, and capacitor C7 maintains the voltage between the second terminal of transistor Tr1 and its back gate. In other words, by determining the voltage supplied to the back gate of transistor Tr1 by wiring VTL, the threshold voltage of transistor Tr1 can be changed, and the threshold voltage of transistor Tr1 can be fixed by transistor Tr3 and capacitor C7.

[0283] In addition, for example, it can be used Figure 6A The circuit structure of the current source CS in the circuit WCSa_j can also be... Figure 7D The current source CS4 is shown. Current source CS4 has the function of... Figure 7C The back gate of transistor Tr2 in current source CS3 is connected to wiring VTHL but not to the second terminal of transistor Tr2. That is, with... Figure 7B Similarly, current source CS4 can vary the threshold voltage of transistor Tr2 based on the potential supplied by wiring VTHL.

[0284] In current source CS4, when a large current flows between the first and second terminals of transistor Tr1, the on-state current of transistor Tr2 needs to be increased in order for this current to flow from terminal U1 to the outside of current source CS4. In this case, by supplying a high-level potential to the wiring VTHL in current source CS4, the threshold voltage of transistor Tr2 is lowered, thereby increasing the on-state current of transistor Tr2. This allows the large current flowing between the first and second terminals of transistor Tr1 to flow from terminal U1 to the outside of current source CS4.

[0285] By Figure 6A The current source CS in the circuit WCSa_j is used as Figures 7A to 7DAny of the current sources CS1 to CS4 shown can be used to output the current corresponding to the first data of M bits. Alternatively, this current quantity can be, for example, the current flowing between the first and second terminals when transistor F1 is operating in the subthreshold region.

[0286] In addition, as Figure 6A The circuit WCSa_j can also be used Figure 6B The circuit shown is WCSa_j. Figure 6B The circuit WCSa_j has wiring DW[0] to wiring DW[M-1] connected to a [0] and a [1] respectively. Figure 7A The structure of the current source CS. Furthermore, when the channel width of transistor Tr1[0] is w[0], the channel width of transistor Tr1[1] is w[1], and the channel width of transistor Tr1[M-1] is w[M-1], the ratio of the channel widths is w[0]:w[1]:w[M-1] = 1:2:2 M-1 The current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, and therefore... Figure 6A The circuit WCSa_j is the same. Figure 6B The circuit WCSa_j shown can output the current corresponding to the first data of M bits.

[0287] Note that transistors Tr1 (including transistors Tr1[0] to Tr1[M-1]), Tr2 (including transistors Tr2[0] to Tr2[M-1]), and Tr3 can be transistors that can be used as transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, or F5D. In particular, OS transistors are preferably used as transistors Tr1 (including transistors Tr1[0] to Tr1[M-1]), Tr2 (including transistors Tr2[0] to Tr2[M-1]), and Tr3.

[0288] [Circuit XCS]

[0289] For example, the circuit XCS has the following function: it allows external wiring via IXL_i (in...) Figure 5 (Not shown in the diagram) The circuit XCS obtains second data as digital data, converts the second data into analog data (current quantity), and supplies the second data to the arithmetic units included in the cell array CA. For example, when the circuit XCS supplies the second data to the multiplication units IM[i,1] to IM[i,n] in the i-th row of the cell array CA, the circuit XCS supplies the second data to the arithmetic units in the i-th row of the cell array CA through wiring XCL_i.

[0290] The circuit XCS includes, for example, circuits XCSa_1 to XCSa_m.

[0291] In addition, circuit XCSa_1 is connected to wiring IXL_1. Furthermore, circuit XCSa_m is connected to wiring IXL_m.

[0292] Each of the wirings IXL_1 to IXL_m is used as a wiring to transmit second data as digital data from the outside to each of the circuits XCSa_1 to XCSa_m.

[0293] Each of circuits XCSa_1 to XCSa_m has, for example, the function of acquiring reference data (described later) from each of wirings IXL_1 to IXL_m and supplying signals corresponding to the reference data to wirings XCL_1 to XCL_m. Alternatively, each of circuits XCSa_1 to XCSa_m has, for example, the function of acquiring second data from each of wirings IXL_1 to IXL_m and supplying signals corresponding to the second data. Note that in Figure 5 In the cell array CA, the above signals are preferably analog data (current).

[0294] Figure 6C It shows that it can be used Figure 5 A block diagram of an example of the circuit XCSa_i (where i is an integer greater than 1 and less than m) of the circuit XCS. Note that... Figure 6C The abstract shows circuit XCSa_i as any one of circuits XCSa_1 to XCSa_m. Additionally, in Figure 6C To illustrate the electrical connection between circuit XCS and its surrounding circuits, wiring XCL_i is also shown. Therefore, wiring XCL_i is connected to circuit XCSa_i.

[0295] Figure 6C The circuit XCSa_i shown includes, for example, a switch SWX. The first terminal of switch SWX is connected to wiring XCL_i, and the second terminal of switch SWX is connected to wiring VINIL2. Wiring VINIL2 is used to supply an initialization potential to wiring XCL_i; this initialization potential can be ground (GND), a low-level potential, or a high-level potential. Alternatively, the initialization potential supplied by wiring VINIL2 can be made equal to the potential supplied by wiring VINIL1. Note that switch SWX is only in the on state when supplying an initialization potential to wiring XCL_i; otherwise, it is in the off state.

[0296] For example, a switch SWX can be a switch that can be used to switch SWW.

[0297] in addition, Figure 6CThe circuit structure of XCSa_i can be adopted with... Figure 6A The circuit WCSa_j has a roughly the same structure. Specifically, the circuit XCSa_i has the function of outputting reference data as a current quantity and outputting L-bit (2 L The second data output (where L is an integer greater than or equal to 1) functions as the current quantity. In this case, the circuit XCSa_i includes 2... L -1 current source CS. Circuit XCSa_i includes one current source CS that outputs the value of bit 0 as current, two current sources CS that output the value of bit 1 as current, and 2 L-1 A current source CS that outputs the value of the (L-1)th bit as current.

[0298] Additionally, the reference data for the current output of the circuit XCSa_i can be, for example, information where the value of the 0th bit is "1" and the values ​​of the bits after the 1st bit are "0".

[0299] exist Figure 6C In the circuit, terminal U2 of one current source CS is connected to wiring DX[0], and terminal U2 of two current sources CS are respectively connected to wiring DX[1]. L-1 The terminals U2 of each current source CS are connected to wiring DX[L-1].

[0300] Multiple current sources CS in circuit XCSa_i have the same quantity I. Xut The constant current is output from terminal U1. Xut The function is as follows. Additionally, wiring DX[0] to wiring DX[L-1] can be the aforementioned wiring IXL_i, used as wiring to obtain reference data or second data from the outside as digital data. Specifically, wiring DX[0] to wiring DX[L-1] is used to transmit I from the current source CS connected to them. Xut The control signal is routed. That is, the circuit XCSa_i has the function of causing the current corresponding to the L bits of information sent from route DX[0] to route DX[L-1] to flow through route XCL_i.

[0301] Specifically, consider the circuit XCSa_i when L is 2. For example, when the value of bit 0 is "1" and the value of bit 1 is "0", wiring DX[0] is supplied with a high level potential and wiring DX[1] is supplied with a low level potential. At this time, the quantity I Xut The constant current flows from circuit XCSa_i to wiring XCL_i. Additionally, for example, when the value of bit 0 is "0" and the value of bit 1 is "1", wiring DX[0] is supplied with a low-level potential and wiring DX[1] is supplied with a high-level potential. At this time, the amount 2I... XutThe constant current flows from circuit XCSa_i to wiring XCL_i. Additionally, for example, when the value of bit 0 is "1" and the value of bit 1 is "1", wiring DX[0] and wiring DX[1] are supplied with a high-level potential. At this time, the amount 3I... Xut The constant current flows from circuit XCSa_i to wiring XCL_i. Additionally, for example, when the value of bit 0 is "0" and the value of bit 1 is "0", wiring DX[0] and wiring DX[1] are supplied with a low-level potential. At this time, the constant current does not flow from circuit XCSa_i to wiring XCL_i. Note that at this time, in this specification, etc., the current sometimes referred to as current quantity 0 flows from circuit XCSa_i to wiring XCL_i. Furthermore, the current quantity 0 and I output by circuit XCSa_i... Xut 2I Xut 3I Xut This can be the second data output by the circuit XCSa_i, especially the current I output by the circuit XCSa_i. Xut It can be the reference data output by the circuit XCSa_i.

[0302] When errors occur due to fluctuations in the electrical characteristics of the transistors in each current source CS of circuit XCSa_i, the constant current I output by each terminal U1 of the multiple current sources CS... Xut The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. Note that in this embodiment, it is assumed that the constant current I output from the terminal U1 of the plurality of current sources CS in the circuit XCSa_i is... Xut Explanation without error.

[0303] In addition, similar to the current source CS in circuit WCSa_j, the current source CS in circuit XCSa_i can also be used. Figures 7A to 7D Any one of the current sources CS1 to CS4. In this case, wiring DX[0] to wiring DX[L-1] can be used instead. Figures 7A to 7D The wiring DW[0] to wiring DW[M-1] are shown. Thus, circuit XCSa_i can be used as reference data or L-bit second data to allow current in the subthreshold region to flow through wiring XCL_i.

[0304] in addition, Figure 6C The circuit XCSa_i can be used with Figure 6B The circuit structure shown is the same as that of circuit WCSa_j. This time, circuit XCSa_i is used instead. Figure 6BThe circuit shown can be considered by replacing the wiring IWL_j with wiring IXL_i, replacing wiring DW[0] with wiring DX[0], replacing wiring DW[1] with wiring DX[1], replacing wiring DW[M-1] with wiring DX[L-1], replacing switch SWW with switch SWX, and replacing wiring VINIL1 with wiring VINIL2.

[0305] [Circuit ITS]

[0306] The circuit ITS includes, for example, circuits that perform function-type operations (e.g., nonlinear function-type operations) and analog-to-digital conversion circuits. In particular, the circuits that perform function-type operations preferably have the function of performing function-type operations with a value corresponding to the input current quantity as input value, and outputting digital data (voltage) corresponding to the result of the operation.

[0307] Figure 8A An example of the circuit structure of the ITS circuit is shown. Figure 8A The circuit shown, ITS, is usable Figure 5 The circuit shown is an example of an ITS circuit. Note that in Figure 8A In the diagram, wiring WCL_j is also shown to illustrate the electrical connection between circuit ITS and its surrounding circuitry. Furthermore, wiring WCL_j is... Figure 5 Any one of the wirings WCL_1 to WCL_n shown, switch SB_j is Figure 5 The circuit SWCB shown includes any one of the switches SB_1 to SB_n.

[0308] As a switch SB_j, for example, it can be used as... Figure 5 The switches SA_1 to SA_n are shown. For example, switch SB_j can be an electrical switch or a mechanical switch.

[0309] Figure 8A The circuit ITS includes circuit SWCB, circuits ITSa_1 to ITSa_n. Note that... Figure 8A The abstract shows circuit ITSa_j as any one of circuits ITSa_1 to ITSa_n. Furthermore, circuit ITSa_j includes a conversion circuit RL_j and an analog-to-digital converter (ADC).

[0310] In addition, the conversion circuit RL_j includes terminals RTi_j and RTo_j.

[0311] The first terminal of switch SB_j is connected to wiring WCL_j, the second terminal of switch SB_j is connected to terminal RTi_j of conversion circuit RL_j, and the control terminal of switch SB_j is connected to wiring SWLB. Additionally, terminal RTo_j of conversion circuit RL_j is connected to the input terminal of analog-to-digital converter (ADC), and the output terminal of ADC is connected to wiring OL_j.

[0312] As an example, the SWLB wiring is used to switch the on and off states of switches SB_1 to SB_n. Therefore, the SWLB wiring is supplied with either a high-level or low-level potential.

[0313] Wiring OL_j ( Figure 5 The wiring OL_1 to OL_n in the circuit is used as wiring to output the operation results in the arithmetic circuit ANP as digital data to the outside.

[0314] The conversion circuit RL_j can be the aforementioned function-type operation circuit. As a function-type operation circuit, for example, it can use nonlinear function operation circuits such as the sigmoid function, tanh function, softmax function, ReLU function, or threshold function. Alternatively, the conversion circuit RL_j can also include a circuit for pooling processing instead of a function-type operation circuit. Furthermore, when using... Figure 8A In the case of the structure, the conversion circuit RL_j preferably outputs voltage from terminal RTo_j.

[0315] Alternatively, the conversion circuit RL_j can also be a current-to-voltage conversion circuit.

[0316] When the conversion circuit RL_j is a current-to-voltage conversion circuit, it is preferable that, for example, the conversion circuit RL_j generates an analog voltage corresponding to the current input from wiring WCL_j through switch SB_j to terminal RTi_j of the conversion circuit RL_j, and outputs it to terminal RTo_j of the conversion circuit RL_j.

[0317] In addition, the analog-to-digital converter (ADC) preferably converts the analog voltage supplied from the terminal RTo_j of the conversion circuit RL_j into a digital signal and outputs it to the wiring OL_j.

[0318] in addition, Figure 8B This shows an example of the circuit ITS structure when the conversion circuit RL_j is a current-to-voltage conversion circuit. Figure 8B The conversion circuit RL_j shown includes, for example, a load LE and an operational amplifier OP.

[0319] The inverting input terminal of operational amplifier OP is connected to the first terminal of load LE and the second terminal of switch SB_j. The non-inverting input terminal of operational amplifier OP is connected to wiring VRL. The output terminal of operational amplifier OP is connected to the second terminal of load LE and terminal RTo_j.

[0320] VRL wiring is used to supply a fixed potential. This fixed potential can be, for example, ground potential (GND), low-level potential, etc.

[0321] In particular, when the fixed potential supplied by the wiring VRL is the ground potential (GND), the inverting input terminal of the operational amplifier OP is virtually grounded, so the analog voltage output to the wiring OL_j can be a voltage based on the ground potential (GND).

[0322] When the circuit ITS has Figure 8B In this configuration, the value corresponding to the current flowing from wiring WCL_j through switch SB_j to terminal RTi_j of the conversion circuit RL_j can be output as an analog voltage to terminal RTo_j. Furthermore, this analog voltage can be converted into a digital signal by an analog-to-digital converter (ADC) and output to wiring OL_j.

[0323] Note that when the circuit ITS outputs an analog voltage instead of a digital signal to the wiring OL_j, such as Figure 8C As shown in the circuit ITS, the analog-to-digital converter (ADC) circuit can also be omitted in the circuit ITSa_j. Additionally, in Figure 8C Preferably, the conversion circuit RL_j performs a function-type operation with the value corresponding to the current flowing through terminal RTi_j as input, and outputs the result as an analog current to terminal RTo_j. In this case, for example, when the operation result of circuit ITS is not stored in the storage circuit section ME11 but directly input to the analog operation circuit for the next fully connected layer, Figure 8C The circuit shown, ITS, is valid.

[0324] <Examples of operational circuits>

[0325] Next, an example of the operation of the operational circuit ANP will be explained.

[0326] First, the first data, as digital data, is input from the outside into wiring IWL_1 to wiring IWL_n.

[0327] Here, in Figure 5 The operational circuit ANP includes the circuit WCS as follows: Figure 6AWhen the circuit WCS is shown, each of circuits WCSa_1 to WCSa_n generates a current corresponding to the value of each digital data sent to wirings IWL_1 to IWL_n. Additionally, when switches SA_1 to SA_n of circuit SWCA are all in the open state, the currents generated by circuits WCSa_1 to WCSa_n flow through wirings WCL_1 to WCL_n.

[0328] In addition, Figure 5 In the circuit WSD, for example, when row i is selected in the cell array CA, current from wiring WCL_1 to wiring WCL_n flows through each of the multiple multiplication units IM[i,1] to IM[i,n] configured in row i. Here, by maintaining the potential of the gate of the transistor F2 of each multiplication unit IM[i,1] to IM[i,n], the amount of current flowing between the source and drain of transistor F2 can be set.

[0329] Additionally, during the period when the current from wiring WCL_1 to wiring WCL_n flows through each of the plurality of multiplication units IM[i,1] to multiplication unit IM[i,n] configured in the i-th row of the cell array CA as described above, the circuit XCS causes the reference current I... ref0 The gate potential of transistor F2d in the driving unit IMD_i is maintained by the flow through wiring XCL_i. Therefore, the amount of current flowing between the source and drain of transistor F2d in the driving unit IMD_i can be set to I. ref0 Note that the current flowing to the drive unit IMD of the cell array CA is set together with the current setting of the multiplication unit IM.

[0330] Note that the reference current I ref0 The quantity is, for example, the amount of current flowing through the wiring XCL when the second data sent to the multiplication unit IM is "1".

[0331] Therefore, the current I0[i,j] flowing through the transistor F2 of the multiplication unit IM[i,j] is calculated as follows (2.1).

[0332] [Equation 1]

[0333] Note that w[i,j] is the first data written into the multiplication unit IM[i,j]. When performing operations on a fully associative layer neural network in the arithmetic circuit ANP, the first data can also be referred to as the weight coefficients (sometimes called the associative strength). Furthermore, w[i,j] is defined as follows (2.2). Additionally, I ref0 As shown in the following formula (2.3).

[0334] [Equation 2]

[0335] Note that V g [i, j] represents the gate-source voltage of transistor F2 in multiplication unit IM[i, j], V th [i, j] represents the threshold voltage of transistor F2 in the multiplication unit IM[i, j]. Furthermore, V gm [i] represents the gate-source voltage of transistor F2D in the driving unit IMD_i, V thm [i] represents the threshold voltage of transistor F2 in the driving unit IMD_i. Note that I a V represents gm [i] is V thm [i] when I ref0 The current is J, which represents the correction factor determined by factors such as temperature and device structure.

[0336] Next, second data, as digital data, is input from the outside into wiring IXL_1 to wiring IXL_m.

[0337] Here, in Figure 5 The operational circuit ANP includes the circuit XCS as follows: Figure 6C When circuit XCS is shown, each of circuits XCSa_1 to XCSa_m generates a current corresponding to the value of each digital data sent to wirings IXL_1 to IXL_m. Thus, the currents generated by circuits XCSa_1 to XCSa_m flow through wirings XCL_1 to XCL_m.

[0338] The potentials of wirings XCL_1 to XCL_m are determined by the amount of current flowing through them. Furthermore, due to the potential changes of wirings XCL_1 to XCL_m, the potential of the gate (node ​​N) of transistor F2 in each of the multiplication units IM[1,1] to IM[m,n] changes. At this time, the current I1[i,j] flowing through transistor F2 in the multiplication unit IM[i,j] is calculated as follows (2.4).

[0339] [Equation 3]

[0340] Note that x[i] is the second data sent from circuit XCSa_i to wiring XCL_i. When performing operations on a fully combined layer neural network in the operational circuit ANP, the second data can also be referred to as the input signal of the neuron, etc. In addition, x[i] is as shown in the following formula (2.5).

[0341] [Equation 4]

[0342] ΔV[i] indicates the amount of current flowing through wiring XCL_i from I. ref0 The change is the change in potential of wiring XCL_i corresponding to the current quantity [i]. Additionally, p is the coupling capacitance coefficient between the first and second terminals of the capacitor element C1 of the multiplication unit IM[i,j].

[0343] Here, Figure 5 The operational circuit ANP includes the following circuit ITS: Figure 8A The circuit ITS is shown. At this time, switches SA_1 to SA_n of circuit SWCA, which is included in circuit WCS, are all closed, and switches SB_1 to SB_n of circuit SWCB, which is included in circuit ITS, are all open. Therefore, in the j-th column of the cell array CA, the sum of the currents flowing through each of the multiplication units IM[1,j] to IM[m,j] is input to circuit ITSa_j. At this time, the amount of current I input to circuit ITSa_j is... SUM [j] is as follows.

[0344] [Equation 5]

[0345] In other words, the amount of current I flowing through circuit ITSa_j SUM [j] is determined based on the sum of the product of the first data and the second data.

[0346] In circuit ITSa_j, the terminal RTi_j of the conversion circuit RL_j is input as the product result I. SUM [j]. Therefore, the conversion circuit RL_j performs I... SUM [j] represents a function operation on the input value. Furthermore, the conversion circuit RL_j outputs the result of the above function operation as an analog potential to terminal RTo_j and inputs it to the analog-to-digital converter (ADC). The ADC then converts this analog potential into digital data. This digital data is then output to the outside via wiring OL_j. Thus, the arithmetic circuit ANP can perform product and function operations.

[0347] In particular, the computational circuit ANP can appropriately perform operations on fully associative layer neural networks. For example, by using the values ​​of the input signals of neurons—which are the first data retaining weights in the multiplication unit IM of the cell array CA of the computational circuit ANP and the wiring XCL as the second data input—a product sum operation can be performed between the weights and the neuron's input signal. Furthermore, by using the computational circuit ITSa_j, which is the circuit for the activation function of the fully associative layer neural network, the value of the activation function, with the result of this product sum operation as its input value, can be output. This value can then be input to the next hidden layer, output layer, etc.

[0348] Analog-mode computation can be performed using the arithmetic circuit ANP of the arithmetic device CDV as a fully connected layer, for example, as described in Embodiment 4. Figure 16 This enables large-scale operations such as the product summation of fully connected layers FC6 to FC8 in AlexNet. Specifically, a subthreshold current flows through the transistors F2 of the multiplication units IM[1,1] to IM[m,n] in the cell array CA, thus reducing the power consumption of a single multiplication unit IM. Therefore, the number of multiplication units IM in the cell array CA can be increased, allowing the product summation of fully connected layers to be performed within a single cell array CA.

[0349] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. In addition, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with configurations, structures, methods, etc. shown in other embodiments, etc.

[0350] (Implementation Method 3)

[0351] In this embodiment, a method for reducing the overall computational load when performing multilayer neural network (e.g., multilayer perceptron) operations in the semiconductor device described in the above embodiments is explained.

[0352] Figures 9A to 9C This is a schematic diagram illustrating an example of lightweighting a multi-layer neural network model. (See reference...) Figures 9A to 9C This explains how a lightweight multilayer neural network model can be used in the implementation methods described above. Figure 5 An example of an ANP operational circuit.

[0353] like Figures 9A to 9C As shown, the multilayer neural network consists of operational circuits ANP[1] to ANP[4]. Figures 9A to 9CIn this context, the polarity (positive or negative) and magnitude of the weight coefficients are indicated by the type of wire (solid or dashed) and its thickness.

[0354] in addition, Figures 9A to 9C Each operational circuit (ANP) shown includes multiple neurons. Each neuron can be... Figure 5 The operational circuit ANP shown includes a series of multiplication units IM[1,j] to IM[m,j] and the circuit ITSa_j. Figures 9A to 9C In the operation circuit ANP[1], the multiplication units IM[1,1] to IM[m,1] and the circuit ITSa_1 can be represented as the operation unit ANPa_1, and the multiplication units IM[1,n] to IM[m,n] and the circuit ITSa_n of the operation circuit ANP[1] can be represented as the operation unit ANPa_n.

[0355] First of all, Figure 9A The general DNN (Deep Neural Network) shown is simplified by reducing the number of bits in the weight coefficients. Therefore, we can obtain... Figure 9B The neural network shown is low-bit (in the attached diagram, the low-bit network is narrowed). By low-bit reduction, the ratio of weight coefficients that are 0 increases. For example, by low-bit reduction, the weight coefficients can also be set to 1 bit. By setting the weight coefficients to 1 bit, for example, an adder circuit can be used instead of a multiplier circuit, thereby reducing the circuit size.

[0356] Next, regarding Figure 9B The low-order neural network shown is pruned to trim the network down to zero (sometimes referred to as "pruning"). Therefore, we can obtain... Figure 9C The neural network shown has undergone low-level reduction and pruning (in the attached figure, the pruned network is shown by deleting the pruned network). Due to the aforementioned low-level reduction, the ratio of weight coefficients that become 0 increases, thus increasing the number of networks that become 0, i.e., the number of networks that can be pruned.

[0357] Figure 9C The low-order and pruned neural network shown can be constructed by appropriately setting the first data to 0 in each of the multiple operational circuits ANP (operational circuits ANP[1] to ANP[4]). In this neural network, for example, when the weight coefficient held by the operation unit ANPa_1 included in the operation circuit ANP[1] is 0, the first data (weight coefficient) can be made 0 by setting the current of the multiplication unit IM of the operation unit ANPa_1 to 0. Furthermore, for example, by setting the second data (output signal of the neuron) input to the multiplication unit IM of the operation unit ANPa_1 included in the operation circuit ANP[1] to 0, the result of the multiplication operation of the first data and the second data can be made 0.

[0358] Therefore, for example, when all the second data (output signals of the neuron) input to the arithmetic unit ANPa_1 included in the arithmetic circuit ANP[1] are 0, the power consumption of the circuit ITSa_1 of the arithmetic unit ANPa_1 included in the arithmetic circuit ANP[1] can be approximately 0. In addition, for example, when at least one of the first data and the second data in the arithmetic circuit ANP[1] is 0, the power consumption of the multiplication unit IM[1,1] to the multiplication unit IM[m,n] that performs the multiplication operation of the first data and the second data in each of the arithmetic units ANPa_1 to ANPa_n included in the arithmetic circuit ANP[1] can be approximately 0.

[0359] In other words, a neural network composed of computational circuits (ANPs) can achieve the same low-power effect as pruning and zero-hopping, without needing to delete the network pruned by pruning or to set up a separate circuit to determine that the data is 0 by zero-hopping.

[0360] Note that the inference accuracy of neural networks sometimes decreases due to low-order processing and pruning. Therefore, to recover from the decrease in inference accuracy, one can perform operations of any function (e.g., sigmoid, tanh, softmax, ReLU, or threshold functions) on all circuits ITSa_1 to ITSa_n of the operational circuit ANP.

[0361] Furthermore, each of the arithmetic units ANPa_1 to ANPa_n included in the arithmetic circuits ANP[1] to ANP[4] can perform multi-bit operations as described in Embodiment 2 above. Therefore, the neural network composed of arithmetic circuits ANP[1] to ANP[4] can improve inference accuracy without performing the optimization of the aforementioned nonlinear function. For example, the inference accuracy can be improved by relearning the pruned neural network with 8-bit weight coefficients.

[0362] Furthermore, the power consumption of the multiplication unit IM included in each of the arithmetic circuits ANP[1] to ANP[4] is proportional to the multiplication operation of the first current corresponding to the first data and the second current corresponding to the second data. Therefore, the closer the first data and the second data are to 0, the lower the power consumption. Therefore, by using a neural network composed of arithmetic circuits ANP[1] to ANP[4], for example, the weight coefficients are mostly distributed near 0 due to weight decay, the power consumption can be reduced.

[0363] Reference Figure 10A and Figure 10B The above specific examples illustrate this.

[0364] Figure 10A and Figure 10B Summary shows Figure 5 The operational circuit ANP includes the multiplication unit IM[1,j], the multiplication unit IM[m,j] located in the j-th column, and the circuit ITSa_j. Additionally, Figure 10A and Figure 10B The circuit WCS, circuit XCS, and control unit CTL are also shown.

[0365] The control unit CTL has the function of reading the model of the pruned neural network and inputting first data Dw[1] to first data Dw[m] into the arithmetic circuit ANP in such a way that the weight coefficients of the pruned network are 0. In other words, the control unit CTL has the function of making at least one of the first data Dw[1] to first data Dw[m] in the arithmetic circuit ANP 0 by performing pruning.

[0366] exist Figure 10A In the example shown, pruning is performed to trim a portion of the network between neurons in the previous layer and neurons in the next layer. The control unit CTL, via the circuit WCS, controls the multiplication unit IM (in the pruned network) corresponding to the pruned network. Figure 10A In the example, the multiplication unit IM[m,j] is written as 0 as the first data Dw[m] (Dw[m]="0").

[0367] In addition, Figure 10B In the example of pruning the entire network between neurons in the previous layer and neurons in the next layer by performing pruning, the following situation is shown: the control unit CTL writes 0 as first data Dw[1] to first data Dw[m] for each of the multiplication units IM[1,j] to IM[m,j] via the circuit WCS. In particular, at this time, the result of the product of all input signals from the neurons in the next layer to the neurons in the layer below and the weight coefficients is 0 (ΣDw[i]×Dx[i]=0).

[0368] The control unit (CTL) may also have functions such as learning, low-bit reduction, pruning, zero-jumping, function optimization, weight decay, or relearning of the operational circuit (ANP).

[0369] By setting a control unit CTL in the arithmetic circuit ANP and setting at least one of the first data Dw[1] to the first data Dw[m] to 0, the same low-power effect as pruning and zero-jump can be obtained without deleting the net pruned by pruning on the circuit or setting up a separate circuit to determine that the data is 0 by zero-jump.

[0370] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. In addition, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with configurations, structures, methods, etc. shown in other embodiments, etc.

[0371] (Implementation Method 4)

[0372] In this embodiment, a computing device according to one aspect of the present invention will be described.

[0373] <Example of the structure of a computing device>

[0374] Figure 11 An example of the structure of a computing device CDV, which is one aspect of the present invention, is shown.

[0375] The computing device CDV is used as an accelerator to execute programs (such as convolution kernel programs). These programs are invoked, for example, by a host program stored in the external storage of the computing device CDV. The computing device CDV can, for example, perform parallel processing of row and column operations in graphics processing, parallel processing of product sum operations in neural networks, or parallel processing of floating-point operations in scientific and technological computing.

[0376] In particular, the computing device CDV can perform model operations on convolutional neural networks. Convolutional neural networks include, for example, convolutional layers, pooling layers, and fully connected layers. By taking a multi-layered input image with these layers as a combination, feature extraction and recognition can be performed on the image.

[0377] The computing device CDV includes, for example, a computing circuit DGP, a computing circuit ANP, and a storage circuit MEM.

[0378] A digital processing circuit (DGP) is a circuit that performs calculations on input data (digital data) and outputs the result as digital data. Specifically, a DGP may, for example, perform product summation operations in the convolutional layers of a convolutional neural network and output the result as digital data.

[0379] The arithmetic circuit ANP is the analog arithmetic circuit ANP described in Embodiment 2. It performs calculations on input data that is input as digital data and outputs the result as analog data. Specifically, the arithmetic circuit ANP, for example, has the function of performing product summation operations in the fully connected layers of a convolutional neural network and outputting the product summation result as analog data.

[0380] The storage circuit MEM is used, for example, as a storage circuit to store input data used for operations performed in the arithmetic circuit DGP or arithmetic circuit ANP. Furthermore, the storage circuit MEM is used, for example, as a storage circuit to store output data, which is the result of the operations performed by the arithmetic circuit DGP or arithmetic circuit ANP. Note that in this embodiment, the storage circuit MEM is described as a storage circuit for holding digital data. Additionally, when the operation result output from the arithmetic circuit ANP is stored in the storage circuit MEM, the analog data, which is the output data of the arithmetic circuit ANP, is converted into digital data by a digital-to-analog converter circuit or the like, and this digital data is stored in the storage circuit MEM.

[0381] The arithmetic circuit DGP includes, for example, a switching unit D10, an arithmetic unit D20, and a processing unit D30.

[0382] The storage circuit MEM includes, for example, storage circuit sections ME11 to ME13.

[0383] Operational circuits (ANPs) include, for example, cell arrays (CAs), circuits (WCSs), circuits (XCSs), and circuits (ITSs).

[0384] The input terminal TM1i of the switching unit D10 is connected to the wiring ILA, the input terminal TM2i of the switching unit D10 is connected to the wiring ILB, and the output terminal TMo of the switching unit D10 is connected to the wiring MLA.

[0385] The input terminal TN1i of the arithmetic unit D20 is connected to the wiring MLA, the input terminal TN2i of the arithmetic unit D20 is connected to the wiring MLB, and the output terminal TNo of the arithmetic unit D20 is connected to the wiring CNL.

[0386] The processing unit D30 is connected to the wiring POL.

[0387] Storage circuit section ME11 is connected to wiring ILB. Additionally, storage circuit section ME11 is connected to wiring CNL. Additionally, storage circuit section ME11 is connected to wiring POL. Additionally, storage circuit section ME11 is connected to wirings IXL_1 to IXL_m (where m is an integer of 1 or more). Additionally, storage circuit section ME12 is connected to wiring MLB. Additionally, storage circuit section ME13 is connected to wirings IWL_1 to IWL_n (where n is an integer of 1 or more).

[0388] Regarding routing IXL_1 to IXL_m and routing IWL_1 to IWL_n, refer to the description in Implementation Method 2. Figure 5 The operational circuit ANP is connected by wiring IXL_1 to wiring IXL_m and wiring IWL_1 to wiring IWL_n.

[0389] Each of the multiple input terminals of circuit WCS is connected to wiring IWL_1 to wiring IWL_n. Additionally, each of the multiple output terminals of circuit WCS is connected to wiring WCL_1 to wiring WCL_n.

[0390] Each of the multiple input terminals of circuit XCS is connected to wirings IXL_1 to IXL_m. Additionally, each of the multiple output terminals of circuit XCS is connected to wirings XCL_1 to XCL_m.

[0391] exist Figure 11 In this array, routing WCL_1 to WCL_n extends in the column direction of cell array CA. Additionally, routing XCL_1 to XCL_m extends in the row direction of cell array CA.

[0392] Furthermore, the cell array CA includes multiple operational units, which are configured in a matrix-like manner, for example, within the cell array CA. Details will be explained later. The operational unit in the i-th row and j-th column of the cell array CA (where i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n) is connected to routing WCL_j and routing XCL_i.

[0393] Each of the multiple input terminals of the circuit ITS is connected to wirings WCL_1 to WCL_n. Additionally, each of the multiple output terminals of the circuit ITS is connected to wirings OL_1 to OL_n.

[0394] The wiring ILA is used, for example, as wiring to input data from outside the computing device CDV to the input terminal TM1i of the switching unit D10. Note that the input data here can be, for example, an image. Additionally, in Figure 11 In the process, the input data is recorded as image P. in .

[0395] The ILB wiring is used, for example, as the wiring for inputting input data read from the storage circuit section ME11 to the input terminal TM2i of the switching section D10. Note that the input data here can be, for example, convolutional data or pooled data. Additionally, in Figure 11 In the text, the input data is recorded as "P". Cin or P Pin "P" Cin P represents the data processed by convolution. Pin This represents data that has undergone pooling.

[0396] For example, wiring MLA is used to input digital data output from the output terminal TMo of the switching unit D10 to the input terminal TN1i of the arithmetic unit D20. Note that in Figure 11 In the text, this numerical data is recorded as "P". in PCin or P Pin ".

[0397] The MLB wiring is used, for example, as wiring to input digital data read from the storage circuit section ME12 to the input terminal TN2i of the arithmetic section D20. Note that this digital data can be, for example, a filtered value used for convolution processing in the arithmetic section D20. Additionally, in Figure 11 In this context, the filtered value is recorded as K.

[0398] The wiring CNL is used, for example, as wiring to input digital data output from the output terminal TNo of the arithmetic unit D20 to the storage circuit unit ME13. Note that the digital data here can be, for example, data resulting from convolution processing performed in the arithmetic unit D20. Furthermore, in Figure 11 In the middle, this data is recorded as P. Cout .

[0399] The POL wiring is used, for example, as wiring to input digital data read from the storage circuit section ME11 to the processing section D30. Note that this digital data can be, for example, data that undergoes pooling processing in the processing section D30. Furthermore, in... Figure 11 In the middle, this data is recorded as P. C .

[0400] Furthermore, the POL wiring can also be used, for example, as wiring to send digital data processed by the processing unit D30 to the storage circuit unit ME11. Note that the digital data here can be, for example, data that has undergone pooling processing in the processing unit D30. Furthermore, in Figure 11 In the middle, this data is recorded as P. Pout .

[0401] Wiring IWL_1 is used, for example, as wiring to input data (which may be the first data described in the above embodiment) read from the storage circuit section ME13 into the circuit WCS. Similarly, wiring IWL_n is used, for example, as wiring to input data read from the storage circuit section ME13 into the circuit WCS. Note that the input data here may be, for example, one of the multiplier and multiplicand used to operate on the product and multiplication of fully connected layers in the cell array CA. In particular, one of the multiplier and multiplicand here is a weighting coefficient. In addition, in Figure 11 In the middle, the input data is recorded as W. in (1) and W in (n).

[0402] Wiring IXL_1 is used, for example, as wiring to input input data (which may be the second data described in the above embodiment) read from the storage circuit unit ME11 to the circuit XCS. Similarly, wiring IXL_m is used, for example, as wiring to input input data read from the storage circuit unit ME11 to the circuit XCS. Note that the input data here may be, for example, another of the multiplier and multiplicand used to operate the product and multiplicand of the fully connected layers in the cell array CA. In particular, the other of the multiplier and multiplicand here is the value of the signal input to the neuron in the fully connected layer. In addition, in Figure 11 In the middle, the input data is recorded as X in (1) and X in (m).

[0403] Wiring OL_1 is used, for example, as the wiring for inputting digital data output from the output terminal of the first column of the circuit ITS into the storage circuit ME11. Similarly, wiring OL_n is used, for example, as the wiring for inputting digital data output from the output terminal of the nth column of the circuit ITS into the storage circuit ME11. Note that the digital data here is, for example, the value of the signal output from the neuron in the fully connected layer. Furthermore, in Figure 11 In the text, this numerical data is recorded as X. out (1) and X out (n).

[0404] [Switching Unit D10]

[0405] The switching unit D10, for example, has the function of selecting one of the input terminals TM1i and TM2i and outputting the data input to the selected terminal to the output terminal TMo. In other words, the switching unit D10 has the function of making one of the input terminals TM1i and TM2i connected to the output terminal TMo and making the other of the input terminals TM1i and TM2i disconnected from the output terminal TMo.

[0406] Notice, Figure 11 The switch unit D10 is shown to have one input terminal TM1i and one input terminal TM2i, but the number of input terminals TM1i and TM2i of the switch unit D10 can also be multiple instead of one. Similarly, Figure 11 The switch unit D10 is shown to have one output terminal TMo, but the number of output terminals TMo of the switch unit D10 can also be multiple.

[0407] [Computation Department D20]

[0408] The arithmetic unit D20, for example, has the function of performing calculations on the product of digital data input to the input terminal TN1i and the digital data input to the input terminal TN1i. In addition, the arithmetic unit D20 has the function of adding up multiple products and outputting the digital data corresponding to the sum of the products to the output terminal TNo.

[0409] Figure 12A An example of the arithmetic unit D20 is shown. Figure 12A The arithmetic unit D20 shown includes a multiplication circuit MP, an addition circuit AP, and a register RG.

[0410] In the arithmetic unit D20, the multiplication circuit MP processes digital data (e.g., image P) input from the wiring MLA. in Data P Cin Or data P Pin The product of the multiplication circuit MP and the digital data (e.g., the filter value K) input from the routing MLB is calculated. Additionally, the result of the multiplication circuit MP is input to the adder circuit AP, and the output of the adder circuit AP is stored in register RG. After the output of the adder circuit AP is stored in register RG, when other product operations are performed in the multiplication circuit MP, the value of that product in the adder circuit AP is added to the value stored in register RG, and the result is input to register RG. This process is repeated to perform the product summation. Furthermore, the product summation result is output as digital data to the routing CNL. Note that register RG is controlled by the clock signal input to the routing CLKL and the reset signal input to the routing RSTL.

[0411] For example, in Figure 12A When the arithmetic unit D20 adopts a structure that performs product and sum operations on 8-bit input data, Figure 12A The digital data processed by the arithmetic unit D20 can be as follows Figure 12B As shown. Specifically, when the multiplication circuit MP receives 8 bits of digital data from wiring MLA and 8 bits of digital data from wiring MLB as inputs, the multiplication circuit MP outputs 16 bits of digital data as the result of the multiplication operation. Furthermore, when the adder circuit AP receives 16 bits of digital data from the multiplication circuit MP and 17+α bits of digital data output from register RG as inputs, the adder circuit AP outputs 17+α bits of digital data as the result of the addition operation. Note that α represents the increase in the number of bits produced during the addition operation in the adder circuit AP.

[0412] Note that in Figure 11 In the CDV computing device, the computing unit D20 has a structure that performs a product summation operation based on the data sent to the wiring MLA and the wiring MLB respectively. However, for example, when performing convolution processing in the computing unit D20, the same filter value (sometimes referred to as weight coefficient, multiplier, or multiplicand) is sometimes used repeatedly.

[0413] Therefore, the following instructions specify multiple settings. Figure 12A The shown arithmetic unit D20 is a structure that performs multiple product sum operations simultaneously using multiple identical filter values.

[0414] Figure 13A It is shown Figure 11 The diagram shows a structural example of one of the switching unit D10 and the arithmetic unit D20. Note that... Figure 13A The storage circuit section ME12 is also shown.

[0415] exist Figure 13A In this context, the arithmetic unit D20 includes, for example, arithmetic units D20_1 to D20_k (where k is an integer greater than or equal to 1).

[0416] Note that arithmetic units D20_1 to D20_k can, for example, use... Figure 12A The circuit shown. Specifically, the arithmetic units D20_1 to D20_k can use Figure 13B The arithmetic unit D20_h is shown (h is an integer greater than or equal to 1 and less than or equal to k). For more information on the arithmetic unit D20_h, please refer to [reference needed]. Figure 12A and Figure 12B Explanation of the arithmetic unit D20.

[0417] Additionally, the routing ILA includes, for example, routing ILA_1 to routing ILA_k. Additionally, the routing ILB includes, for example, routing ILB_1 to routing ILB_k. Additionally, the routing MLA includes, for example, routing MLA_1 to routing MLA_k. Additionally, the routing CNL includes, for example, routing CNL_1 to routing CNL_k.

[0418] Each of the multiple output terminals TMo of the switching unit D10 is connected to wiring MLA_1 to wiring MLA_k in a one-to-one manner.

[0419] The input terminal TN1i of the arithmetic unit D20_1 is connected to wiring MLA_1, the input terminal TN2i of the arithmetic unit D20_1 is connected to wiring MLB, and the output terminal TNo of the arithmetic unit D20_1 is connected to wiring CNL_1. Similarly, the input terminal TN1i of the arithmetic unit D20_k is connected to wiring MLA_k, the input terminal TN2i of the arithmetic unit D20_k is connected to wiring MLB, and the output terminal TNo of the arithmetic unit D20_k is connected to wiring CNL_k.

[0420] In other words, the input terminal TN1i of each of the arithmetic units D20_1 to D20_k is connected to each of the plurality of output terminals TNo of the switching unit D10 in a one-to-one manner.

[0421] Image P inA portion of the area (hereinafter referred to as A) in Multiple digital data included in (x) are sent together to each of the wiring ILA_1 to ILA_k. Specifically, for example, the image P, which is the object of the convolution processing performed in the arithmetic units D20_1 to D20_k. in Multiple digital data contained within a portion of the area are sent to each of the wirings ILA_1 to ILA_k.

[0422] In addition, data P Cin A portion of the area includes multiple digital data or data P Pin Multiple digital data points encompassing a portion of the inner area are sent to each of the wiring ILB_1 to ILB_k. Specifically, for example, data P is the object of convolution processing performed in the arithmetic units D20_1 to D20_k. Cin A portion of the area includes multiple digital data or data P Pin Multiple digital data contained within a portion of the area are sent to each of the wiring ILB_1 to wiring ILB_k.

[0423] Here, the switching unit D10 has, for example, the following function: selecting one of the input terminal TM1i connected to wiring ILA_1 and the input terminal TM2i connected to wiring ILB_1, and outputting the data input to the selected terminal to the output terminal TMo connected to wiring MLA_1. Similarly, the switching unit D10 has, for example, the following function: selecting one of the input terminal TM1i connected to wiring ILA_k and the input terminal TM2i connected to wiring ILB_k, and outputting the data input to the selected terminal to the output terminal TMo connected to wiring MLA_k.

[0424] For example, wiring MLA_1 is used to input digital data output from the first output terminal TMo of the switching unit D10 to the input terminal TN1i of the arithmetic unit D20_1. Similarly, wiring MLA_k is used, for example, to input digital data output from the kth output terminal TMo of the switching unit D10 to the input terminal TN1i of the arithmetic unit D20_k. Note that in Figure 13A In the image P, the numerical data is recorded as A(1) and A(k) respectively. Furthermore, A(1) and A(k) can be included in the above image P. in Digital data in a portion of the area, including data P Cin Digital data within a portion of the area or included in data P Pin Digital data within a portion of the area.

[0425] Wiring CNL_1 is used, for example, as the wiring for inputting digital data output from the output terminal TNo of the arithmetic unit D20_1 to the storage circuit unit ME13. Similarly, wiring CNL_k is used, for example, as the wiring for inputting digital data output from the output terminal TNo of the arithmetic unit D20_k to the storage circuit unit ME13. Note that the digital data here can be, for example, the data resulting from convolution processing performed in the arithmetic unit D20. Furthermore, in Figure 13A In the middle, this data is recorded as P. Cout (1) and P Cout (k). Note that the above P Cout It can be P Cout (1) and P Cout Combinations of (k).

[0426] By Figure 13A The structure of the switching unit D10 and the arithmetic unit D20 shown is applied to Figure 11 The arithmetic unit CDV can input multiple identical filter values ​​to each of the arithmetic units D20_1 to D20_k, and can simultaneously perform a product-sum operation on each of the arithmetic units D20_1 to D20_k. Note that in Figure 13A The input order of data will be explained later in the switching unit D10 and the arithmetic unit D20 shown.

[0427] [Processing Department D30]

[0428] Processing unit D30, for example, has the function of processing data P read from storage circuit unit ME11. C It performs pooling processing. Furthermore, the processing unit D30 also has the function of processing the data P output through pooling processing. Pout The function of sending data to the storage circuit section ME11 is also included. In addition to pooling processing, the processing section D30 can also perform function operations and normalization operations (constantization). Furthermore, an activation function can be used as such a function.

[0429] [Storage Circuit Section ME11 to Storage Circuit Section ME13]

[0430] The storage circuit section ME11 is used to hold input data (e.g., data P) input to the arithmetic unit D20 in the arithmetic device CDV. Cin or P Pin ) and output data (e.g., data P) from the arithmetic unit D20 Cout The storage device is used to store input data (e.g., filter value K) input to the arithmetic unit D20. Additionally, the storage circuit section ME12 is used to store input data (e.g., filter value K) input to the arithmetic unit D20. Furthermore, the storage circuit section ME13 is used to store input data W that is input to the circuit WCS. in (1) to W in(n) storage device (e.g., weight coefficients).

[0431] Particularly preferred is that the storage circuit section ME12 is disposed, for example, near the arithmetic section D20, to read the filtered value K and send it to the arithmetic section D20. For example, the storage circuit section ME12 is preferably stacked above or below the arithmetic section D20.

[0432] Furthermore, it is preferable that the storage circuit section ME13 is disposed, for example, near the circuit WCS, to read out the weighting coefficients and send them to the circuit WCS. For example, the storage circuit section ME13 is preferably stacked above or below the circuit WCS.

[0433] Figure 14A The storage circuit MEX is an example of a circuit structure that can be applied to each of the storage circuit sections ME11 to ME13 included in the computing device CDV.

[0434] in addition, Figure 14A The diagram illustrates a cell array MEA and matrix-like memory cells MC[1,1], MC[u,1], MC[1,v], and MC[u,v] arranged in u rows and v columns within the MEA (where u is an integer greater than or equal to 1, and v is an integer greater than or equal to 1). Additionally... Figure 14A The diagram shows routing from WWL_1 to WWL_u, from RWL_1 to RWL_u, from WBL_1 to WBL_v, and from RBL_1 to RBL_v. Additionally, Figure 14A The circuits WWD, RBD, WBD, and RBD are shown. Additionally, Figure 14A The wiring DIL connected to circuit WBD and the wiring DOL connected to circuit RBD are shown.

[0435] The storage cell MC[1,1] configured in the first row and first column is connected to wiring WWL_1, wiring RWL_1, wiring WBL_1, and wiring RBL_1. Furthermore, the storage cell MC[u,1] configured in the u-th row and first column is connected to wiring WWL_u, wiring RWL_u, wiring WBL_1, and wiring RBL_1. Furthermore, the storage cell MC[1,v] configured in the first row and v-th column is connected to wiring WWL_1, wiring RWL_1, wiring WBL_v, and wiring RBL_v. Furthermore, the storage cell MC[u,v] configured in the u-th row and v-th column is connected to wiring WWL_u, wiring RWL_u, wiring WBL_v, and wiring RBL_v.

[0436] The circuit WWD is connected to each of the wirings WWL_1 to WWL_u. Additionally, the circuit RWD is connected to each of the wirings RWL_1 to RWL_u. Additionally, the circuit WBD is connected to each of the wirings WBL_1 to WBL_v. Additionally, the circuit RBD is connected to each of the wirings RBL_1 to RBL_v.

[0437] The WWD circuit is used, for example, as a write word line driver circuit. Additionally, the RWD circuit is used, for example, as a read word line driver circuit. Furthermore, the WBD circuit is used, for example, as a write bit line driver circuit. Additionally, the RBD circuit is used, for example, as a read bit line driver circuit.

[0438] Additionally, the circuit WBD has the function of receiving input data sent to the wiring DIL and sending the input data to one of the wirings WBL_1 to WBL_v. Furthermore, the circuit WBD has the function of selecting one of the wirings RBL_1 to RBL_v and sending the read data from the memory cell MC flowing through the selected wiring to the wiring DOL.

[0439] For example, in Figure 11 The storage circuit section ME11 uses Figure 14A When the storage circuit MEX is shown, the wiring ILB and Figure 14A The wiring DOL connection. Additionally, in Figure 11 The storage circuit section ME12 uses Figure 14A When the storage circuit MEX is shown, the wiring MLB and Figure 14A The wiring DOL connection. Additionally, in Figure 11 The storage circuit section ME11 uses Figure 14A When the storage circuit MEX is shown, the wiring CNL and Figure 14A DIL wiring connection.

[0440] For example, in Figure 11 The storage circuit section ME13 uses Figure 14A When the storage circuit MEX is shown, any one of the wirings IWL_1 to IWL_n is connected to... Figure 14A The wiring DOL connection. Additionally, in Figure 11 The storage circuit section ME11 uses Figure 14A When the storage circuit MEX is shown, any one of the wirings IXL_1 to IXL_m is connected to... Figure 14A The wiring DOL connection. Additionally, in Figure 11 The storage circuit section ME11 uses Figure 14A When the storage circuit MEX is shown, wiring OL_1 to wiring OL_n is connected to... Figure 14A DIL wiring connection.

[0441] Next, the memory cells applicable to memory cells MC[1,1] to memory cells MC[u,v] will be described.

[0442] Figure 14B This is a diagram illustrating an example of the circuit structure for each of the memory cells MC[1, 1] to MC[u, v] applicable to the memory circuit MEX. Figure 14B In the memory cell MC, transistors M1, M2, and M3 are included, along with capacitor C1. Figure 14B The memory cell MC shown has a structure including a gain unit with three transistors. In particular, when transistors M1 and M3 are OS transistors, the memory cell MC is sometimes referred to as NOSRAM (registered trademark) (NonvolatileOxide Semiconductor Random Access Memory).

[0443] In particular, by using one or more OS transistors selected from transistors M1 to M3, the leakage current of the selected transistors can be suppressed, thereby reducing the power consumption of the arithmetic circuit. Specifically, when transistor M1 is in a non-conducting state, the leakage current from the holding node (e.g., the first terminal of transistor M1, the first terminal of capacitor C1, and the gate of transistor M2) to the wiring WBL can be made very small, thus reducing the refresh operation of the holding node potential. Furthermore, by reducing the refresh operation, the power consumption of the arithmetic circuit can be reduced.

[0444] Furthermore, the circuits WWD, RWD, WBD, and RBD preferably all include CMOS circuits. Moreover, the CMOS circuits preferably include Si transistors. For example, from a reliability point of view, Si transistors are preferred over OS transistors when manufacturing p-channel transistors. Therefore, it is preferable to fabricate the circuits WWD, RWD, WBD, and RBD on a semiconductor substrate made of silicon, and to fabricate the memory cell MC above the circuits WWD, RWD, WBD, and RBD.

[0445] Furthermore, when semiconductor devices are highly integrated onto a chip, heat is sometimes generated within the chip due to circuit driving. This heat increases the temperature of the transistor, causing changes in its characteristics, potentially leading to changes in field-effect mobility and a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, thus they are less prone to changes in field-effect mobility due to temperature variations and less prone to a decrease in operating frequency. Moreover, even at higher temperatures, OS transistors tend to maintain the characteristic of an exponential increase in drain current relative to the gate-source voltage. Therefore, by using OS transistors, computation and processing can be easily performed even in high-temperature environments. Therefore, when constructing a semiconductor device with high resistance to heat generated by driving circuits such as WWD, RWD, WBD, and RBD on a silicon-based semiconductor substrate, OS transistors are preferably used as the transistors included in the circuit positioned above the driving circuit.

[0446] Figure 14B Transistors M1 through M3 are shown, each including a back gate. Although the connection structure of this back gate is not illustrated, its electrical connections can be determined during the design process. For example, in transistors including a back gate, to increase the transistor's on-state current, connections may be made with... Figure 3A Transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D shown can similarly have their gates connected to the back gate. That is, for example, the gate of transistor M1 can also be connected to the back gate. Furthermore, for example, in transistors including a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, [the following can be done]... Figure 3B The transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D shown can also be provided with wiring to connect the back gate of the transistor to external circuits, etc., and the back gate of the transistor can be supplied with potential through the external circuits, etc.

[0447] In addition, although Figure 14B Transistors M1 to M3 shown include a back gate, but Figure 14B Transistors M1 to M3 in the memory cell MC can also be connected to... Figure 1A Transistors F1a, F1b, F2, F5, F1Da, F1Db, F2D, and F5D shown are also single-gate transistors without a back gate. Alternatively, they may have a structure where some transistors include a back gate and others do not.

[0448] In addition, although Figure 14B Transistors M1 to M3 shown are n-channel transistors, but the structure of the memory cell MC is not limited to this. For example, n-channel transistors can be used as transistors M2 and M3, and transistor M1 can be replaced with a p-channel transistor.

[0449] The first terminal of transistor M1 is connected to the gate of transistor M2 and the first terminal of capacitor C1. The second terminal of transistor M1 is connected to wiring WBL, and the gate of transistor M1 is connected to wiring WWL. Additionally, the first terminal of transistor M2 is connected to the first terminal of transistor M3, and the second terminal of transistor M2 is connected to wiring CVLB. The second terminal of transistor M3 is connected to wiring RBL, and the gate of transistor M3 is connected to wiring RWL.

[0450] Figure 14B The wiring shown in the diagram can be WWL Figure 14A The shown wiring is any one of WWL_1 to WWL_u. Additionally, Figure 14B The wiring RWL shown can be Figure 14A Any one of the wirings RWL_1 to RWL_u shown. Figure 14B The wiring WBL shown can be Figure 14A Any one of the wirings WBL_1 to WBL_v shown. Additionally, Figure 14B The wiring RBL shown can be Figure 14A Any one of the wirings RBL_1 to RBL_v shown.

[0451] Additionally, the CVLA (Cable CVA) is used as a cable to supply a fixed potential. This fixed potential can be, for example, a high-level potential, a low-level potential, a ground potential, or a negative potential. Similarly, the CVLB (Cable CVB) is also used as a cable to supply the fixed potentials mentioned above. Furthermore, the potential sent to the CVLA and CVLB can also be, for example, a variable potential (e.g., also referred to as a pulse voltage or pulse signal) instead of a fixed potential.

[0452] exist Figure 14B In the memory cell MC shown, by using an OS transistor as transistor M1, the current flowing between the source and drain of transistor M1 in the off state (sometimes called leakage current) can be minimized. That is, Figure 14B The memory cell MC shown uses an OS transistor as a transistor M1 and takes advantage of the fact that the charge corresponding to the data is kept in the storage circuit by taking advantage of the fact that the leakage current is very small, so it can be used as a non-volatile memory.

[0453] In addition, Figure 14B In addition to the storage unit MC, for example, it can be Figure 14CThe storage unit MC shown is used for Figure 14A The storage circuit MEX has storage cells MC[1,1] to storage cells MC[u,v]. Figure 14C storage unit MC and Figure 14B The difference between the memory cell MC and the wired wiring WBL and RBL is that the wiring WBL and RBL are combined into a single wired wiring BL. Figure 14B Compared to the structure of the storage cell MC shown, Figure 14C The structure of the memory cell MC shown can reduce the wiring extending in the column direction, thus reducing the circuit area. Furthermore, depending on the situation, the recording density of the memory section can be increased.

[0454] Available for Figure 14A The circuit structure of the storage circuit MEX is not limited to Figure 14B and Figure 14C The storage unit MC is shown. For example, it can be... Figure 15A The storage unit MC shown is used for Figure 14A The storage circuit MEX. In Figure 15A In this, the storage unit MC includes a transistor M1 and a capacitor C1. Figure 15A The memory cell MC shown includes a transistor. Thus, a circuit consisting of a transistor and a capacitor is sometimes called DRAM (Dynamic Random Access Memory). In particular, when transistor M1 is an OS transistor, the memory cell MC is sometimes called DOSRAM (a registered trademark) (Dynamic Oxide Semiconductor Random Access Memory).

[0455] Figure 15A The diagram shows a memory cell MC including transistor M1 and capacitor C1. Alternatively, the aforementioned OS transistor can be used as transistor M1.

[0456] exist Figure 15A In this circuit, the first terminal of transistor M1 is connected to the first terminal of capacitor C1, the second terminal of transistor M1 is connected to wiring WBL, and the gate of transistor M1 is connected to wiring WWL. Additionally, the second terminal of capacitor C1 is connected to wiring CVLA.

[0457] Figure 15A The wiring shown, WWL, is used as both the write word line and the read word line. Therefore, in... Figure 15A The storage unit MC is used as Figure 14A When the storage circuit MEX is in the storage cell MC, Figure 14AThe circuit shown, WWD, is preferably used as both the write word line driver circuit and the read word line driver circuit. At this time, in Figure 14A In the storage circuit MEX, circuit RWD and wiring RWL_1 to wiring RWL_u can also be omitted.

[0458] in addition, Figure 15A The wiring diagram WBL shown is used as both the write bit line and the read bit line. Therefore, when... Figure 15A The storage unit MC is used as Figure 14A When the storage circuit MEX is in the storage cell MC, Figure 14A Each of the wirings WBL_1 to WBL_v shown is preferably connected to the circuit RBD. At this time, in Figure 14A In the storage circuit MEX, wiring RBL_1 to wiring RBL_v may not be set.

[0459] In addition, as a product that can be used Figure 14A The circuit structure of the storage circuit MEX, for example, Figure 15B As shown in the memory cell MC, a 2T (transistor) type NOSRAM circuit structure can also be used. Figure 15B The diagram shows a storage circuit MEX including transistor M1, transistor M2, and capacitor C1. Alternatively, the aforementioned OS transistor can be used as transistors M1 and M2.

[0460] exist Figure 15B In this configuration, the first terminal of transistor M1 is connected to the gate of transistor M2 and the first terminal of capacitor C1. The second terminal of transistor M1 is connected to wiring WBL, and the gate of transistor M1 is connected to wiring WWL. The first terminal of transistor M2 is connected to wiring RBL, and the second terminal of transistor M2 is connected to wiring SL. Additionally, the second terminal of capacitor C1 is connected to wiring RWL.

[0461] Figure 15B The wiring shown, WWL, is used as the write word line. Figure 15B The routing RWL shown is used as the read word line. Additionally, Figure 15B The wiring WBL shown is used as the write bit line. Figure 15B The wiring RBL shown is used as the read bit line.

[0462] in addition, Figure 15B The wiring SL shown is used as the source line. Alternatively, wiring SL can be supplied with a fixed or variable potential. Furthermore, wiring SL can be supplied with any amount of current.

[0463] As available Figure 14A The circuit structure of the storage circuit MEX, for example, Figure 15CAs shown in the memory cell MC, a circuit combining three transistors of NOSRAM can also be used. Figure 15C The storage unit MC includes storage units MCP and MCN. Each storage unit MCP and MCN holds logically distinct data. In other words, storage units MCP and MCN are used as complementary storage units.

[0464] The structures of the storage unit MCP and storage unit MCN can be referred to Figure 14B The description of the memory cell MC shown is provided below. Note that the following is also shown. Figure 15C The storage cell MCP and storage cell MCN shown are Figure 14B Different parts of the storage unit MC shown.

[0465] The gates of transistors M1 included in memory cells MCP and MCN are connected to wiring WWL. Furthermore, the second terminals of capacitors C1 included in memory cells MCP and MCN are connected to wiring CVLA. Additionally, the gates of transistors M3 included in memory cells MCP and MCN are connected to wiring RWL. Furthermore, the second terminals of transistors M2 included in memory cells MCP and MCN are connected to wiring CVLB.

[0466] In the memory cell MCP, the second terminal of transistor M1 is connected to wiring WBLP. Additionally, the second terminal of transistor M3 is connected to wiring RBLP.

[0467] Additionally, in the memory cell MCN, the second terminal of transistor M1 is connected to wiring WBLN. Furthermore, the second terminal of transistor M3 is connected to wiring RBLN.

[0468] and Figure 14A The wiring WBL shown is the same. Figure 15C The wiring WBLP and WBLN shown are used as write bit lines. Additionally, with... Figure 14A The wiring RBL shown is the same. Figure 15C The wiring RBLP and wiring RBLN shown are used as read bit lines.

[0469] In particular, by acting as Figures 15A to 15C The transistors included in the memory cell MC shown are OS transistors and are used as... Figures 1A to 4B The transistors included in the multiplication unit IM and the drive unit IMD shown are OS transistors, which can be manufactured in the same process. Figure 14A The cell array MEA shown Figure 5The shown arithmetic circuit ANP has a cell array CA. This reduces the number of steps required to manufacture the arithmetic device CDV, thereby lowering production costs. Furthermore, by using OS transistors as the transistors included in the memory cell MC, multiplication cell IM, and drive cell IMD, the cell array MEA and cell array CA can be overlapped. This reduces the circuit area of ​​the arithmetic device CDV.

[0470] <Examples of how a computing device works>

[0471] Next, the explanation Figure 11 The diagram shows an example of the operation of a computing device CDV. Note that the switching unit D10 and the computing unit D20 included in the computing device CDV employ... Figure 13A The structure shown.

[0472] Here, we will explain the process. Figure 16 The operation of the CDV computing device for AlexNet computation is shown. Figure 16 AlexNet consists of an input layer INLY, convolutional layers CNV1 to CNV5, pooling layers PL1, PL2, PL5, and fully connected layers FC6 to FC8. Figure 16 AlexNet consists of an input layer INLY, a convolutional layer CNV1, a pooling layer PL1, a convolutional layer CNV2, a pooling layer PL2, a convolutional layer CNV3, a convolutional layer CNV4, a convolutional layer CNV5, a pooling layer PL5, a fully connected layer FC6, a fully connected layer FC7, and a fully connected layer FC8.

[0473] [Input Layer INLY]

[0474] In the work of INLY in the input layer, Figure 11 The computing device CDV, for example, is input with an image P of 224×224 pixels. in Note that a pixel includes red, green, and blue subpixels, and the total number of subpixels is three colors (red, green, and blue) × 224 × 224. Additionally, image P... in The image has three channels: red, green, and blue. Therefore, image P... in The amount of image data included that is input to the CDV computing device is 3×224×224.

[0475] exist Figure 11 In the CDV computing device, the wiring ILA is input to the image P. in Therefore, the input terminal TM1i of the switching section D10 of the arithmetic circuit DGP is input to the image P. in .

[0476] Note that in this example, image P inThe input value of the x-th row and y-th column of the z-th input channel (where z is an integer greater than 1 and less than 3) is recorded as p. in [x, y, z]. Note that x represents the image P. in The line address, y represents the image P in The column address. In other words, in the input layer INLY, x is an integer greater than 1 and less than 2^24, and y is an integer greater than 1 and less than 2^24.

[0477] [Convolutional layer CNV1]

[0478] In the convolutional layer CNV1, the computation unit D20 processes the image P. in Convolution processing is performed. Specifically, a filter (also called a convolution kernel) for the convolution process CNV1 is applied to the image P. in Area A in The product and sum operation of the included image data.

[0479] In the convolutional layer CNV1, the filter size (also known as the kernel size) is set to 11, the number of output channels (also known as the number of kernels) is set to 96, and the stride is set to 4. This applies to images selected from P. in The region is subjected to convolution processing. Furthermore, the number of filtered values ​​in a single convolution kernel is (filter size). 2 × (Number of input channels). Due to image P in The number of input channels is 3, so the number of filtered values ​​in one convolutional kernel of convolutional layer CNV1 is 11×11×3.

[0480] Here, the s-th convolutional kernel in the CNV1 convolutional layer (where s is an integer greater than 1 and less than 96) is denoted as K. C1 （s） Additionally, the convolution kernel K... C1 The included filter values ​​are recorded as k. C1 （s） [p, q, r]. Note that p represents the row address of the convolution kernel, q represents the column address of the convolution kernel, and r represents the ordinal number of the input channel. In other words, in the convolutional layer CNV1, p is an integer greater than or equal to 1 and less than 11, q is an integer greater than or equal to 1 and less than 11, and r is an integer greater than or equal to 1 and less than 3.

[0481] For example, Figure 17 This shows the process selected from image P. in Area A in (1) with convolution kernel K C1 （1） Perform a product sum operation and output the data p as the result. C1 （1） Example of (1). Region A in(x) where x represents the image selected from P. in The ordinal number of the region. Furthermore, the data p C1 （s） In (x), s represents the ordinal number of the output channel. Additionally, the data p... C1 （s） (x) where x is region A in The ordinal number x of (x).

[0482] Additionally, since the step size is 4, it will start from region A. in (1) The region that drifts 4 in the direction of movement is called region A. in (2). For example, Figure 18 This shows the process selected from image P. in Area A in (2) with convolution kernel K C1 （1） Perform a product sum operation and output the data p as the result. C1 （1） (2) is an example.

[0483] Note that in image P in Given an image P with a pixel count of 224×224 and a step size of 4, the image selected is... in The number of regions is 3025 (=55) 2 In this embodiment, they will be referred to as region A. in (1) To region A in (3025).

[0484] As described above, the selection from image P is sequentially made according to the step size. in The region drift is performed, and each time the region drifts, the region is processed with the convolution kernel K. C1 （1） The product and sum operations yield a matrix-like output data of 55 rows and 55 columns. Furthermore, the convolution kernel in the CNV1 convolutional layer is kernel K. C1 （1） To convolution kernel K C1 （96） (The number of kernels in convolutional layer CNV1 is 96), therefore the result is P, which is the output data of convolutional layer CNV1 as 55×55×96. C1 .

[0485] Here, in the convolution processing of the CNV1 convolution layer, a convolution kernel is subjected to convolution with the image P. in The product and sum operation is performed on each of the selected multiple regions. Therefore, as the structure of the arithmetic circuit, it is preferable to perform the filtering values ​​included in a convolution kernel together with those from the image P. in The operation of multiplying the data included in each of the selected regions.

[0486] For example, preferably, in Figure 11 And in the structure of the computing device CDV shown in Figure 13, region A in (1) The included data is sent to the input terminal TN1i (wiring MLA_1) of the arithmetic unit D20_1, area A in (2) The included data is sent to the input terminal TN1i (wiring MLA_2 (not shown)) of the arithmetic unit D20_2 (not shown), area A in (3) The included data is sent to the input terminal TN1i (wiring MLA_3 (not shown)) of the arithmetic unit D20_3 (not shown). Similarly, area A in The data included in (3025) is preferably sent to the wiring MLA_3025 (not shown). Note that at this time, the k of the wiring MLA_k and the arithmetic unit D20_k shown in FIG13 is preferably 3025 or higher.

[0487] Figure 19 The timing diagram shows the specific order in which each data item is sent. Figure 19 This is a timing diagram showing the data input to wirings MLA_1 to MLA_3 (input terminals TN1i of the arithmetic unit D20) from time T01 to time T04 and in the vicinity, the filtered value input to wiring MLB (input terminal TN2i of the arithmetic unit D20), and the data output to wirings CNL_1 to CNL_3 (output terminals TNo of the arithmetic unit D20). Note that the data output to wirings MLA_4 to MLA_3025 and wiring CNL_4 to CNL_3025 is omitted from this timing diagram.

[0488] First, consider the period from time T01 to time T02. When the wiring MLB input convolution kernel K... C1 （1） The filter value k C1 （1） When [1, 1, 1] (i.e., the filter value k is read from the storage circuit section ME12), the filter value k is then read out. C1 （1） When [1, 1, 1], it is preferable to input p to the wiring MLA_1. in [1, 1, 1], input p to MLA_2 for routing in [1, 5, 1], input p to routing MLA_3 in [1, 9, 1]. Additionally, it is preferable that the filter value input to the wiring MLB is from k... C1 （1） [1, 1, 1] becomes k C1 （1） At [1, 2, 1] (i.e., the filter value k is read from the storage circuit section ME12), C1（1） When [1, 2, 1], wiring MLA_1 is input p in [1, 2, 1], routing MLA_2 is input p in [1, 6, 1], routing MLA_3 is input to p in [1, 10, 1].

[0489] Thus, in region A in (1) To region A in Each of (3025) includes data and convolution kernel K. C1 （1） When the calculation of the product of the included filter values ​​is completed, the arithmetic unit D20_1 outputs the output of the wiring CNL_1 as region A. in (1) with convolution kernel K C1 （1） p, the result of the product of the product C1 （1） (1). In addition, the arithmetic unit D20_2 outputs the wiring CNL_2 as region A. in (2) with convolution kernel K C1 （1） p, the result of the product of the product C1 （1） (2). In addition, the arithmetic unit D20_3 outputs the wiring CNL_3 as region A. in (3) with convolution kernel K C1 （1） p, the result of the product of the product C1 （1） (3).

[0490] Additionally, p is output to routing CNL_1 to routing CNL_3025 respectively. C1 （1） (1) to p C1 （1） (3025) is written to the storage circuit section ME11.

[0491] During the period from time T02 to time T03, the convolution kernel K is used in the same way as during the period from time T01 to time T02. C1 （2） Perform area A in (1) To region A in Each of (3025) undergoes convolution processing. At this point, the resulting data (e.g., p) C1 （2） (1) to p C1 （2） (3025) was written to the storage circuit section ME11.

[0492] Additionally, at the end of the convolution kernel K C1（2） After convolution processing, the convolution kernel is changed sequentially to convolution kernel K. C1 （3） To convolution kernel K C1 （95） Using each convolution kernel to perform region A in (1) To region A in Each of (3025) undergoes convolution processing. Additionally, in the convolution kernel K... C1 （3） To convolution kernel K C1 （95） In each of them, the data output from wiring CNL_1 to wiring CNL_3025 is written to the storage circuit section ME11 in the same way as described above.

[0493] During the period from time T03 to time T04, the convolution kernel K is used in the same way as during the period from time T01 to time T02. C1 （96） Perform area A in (1) To region A in Each of (3025) is convolved. Then, in region A... in (1) To region A in Each of (3025) includes data and convolution kernel K. C1 （96） When the calculation of the product of the included filter values ​​is completed, the arithmetic unit D20_1 outputs the output of the wiring CNL_1 as region A. in (1) with convolution kernel K C1 （96） p, the result of the product of the product C1 （96） (1). In addition, the arithmetic unit D20_2 outputs the wiring CNL_2 as region A. in (2) with convolution kernel K C1 （96） p, the result of the product of the product C1 （96） (2). In addition, the arithmetic unit D20_3 outputs the wiring CNL_3 as region A. in (3) with convolution kernel K C1 （96） p, the result of the product of the product C1 （96） (3).

[0494] Additionally, p is output to routing CNL_1 to routing CNL_3025 respectively. C1 （96） (1) to p C1 （96） (3025) is written to the storage circuit section ME11.

[0495] like Figure 19 As shown in the timing diagram, by sequentially sending data corresponding to the region of each of the plurality of first terminals of the arithmetic unit D20 and sequentially sending the filter value included in the convolution kernel to the second terminals of the arithmetic unit D20, the arithmetic unit D20 can simultaneously process multiple regions (the aforementioned region A) in one convolution kernel. in (1) To region A in (3025)) each convolution process. Additionally, by sequentially switching the convolution kernels and repeatedly performing the same operation, P, which is the output data from convolutional layer CNV1, can be obtained. C1 .

[0496] [Pooling layer PL1]

[0497] In pooling layer PL1, P, which is the output data from convolutional layer CNV1, C1 Pooling is performed. Pooling refers to the following process: sequentially selecting specified regions from the data output from convolutional layers, performing specified processing in each region to extract features, and then configuring these features into a matrix.

[0498] like Figure 16 As shown, in the pooling layer PL1, the convolution kernel size is 3 pairs of data P C1 The selected regions are subjected to pooling. Note that the step size is 2, and this pooling process is max pooling.

[0499] For example, Figure 20A Showing data selected from P C1 Area A of the first input channel C1in （1） (1) Perform max pooling and output the data p as the processing result. p1 （1） (1) is an example. Additionally, because the kernel size is 3, region A... C1in （1） (1) Includes 3×3 data.

[0500] Note that area A C1in （s） (A) s represents data P C1 The ordinal number of the input channel, region A C1in （s） (A) where A represents data selected from P. C1 The ordinal number of the region, data p p1 （s） (A) where s represents the ordinal number of the output channel and p represents the data. p1 （s） (A) where A is region A C1in （s） The ordinal number A of (A).

[0501] Additionally, since the step size is 2, from region A... C1in （1） (1) The region that drifts 2 in the direction of movement is region A. C1in （1） (2). For example, Figure 20B Showing the selection of data P C1 Area A C1in （1） (2) Perform max pooling and output the data p as the processing result. p1 （1） (2) is an example.

[0502] Note that in data P C1 Given a quantity of 55×55×96 and a step size of 2, select from data P C1 The number of regions is 729 (=27) 2 ).

[0503] As described above, by sequentially processing the data selected from P according to the step size... C1 Pooling the region yields a 27x27 matrix output. Additionally, although the data P was explained above... C1 The first input channel, but by similarly pooling the second to 96th input channels, the result is that the output from the pooling layer PL1 is P as 27×27×96 output data. P1 .

[0504] exist Figure 11 In the operation of the shown computing device CDV, for example, P, which is the output data of the convolutional layer CNV1, is read from the storage circuit section ME11. C1 The pooling process can then be performed in the processing unit D30. Furthermore, at the end of the pooling process, the processing unit D30 outputs the data P as the result of the processing. P1 Additionally, the data P output from the processing unit D30 P1 It was written to the storage circuit section ME11.

[0505] [Convolutional Layer CNV2]

[0506] In the convolutional layer CNV2, the data P output by the pooling layer PL1 is... P1 Convolution processing is performed. Specifically, a convolution kernel selected from P is used for the CNV2 convolution processing. P1 The product and sum of data within the region.

[0507] like Figure 16 As shown, in the convolutional layer CNV2, pairs of kernels selected from P are used with a kernel size of 5 and a kernel number of 256. P1The region is processed by convolution. Note that the stride is 1.

[0508] Similar to the description of convolutional layer CNV1, convolution processing is performed in convolutional layer CNV2, and P is output from convolutional layer CNV2 as 27×27×256 output data. C2 .

[0509] exist Figure 11 In the operation of the shown computing device CDV, for example, P, which is the output data of the pooling layer PL1, is read from the storage circuit section ME11. P1 And send it to the wiring ILB. Furthermore, in the switching unit D10, the signal input from the wiring ILB is switched to be sent to the wiring MLA, and P is input to multiple input terminals of the arithmetic unit D20. P1 .

[0510] In addition, similar to convolutional layer CNV1, 256 convolutional kernels of convolutional layer CNV2 are sequentially read from the storage circuit section ME12 and P is performed in the arithmetic section D20. P1 This can be achieved through convolution processing. Therefore, the data P output from the computation unit D20... C2 It was written to the storage circuit section ME11.

[0511] [Pooling layer PL2]

[0512] In pooling layer PL2, P, which is the output data from convolutional layer CNV2, C2 Perform pooling processing.

[0513] like Figure 16 As shown, in the pooling layer PL2, the convolution kernel size is 3 pairs of data P C2 The selected regions are subjected to pooling. Note that the step size is 2, and this pooling process is max pooling.

[0514] Similar to the description of pooling layer PL1, by performing pooling processing in pooling layer PL2, P is output from pooling layer PL2 as 13×13×256 output data. P2 .

[0515] In addition, in pooling layer PL2 Figure 11 The operation of the computing device CDV shown can be referenced from the description of the operation of the computing device CDV in the pooling layer PL1.

[0516] [Convolutional Layer CNV3]

[0517] In the convolutional layer CNV3, the data P output by the pooling layer PL2 is... P2 Convolution processing is performed. Specifically, a convolution kernel selected from P is used for the CNV3 convolution processing. P2 The product and sum of data within the region.

[0518] like Figure 16 As shown, in the convolutional layer CNV3, pairs of kernels with a kernel size of 3 and a kernel number of 384 are selected from P. P2 The region is processed by convolution. Note that the stride is 1.

[0519] Similar to the description of convolutional layer CNV1, convolution processing is performed in convolutional layer CNV3, and P is output from convolutional layer CNV3 as 13×13×384 output data. C3 .

[0520] Additionally, in the CNV3 convolutional layer Figure 11 The operation of the shown computing device CDV can be referenced from the description of the operation of the computing device CDV in the convolutional layer CNV2.

[0521] [Convolutional layer CNV4]

[0522] In convolutional layer CNV4, the data P output by convolutional layer CNV3 is processed. C3 Convolution processing is performed. Specifically, a convolution kernel selected from P is used for the CNV4 convolution processing. C3 The product and sum of data within the region.

[0523] like Figure 16 As shown, in the convolutional layer CNV4, pairs of kernels with a kernel size of 3 and a kernel number of 384 are selected from P. C3 The region is processed by convolution. Note that the stride is 1.

[0524] Similar to the description of convolutional layer CNV1, convolution processing is performed in convolutional layer CNV4, and P is output from convolutional layer CNV4 as 13×13×384 output data. C4 .

[0525] Additionally, in the CNV4 convolutional layer Figure 11 The operation of the shown computing device CDV can be referenced from the description of the operation of the computing device CDV in the convolutional layer CNV2.

[0526] [Convolutional layer CNV5]

[0527] In convolutional layer CNV5, the data P output by convolutional layer CNV4 is processed. C4 Convolution processing is performed. Specifically, a convolution kernel of CNV5 and a kernel selected from P are used for convolution processing. C4 The product and sum of data within the region.

[0528] like Figure 16 As shown, in the convolutional layer CNV5, pairs of kernels with a kernel size of 3 and a kernel number of 256 are selected from P. C4The region is processed by convolution. Note that the stride is 1.

[0529] Similar to the description of convolutional layer CNV1, convolution processing is performed in convolutional layer CNV5, and P is output from convolutional layer CNV5 as 13×13×256 output data. C5 .

[0530] Additionally, in the CNV5 convolutional layer Figure 11 The operation of the shown computing device CDV can be referenced from the description of the operation of the computing device CDV in the convolutional layer CNV2.

[0531] [Pooling layer PL5]

[0532] In pooling layer PL5, P, which is the output data from convolutional layer CNV5, C5 Perform pooling processing.

[0533] like Figure 16 As shown, in pooling layer PL5, a convolution kernel size of 3 is used to generate data from P... C5 The selected regions are subjected to pooling. Note that the step size is 2, and this pooling process is max pooling.

[0534] Similar to the description of pooling layer PL1, pooling is performed in pooling layer PL5, and P is output from pooling layer PL5 as 6×6×256 output data. P5 .

[0535] In addition, in pooling layer PL5 Figure 11 The operation of the computing device CDV shown can be referenced from the description of the operation of the computing device CDV in the pooling layer PL1.

[0536] [Fully Connected Layer FC6]

[0537] In the fully connected layer FC6, the P in the arithmetic circuit ANP of the arithmetic device CDV is the output data from the pooling layer PL5. P5 Perform operations on the fully connected layer.

[0538] like Figure 16 As shown, in the fully connected layer FC6, the number of input channels is 9126 (=6×6×256), and the number of output channels is 4096. In the fully connected layer, for each output channel, the product of all input channel data and its corresponding weight coefficient (first data) is performed to calculate the value of the activation function, which is then used as the input value. Therefore, the number of weight coefficients (first data) required in the fully connected layer FC6 is 4096×9126.

[0539] The data for the Nth output channel (where N is an integer greater than 1 and less than 4096) of the fully connected layer FC6 is z.FC6 When (N), z FC6 (N) can be represented by the following formula (4.1).

[0540] [Equation 6]

[0541] Note that f is the activation function of the fully connected layer FC6. Examples of activation functions include the sigmoid function, tanh function, softmax function, ReLU function, or thresholding function. Furthermore, u FC6 (N) is as shown in the following formula (4.2).

[0542] [Equation 7]

[0543] In addition, p p5 （s） (A) is the A-th data point from the s-th output channel in pooling layer PL5. Furthermore, w FC6（N） （s） (A) corresponds to the Nth channel and p in the fully connected layer FC6. p5 （s） (A) weighting coefficients (first data).

[0544] By using the above formulas (4.1) and (4.2), the z-values ​​of the data from the first output channel to the 4096th output channel of the fully connected layer FC6 can be calculated. FC6 (1) to z FC6 (4096).

[0545] Note that the operation of the above-mentioned fully bonded layer FC6 is preferably performed in... Figure 11 The operation is performed in the arithmetic circuit ANP of the arithmetic device CDV shown. Furthermore, the operation of the arithmetic circuit ANP can be referred to in Embodiment 2.

[0546] Specifically, the first data (weighting coefficient) as digital data is read from the storage circuit section ME13 and input into wiring IWL_1 to wiring IWL_n (here, n is preferably an integer of 4096 or more, for example).

[0547] Here, in Figure 11 The circuitry WCS included in the CDV computing unit is Figure 6AWhen the circuit WCS is shown, each of circuits WCSa_1 to WCSa_n generates a current corresponding to the value of each digital data sent to wirings IWL_1 to IWL_n. Additionally, when switches SA_1 to SA_n of circuit SWCA are all in the open state, the currents generated by circuits WCSa_1 to WCSa_n flow through wirings WCL_1 to WCL_n.

[0548] In addition, Figure 5 In the circuit WSD, for example, when row i is selected in the cell array CA, current from wiring WCL_1 to wiring WCL_n flows through each of the plurality of multiplication units IM[i,1] to IM[i,n] arranged in the i-th row. Here, by maintaining the potential of the gate of the transistor F2 of each of the multiplication units IM[i,1] to IM[i,n], the amount of current flowing between the source and drain of the transistor F2 can be set. Note that the amount of current flowing to the multiplication units IM in the cell array CA is set for rows 1 to 9126. Therefore, the number of rows m of the cell array CA is preferably 9126 or more.

[0549] Additionally, during the period when the current from wiring WCL_1 to wiring WCL_n flows through each of the plurality of multiplication units IM[i,1] to multiplication unit IM[i,n] configured in the i-th row of the cell array CA as described above, the circuit XCS causes the reference current I... ref0 The gate potential of transistor F2d, which flows through wiring XCL_i and maintains the driving unit IMD_i, can be set to I. ref0 Note that the current flowing to the drive unit IMD of the cell array CA is set along with the current setting of the multiplication unit IM. That is, when the current flowing to the multiplication unit IM of the cell array CA is set for rows 1 to 9126, rows 1 to 9126 of the drive unit IMD are also set simultaneously. Through the above process, the first data (weighting coefficients) of the fully connected layer FC6 is written to the multiplication unit IM of the cell array CA.

[0550] Next, after the current settings for the multiplication unit IM and the drive unit IMD of the cell array CA are completed, the output data P from the pooling layer PL5 is read from the storage circuit section ME13. P5 They are then sent to wiring IXL_1 through wiring IXL_m respectively. Figure 11 The circuit XCS in the CDV computing device is Figure 6C When the circuit XCS is shown, P corresponding to digital data is generated in each of circuits XCSa_1 to XCSa_m. P5The amount of current. Therefore, the currents generated by circuits XCSa_1 to XCSa_m flow through wiring XCL_1 to XCL_m. Through the above operation, the second data (P) is input to the multiplication unit IM and the drive unit IMD of the cell array CA. P5 ).

[0551] Through the above work, the cell array CA executes the first data (weight coefficients) and the second data (P). P5 u is obtained by performing a product and sum operation on ) FC6 (1) to u FC6 (4096). Additionally, through... Figure 11 The circuit ITS of the shown arithmetic device CDV performs u FC6 (1) to u FC6 Each of (4096) is an activation function operation for the input value, from which z is obtained. FC6 (1) to z FC6 (4096). Thus, z is output from the fully bonded layer FC6. FC6 (1) to z FC6 The output signal of (4096). Additionally, z FC6 (1) to z FC6 (4096) After being converted into digital data, it is output from the circuit ITS and stored in the storage circuit ME11.

[0552] [Fully Connected Layer FC7]

[0553] In the fully connected layer FC7, the z-axis of the data as the output channel from the fully connected layer FC6... FC6 (1) to z FC6 (4096) Perform the operation of the fully connected layer.

[0554] like Figure 16 As shown, in the fully connected layer FC7, there are 4096 input channels and 4096 output channels. Similar to the fully connected layer FC6, in the fully connected layer FC7, for each output channel, the product of all input channel data and its corresponding weight coefficient (first data) is performed to calculate the value of the activation function, using the result as the input value. Therefore, the number of weight coefficients (first data) required in the fully connected layer FC7 is 4096 × 4096.

[0555] Note that the product sum operation and activation function operation in the fully connected layer FC7 can be found in the description of the fully connected layer FC6.

[0556] In the fully connected layer FC7, the z-axis is input as the output channel of the fully connected layer FC6. FC6 (1) to z FC6At (4096), the z-values ​​of the data output as the first to the 4096th output channels of the fully connected layer FC7 are... FC7 (1) to z FC7 (4096).

[0557] Additionally, in the fully connected layer FC7 Figure 11 The operation of the shown computing device CDV can be referenced from the description of the operation of the computing device CDV in the fully connected layer FC6.

[0558] [Fully Connected Layer FC8]

[0559] In the fully connected layer FC8, the z-axis of the data as the output channel from the fully connected layer FC7... FC7 (1) to z FC7 (4096) Perform the operation of the fully connected layer.

[0560] like Figure 16 As shown, in the fully connected layer FC8, there are 4096 input channels and 1000 output channels. Similar to the fully connected layer FC6, in the fully connected layer FC8, for each output channel, the product of all input channel data and its corresponding weight coefficient (first data) is performed to calculate the value of the activation function, using the result as the input value. Therefore, the number of weight coefficients (first data) required in the fully connected layer FC8 is 1000 × 4096.

[0561] Note that the product summation and activation function operations in the fully connected layer FC8 can be found in the documentation for the fully connected layer FC6.

[0562] In the fully connected layer FC8, the z-axis is input as the output channel of the fully connected layer FC7. FC7 (1) to z FC7 (4096) When the z-axis is output as the data of the first output channel to the 1000th output channel of the fully connected layer FC8, it is used as the output of the fully connected layer FC8. FC8 (1) to z FC8 (1000).

[0563] Additionally, in the fully connected layer FC8 Figure 11 The operation of the shown computing device CDV can be referenced from the description of the operation of the computing device CDV in the fully connected layer FC6.

[0564] As described above, by using the computing device CDV, it is possible to perform Figure 16 The AlexNet operation is shown. Furthermore, by performing digital operations using the computation circuit DGP of the CDV (Convolution Processing Device) as the computation unit, the update frequency of the filter values ​​can be reduced compared to existing structures, thus reducing the power consumption required for updating the filter values.

[0565] Furthermore, by using the arithmetic circuit ANP of the arithmetic device CDV as a fully connected layer for processing, analog-mode operations can be performed, such as large-scale operations like the product summation of fully connected layers FC6 to FC8. Specifically, a subthreshold current flows through each transistor F2 of the multiplication units IM[1,1] to IM[m,n] included in the cell array CA, thus reducing the power consumption of a single multiplication unit IM. Therefore, the number of multiplication units IM included in the cell array CA can be increased, allowing the product summation of the fully connected layer to be performed within a single cell array CA.

[0566] Note that in this example, the computing device CDV is described as performing... Figure 16 The diagram illustrates the operation of AlexNet, but the computational model performed by the CDV computing device is not limited to AlexNet. For example, in the input layer INLY, a 224×224 pixel image P... in The image is input to the CDV processing unit, but the image size can also be arbitrarily determined. Furthermore, the number of convolution kernels used for convolutional layers CNV1 to CNV5 and the filter values ​​they include can also be arbitrarily determined. Additionally, the CDV processing unit can also... Figure 16 The operational model of AlexNet is used in convolutional neural networks.

[0567] Note that one aspect of the present invention is not limited to the computing device CDV described in this embodiment. The structure of the computing device CDV described in this embodiment may also be modified depending on the circumstances.

[0568] For example, Figure 11 The arithmetic circuit DGP of the arithmetic device CDV shown can also be changed to Figure 21A The structure shown. Figure 21A The operational circuit DGP shown is Figure 11 The difference between the DGP and the other circuits is that the DGP does not have a switching unit D10; and it includes multiple arithmetic units D20 and multiple processing units D30. Specifically, Figure 21A The arithmetic circuit DGP shown includes arithmetic units D20[1] to D20[5], processing unit D30[1], processing unit D30[2] and processing unit D30[5].

[0569] The arithmetic units D20[1] to D20[5] can be referred to in the description of the arithmetic unit D20 above. In addition, the processing units D30[1], D30[2] and D30[5] can be referred to in the description of the processing unit D30 above.

[0570] Figure 21A The illustrated operational circuit DGP includes components corresponding to... Figure 16 The circuitry for each of the input layer INLY, convolutional layers CNV1 through CNV5, pooling layers PL1, PL2, and PL5 in the convolutional neural network is shown. For example, Figure 16 The input layer INLY shown corresponds to the routing ILA. Additionally, for example... Figure 16 The convolutional layers CNV1 to CNV5 shown correspond to the computation units D20[1] to D20[5], respectively. Additionally, for example... Figure 16 The pooling layers PL1, PL2, and PL5 shown correspond to processing unit D30[1], processing unit D30[2], and processing unit D30[5], respectively. That is, in Figure 21A In the DGP arithmetic circuit, between the wiring ILA and the storage circuit ME11, there are sequentially arranged arithmetic unit D20[1], processing unit D30[1], arithmetic unit D20[2], processing unit D30[2], arithmetic unit D20[3], arithmetic unit D20[4], arithmetic unit D20[5] and processing unit D30[5].

[0571] exist Figure 11 In the arithmetic circuit DGP of the arithmetic device CDV shown, during execution Figure 16 During the operation of the convolutional layer CNV1 to the pooling layer PL5 in the convolutional neural network, this operation is performed by repeatedly operating an operation unit D20 and a processing unit D30. On the other hand, in Figure 21A In the DGP arithmetic circuit shown, during execution Figure 16 When the convolutional layer CNV1 to the pooling layer PL5 of the convolutional neural network are operated, the operation is performed by sequentially operating the operation unit D20 (convolutional layer CNV1) to the processing unit D30 (pooling layer PL5).

[0572] Note that, although in Figure 21A Although not shown in the figure, in order to temporarily store the output data of each layer after the operation of each layer, the operation circuit DGP and the storage circuit MEM can also store the output data in the storage circuit section of the storage circuit MEM.

[0573] In addition, for example Figure 11 The arithmetic circuit ANP of the arithmetic device CDV shown can also be changed to Figure 21B The structure shown. Figure 21B The operational circuit ANP shown is Figure 11 The difference between the operational circuit ANP and the other circuit lies in the presence of multiple cell arrays (CA), multiple circuits (WCS), and multiple circuits (ITS). Specifically, Figure 21BThe operational circuit ANP shown includes cell arrays CA[6] to CA[8], circuits WCS[6] to WCS[8], circuit XCS, and circuits ITS[6] to ITS[8].

[0574] Figure 21B The cell arrays CA[6] to CA[8] can be referenced. Figure 11 Description of the cell array CA shown. Figure 21B The circuits WCS[6] to WCS[8] can be referenced. Figure 11 The circuit diagram WCS is shown below. Additionally, Figure 21B The circuit XCS can be referenced. Figure 11 Explanation of the circuit XCS shown.

[0575] In addition, circuit ITS[6] and circuit ITS[7] can be used Figure 8C The circuit ITS shown. Additionally, the circuit ITS[8] can be used... Figure 8A or Figure 8B The circuit ITS shown is shown.

[0576] The storage circuit section ME13 is connected to the circuit WCS[6] via wiring IWL[6]. Furthermore, the storage circuit section ME13 is connected to the circuit WCS[7] via wiring IWL[7]. Furthermore, the storage circuit section ME13 is connected to the circuit WCS[8] via wiring IWL[8].

[0577] Routing IWL[6] to Routing IWL[8] can each be a group of cabling that includes multiple cablings. Specifically, for example, Routing IWL[6] can be a combination Figure 11 The wiring group formed by wiring IWL_1 to wiring IWL_n is shown. Similarly, wiring IWL[7] can also be a combination. Figure 11 The wiring group formed by wiring IWL_1 to wiring IWL_n shown, wiring IWL[8] can also be a combination Figure 11 The wiring group shown is formed by wiring IWL_1 to wiring IWL_n.

[0578] The storage circuit section ME11 is connected to the circuit XCS via a wiring IXL. Note that the wiring IXL here can be a group of wirings comprising multiple wirings. Specifically, for example, the wiring IXL can be a combination of... Figure 11 The wiring group shown consists of wiring IXL_1 to wiring IXL_m.

[0579] Circuit WCS[6] is connected to circuit ITS[6] via wiring WCL[6]. Additionally, circuit WCS[7] is connected to circuit ITS[7] via wiring WCL[7]. Furthermore, circuit WCS[8] is connected to circuit ITS[8] via wiring WCL[8].

[0580] Each of the wiring WCLs [6] to [8] can be a wiring group comprising multiple wirings. Specifically, for example, the wiring WCL [6] can be a combination Figure 11 The wiring group shown is formed by wiring WCL_1 to wiring WCL_n. Similarly, wiring WCL[7] can also be a combination. Figure 11 The wiring group shown is composed of wiring WCL_1 to wiring WCL_n. Wiring WCL[8] can also be a combination. Figure 11 The wiring group formed by wiring WCL_1 to wiring WCL_n is shown. In addition, wiring WCL[6] extends in the column direction of cell array CA[6], wiring WCL[7] extends in the column direction of cell array CA[7], and wiring WCL[8] extends in the column direction of cell array CA[8].

[0581] The circuit XCS is connected to the wiring XCL[6]. The wiring XCL[6] can be a group of wirings that includes multiple wirings. Specifically, for example, the wiring XCL[6] can be a combination Figure 11 The wiring group shown is formed by wiring XCL_1 to wiring XCL_m. In addition, wiring XCL[6] extends in the row direction of cell array CA[6].

[0582] The circuit ITS[6] is connected to the wiring XCL[7]. The wiring XCL[7] can be a group of wirings that includes multiple wirings. Specifically, for example, the wiring XCL[7] can be a combination Figure 11 The wiring group shown is formed by wiring XCL_1 to wiring XCL_m. In addition, wiring XCL[7] extends in the row direction of cell array CA[7].

[0583] The circuit ITS[7] is connected to the wiring XCL[8]. The wiring XCL[8] can be a group of wirings that includes multiple wirings. Specifically, for example, the wiring XCL[8] can be a combination Figure 11 The wiring group formed by wiring XCL_1 to wiring XCL_m is shown. In addition, wiring XCL[8] extends in the row direction of cell array CA[8].

[0584] The circuit ITS[8] is connected to the wiring OL[8]. Additionally, the wiring OL[8] can be a group of wirings comprising multiple wirings. Specifically, for example, the wiring OL[8] can be a combination... Figure 11 The wiring group shown is formed by wiring OL_1 to wiring OL_n.

[0585] Figure 21B The operational circuit ANP shown includes corresponding to Figure 16 The circuitry for each of the fully connected layers FC6 to FC8 in the convolutional neural network shown is illustrated. For example, Figure 16 The fully connected layer FC6 shown corresponds to the cell array CA[6] and the circuit ITS[6]. Furthermore, for example, Figure 16 The fully connected layer FC7 shown corresponds to the cell array CA[7] and the circuit ITS[7]. Figure 16 The fully connected layer FC8 shown corresponds to the cell array CA[8] and the circuit ITS[8].

[0586] Figure 11 The arithmetic circuit ANP of the arithmetic device CDV shown is executing... Figure 16 During the operation of fully connected layers FC6 to FC8 in a convolutional neural network, this operation is performed by repeatedly operating a cell array CA, a circuit WCS, a circuit XCS, and a circuit ITS. On the other hand, in Figure 21B The operational circuit ANP shown executes... Figure 16 When the fully connected layers FC6 to FC8 of the convolutional neural network are operated, the operation is performed by sequentially activating the cell arrays CA and circuits ITS corresponding to each fully connected layer.

[0587] Figure 21B The operational circuit ANP shown is Figure 11 The difference between the CDV's arithmetic circuit ANP and the CDV's arithmetic circuit lies in the fact that no analog-to-digital conversion is performed in the ITS[6] and ITS[7] circuits. That is to say, Figure 21B The arithmetic circuit ANP shown has a structure in which no analog-to-digital conversion circuit is provided in circuit ITS[6] and circuit ITS[7]. By not providing an analog-to-digital conversion circuit in circuit ITS[6] and circuit ITS[7], the circuit area and power consumption of the arithmetic device CDV can be reduced.

[0588] Note that, although in Figure 21B Although not illustrated, in order to temporarily store the output data of each fully connected layer after the operation of each layer, the operation circuit ANP and the storage circuit MEM can also store the output data in the storage circuit section of the storage circuit MEM.

[0589] Furthermore, for example, in this work, max pooling is described as the pooling process, but average pooling, Lp pooling, etc., may also be used depending on the situation.

[0590] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. In addition, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with configurations, structures, methods, etc. shown in other embodiments, etc.

[0591] (Implementation Method 5)

[0592] In this embodiment, an example of the structure of the computing device CDV described in the above embodiment will be explained.

[0593] Figure 22 This is a schematic perspective view of the computing device CDV described in Embodiment 4. Figure 22 The illustrated computing device CDV includes, for example, a circuit layer PHRL, a memory layer OMEL, and an operational layer OMAL. Furthermore, the circuit layer PHRL is located below the memory layer OMEL, and the operational layer OMAL is located above the memory layer OMEL. That is to say, Figure 22 The CDV has a structure in which the circuit layer PHRL, the storage layer OMEL, and the computing layer OMAL are stacked sequentially from bottom to top.

[0594] Figure 23 It is shown Figure 22 The block diagrams show examples of the structure of the circuit layer PHRL, the storage layer OMEL, and the operation layer OMAL.

[0595] exist Figure 23 In the circuit layer PHRL, for example, it includes Figure 11 The switching unit D10, the arithmetic unit D20, and the processing unit D30 are shown. Furthermore, the storage layer OMEL includes, for example, […]. Figure 11 The storage circuit sections ME11, ME12, and ME13 are shown. Furthermore, the operational layer OMAL includes, for example, a cell array CA, a circuit WCS, a circuit XCS, and a circuit ITS.

[0596] Note that, as Figure 24 As shown, Figure 11 The circuits WCS, XCS, and ITS shown can also be included in the circuit layer PHRL. Figure 24 The abstract shows the cell array CA, circuit WCS, circuit XCS, circuit ITS, storage circuit section ME11, and storage circuit section ME13. Alternatively, selected from... Figure 11 One or more of the circuits WCS, XCS, and ITS shown may also be included in the storage layer OMEL.

[0597] The circuit layer PHRL can be constructed, for example, by placing circuit elements such as transistors and capacitors on a substrate. Furthermore, a semiconductor substrate (e.g., a single-crystal silicon substrate or a single-crystal germanium substrate) can be used as the substrate. Other substrates besides semiconductor substrates include, for example, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates containing stainless steel foil, tungsten substrates, substrates containing tungsten foil, flexible substrates, laminated films, and paper or substrate films containing fibrous materials. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Additionally, examples of flexible substrates, laminated films, or substrate films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, synthetic resins such as acrylic resins can be used as other examples. Alternatively, polypropylene, polyester, ethylene fluoride, or polyvinyl chloride can be used as other examples. Other examples include polyamides, polyimides, aromatic polyamides, epoxy resins, inorganic vapor-deposited films, or paper. Furthermore, when the manufacturing process of the CDV (Computing Device for Display) includes heat treatment, a material with high heat resistance is preferably selected as the substrate.

[0598] Note that in this embodiment, the description is based on the premise that the substrate included in the circuit layer PHRL is a semiconductor substrate containing silicon.

[0599] By using a semiconductor substrate, such as silicon, as the substrate included in the circuit layer PHRL, transistors included in each of the switching section D10, the arithmetic section D20, and the processing section D30 can be formed in the semiconductor substrate. In this case, the transistor is a Si transistor. Because Si transistors have high field-effect mobility, they can carry large on-state currents. This improves the driving speed of the aforementioned circuits and expands the signal range, etc. Furthermore, in the arithmetic device CDV... Figure 24 In the case of the structural example shown, since the transistors included in each of the circuits WCS, XCS and ITS can also be formed on a semiconductor substrate made of silicon, each of the circuits WCS, XCS and ITS can improve the driving speed and expand the signal range, etc.

[0600] Alternatively, a stacked structure of the circuit layer PHRL and the memory layer OMEL can be manufactured by forming the memory layer OMEL directly on top of the circuit layer PHRL. Alternatively, the stacked structure can be manufactured by having the memory layer OMEL have circuit elements such as transistors and capacitors disposed on a substrate, and then mounting that substrate on top of the circuit layer PHRL.

[0601] When the memory layer OMEL is formed directly on top of the circuit layer PHRL, the memory layer OMEL preferably includes an OS transistor. Because OS transistors can be formed not only on a semiconductor substrate, but also on an insulating substrate, a conductive substrate, a conductive film, an insulating film, and a semiconductor film, they are easy to place on a semiconductor substrate (on the circuit layer PHRL) where Si transistors are formed.

[0602] Furthermore, when circuit elements such as transistors and capacitors are formed on a substrate as the storage layer OMEL and the substrate is mounted on the circuit layer PHRL, flip-chip bonding or wire bonding methods can be used. Alternatively, a first bonding layer can be provided on one side of the circuit layer PHRL, and a second bonding layer can be provided on the substrate of the storage layer OMEL. The first bonding layer and the second bonding layer can be bonded together using one or both of surface activation bonding and hydrophilic bonding methods, thereby mounting the storage layer OMEL on the circuit layer PHRL. In particular, the bonding of copper (Cu) in the conductors included in the first and second bonding layers and the copper (Cu) bonding to each other is called Cu-Cu bonding.

[0603] <Example 1 of cross-sectional structure>

[0604] Next, the explanation Figure 22 and Figure 23 The diagram shows a specific structural example of the computing device CDV. Figure 25 yes Figure 22 and Figure 23 A cross-sectional schematic diagram of an example of a computing device CDV is shown.

[0605] Figure 25 A cross-sectional schematic diagram of the circuit layer PHRL, the memory layer OMEL, and the operational layer OMAL is shown. Additionally, in Figure 25 In the CDV (Computational Device for Computers), the OMEL (Memory Layer) is directly formed on the PHRL (Circuit Layer), and the OMAL (Computational Layer) is directly formed on the OMEL (Memory Layer).

[0606] Figure 25 The diagram illustrates a transistor 400 included in the circuit layer PHRL. The transistor 400 is disposed on a substrate 311 and includes: a conductive layer 316 serving as a gate; insulating layers 315 and 317 serving as gate insulating films; a semiconductor region 313 comprising a portion of the substrate 311; and low-resistance regions 314a and 314b comprising a portion of the substrate and serving as source or drain regions. The transistor 400 can be a p-channel transistor or an n-channel transistor. The substrate 311 can, for example, be a single-crystal silicon substrate.

[0607] Here, in Figure 25In the transistor 400 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductive layer 316 is provided such that it covers the sides and top surface of the semiconductor region 313 with an insulating layer 315 in between. The conductive layer 316 can also be made of a material with an adjustable work function. Because it utilizes the convex portion of the semiconductor substrate, this transistor 400 is also referred to as a finned transistor. Furthermore, an insulating layer for forming the convex portion can be included in such a way that it contacts the top of the convex portion. Although the case shown here is of forming the convex portion by processing a portion of the semiconductor substrate, a semiconductor film with a convex shape can also be formed by processing an SOI substrate.

[0608] Notice, Figure 25 The structure of transistor 400 shown is just an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0609] A wiring layer, including interlayer membranes, wiring, and connectors, can also be provided between the various structures. Furthermore, multiple wiring layers can be configured according to the design. Additionally, in this specification, wiring and connectors connecting to the wiring can also be considered as components. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a connector.

[0610] For example, insulating layers 320, 324, and 326 are sequentially stacked as interlayer films on transistor 400. Furthermore, conductive layers 328 and the like are embedded in insulating layer 320. Furthermore, conductive layers 330 and the like are embedded in insulating layers 324 and 326. Furthermore, conductive layers 328 and 330 are used as contact plugs or wiring.

[0611] Furthermore, the insulating layer used as an interlayer film can also be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of the insulating layer 320, its top surface can also be planarized by a planarization process using chemical mechanical polishing (CMP).

[0612] Wiring layers can also be disposed on the insulating layer 326 and the conductive layer 330. For example, in Figure 25 In this structure, insulating layers 350, 357, 352, and 354 are sequentially stacked on insulating layer 326 and conductive layer 330. Conductive layer 356 is formed in insulating layers 350, 357, and 352. Conductive layer 356 is used as a contact plug or wiring.

[0613] An insulating layer 354 is provided on the insulating layer 352 and the conductive layer 356. The insulating layer 354 may also contain contact plugs or wiring for connecting to the circuitry above (e.g., circuitry in the storage layer OMEL or circuitry in the computing layer OMAL).

[0614] in addition, Figure 25 This shows the memory cells MC included in the storage layer OMEL. Specifically, Figure 25 The diagram shows transistors M1, M2, and M3, and capacitor C1 included in the memory cell MC. Note that the memory cell MC can be any of the components described in the above embodiment. Figure 14C The storage unit MC shown is shown.

[0615] exist Figure 25 In the storage layer OMEL of the CDV computing device, transistors M2 and M3 are formed on the insulating layer STJ1. Additionally, transistor M1 and capacitor C1 are formed on the insulating layer STJ2. Furthermore, the insulating layer STJ2 is located above the insulating layer STJ1. Therefore, transistor M1 and capacitor C1 are located above transistors M2 and M3.

[0616] exist Figure 25 In the memory layer OMEL, transistors M2 and M3 share a fin semiconductor layer SC1. Specifically, the gate insulating film and gate electrode of transistor M2 are formed to overlap with one of the two regions of the fin semiconductor layer SC1, and the gate insulating film and gate electrode of transistor M3 are formed to overlap with the other of the two regions of the fin semiconductor layer SC1.

[0617] Furthermore, one of the source and drain electrodes of transistor M2 is connected to a conductive layer used as a wiring CVLB. Similarly, one of the source and drain electrodes of transistor M5 is connected to a conductive layer used as a wiring BL. As an example, the wiring CVLB and wiring BL extend in the channel width direction of transistor M2 or transistor M3. Additionally, the conductive layer used as the wiring CVLB is formed overlapping the fin semiconductor layer SC1, and the conductive layer used as the wiring BL is disposed overlapping the fin semiconductor layer SC1.

[0618] In addition, a conductive layer, serving as the gate electrode of transistor M3, extends in the channel width direction. Furthermore, this conductive layer is also used as a wiring RWL.

[0619] An insulating layer serving as an interlayer film is formed between transistors M2 and M3 and transistor M1. Furthermore, openings are provided in this insulating layer in the regions overlapping with the gate electrode of transistor M2 and with the wiring BL, and these openings are respectively filled with conductive layers. One conductive layer is connected to one of the source and drain electrodes of transistor M1, and the other conductive layer is connected to the other of the source and drain electrodes of transistor M1.

[0620] Additionally, as described above, transistor M1 is located above transistors M2 and M3. Furthermore, transistor M1 includes a portion of the finned semiconductor layer SC2. Additionally, a portion of the conductive layer serving as one of the source and drain electrodes of transistor M1 has a region of an insulating layer forming the dielectric of capacitor element C1, and a conductive layer serving as the second terminal of capacitor element C1 is formed in this insulating layer region. Furthermore, this conductive layer also serves as the wiring CVLA.

[0621] Additionally, as described in Embodiment 4, the potentials supplied by the wiring CVLA and the wiring CVLB can also be equal. When the potentials supplied by the wiring CVLA and the wiring CVLB are equal, the wiring CVLA and the wiring CVLB can also be connected to each other (not shown).

[0622] The gate insulating film and gate electrode of transistor M1 are formed in a manner that overlaps with a portion of the fin-shaped semiconductor layer SC2 of transistor M1. In particular, the conductive layer serving as the gate electrode of transistor M1 extends in the channel width direction. Furthermore, this conductive layer also serves as the wiring WWL.

[0623] Note that, although in Figure 25 Although not illustrated, in transistor M1, the conductive layer used as the back gate can also be disposed below the insulating layer STJ2. Similarly, in transistors M2 and M3, the conductive layer used as the back gate can also be disposed below the insulating layer STJ1. By providing a back gate in each transistor and changing the potential of the back gate, the threshold voltage of the transistor can be changed.

[0624] For example, by using a transistor including a back gate as transistor M1, the influence of external electric fields can be mitigated, and the transistor can be stably kept in the off state. Therefore, data written to the first terminal of capacitor element C1 can be stably maintained. By setting the back gate, the operation of the memory cell MC is stabilized, and the reliability of the memory layer OMEL including the memory cell MC can be improved.

[0625] As the semiconductor layer forming the channels of transistors M1, M2, and M3, one or more of the following can be used: single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, and amorphous semiconductors. As the semiconductor material, for example, as described in Embodiment 1, silicon or germanium can be used. Furthermore, as other examples, compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, or nitride semiconductors can also be used.

[0626] Furthermore, transistors M1, M2, and M3 are preferably oxide semiconductor transistors (OS transistors) in which one of the metal oxides is used in the semiconductor layer forming the channel. Since the bandgap of oxide semiconductors is 2 eV or more, the off-state current is significantly small. Therefore, the power consumption of the memory cell MC can be reduced. Therefore, the power consumption of the computing device CDV including the memory cell MC can be reduced.

[0627] Furthermore, a memory cell including an OS transistor can be referred to as "OS memory". Additionally, a computing device CDV including this memory cell can also be referred to as "OS memory". In this case, the computing device CDV can be referred to as a storage device.

[0628] Furthermore, OS transistors operate stably even at high temperatures with minimal characteristic variation. For example, their off-state current barely increases even at high temperatures. Specifically, their off-state current barely increases even at temperatures above room temperature (e.g., 30°C) and below 200°C. Moreover, their on-state current does not easily decrease even at high temperatures. Therefore, OS memories operate stably and reliably even at high temperatures.

[0629] in addition, Figure 25 This shows the multiplication unit IM included in the OMAL computation layer. Specifically, Figure 25 The diagram shows transistors F1a, F1b, F2, and F5, as well as capacitors C4 and C5, included in the multiplication unit IM. Note that the multiplication unit IM can be the same as those described in the above embodiments. Figure 1A The multiplication unit IM is shown.

[0630] exist Figure 25 In the operational layer OMAL of the CDV (Computational Device for Vehicles), transistors F2 and F5 are formed on the insulating layer STJ3. Additionally, transistors F1a and F1b, capacitors C4 and C5 are formed on the insulating layer STJ4. Furthermore, the insulating layer STJ4 is located above the insulating layer STJ3. Therefore, transistors F1a and F1b, and capacitors C4 and C5 are located above transistors F2 and F5.

[0631] exist Figure 25 In the operational layer OMAL, transistors F2 and F5 share a fin semiconductor layer SC3. Specifically, the gate insulating film and gate electrode of transistor F2 are formed to overlap with one of the two regions of the fin semiconductor layer SC3, and the gate insulating film and gate electrode of transistor F5 are formed to overlap with the other of the two regions of the fin semiconductor layer SC3.

[0632] Furthermore, one of the source and drain electrodes of transistor F2 is connected to a conductive layer used as wiring VE0. Similarly, one of the source and drain electrodes of transistor F5 is connected to a conductive layer used as wiring WCL. As an example, wiring VE0 and wiring WCL extend in the channel width direction of transistor F2 or transistor F5. Additionally, the conductive layer used as wiring VE0 is formed in a manner overlapping with the fin semiconductor layer SC3, and the conductive layer used as wiring WCL is disposed in a manner overlapping with the fin semiconductor layer SC3.

[0633] Furthermore, the conductive layer serving as the gate electrode of transistor F2 extends in the channel width direction. Additionally, in Figure 25 In this context, the conductive layer is represented as wiring ME.

[0634] Furthermore, the conductive layer serving as the gate electrode of transistor F5 extends in the channel width direction. This conductive layer is also used for wiring VE1.

[0635] As an example of transistors F2 and F5, Figure 26A and Figure 26B A three-dimensional schematic diagram of them is shown. Figure 26B From Figure 26A A three-dimensional schematic diagram of wiring VE0, wiring WCL, a portion of the insulating layer, and a portion of the conductive layer is omitted.

[0636] Figure 26A and Figure 26B Two fin-shaped semiconductor layers SC3 are shown, each with a region having a rectangular opening. Therefore, it can be said that the semiconductor layer SC3 has a circumferential and fin-like structure. Furthermore, the opening can be rectangular or a closed curve.

[0637] like Figure 26A and Figure 26BAs shown, wiring ME and wiring VE1 are formed in a manner that overlaps with a portion of the sidewalls of the two fin-shaped semiconductor layers SC3. Thus, transistors F2 and F5 can be formed by using wiring ME and wiring VE1, separated by a gate insulating film, around the semiconductor layer SC3 that forms the channel. This prevents electric fields generated outside transistor F2 or transistor F5 from affecting the semiconductor forming the channel. In other words, an electrostatic shielding function can be added to transistor F2 or transistor F5. This prevents changes in the electrical characteristics of the transistor due to the influence of external electric fields such as static electricity.

[0638] In addition, such as Figure 26A As shown, wiring VE0 and wiring WCL are formed in a manner that overlaps with a portion of the side surface of the two fin-shaped semiconductor layers SC3. Furthermore, a conductive layer is formed between wiring VE0 or wiring WCL and the semiconductor layer SC3 (in... Figure 26A and Figure 26B (not shown in the figure), so there is a current flow between wiring VE0 or wiring WCL and semiconductor layer SC3.

[0639] As an example of transistors F1a and F1b, Figure 27A and Figure 27B A three-dimensional schematic diagram of them is shown. Figure 27B From Figure 27A A three-dimensional schematic diagram of two wiring WSLs and part of the insulation layer is omitted.

[0640] Similar to semiconductor layer SC3, Figure 27A and Figure 27B Two fin-shaped semiconductor layers SC4 are shown, each with a region having a rectangular opening. Therefore, it can be said that the semiconductor layer SC4 has a circumferential and fin-like structure. Furthermore, the opening can be rectangular or a closed curve.

[0641] like Figure 26A and Figure 26B As shown, two wiring lines (WSL) are formed overlapping a portion of the sidewalls of two finned semiconductors (SC4). Thus, transistors F1a and F1b can be formed by using the two wiring lines (WSL) to surround the semiconductor layer (SC4) forming the channel, separated by a gate insulating film. This prevents electric fields generated outside transistors F1a or F1b from affecting the semiconductor forming the channel. In other words, an electrostatic shielding function can be added to transistors F1a or F1b. This prevents changes in the electrical characteristics of the transistors due to external electric fields such as static electricity.

[0642] In addition, such as Figure 27A and Figure 27BAs shown, the wiring XCL is formed in a manner that overlaps with a portion of the side surface of the two fin-shaped semiconductor layers SC4. Furthermore, an insulating layer serving as a dielectric is formed between the wiring XCL and the semiconductor layer SC4. Figure 27A and Figure 27B (Not shown in the diagram), so the capacitor element C4 is formed in the area where the wiring XCL overlaps with the semiconductor layer SC4. Additionally, the first terminal of the capacitor element C4 can be a conductive layer formed on the semiconductor layer SC4.

[0643] An insulating layer serving as an interlayer film is formed between transistors F2 and F5 and transistors F1a and F1b. Furthermore, openings are provided in this insulating layer in regions overlapping with wiring ME and WCL, and these openings are respectively filled with a conductive layer. One conductive layer is connected to one of the source and drain electrodes of transistor Fa1, and the other conductive layer is connected to one of the source and drain electrodes of transistor F1b.

[0644] Additionally, as described above, transistor F1 is located above transistors F2 and F5. Furthermore, transistor F1 includes a portion of the finned semiconductor layer SC4. Additionally, a portion of the conductive layer serving as one of the source and drain electrodes of transistor F1 has a region of an insulating layer forming the dielectric of capacitor element C5, and a conductive layer serving as the second terminal of capacitor element C5 is formed in this insulating layer region. This conductive layer also serves as wiring XCL. Furthermore, both the conductive layer serving as the second terminal of capacitor element C5 and the conductive layer serving as the second terminal of capacitor element C4 can be wiring XCL; for example, each conductive layer can be configured as the same wiring.

[0645] <<Examples of Transistor Structures>>

[0646] Next, the explanation is as follows: Figure 25 The cross-sectional schematic diagram shows the structures of transistors F1a, F1b, F2, F5, M1, M2, and M3 used in the diagram.

[0647] Similar to the transistors mentioned above, Figures 28A to 28D These are a planar schematic and a cross-sectional schematic of a 500mf transistor, showing the structure of a transistor comprising two fin-shaped and circumferential semiconductor layers. Note that, unlike the transistors described above, Figures 28A to 28D The 500mf transistor has a structure that does not share the same semiconductor layer with more than two transistors.

[0648] Figure 28A They can be used separately as Figure 25A planar schematic diagram of transistors F1a, F1b, F2, F5, M1, M2, and M3 of the CDV computing device. Figures 28B to 28D These are schematic cross-sectional views of a 500mF transistor. In particular, Figure 28B It is along Figure 28A The cross-sectional diagram of the section marked with dotted lines A1-A2 is also a cross-sectional diagram of the 500mF transistor along the channel width direction. Additionally, Figure 28C It is along Figure 28A The cross-sectional diagram of the section marked with dotted lines A3-A4 is also a cross-sectional diagram of the 500mF transistor along the channel width direction. Additionally, Figure 28D It is along Figure 28A The cross-sectional view of the section marked with dotted lines A5-A6 is also a cross-sectional view along the channel length of the 500mF transistor. Here, dotted lines A5-A6 are orthogonal to dotted lines A1-A2 and A3-A4, respectively, and dotted lines A1-A2 and A3-A4 are parallel to each other. Note that in Figure 28A In the plan view, for clarity, some constituent elements are omitted, and the view is shown through a portion of the constituent elements. Additionally, Figure 29A and Figure 29B Show Figures 28A to 28D A 3D schematic diagram of a 500mF transistor. Note that... Figure 29B From Figure 29A A three-dimensional schematic diagram of conductive layer 540a, conductive layer 540b, a portion of the insulating layer, and a portion of the conductive layer is omitted. Additionally, Figure 30A Show Figure 28D A magnified view of the conductive layer near 560. Additionally, Figure 30B Show Figure 28B A magnified view of the area near semiconductor layer 530. Additionally, Figure 30C Show Figure 28C A magnified view of the area near semiconductor layer 530.

[0649] Transistor 500mf includes an insulating layer 516 on insulating layer 514, an insulating layer 521 on insulating layer 516, an insulating layer 522 on insulating layer 521, a semiconductor layer 530 on insulating layer 522, conductive layers 542a and 542b on semiconductor layer 530 and insulating layer 522, an insulating layer 550 on semiconductor layer 530, and conductive layers 560 (conductive layers 560a and 560b) on insulating layer 550. Note that conductive layers 542a and 542b are sometimes collectively referred to as conductive layer 542 below.

[0650] An insulating layer 575 is disposed on the conductive layer 542, and an insulating layer 580 is disposed on the insulating layer 575. The insulating layer 550 and the conductive layer 560 are disposed within an opening disposed in the insulating layer 580 and the insulating layer 575. This opening reaches the semiconductor layer 530, and the insulating layer 550 contacts the semiconductor layer 530 within this opening. Additionally, an insulating layer 582 is disposed on the insulating layer 580 and the conductive layer 560. Furthermore, an insulating layer 583 is disposed on the insulating layer 582.

[0651] An insulating layer 541a is provided in contact with the inner wall of an opening in an insulating layer 580, etc., and a conductive layer 540a is provided in contact with the side surface of the insulating layer 541a. The bottom surface of the conductive layer 540a is in contact with the top surface of the conductive layer 542a. An insulating layer 541b is provided in contact with the inner wall of an opening in an insulating layer 580, etc., and a conductive layer 540b is provided in contact with the side surface of the insulating layer 541b. The bottom surface of the conductive layer 540b is in contact with the top surface of the conductive layer 542b. Hereinafter, conductive layers 540a and 540b are sometimes collectively referred to as conductive layer 540. In addition, insulating layers 541a and 541b are sometimes collectively referred to as insulating layer 541.

[0652] The insulating layers 541a and 541b are preferably made of insulating films that inhibit oxygen permeation to prevent a decrease in conductivity caused by oxidation of the conductive layers 542a and 542b. For example, silicon nitride is preferably deposited using the PEALD method.

[0653] Insulating layer 516, for example, is used as a planarization film to flatten steps caused by plugs, etc., similar to insulating layer 320. Therefore, like insulating layer 320, insulating layer 516 can use a material that is used as a planarization film. Furthermore, by using a material with a low relative permittivity in insulating layer 516, parasitic capacitance between wirings can be reduced. Thus, insulating layer 516 can, for example, use a material that can be used for insulating layer IS1, which will be described later.

[0654] Similar to insulating layers 324 and 350, insulating layers 521 and 522 preferably use insulating layers that are barrier to one or more of hydrogen, oxygen and water.

[0655] Semiconductor layer 530 has a region serving as the channel formation region for transistor 500mf. Additionally, conductive layer 560 has a region serving as the first gate electrode (upper gate electrode) for transistor 500mf. Insulating layer 550 has a region serving as the first gate insulating film for transistor 500mf.

[0656] In particular, semiconductor layer 530 can be a metal oxide used as an oxide semiconductor. In this case, transistor 500mf is an OS transistor. Semiconductor layer 530 can be used as one or more of the aforementioned semiconductor layers SC1 to SC4.

[0657] Furthermore, the semiconductor layer 530 may use an AG CAAC (Axial Growth CAAC) oxide semiconductor. AGCAAC refers to an oxide semiconductor with a CAAC structure, formed by solid-phase growth of a metal oxide contained in the first layer using the second layer as a nucleus or seed in an oxide semiconductor layer comprising a first layer and a second layer with a higher crystallinity than the first layer.

[0658] For example, atomic layer deposition (ALD) or chemical vapor deposition (CVD) are preferred methods for depositing the first layer. Wet deposition methods can also be used. Furthermore, molecular beam epitaxy (MBE) can be used, a deposition method for growing thin films that reflect the crystal structure of the substrate. In addition, examples of CVD methods include plasma-enhanced CVD (PECVD), thermal CVD, photo-CVD, and metal-organic CVD (MOCVD). Moreover, compared to sputtering methods, these deposition methods can reduce damage to the surface being formed.

[0659] Next, sputtering or pulsed laser deposition (PLD) is preferably used as the deposition method for the second layer. In particular, by forming the second layer after the first layer, the formation of a mixed layer at the interface between the first and second layers can be suppressed. Furthermore, impurities contained in the formed surface can be prevented from entering the second layer. This further improves the crystallinity of the second layer.

[0660] Furthermore, methods for solid-state growth of the metal oxide contained in the first layer using the second layer as a core or species include, for example, heat treatment, plasma treatment, microwave treatment (typically 2.45 GHz), microwave plasma treatment, and light (e.g., ultraviolet light) irradiation. Note that multiple of these treatments can be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment can be performed simultaneously. Alternatively, microwave plasma treatment can be performed after heat treatment.

[0661] In this specification and the like, microwaves refer to electromagnetic waves with a frequency of 300 MHz or higher and 300 GHz or lower. Furthermore, microwave plasma treatment refers, for example, to a process using a device that includes a power source for generating high-density plasma with microwaves. Additionally, microwave plasma treatment can also be referred to as microwave-excited high-density plasma treatment.

[0662] Furthermore, it is more preferable to perform multiple treatments to improve the crystallinity of the oxide semiconductor layer during deposition. For example, when forming the oxide semiconductor layer using the ALD method, it is preferable to perform microwave plasma treatment each time one atomic layer is formed. Alternatively, by performing treatments to improve crystallinity each time an oxide semiconductor layer with a predetermined thickness is formed, productivity can be improved, and this is therefore preferred. Specifically, it is preferable to form a first oxide semiconductor layer of 1 nm or more and 10 nm or less and perform a first microwave plasma treatment, and then form a second oxide semiconductor layer of 1 nm or more and 10 nm or less and perform a second microwave plasma treatment. Note that there are no particular limitations on the deposition methods of the first and second oxide semiconductor layers; either the ALD method or sputtering method can be used, respectively. In particular, by using the ALD method to deposit the first oxide semiconductor layer, it is possible to prevent elements constituting the layer of the formed surface from mixing into the first and second oxide semiconductor layers (also known as mixing), which is therefore preferred. In particular, it is suitable for cases where the element in the layer constituting the formed surface blocks the crystallization of the oxide semiconductor (e.g., cases containing silicon, carbon, etc.). Furthermore, the first oxide semiconductor layer and the second oxide semiconductor layer may have different compositions. Additionally, a stacked structure of the first oxide semiconductor layer and the second oxide semiconductor layer is shown here, but it is not limited to this. The same treatment can also be applied when the oxide semiconductor layer has a single-layer structure or a stacked structure of three or more layers.

[0663] Furthermore, the treatment to improve the crystallinity of the oxide semiconductor layer can also be performed after the oxide semiconductor layer is deposited. Specifically, this treatment can be performed directly on the deposited oxide semiconductor layer or in the presence of other films, such as insulating films, deposited on the oxide semiconductor layer. For example, microwave plasma treatment can be performed after the oxide semiconductor layer is deposited, or an insulating film (e.g., silicon nitride film, silicon oxide film, aluminum oxide film, etc.) can be deposited after the oxide semiconductor layer is deposited, and then the oxide semiconductor layer can be subjected to heat treatment or microwave plasma treatment in the presence of the insulating film.

[0664] Note that the above-described treatment for improving the crystallinity of the oxide semiconductor layer can also serve as a treatment for removing impurities from the oxide semiconductor layer. For example, carbon, hydrogen, nitrogen, etc., can be appropriately removed from the oxide semiconductor layer. Alternatively, by performing the treatment for improving the crystallinity of the oxide semiconductor layer under an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0665] When performing a process to improve the crystallinity of the oxide semiconductor layer, it is preferable to set the substrate temperature to room temperature (e.g., 25°C) or higher, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower. Furthermore, the temperature for the heat treatment is preferably 100°C or higher and 700°C or lower, or 300°C or higher and 450°C or lower.

[0666] By further improving the crystallinity of the oxide semiconductor layer in addition to the manufacturing method described above, a transistor with high reliability can be achieved.

[0667] For example, such as Figure 23 As shown in Figure B, the semiconductor layer 530 may include a semiconductor layer 530a, a semiconductor layer 530b in contact with the semiconductor layer 530a, and a semiconductor layer 530c in contact with the semiconductor layer 530b. In addition, the side surfaces of the semiconductor layers 530 (semiconductor layers 530a to semiconductor layers 530c) are preferably perpendicular to or substantially perpendicular to the substrate surface.

[0668] As described above, in the cross-section of semiconductor layer 530 (semiconductor layers 530a to 530c) observed using TEM images, it was confirmed that the metal atoms were arranged in layers in a direction parallel or substantially parallel to the surface to which they were formed. In other words, in the cross-section of semiconductor layer 530 (semiconductor layers 530a to 530c) observed using TEM images, it was confirmed that the metal atoms were arranged in layers in a direction perpendicular or substantially perpendicular to the substrate surface. Furthermore, it can be stated that the c-axis of AGCAAC is substantially parallel to the normal direction of the side surface of semiconductor layer 530.

[0669] Thus, by using the semiconductor layer 530, which serves as the AG CAAC, in the channel formation region of the transistor 500mf, a transistor with high on-state current, high field-effect mobility, good S-value, high frequency characteristics, and high reliability can be provided. Note that the S-value refers to the subthreshold swing value, which represents the amount of gate voltage change in the subthreshold region required to change the drain current by one digit with a fixed drain voltage. The smaller the S-value, the steeper the slope of the drain current relative to the gate voltage, thereby improving the switching characteristics.

[0670] For example, a pillar serving as a sacrificial layer is provided on the insulating layer 522, and a first semiconductor film that will become semiconductor layer 530a, a second semiconductor film that will become semiconductor layer 530b, and a third semiconductor film that will become semiconductor layer 530c are sequentially deposited on the side of the pillar. The first to third semiconductor films located on the top surface of the insulating layer 522 and the top surface of the pillar are removed, and then the pillar is removed, thereby forming semiconductor layers 530a to 530c.

[0671] As described above, when the semiconductor layer 530 has a three-layer structure consisting of semiconductor layers 530a to 530c, semiconductor layers 530a, 530b, and 530c are sequentially formed around the region where the pillars are formed. That is, as... Figure 28A As shown, the semiconductor layer 530 has a structure surrounding the region where the pillars are formed when viewed from above.

[0672] The semiconductor layer 530 has a channel forming region for a transistor 500mF, as well as a source region and a drain region disposed in a manner that clamps the channel forming region. At least a portion of the channel forming region overlaps with the conductive layer 560. The source region overlaps with the conductive layer 542a, and the drain region overlaps with the conductive layer 542b. Note that the source region and the drain region can also be interchanged.

[0673] Because it has fewer oxygen vacancies or lower impurity concentrations compared to the source and drain regions, the channel formation region is a high-resistivity region with low carrier concentration. Therefore, the channel formation region can be considered an i-type (intrinsic) or essentially i-type region.

[0674] Furthermore, due to the abundance of oxygen vacancies or the high concentration of impurities such as hydrogen, nitrogen, and metal elements, the source and drain regions are low-resistance regions with high carrier concentration. In other words, the source and drain regions are n-type regions (low-resistance regions) with higher carrier concentration compared to the channel formation region.

[0675] The preferred carrier concentration in the channel formation region is 1×10⁻⁶. 18 cm -3 Below, less than 1×10 17 cm -3 Less than 1×10 16 cm -3 Less than 1×10 15 cm -3 Less than 1×10 14 cm -3 Less than 1×10 13 cm -3 Less than 1×10 12 cm -3 Less than 1×10 11 cm-3 Or less than 1×10 10 cm -3 Note that there is no specific limit to the lower limit of carrier concentration in the channel formation region; for example, it can be 1 × 10⁻⁶. -9 cm -3 .

[0676] When the aim is to reduce the carrier concentration in the semiconductor layer 530, the impurity concentration in the semiconductor layer 530 is reduced to reduce the defect state density. In this specification and the like, a state with low impurity concentration and low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic. Furthermore, oxide semiconductors (or metal oxides) with low carrier concentration are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors (or metal oxides).

[0677] To stabilize the electrical characteristics of the transistor 500mF, reducing the impurity concentration in the channel formation region of the semiconductor layer 530 is effective. To further reduce the impurity concentration in the semiconductor layer 530, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in the semiconductor layer 530 refer, for example, to elements other than the main components constituting the semiconductor layer 530. For example, elements with a concentration less than 0.1 atomic% can be considered impurities.

[0678] Furthermore, in the semiconductor layer 530, it is sometimes difficult to clearly observe the boundaries of each region. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are not limited to varying in stages according to each region, but can also vary gradually in each region. That is to say, the closer to the channel formation region, the lower the concentration of metal elements and impurity elements such as hydrogen and nitrogen can be.

[0679] In transistors using oxide semiconductors in semiconductor layer 530, the electrical characteristics can easily change and sometimes reduce reliability if impurities and oxygen vacancies are present in the region where the oxide semiconductor forms the channel. Furthermore, hydrogen near the oxygen vacancy forms a defect where hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V). O H) may generate electrons that become charge carriers. Therefore, when oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor is prone to becoming always-on. Thus, it is preferable to minimize impurities, oxygen vacancies, and V in the channel formation region of an oxide semiconductor. O H. In other words, the preferred channel formation region in an oxide semiconductor is a region where the carrier concentration is reduced and it is i-typed (intrinsic) or substantially i-typed.

[0680] In contrast, by performing heat treatment with an insulating layer containing oxygen that has been removed by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor, oxygen can be supplied to the oxide semiconductor from the insulating layer, thereby reducing oxygen vacancies and V. O H. Note that supplying excessive oxygen to the source or drain regions may cause a decrease in the transistor's 500mF on-state current or a decrease in field-effect mobility. Furthermore, when the amount of oxygen supplied to the source or drain regions is uneven within the substrate surface, the characteristics of the semiconductor device, including the transistor, become non-uniform. Additionally, when oxygen supplied from the insulating layer to the oxide semiconductor diffuses to the conductive layers such as the gate, source, and drain electrodes, these conductive layers may sometimes be oxidized, leading to a loss of conductivity and thus negatively impacting the transistor's electrical characteristics and reliability.

[0681] Therefore, preferably, in the oxide semiconductor, the channel formation region is a region with reduced carrier concentration and is i-type or substantially i-type, while the source and drain regions are regions with high carrier concentration and are n-type. In other words, it is preferable to reduce oxygen vacancies and V0 in the channel formation region of the oxide semiconductor. O H. Furthermore, it is preferable that the source and drain regions are not supplied with excessive oxygen and that the V in the source and drain regions... O The amount of hydrogen (H) is not excessively reduced. Furthermore, a structure that suppresses the decrease in conductivity of conductive layers 560, 542a, and 542b is preferred. For example, a structure that suppresses oxidation of conductive layers 560, 542a, and 542b is preferred. Note that hydrogen in oxide semiconductors may form V0. O H, therefore, in order to reduce V O The amount of H needs to be reduced, so the hydrogen concentration needs to be lowered.

[0682] like Figure 30B As shown, insulating layer 550 includes insulating layer 550a, insulating layer 550b, insulating layer 550c, and insulating layer 550d. Furthermore, insulating layers 550a to 550d serve as part of the first gate insulating film. Insulating layers 550a to 550d are disposed in openings formed in insulating layer 580, similar to the conductive layer 560 described below. To achieve miniaturization of the transistor 500mf, the thickness of insulating layers 550a to 550d is preferably small. The thickness of insulating layers 550a to 550d is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, further preferably 0.5 nm or more and 5.0 nm or less, even more preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less. Furthermore, at least a portion of each of insulating layers 550a to 550d may include a region having the thicknesses described above.

[0683] In addition, the thickness of the silicon oxide film used as the insulating layer 550 is preferably 0.7 nm or more and 3 nm or less.

[0684] To reduce the thickness of insulating layers 550a to 550d as described above, atomic layer deposition (ALD) is preferably used for deposition. Furthermore, to provide insulating layers 550a to 550d within openings in insulating layers 580, etc., ALD is also preferred. ALD methods include thermal ALD, which uses only thermal energy to react the precursors and reactants, and PEALD, which uses reactants excited by plasma. In PEALD, deposition can be performed at lower temperatures by utilizing plasma, and is therefore sometimes preferred.

[0685] The ALD method can deposit atoms layer by layer, thus enabling the deposition of very thin films, high aspect ratio structures, deposition with fewer defects such as pinholes, high coverage deposition, and deposition at low temperatures. Therefore, a thin insulating layer 550 can be deposited with high coverage on the sides of the opening formed in the insulating layer 580.

[0686] Note that the precursors used in the ALD method sometimes contain carbon and other impurities. Therefore, films formed using the ALD method sometimes contain more carbon and other impurities compared to films formed using other deposition methods. Furthermore, the quantification of impurities can be performed using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0687] Note that while the above description indicates that the insulating layer 550 has a four-layer structure consisting of insulating layers 550a to 550d, the present invention is not limited thereto. The insulating layer 550 may have a structure including at least one of insulating layers 550a to 550d. By having the insulating layer 550 comprise one, two, or three of insulating layers 550a to 550d, the manufacturing process of semiconductor devices can be simplified, thereby improving productivity.

[0688] For example, insulating layer 550 may also have a three-layer structure. In this case, insulating layer 550 preferably has a stacked structure of insulating layer 550a, insulating layer 550b on insulating layer 550a, and insulating layer 550c on insulating layer 550b. That is, it may also have a structure consisting of insulating layer 550a, insulating layer 550b on insulating layer 550a, and insulating layer 550c on insulating layer 550b. Figure 30A The structure shown is the structure with the insulation layer removed by 550d.

[0689] When forming the insulating layer 550, it is preferable to perform the ALD process twice or more. For example, it is preferable that the insulating layer 550 has a laminated structure composed of multiple insulating films, and that two or more of the multiple insulating films are formed using the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and thickness uniformity of the insulating layer 550 can be improved. In addition, by continuously forming two or more different films, such as two or more insulating films, using the ALD process, productivity can be improved.

[0690] As an example, insulating layer 550a is preferably made of alumina or the like, which has a high ability to trap or fix hydrogen. In addition, insulating layer 550b is preferably made of silicon oxide or the like, which has high dielectric strength. Furthermore, insulating layer 550c is preferably made of hafnium oxide or the like, which has a high ability to trap or fix hydrogen. Furthermore, insulating layer 550d is preferably made of silicon nitride or the like, which has high hydrogen barrier properties.

[0691] exist Figure 28D In this embodiment, the conductive layer 560 has a two-layer structure. Preferably, the conductive layer 560 includes a conductive layer 560a and a conductive layer 560b disposed on the conductive layer 560a. For example, it is preferable that the conductive layer 560a is disposed such that it surrounds the bottom and side surfaces of the conductive layer 560b. In this case, as the conductive layer 560a, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion.

[0692] The conductive layer 560a preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, a conductive material that has the function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) is preferably used.

[0693] Furthermore, when the conductive layer 560a has the function of suppressing oxygen diffusion, it can prevent the oxygen contained in the insulating layer 580, etc., from oxidizing the conductive layer 560b and causing a decrease in conductivity. As a conductive material with the function of suppressing oxygen diffusion, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc., are preferably used, for example. Alternatively, the conductive layer 560a can also use the materials described above that can be used in the conductive layer ME1.

[0694] Furthermore, conductive layer 560b is preferably a conductive layer with high conductivity. For example, conductive layer 560b can use a conductive material with tungsten, copper, or aluminum as the main component. Additionally, conductive layer 560b can have a stacked structure, for example, a stacked structure of titanium or titanium nitride with the aforementioned conductive material. Alternatively, conductive layer 560b can also use the materials described above that can be used in conductive layer ME1.

[0695] Furthermore, in transistor 500mf, conductive layer 560 is formed in a self-aligned manner by embedding it into openings formed in insulating layer 580, etc. Here, the side surface of insulating layer 580 in the aforementioned opening is aligned or substantially aligned with the side surface of conductive layer 542a and conductive layer 542b. Therefore, conductive layer 560 can be configured to overlap with the region between conductive layer 542a and conductive layer 542b without positional alignment.

[0696] Conductive layer 542a has a region that serves as one of the source and drain electrodes of transistor 500mf. Conductive layer 540a is used as a connector to conductive layer 542a. Conductive layer 542b has a region that serves as the other of the source and drain electrodes of transistor 500mf. Conductive layer 540b is used as a connector to conductive layer 542b.

[0697] As conductive layers 542a and 542b, conductive materials that are not easily oxidized or conductive materials that suppress oxygen diffusion are preferably used. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. This suppresses the decrease in conductivity of conductive layers 542a and 542b. When conductive materials containing metal and nitrogen are used as conductive layers 542a and 542b, the conductive layers 542a and 542b are conductive layers containing at least metal and nitrogen. For example, as materials for conductive layers 542a and 542b, conductive materials that are not easily oxidized or conductive materials that suppress oxygen diffusion can be selected from the materials available for conductive layer ME1 described above.

[0698] Conductive layers 540a and 540b preferably use conductive materials with tungsten, copper, or aluminum as the main components. Alternatively, conductive layer 540 can also be a stacked structure in which a first conductive layer is disposed in contact with the side of insulating layer 541 and a second conductive layer is disposed inside it. In this case, the aforementioned conductive material can be used as the second conductive layer. Furthermore, conductive layers 540a and 540b can also use the materials described above that can be used for conductive layer ME1. Here, the aforementioned...

Claims

1. A multiplication circuit, comprising: Unit 1; as well as Unit 2 The first unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor element, and a second capacitor element. The second unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a third capacitor, and a fourth capacitor. One of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor and the first terminal of the first capacitor element. The other of the source and drain of the second transistor is electrically connected to the gate of the third transistor and the first terminal of the second capacitor element. One of the source and drain terminals of the third transistor is electrically connected to one of the source and drain terminals of the fourth transistor. One of the source and drain terminals of the fifth transistor is electrically connected to one of the source and drain terminals of the sixth transistor and the first terminal of the third capacitor element. The other of the source and drain of the sixth transistor is electrically connected to the gate of the seventh transistor and the first terminal of the fourth capacitor element. One of the source and drain of the seventh transistor is electrically connected to one of the source and drain of the eighth transistor. The other of the source and drain of the first transistor and the other of the source and drain of the fourth transistor are both electrically connected to the first wiring. The other of the source and drain of the fifth transistor, the other of the source and drain of the eighth transistor, the second terminal of the first capacitor element, the second terminal of the second capacitor element, the second terminal of the third capacitor element, and the second terminal of the fourth capacitor element are electrically connected to the second wiring. Furthermore, the gates of the first transistor, the second transistor, the fifth transistor, and the sixth transistor are electrically connected to the third wiring.

2. A multiplication circuit, comprising: Unit 1; as well as Unit 2 The first unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor element, and a second capacitor element. The second unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a third capacitor, and a fourth capacitor. One of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor and the first terminal of the first capacitor element. The other of the source and drain of the second transistor is electrically connected to the gate of the third transistor and the first terminal of the second capacitor element. One of the source and drain terminals of the third transistor is electrically connected to one of the source and drain terminals of the fourth transistor. One of the source and drain terminals of the fifth transistor is electrically connected to one of the source and drain terminals of the sixth transistor and the first terminal of the third capacitor element. The other of the source and drain of the sixth transistor is electrically connected to the gate of the seventh transistor and the first terminal of the fourth capacitor element. One of the source and drain of the seventh transistor is electrically connected to one of the source and drain of the eighth transistor. The other of the source and drain of the first transistor and the other of the source and drain of the fourth transistor are both electrically connected to the first wiring. The other of the source and drain of the fifth transistor, the other of the source and drain of the eighth transistor, the second terminal of the first capacitor element, the second terminal of the second capacitor element, the second terminal of the third capacitor element, and the second terminal of the fourth capacitor element are all electrically connected to the second wiring. The gates of the first transistor and the fifth transistor are electrically connected to the third wiring. Furthermore, the gates of the second transistor and the sixth transistor are electrically connected to the fourth wiring.

3. The multiplication circuit according to claim 1 or 2, The electrostatic capacitance of the second capacitor element is greater than that of the first capacitor element. Furthermore, the electrostatic capacitance value of the fourth capacitor element is greater than that of the third capacitor element.

4. The multiplication circuit according to claim 3, The first to the eighth transistors all contain oxide semiconductors in the channel formation region. The oxide semiconductor comprises one or more elements selected from indium, zinc, and element M. And the element M is selected from one or more of aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt and antimony.

5. The multiplication circuit according to claim 4, The second unit has the function of maintaining the gate potential of the seventh transistor by means of a reference current flowing between the source and drain of the seventh transistor. The first unit has the function of maintaining the gate potential of the third transistor by means of a first current flowing between the source and drain of the third transistor. Furthermore, the first unit has the following function: due to the capacitive coupling of the fourth capacitor element, the gate potential of the seventh transistor changes, causing the reference current flowing between the source and drain of the seventh transistor to change to a second current, thereby amplifying the first current flowing between the source and drain of the third transistor to a third current according to the ratio of the reference current to the second current.

6. An operational circuit, comprising: The multiplication circuits as described in claims 5; First circuit; Second circuit; as well as Third circuit, Each of the multiple multiplication circuits is electrically connected to the same first wiring. Each of the multiple multiplication circuits is electrically connected to a different second wiring. The first circuit has the function of generating the first current based on the first data and inputting the first current through the first wiring to one of the plurality of multiplication circuits. The second circuit has the function of generating the second current based on the second data and inputting the second current into the multiplication circuit electrically connected to one of the plurality of second wirings. Furthermore, the third circuit has the following function: taking the sum of the third currents flowing through each of the plurality of multiplication circuits in the first wiring as input value, performing a nonlinear function operation, and thereby outputting the result.

7. An electronic device comprising the computing circuit and the housing as described in claim 6.

8. A multiplication circuit, comprising: Unit 1; as well as Unit 2 The first unit includes K (K is an integer greater than or equal to 3) first transistors, second transistors, third transistors, K-1 first capacitor elements, and second capacitor elements. The second unit includes L fourth transistors, fifth transistors, sixth transistors (L is an integer greater than or equal to 3), L-1 third capacitor elements, and fourth capacitor elements. K first transistors are connected in series. In the K first transistors connected in series, the connection portions of two consecutive first transistors are electrically connected to the first terminal of a first capacitor element. One of the two ends of the K first transistors connected in series is electrically connected to the gate of the second transistor and the first terminal of the second capacitor element. One of the source and drain of the second transistor is electrically connected to one of the source and drain of the third transistor. The L fourth transistors are connected in series. In the L fourth transistors connected in series, the connection portions of two consecutive fourth transistors are both electrically connected to the first terminal of a third capacitor element. One of the two ends of the L fourth transistors connected in series is electrically connected to the gate of the fifth transistor and the first terminal of the fourth capacitor element. One of the source and drain terminals of the fifth transistor is electrically connected to one of the source and drain terminals of the sixth transistor. One of the K first transistors connected in series and the other of the source and drain of the third transistor are electrically connected to the first wiring. The other terminal of one of the L fourth transistors connected in series, the other source and drain of the sixth transistor, each of the second terminals of the K-1 first capacitor elements, the second terminal of the second capacitor element, each of the second terminals of the L-1 third capacitor elements, and the second terminal of the fourth capacitor element are electrically connected to the second wiring. Furthermore, each of the gates of the K first transistors and each of the gates of the L fourth transistors are electrically connected to the third wiring.

9. The multiplication circuit according to claim 8, The first to the sixth transistors all contain oxide semiconductors in the channel formation region. The oxide semiconductor comprises one or more elements selected from indium, zinc, and element M. And the element M is selected from one or more of aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt and antimony.

10. The multiplication circuit according to claim 9, The second unit has the function of maintaining the gate potential of the fifth transistor by means of a reference current flowing between the source and drain of the fifth transistor. The first unit has the function of maintaining the gate potential of the second transistor by having a first current flow through the source-drain junction of the second transistor. Furthermore, the first unit has the following function: due to the capacitive coupling of the fourth capacitor element, the gate potential of the fifth transistor changes, causing the reference current flowing between the source and drain of the fifth transistor to change to a second current, thereby amplifying the first current flowing between the source and drain of the second transistor to a third current according to the ratio of the reference current to the second current.

11. An operational circuit, comprising: The multiplication circuit as described in claims 10; First circuit; Second circuit; as well as Third circuit, Each of the multiple multiplication circuits is electrically connected to the same first wiring. Each of the multiple multiplication circuits is electrically connected to a plurality of second wirings that are different from each other. The first circuit has the function of generating the first current based on the first data and inputting the first current through the first wiring to one of the plurality of multiplication circuits. The second circuit has the function of generating the second current based on the second data and inputting the second current into the multiplication circuit electrically connected to one of the plurality of second wirings. Furthermore, the third circuit has the following function: taking the sum of the third currents flowing through each of the plurality of multiplication circuits in the first wiring as input value, performing a nonlinear function operation, and thereby outputting the result.

12. An electronic device comprising the computing circuitry and housing as described in claim 11.

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