Programmable logic controller implicit access address identification method, system and electronic device

Abstract

The application provides a programmable logic controller implicit access address identification method, system and electronic equipment, and the method comprises the following steps: in the compiling process of a user program, scanning relevant program codes to find out target instructions; according to preset address interval analysis rules, the target instructions are analyzed to identify all register addresses corresponding to the target instructions, and all identified register addresses are determined as implicit access addresses; and the implicit access addresses are identified in a cross-reference table in a preset format. Through identification of the implicit access register addresses and intuitive identification in the cross-reference table, the application can help electrical engineers to more quickly and conveniently check the use of the register addresses, effectively improve program checking efficiency and reduce the difficulty of program debugging and maintenance.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, system, and electronic device for identifying implicit access addresses of a programmable logic controller. Background Technology

[0002] In PLC (Programmable Logic Controller) programming, data interaction of communication instructions relies on specific data register addresses. For example, receive data is stored in the address range VB0 to VB100, and send data is stored in the address range VB200 to VB300. However, existing PLC programming software has a deficiency in its cross-reference table for identifying these continuous address ranges. When the program is compiled using programming software from other manufacturers, the cross-reference table typically only displays the start and end addresses of the address range, i.e., only VB0, VB100, VB200, and VB300 are visible. But in actual operation, all 202 register addresses from VB0 to VB100 and VB200 to VB300 are used. This makes it difficult for electrical engineers to quickly and comprehensively grasp the actual usage of register addresses when checking the program, and makes it difficult to quickly identify the actual occupied range of the communication buffer during debugging, increasing the difficulty of program debugging and maintenance, and reducing work efficiency. It also causes address overlap, leading to data overwriting and runtime errors.

[0003] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a method, system, and electronic device for identifying implicit access addresses of programmable logic controllers. By identifying the addresses of implicitly accessed registers and visually marking them in a cross-reference table, this invention can help electrical engineers to view the usage of register addresses more quickly and conveniently, effectively improving program inspection efficiency and reducing the difficulty of program debugging and maintenance.

[0005] To achieve the above objectives, the present invention provides a method for identifying implicit access addresses of a programmable logic controller, comprising:

[0006] During the compilation of the user program, the relevant program code is scanned to find the target instructions;

[0007] The target instruction is parsed according to the preset address range parsing rules to identify all register addresses corresponding to the target instruction, and all identified register addresses are determined to be implicit access addresses;

[0008] The implicit access address is identified in the cross-reference table using a preset format.

[0009] Optionally, the implicit access address identification method for programmable logic controllers provided by the present invention further includes:

[0010] The tagging information identifies each of the implicit access addresses. The tagging information includes a label and detailed information, including the instruction type to which the implicit access address belongs, the name of the program module in which it is located, and its location.

[0011] Optionally, the step of identifying the hidden access address in the cross-reference table using a preset format includes:

[0012] A label is displayed next to the hidden access address, and detailed information about the hidden access address is indicated by a mouse hover tooltip.

[0013] Optionally, the implicit access address identification method for programmable logic controllers provided by the present invention further includes:

[0014] Create an address tag database and store each of the implicit access addresses and their tag information in the address tag database according to a preset data structure.

[0015] Optionally, the step of identifying the hidden access address in the cross-reference table using a preset format includes:

[0016] For each target instruction, all implicit access addresses corresponding to the target instruction are folded and marked in the cross-reference table along with the corresponding implicit memory area.

[0017] Optionally, the step of identifying the hidden access address in the cross-reference table using a preset format includes:

[0018] The implicit access address is highlighted in the cross-reference table.

[0019] Optionally, the implicit access address identification method for programmable logic controllers provided by the present invention further includes:

[0020] Provides a hidden access address filtering function, allowing users to filter hidden access addresses and present the filtering results in a list format.

[0021] Optionally, the implicit access address identification method for programmable logic controllers provided by the present invention further includes:

[0022] It provides an import function for free monitoring tables, allowing users to freely import hidden access addresses that need to be monitored.

[0023] Optionally, the user program is a program written by the user in the programmable logic controller programming software that specifies the data register address range.

[0024] To achieve the above objectives, the present invention also provides a programmable logic controller (PLC) implicit access address identification system, comprising: a target instruction lookup module configured to scan relevant program code during the compilation of a user program to find a target instruction; an address identification module configured to parse the target instruction according to a preset address range parsing rule to identify all register addresses corresponding to the target instruction, and to determine all identified register addresses as implicit access addresses; and an address identification module configured to identify the implicit access addresses in a cross-reference table using a preset format.

[0025] Optionally, the implicit access address identification system for programmable logic controllers provided by the present invention further includes: an address marking module, configured to identify the marking information of each implicit access address, wherein the marking information includes a label and detailed information, wherein the detailed information includes the instruction type to which the implicit access address belongs, the name of the program module to which it belongs, and the location.

[0026] Optionally, the implicit access address identification system for programmable logic controllers provided by the present invention further includes: an address filtering module, configured to provide an implicit access address filtering function so that users can filter implicit access addresses and present the filtering results in a list format.

[0027] Optionally, the implicit access address identification system for programmable logic controllers provided by the present invention further includes: an address monitoring module configured to provide an import function for a free monitoring table, allowing users to freely import implicit access addresses that need to be monitored.

[0028] To achieve the above objectives, the present invention also provides an electronic device, the electronic device including a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, it implements the implicit access address identification method of the programmable logic controller described in any of the preceding claims.

[0029] Compared with the prior art, the programmable logic controller implicit access address identification method, system, and electronic device provided by the present invention have the following advantages:

[0030] The implicit access address identification method for programmable logic controllers provided by this invention scans relevant program code during the compilation process of the user program to find target instructions that specify a data register address range. By parsing the target instructions using preset address range parsing rules, it can automatically identify all register addresses within the data register address range (i.e., all register addresses corresponding to the target instruction) and determine these identified register addresses as implicit access addresses. Finally, it uses a preset format to mark all the identified implicit access addresses in a cross-reference table. Thus, by identifying implicit access register addresses and intuitively marking them in a cross-reference table, this invention can effectively compensate for the deficiencies of existing cross-reference tables in PLC (Programmable Logic Controller) programming software. This allows electrical engineers to have a comprehensive and intuitive understanding of register address usage, avoiding program checks that are missed due to incomplete address information, effectively improving the accuracy of program checks. At the same time, it can also greatly shorten the debugging and maintenance time of electrical engineers, improve their work efficiency, and effectively reduce the company's labor and time costs. Furthermore, by using a preset format to identify the implicit access address in the cross-reference table, a unified and standardized method for identifying implicit access addresses can be formed, which helps to improve code readability and maintainability across different projects and promotes collaborative team development.

[0031] Since the programmable logic controller implicit access address identification system and electronic device provided by this invention belong to the same inventive concept as the programmable logic controller implicit access address identification method provided by this invention, the programmable logic controller implicit access address identification system and electronic device provided by this invention have at least all the beneficial effects of the programmable logic controller implicit access address identification method provided by this invention. For details, please refer to the relevant descriptions of the beneficial effects of the programmable logic controller implicit access address identification method provided by this invention above, which will not be repeated here. Attached Figure Description

[0032] Figure 1 A flowchart illustrating a method for identifying the implicit access address of a programmable logic controller according to an embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram illustrating the identification of implicit access addresses in a cross-reference table according to an embodiment of the present invention.

[0034] Figure 3 This is a schematic diagram of a hidden access address filtering interface provided in one embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram illustrating one-click import of a free monitoring table according to an embodiment of the present invention.

[0036] Figure 5 This is a schematic diagram illustrating the manual addition of a free monitoring table according to one embodiment of the present invention.

[0037] Figure 6 This is a structural block diagram of a programmable logic controller implicit access address identification system provided in one embodiment of the present invention.

[0038] Figure 7 This is a structural block diagram of an electronic device provided according to an embodiment of the present invention.

[0039] The reference numerals in the attached diagrams are explained as follows: Free monitoring table icon - 10; Target instruction lookup module - 110; Address identification module - 120; Address identification module - 130; Address marking module - 140; Address filtering module - 150; Address monitoring module - 160; Processor - 210; Communication interface - 220; Memory - 230; Communication bus - 240. Detailed Implementation

[0040] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the implicit access address identification method, system, and electronic device for programmable logic controllers proposed in this invention. Please refer to the accompanying drawings for clarity regarding the objectives, features, and advantages of this invention. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely illustrative of the content disclosed in this specification, intended for those skilled in the art to understand and read, and are not intended to limit the implementation conditions of this invention. Any modifications to the structure, changes in proportions, or adjustments to the size, provided they produce the same or similar effects and achieve the same objectives as this invention, should still fall within the scope of the technical content disclosed in this invention.

[0041] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The singular forms “a,” “an,” and “the” include plural objects. The term “or” is generally used to mean “and / or,” the term “several” is generally used to mean “at least one,” and the term “at least two” is generally used to mean “two or more.” Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0042] Furthermore, in the description of this specification, the reference to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., means that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0043] The core idea of ​​this invention is to provide a method, system, and electronic device for identifying implicit access addresses of a programmable logic controller. By identifying the addresses of implicitly accessed registers and visually marking them in a cross-reference table, electrical engineers can more quickly and conveniently view the usage of register addresses, effectively improving program inspection efficiency and reducing the difficulty of program debugging and maintenance.

[0044] It should be noted that the implicit access address identification method for programmable logic controllers provided by the present invention can be applied to the implicit access address identification system for programmable logic controllers provided by the present invention. The implicit access address identification system for programmable logic controllers provided by the present invention can be configured on the electronic device provided by the present invention. The electronic device provided by the present invention can be a personal computer, a mobile terminal, etc., and the mobile terminal can be a mobile phone, a tablet computer, or other hardware device with various operating systems.

[0045] To achieve the above idea, this invention provides a method for identifying the implicit access address of a programmable logic controller. Please refer to [the relevant documentation]. Figure 1 The flowchart illustrating an embodiment of the implicit access address identification method for a programmable logic controller provided by the present invention is shown below. Figure 1 As shown, the implicit access address identification method for the programmable logic controller includes the following steps:

[0046] Step S100: During the compilation of the user program, the relevant program code is scanned to find the target instructions.

[0047] Step S200: Parse the target instruction according to the preset address range parsing rules to identify all register addresses corresponding to the target instruction, and determine all identified register addresses as implicit access addresses.

[0048] Step S300: Identify the hidden access address in the cross-reference table using a preset format.

[0049] The implicit access address identification method for programmable logic controllers provided by this invention scans relevant program code during the compilation process of the user program to find target instructions that specify a data register address range. By parsing the target instructions using preset address range parsing rules, it can automatically identify all register addresses within the data register address range (i.e., all register addresses corresponding to the target instruction) and determine these identified register addresses as implicit access addresses. Finally, it uses a preset format to mark all the identified implicit access addresses in a cross-reference table. Thus, by identifying implicit access register addresses and intuitively marking them in a cross-reference table, this invention can effectively compensate for the deficiencies of existing cross-reference tables in PLC (Programmable Logic Controller) programming software. This allows electrical engineers to have a comprehensive and intuitive understanding of register address usage, avoiding program checks that are missed due to incomplete address information, effectively improving the accuracy of program checks. At the same time, it can also greatly shorten the debugging and maintenance time of electrical engineers, improve their work efficiency, and effectively reduce the company's labor and time costs. Furthermore, by using a preset format to identify the implicit access address in the cross-reference table, a unified and standardized method for identifying implicit access addresses can be formed, which helps to improve code readability and maintainability across different projects and promotes collaborative team development.

[0050] Specifically, the user program can be, but is not limited to, a program written by the user (electrical engineer) in the PLC (Programmable Logic Controller) programming software that specifies a data register address range (e.g., a communication instruction). After the user (electrical engineer) writes the communication instruction or other instruction specifying a data register address range in the PLC programming software, the compilation operation is initiated. During the compiler's compilation task, the relevant program code is scanned line by line to find the target instruction specifying the data register address range. Then, the target instruction is parsed according to a preset address range parsing rule to extract the start address and data length (end address) from the relevant parameters of the target instruction. Based on the start address and the data length, all register addresses can be identified and determined as implicit access addresses. For example, taking a data receiving instruction (a type of communication instruction) as an example, when the data receiving instruction specifies a storage address (register address) of VB0 to VB100, each register address from VB0 to VB100 can be identified sequentially according to the preset address range parsing rule. Similarly, taking a data transmission instruction (a type of communication instruction) as an example, when the specified storage address (register address) in the data transmission instruction is VB200 to VB300, each register address from VB200 to VB300 can be identified sequentially according to the preset address range resolution rules.

[0051] In some exemplary embodiments, the implicit access address identification method for programmable logic controllers provided by the present invention further includes:

[0052] The tagging information identifies each of the implicit access addresses. The tagging information includes a label and detailed information, including the instruction type to which the implicit access address belongs, the name of the program module in which it is located, and its location.

[0053] Therefore, by identifying the hidden access address with its label, instruction type, program module name, and location, electrical engineers can more easily and intuitively understand the usage of register addresses, avoiding omissions in program checks due to incomplete address information identification, and effectively improving the accuracy of program checks.

[0054] Specifically, for each of the identified implicit access addresses, the label of the implicit access address can be set to "implicit access". Further, taking the VB50 address as an example, its label can be marked as "implicit access", its instruction type can be marked as "receive", and its program module can be marked as "data receiving subroutine of the main program module".

[0055] In some exemplary embodiments, the implicit access address identification method for programmable logic controllers provided by the present invention further includes:

[0056] Create an address tag database and store each of the implicit access addresses and their tag information in the address tag database according to a preset data structure.

[0057] Therefore, by storing each of the implicit access addresses and their tagging information in the address tagging database according to a preset data structure, it can be ensured that users can quickly perform address lookup and tagging operations.

[0058] It should be noted that, as those skilled in the art will understand, the present invention does not limit the specific type of the preset data structure. For example, a data structure using a range index table and bitmap technology can be adopted to achieve efficient storage of implicit access addresses and their marking information.

[0059] In some exemplary embodiments, identifying the implicit access address in a cross-reference table using a preset format includes:

[0060] A label is displayed next to the hidden access address, and detailed information about the hidden access address is indicated by a mouse hover tooltip.

[0061] Therefore, displaying labels next to implicit access addresses allows electrical engineers to quickly distinguish between ordinary and implicit addresses. Furthermore, using mouse hover tooltips to highlight detailed information about these implicit access addresses provides engineers with a comprehensive and intuitive understanding of register address usage, preventing omissions in program checks due to incomplete address information and effectively improving the accuracy of program inspections. Specifically, when an electrical engineer hovers the mouse pointer over a hidden access address, a tooltip will pop up displaying detailed information about that address, such as the instruction type and the program module it belongs to, allowing the engineer to quickly understand the role and usage of that implicit access address within the program.

[0062] In some exemplary embodiments, identifying the implicit access address in a cross-reference table using a preset format further includes:

[0063] For each target instruction, all implicit access addresses corresponding to the target instruction are folded and marked in the cross-reference table along with the corresponding implicit memory area.

[0064] Therefore, by folding and marking all implicit access addresses corresponding to each target instruction in the cross-reference table along with the corresponding implicit memory area, all identified implicit addresses can be listed more concisely. This not only avoids the cross-reference table becoming too long, but also allows electrical engineers to have a comprehensive and intuitive understanding of register address usage, avoiding omissions in program checks due to incomplete address information and effectively improving the accuracy of program checks.

[0065] Specifically, for example, if a target instruction corresponds to 100 implicit access addresses from VB100 to VB199, then these 100 implicit access addresses corresponding to the target instruction can be folded and marked in the cross-reference table using the implicit memory area %VB100~%VB199.

[0066] In some exemplary embodiments, identifying the implicit access address in a cross-reference table using a preset format further includes:

[0067] The implicit access address is highlighted in the cross-reference table.

[0068] Therefore, by highlighting the implicit access address in the cross-reference table, electrical engineers can more easily distinguish between ordinary addresses and implicit addresses.

[0069] For details, please refer to Figure 2 This is a schematic diagram illustrating the identification of the implicit access address in the cross-reference table according to an embodiment of the present invention. For example... Figure 2 As shown, for each target instruction, all implicit access addresses corresponding to the target instruction can be folded and marked in the cross-reference table with the corresponding implicit memory area, and highlighted in green font, and the "implicit access" label is displayed (the addresses in the column where the "implicit access" label is located are all implicit access addresses).

[0070] It should be noted that, although Figure 2 Therefore, the implicit access address (implicit memory area) is highlighted in green font. However, as those skilled in the art will understand, this does not constitute a limitation of the present invention. In other embodiments, other font colors (such as red) may be used to highlight the implicit access address. In still other embodiments, bold font or underlined text may be used to identify the implicit access address (implicit memory area). It should also be noted that, as those skilled in the art will understand, Figure 2 The “Sequence Number” column indicates the instruction sequence number, and the “Address” column indicates the starting address for the instruction to perform read or write operations.

[0071] In some exemplary embodiments, the implicit access address identification method for programmable logic controllers provided by the present invention further includes:

[0072] Provides a hidden access address filtering function, allowing users to filter hidden access addresses and present the filtering results in a list format.

[0073] Therefore, by providing a hidden access address filtering function, it is easier for users to filter hidden access addresses, which in turn makes it easier for electrical engineers to accurately locate the range of hidden access addresses, dynamically exclude irrelevant addresses, and thus more efficiently assist electrical engineers in debugging and maintaining programs.

[0074] Please continue to refer to this. Figure 3 This is a schematic diagram of a hidden access address filtering interface provided in one embodiment of the present invention. Figure 3 As shown, the implicit access address filtering function provided by this invention includes filtering options such as "not empty", "contains", "does not contain", "equal to", "not equal to", "starts at", "ends at", and "blank". When the user is not sure whether a certain register address is used, the "contains" filtering option can be used. At this time, the system will automatically calculate whether all implicit memory areas contain the register address and present the filtering results to the user in a list.

[0075] It should be noted that, as those skilled in the art will understand, the "blank" filter can be used to filter out addresses not marked as implicit access; the "not empty" filter can be used to filter out addresses already marked as implicit access; the "equal to" filter can be used to precisely match a single address entered by the user to confirm whether a specific address belongs to the implicit memory area; the "not equal to" filter can be used to exclude a single address entered by the user; the "start at" filter can be used to match implicit memory areas starting at the input address; and the "end at" filter can be used to match implicit memory areas ending at the input address.

[0076] In some exemplary embodiments, the implicit access address identification method for programmable logic controllers provided by the present invention further includes:

[0077] It provides an import function for free monitoring tables, allowing users to freely import hidden access addresses that need to be monitored.

[0078] In actual engineering projects, communication commands involve the transmission and reception of large amounts of data. In ladder diagrams or IL programs, only the value of the starting address can be displayed, and the detailed message of the command cannot be observed. This invention provides a function to import the free monitoring table, which allows users (electrical engineers) to import the hidden memory area into the free monitoring table with one click to observe the message details.

[0079] Please continue to refer to this. Figure 4 This is a schematic diagram illustrating one-click import of a free monitoring table according to an embodiment of the present invention. Figure 4 As shown, each target instruction's corresponding hidden memory area has a free monitoring table icon 10 next to it. After compilation, the user (electrical engineer) can click to view the cross-reference table function, find the hidden memory area of ​​interest, and generate the corresponding free monitoring table for that hidden memory area with one click by clicking the free monitoring table icon 10 next to it (e.g., on the right). The addresses of the hidden memory area are then filled into the table. When the program runs, the variables in the table are automatically monitored, allowing the user (electrical engineer) to observe the message details of the instruction corresponding to that hidden memory area. This avoids tedious manual addition, saving significant time and preventing human error. Please continue to refer to [reference needed]. Figure 4 ,like Figure 4 As shown, the free monitoring table supports display in multiple formats such as BIN (binary), OCT (octal), DEC (decimal), HEX (hexadecimal), and ASCII (American Standard Code for Information Interchange).

[0080] Please continue to refer to this. Figure 5 This is a schematic diagram illustrating the manual addition of a free monitoring table according to an embodiment of the present invention. Figure 5As shown, users (electrical engineers) can also manually write the hidden access addresses that need to be monitored in batches. For example, users can manually write the starting address and quantity in the "Batch Add Registers" interface, and then click "Add" to manually generate the corresponding free monitoring table.

[0081] Based on the same inventive concept, this invention also provides a programmable logic controller implicit access address identification system, please refer to [reference needed]. Figure 6 The diagram illustrates the structural block diagram of a programmable logic controller implicit access address identification system provided by an embodiment of the present invention. Figure 6 As shown, the implicit access address identification system for programmable logic controllers provided by the present invention includes: a target instruction lookup module 110, configured to scan relevant program code during the compilation process of a user program to find a target instruction; an address identification module 120, configured to parse the target instruction according to a preset address range parsing rule to identify all register addresses corresponding to the target instruction, and to determine all identified register addresses as implicit access addresses; and an address identification module 130, configured to identify the implicit access address in a cross-reference table using a preset format.

[0082] Therefore, the implicit access address identification system for programmable logic controllers provided by this invention scans the relevant program code during the compilation process of the user program to find the target instruction that specifies the data register address range. By parsing the target instruction using a preset address range parsing rule, it can automatically identify all register addresses within the data register address range (i.e., all register addresses corresponding to the target instruction) and determine these identified register addresses as implicit access addresses. Finally, it uses a preset format to mark all the identified implicit access addresses in a cross-reference table. Thus, by identifying the implicit access register addresses and intuitively marking them in a cross-reference table, this invention can effectively compensate for the deficiencies of existing cross-reference tables in PLC (Programmable Logic Controller) programming software. This allows electrical engineers to fully and intuitively understand the usage of register addresses, avoid program checks that are missed due to incomplete address information, effectively improve the accuracy of program checks, and also greatly shorten the debugging and maintenance time of electrical engineers, improve their work efficiency, and effectively reduce the labor and time costs of enterprises. Furthermore, by using a preset format to identify the implicit access address in the cross-reference table, a unified and standardized method for identifying implicit access addresses can be formed, which helps to improve code readability and maintainability across different projects and promotes collaborative team development.

[0083] Specifically, the target instruction lookup module 110 is responsible for scanning the relevant program code of instructions (such as communication instructions) that specify the data register address range during the program compilation process. The target instruction lookup module 110 is tightly integrated with the compiler and can obtain code information in real time during the compilation process.

[0084] When an electrical engineer writes a program in PLC programming software that contains instructions (such as communication instructions) that specify data register address ranges, the compilation operation is started. When the compiler executes the compilation task, the target instruction module and the address recognition module 120 automatically intervene. The target instruction module traverses the relevant instructions (such as communication instructions) that specify the data register address range. Taking the data receiving range VB0 to VB100 as an example, the target instruction module scans the program code line by line. When it detects an instruction related to the data receiving range (such as the data receiving instruction that specifies the storage address as VB0 to VB100), the address recognition module 120 will identify each register address from VB0 to VB100 in sequence according to the preset address range parsing rules and record it in the temporary storage area.

[0085] Please continue to refer to this. Figure 6 ,like Figure 6 As shown, in some exemplary embodiments, the implicit access address identification system for programmable logic controllers provided by the present invention further includes: an address tagging module 140, configured to identify tagging information for each of the implicit access addresses, the tagging information including a label and detailed information, the detailed information including the instruction type to which the implicit access address belongs, the name of the program module to which it belongs, and its location.

[0086] In some exemplary embodiments, the address tagging module 140 is further configured to create an address tagging database and store each of the implicit access addresses and their tagging information in the address tagging database according to a preset data structure.

[0087] Specifically, after identification is completed, the address identification module 120 will pass the implicit access address information in the temporary storage area to the address marking module 140. The address marking module 140 marks each implicit access address with an "implicit access" label, and records (marks) detailed information such as the instruction type (e.g., receive or send) to each implicit access address, as well as the name and location of the program module it belongs to, according to the target instruction information.

[0088] In some exemplary embodiments, the address identification module 130 is configured to display a label next to the implicit access address and to identify the details of the implicit access address via a mouse hover tooltip.

[0089] In some exemplary embodiments, the address identification module 130 is configured to, for each target instruction, fold and identify all implicit access addresses corresponding to that target instruction in the cross-reference table along with the corresponding implicit memory regions.

[0090] In some exemplary embodiments, the address identification module 130 is configured to highlight the implicit access address in the cross-reference table.

[0091] Specifically, after compilation, electrical engineers can click to view the cross-reference table function. The address identification module 130 first obtains the compiled address information from the compiler, then queries the address tag database. For identified implicit access addresses, the address identification module 130 marks them in the cross-reference table in a specific format. For example, it lists all addresses from VB0 to VB100 and from VB200 to VB300, highlights them in green font, and adds a "Implicit Access" comment after each address. When an electrical engineer hovers the mouse pointer over an implicit access address, a pop-up dialog box displays detailed tagging information for that implicit access address, such as the type of communication instruction it belongs to and the program module it belongs to, making it easy for electrical engineers to quickly understand the role and usage of that implicit access address in the program.

[0092] Please continue to refer to this. Figure 6 ,like Figure 6 As shown, in some exemplary embodiments, the implicit access address identification system for programmable logic controllers provided by the present invention further includes: an address filtering module 150, configured to provide an implicit access address filtering function so that users can filter implicit access addresses and present the filtering results in a list format.

[0093] Please continue to refer to this. Figure 6 ,like Figure 6 As shown, in some exemplary embodiments, the implicit access address identification system for programmable logic controllers provided by the present invention further includes: an address monitoring module 160, configured to provide a function for importing a free monitoring table, so that users can freely import the implicit access addresses that need to be monitored.

[0094] Specifically, after compilation, the electrical engineer can click the cross-reference table function to find the hidden memory area of ​​interest, click the free monitoring table icon 10 on the right, and the system will automatically generate a free monitoring table and fill in the address of the hidden memory area one by one in the table. When the program runs, it will automatically monitor the variables in the table.

[0095] Based on the same inventive concept, the present invention also provides an electronic device, please refer to... Figure 7 This is a block diagram of an electronic device provided in one embodiment of the present invention. Figure 7 As shown, the electronic device provided by this invention includes a processor 210 and a memory 230. The memory 230 stores a computer program. When the computer program is executed by the processor 210, it implements the programmable logic controller implicit access address identification method described above. Since the electronic device provided by this invention and the programmable logic controller implicit access address identification method provided by this invention belong to the same inventive concept, the electronic device provided by this invention possesses at least all the beneficial effects of the programmable logic controller implicit access address identification method provided by this invention. Therefore, the beneficial effects of the electronic device provided by this invention can be referred to the relevant descriptions of the beneficial effects of the programmable logic controller implicit access address identification method provided by this invention above, and will not be repeated here.

[0096] Please continue to refer to this. Figure 7 ,like Figure 7 As shown, the electronic device also includes a communication interface 220 and a communication bus 240, wherein the processor 210, the communication interface 220, and the memory 230 communicate with each other through the communication bus 240. The communication bus 240 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus 240 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used to represent it in the figure, but this does not indicate that there is only one bus or one type of bus. The communication interface 220 is used for communication between the aforementioned electronic device and other devices.

[0097] It should be noted that the processor 210 referred to in this invention can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor. The processor 210 is the control center of the electronic device, connecting various parts of the electronic device through various interfaces and lines.

[0098] It should also be noted that the memory 230 can be used to store the computer program, and the processor 210 implements various functions of the electronic device by running or executing the computer program stored in the memory 230 and calling the data stored in the memory 230. The memory 230 may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable memory (PROM), electrically programmable memory (EPROM), electrically erasable programmable memory (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, random access memory is available in a variety of forms, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous random access memory (SDRAM), dual data rate synchronous random access memory (DDRSDRAM), enhanced synchronous random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), memory bus direct random access memory (RDRAM), direct memory bus dynamic random access memory (DRDRAM), and memory bus dynamic random access memory (RDRAM), etc.

[0099] In summary, compared with the prior art, the programmable logic controller implicit access address identification method, system, and electronic device provided by the present invention have the following beneficial effects:

[0100] This invention, by scanning relevant program code during the compilation of user programs, can identify target instructions that specify data register address ranges. By parsing these target instructions using preset address range resolution rules, it can automatically identify all register addresses within that data register address range (i.e., all register addresses corresponding to the target instruction). These identified register addresses are then determined to be implicit access addresses. Finally, all identified implicit access addresses are marked in a cross-reference table using a preset format. Thus, by identifying implicit access register addresses and visually marking them in a cross-reference table, this invention effectively overcomes the shortcomings of existing PLC (Programmable Logic Controller) programming software cross-reference tables. This allows electrical engineers to comprehensively and intuitively understand the usage of register addresses, avoiding program checks that are missed due to incomplete address information, effectively improving the accuracy of program checks. It also significantly shortens the debugging and maintenance time for electrical engineers, improves their work efficiency, and effectively reduces the company's labor and time costs. Furthermore, by using a preset format to identify the implicit access addresses in the cross-reference table, a unified and standardized method for identifying implicit access addresses can be formed, thereby helping to improve code readability and maintainability across different projects and promoting collaborative team development. Additionally, this invention provides an import function for the free monitoring table, allowing users (electrical engineers) to import implicit memory areas into the free monitoring table with a single click to observe message details.

[0101] It should be noted that computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof. These programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0102] It should be noted that the apparatus and methods disclosed in the embodiments herein can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments herein. In this regard, each block in a flowchart or block diagram may represent a module, program, or part of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system to perform the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions. In addition, the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0103] It should also be noted that the above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A method for identifying implicit access addresses in a programmable logic controller, characterized in that, include: During the compilation of the user program, the relevant program code is scanned to find the target instructions; The target instruction is parsed according to the preset address range parsing rules to identify all register addresses corresponding to the target instruction, and all identified register addresses are determined to be implicit access addresses; The implicit access address is identified in the cross-reference table using a preset format.

2. The method for identifying the implicit access address of a programmable logic controller according to claim 1, characterized in that, The identification method further includes: The tagging information identifies each of the implicit access addresses. The tagging information includes a label and detailed information, including the instruction type to which the implicit access address belongs, the name of the program module in which it is located, and its location.

3. The method for identifying the implicit access address of a programmable logic controller according to claim 2, characterized in that, The step of identifying the hidden access address in the cross-reference table using a preset format includes: A label is displayed next to the hidden access address, and detailed information about the hidden access address is indicated by a mouse hover tooltip.

4. The method for identifying the implicit access address of a programmable logic controller according to claim 2, characterized in that, The identification method further includes: Create an address tag database and store each of the implicit access addresses and their tag information in the address tag database according to a preset data structure.

5. The method for identifying the implicit access address of a programmable logic controller according to claim 1, characterized in that, The step of identifying the hidden access address in the cross-reference table using a preset format includes: For each target instruction, all implicit access addresses corresponding to the target instruction are folded and marked in the cross-reference table along with the corresponding implicit memory area.

6. The method for identifying the implicit access address of a programmable logic controller according to claim 1, characterized in that, The step of identifying the hidden access address in the cross-reference table using a preset format includes: The implicit access address is highlighted in the cross-reference table.

7. The method for identifying the implicit access address of a programmable logic controller according to claim 1, characterized in that, The identification method further includes: Provides a hidden access address filtering function, allowing users to filter hidden access addresses and present the filtering results in a list format.

8. The method for identifying the implicit access address of a programmable logic controller according to claim 1, characterized in that, The identification method further includes: It provides an import function for free monitoring tables, allowing users to freely import hidden access addresses that need to be monitored.

9. The method for identifying the implicit access address of a programmable logic controller according to claim 1, characterized in that, The user program is a program written by the user in the programmable logic controller programming software that specifies the data register address range.

10. A programmable logic controller implicit access address identification system, characterized in that, include: The target instruction lookup module is configured to scan relevant program code during the compilation process of the user program to find the target instruction. The address recognition module is configured to parse the target instruction according to a preset address range parsing rule, so as to identify all register addresses corresponding to the target instruction, and determine all identified register addresses as implicit access addresses; as well as The address identification module is configured to identify the implicit access address in the cross-reference table using a preset format.

11. The implicit access address identification system for a programmable logic controller according to claim 10, characterized in that, Also includes: The address tagging module is configured to identify the tagging information of each of the implicit access addresses. The tagging information includes a label and detailed information, including the instruction type to which the implicit access address belongs, the name of the program module to which it belongs, and its location.

12. The implicit access address identification system for a programmable logic controller according to claim 10, characterized in that, Also includes: The address filtering module is configured to provide a hidden access address filtering function, allowing users to filter hidden access addresses and present the filtering results in a list format.

13. The implicit access address identification system for a programmable logic controller according to claim 10, characterized in that, Also includes: The address monitoring module is configured to provide the function of importing a free monitoring table, allowing users to freely import the hidden access addresses that need to be monitored.

14. An electronic device, characterized in that, It includes a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, it implements the implicit access address identification method for a programmable logic controller as described in any one of claims 1 to 9.

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