Charge pump circuit and charge pump device

Abstract

A charge pump circuit includes a first pump unit and a second pump unit. The first pump unit generates a pump voltage from an input voltage, a first clock signal and a second clock signal. The first clock signal and the second clock signal are in phase, and the second clock signal has a higher swing than the first clock signal. The second pump unit has a similar structure to the first pump unit, and the first and second pump units alternately output the pump voltage from the input voltage. Transistors in the first pump unit and the second pump unit operate in their safe operating area (SOA) and are disposed in two wells under independent biasing.

Description

Technical Field

[0001] This disclosure relates to a charge pump circuit, and more particularly to a charge pump circuit suitable for low-voltage environments. Background Technology

[0002] To meet the low-power demands of electronic devices, integrated circuits (ICs) have been redesigned to operate in low-voltage environments. While lower voltages are beneficial for reducing power consumption, there are still situations where higher voltages are required. For example, flash memory may require high voltages (positive or negative) to perform program operations or erase operations, and these high voltages are typically supplied by charge pumps.

[0003] However, designing charge pumps that operate in low-voltage environments is extremely challenging. For example, special care must be taken to ensure that the transistors used in the circuit operate within their safe operating areas (SOA). Furthermore, efficient charge transfer at each stage of the charge pump is crucial when operating in low-voltage environments. Therefore, designing efficient charge pumps capable of operating in low-voltage environments has become a pressing problem.

[0004] This "Background Art" section provides background information only. The statements in this "Background Art" section are not an admission that the subject matter disclosed in this section constitutes prior art to this disclosure, and no part of this "Background Art" section should be used as an admission that any part of this application (including this "Background Art" section) constitutes prior art to this disclosure. Summary of the Invention

[0005] This disclosure presents a charge pump circuit. The charge pump circuit includes an input terminal for receiving an input voltage, an output terminal for outputting an output voltage, a first pump unit, a first output transistor, a second pump unit, and a second output transistor. The first pump unit includes a first capacitor, a second capacitor, a first transistor, a second transistor, and a first auxiliary control unit. The first capacitor has a first terminal and a second terminal for receiving a first clock signal. The second capacitor has a first terminal and a second terminal for receiving a second clock signal. The first transistor has a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor. The second transistor has a first terminal coupled to the second terminal of the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal. The first auxiliary control unit is coupled to the control terminal of the second transistor and is used to turn on the second transistor when the first clock signal is at a first high voltage and to turn off the second transistor when the first clock signal is at a low voltage. The first output transistor has a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the output terminal, and a control terminal. The second pump unit includes a third capacitor, a fourth capacitor, a third transistor, a fourth transistor, and a second auxiliary control unit. The third capacitor has a first terminal and a second terminal for receiving a third clock signal. The fourth capacitor has a first terminal and a second terminal for receiving a fourth clock signal. The third transistor has a first terminal coupled to an input terminal, a second terminal coupled to a second terminal of the third capacitor and a control terminal of the first output transistor, and a control terminal coupled to a second terminal of the fourth capacitor. The fourth transistor has a first terminal coupled to a second terminal of the fourth capacitor, a second terminal coupled to a second terminal of the third transistor, and a control terminal. The second auxiliary control unit is coupled to the control terminal of the fourth transistor and is used to turn on the fourth transistor when the third clock signal is at a first high voltage and to turn off the fourth transistor when the third clock signal is at a low voltage. The second output transistor has a first terminal coupled to a second terminal of the third transistor, a second terminal coupled to an output terminal, and a control terminal coupled to a second terminal of the first transistor. The first clock signal is in phase with the second clock signal, and the third clock signal is in phase with the fourth clock signal. The first clock signal is out of phase with the third clock signal. The second clock signal has a larger swing than the first clock signal, and the fourth clock signal has a larger swing than the third clock signal. The first transistor and the second transistor are disposed in the first well, and the third transistor and the fourth transistor are disposed in the second well.

[0006] Another embodiment of this disclosure proposes a charge pump device. The charge pump device includes a multi-stage charge pump circuit, with the input terminal of a subsequent charge pump circuit connected to the output terminal of a preceding charge pump circuit. The first stage charge pump circuit of the multi-stage charge pump circuit includes an input terminal for receiving an input voltage, an output terminal for outputting an output voltage, a first pump unit, a first output transistor, a second pump unit, and a second output transistor. The first pump unit includes a first capacitor, a second capacitor, a first transistor, a second transistor, and a first auxiliary control unit. The first capacitor has a first terminal and a second terminal for receiving a first clock signal. The second capacitor has a first terminal and a second terminal for receiving a second clock signal. The first transistor has a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor. The second transistor has a first terminal coupled to the second terminal of the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal. The first auxiliary control unit is coupled to the control terminal of the second transistor and is used to turn on the second transistor when the first clock signal is at a first high voltage and to turn off the second transistor when the first clock signal is at a low voltage. The first output transistor has a first terminal coupled to a second terminal of the first transistor, a second terminal coupled to an output terminal, and a control terminal. The second pump unit includes a third capacitor, a fourth capacitor, a third transistor, a fourth transistor, and a second auxiliary control unit. The third capacitor has a first terminal and a second terminal for receiving a third clock signal. The fourth capacitor has a first terminal and a second terminal for receiving a fourth clock signal. The third transistor has a first terminal coupled to an input terminal, a second terminal coupled to the second terminal of the third capacitor and the control terminal of the first output transistor, and a control terminal coupled to the second terminal of the fourth capacitor. The fourth transistor has a first terminal coupled to the second terminal of the fourth capacitor, a second terminal coupled to the second terminal of the third transistor, and a control terminal. The second auxiliary control unit is coupled to the control terminal of the fourth transistor and is used to turn on the fourth transistor when the third clock signal is at a first high voltage and to turn off the fourth transistor when the third clock signal is at a low voltage. The second output transistor has a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to an output terminal, and a control terminal coupled to the second terminal of the first transistor. The first clock signal is in phase with the second clock signal, and the third clock signal is in phase with the fourth clock signal. The first clock signal is out of phase with the third clock signal. The second clock signal has a larger swing than the first clock signal, and the fourth clock signal has a larger swing than the third clock signal. The first transistor and the second transistor are disposed in the first well, and the third transistor and the fourth transistor are disposed in the second well. Attached Figure Description

[0007] This disclosure can be understood more fully by referring to the accompanying drawings, detailed description, and claims, in which similar element symbols in different drawings may refer to similar elements.

[0008] Figure 1 A charge pump circuit according to an embodiment of the present disclosure is illustrated; Figure 2 Illustration of an embodiment according to this disclosure Figure 1 The voltage and signal waveforms of the intermediate pump unit; Figure 3 Illustration of an embodiment according to this disclosure Figure 1 Well voltage selection unit for the intermediate pump unit; Figure 4 A charge pump circuit according to another embodiment of this disclosure is illustrated; Figure 5 Illustration of an embodiment according to this disclosure Figure 4 The voltage and signal waveforms of the intermediate pump unit; Figure 6 The waveform of a clock signal according to an embodiment of the present disclosure is illustrated; Figure 7 A charge pump device according to an embodiment of the present disclosure is illustrated. Detailed Implementation

[0009] Figure 1 A charge pump circuit 100 according to an embodiment of the present disclosure is illustrated. The charge pump circuit 100 includes an input terminal IN1, an output terminal OUT1, pump units 110 and 120, and output transistors MO1 and MO2. The input terminal IN1 receives an input voltage VIN, and the output terminal OUT1 outputs a positive output voltage VOUT, which is greater than the input voltage VIN.

[0010] Pump unit 110 can use two clock signals SIG. CLK0 With SIG ACLK0 This is used to boost the input voltage VIN and generate a positive output voltage VOUT. Clock signal SIG CLK0 With SIG ACLK0 In phase, however, the clock signal SIG ACLK0 The swing is greater than the clock signal SIG CLK0 The amplitude of the swing. In this case, pump unit 110 can utilize the clock signal SIG. CLK0 To boost the voltage and utilize the large swing clock signal SIG ACLK0The transistors within are controlled to be fully turned on during charge transfer. Therefore, most of the pump voltage can be delivered by the charge pump circuit 100, resulting in an output voltage VOUT. That is, the charge pump circuit 100 achieves better charge transfer, making it suitable for low-power applications. Furthermore, with appropriate design of the pump units 110 and 120, the transistors can operate in the safe operating area (SOA) relative to the system operating voltage VDD, allowing the charge pump circuit 100 to be implemented with low-voltage transistors having a thin oxide layer.

[0011] like Figure 1 As shown, the pump unit 110 includes capacitor C1, capacitor C2, transistor M1, transistor M2, and auxiliary control unit 112. The first capacitor C1 is used to receive the clock signal SIG. CLK0 The first terminal and the second terminal. The second capacitor C2 has a function for receiving the clock signal SIG. ACLK0 The transistor M1 has a first terminal coupled to the input terminal IN1, a second terminal coupled to the second terminal of capacitor C1, and a control terminal coupled to the second terminal of capacitor C2. The transistor M2 has a first terminal coupled to the second terminal of capacitor C2, a second terminal coupled to the second terminal of transistor M1, and a control terminal. The auxiliary control unit 112 is coupled to the control terminal of transistor M2. The auxiliary control unit 112 can be controlled by the clock signal SIG. CLK0 Transistor M2 is turned on when the first high voltage VH1 is applied, and can be turned on by the clock signal SIG. CLK0 Transistor M2 is off when the voltage VL is low. Output transistor MO1 has a first terminal coupled to the second terminal of transistor M1, a second terminal coupled to the output terminal OUT1, and a control terminal. Output transistor MO1 can be controlled by the clock signal SIG. CLK0 When the voltage is high (VH1), the transistor M1 is turned on, and the voltage VPX at the second terminal of the output transistor M1 (i.e., the voltage at the second terminal of capacitor C1) is used as the output voltage VOUT. The output transistor M1 can also be turned on by the clock signal SIG. CLK0 It is cut off when it is at a low voltage VL.

[0012] Pump unit 120 includes capacitor C3, capacitor C4, transistor M3, transistor M4, and auxiliary control unit 122. Capacitor C3 is used to receive clock signal SIG. CLK1 The first and second terminals. Capacitor C4 has a function to receive the clock signal SIG. ACLK1The transistor M3 has a first terminal coupled to the input terminal IN1, a second terminal coupled to the control terminal of the output transistor MO1, and a control terminal coupled to the second terminal of the capacitor C4. The transistor M4 has a first terminal coupled to the second terminal of the capacitor C4, a second terminal coupled to the second terminal of the transistor M3, and a control terminal. The auxiliary control unit 122 is coupled to the control terminal of the transistor M4. The auxiliary control unit 122 can be activated by the clock signal SIG. CLK1 Transistor M4 is turned on when the first high voltage VH1 is applied, and at clock signal SIG... CLK1 Transistor M4 is off when the voltage VL is low. Output transistor MO2 has a first terminal coupled to the second terminal of transistor M3, a second terminal coupled to the output terminal OUT1, and a control terminal coupled to the second terminal of transistor M1. Output transistor MO2 can be controlled by clock signal SIG. CLK1 When the voltage is high (VH1), it is turned on, and the voltage VPY at the second terminal of output transistor M3 (i.e., the voltage at the second terminal of capacitor C3) is used as the output voltage VOUT. Output transistor MO2 can be activated by the clock signal SIG. CLK1 It is cut off when it is at a low voltage VL.

[0013] Figure 2 The waveforms of voltage and signals for pump units 110 and 120 according to an embodiment of this disclosure are illustrated. Figure 2 As shown, the clock signal SIG CLK0 With clock signal SIG ACLK0 In phase. Clock signal SIG CLK0 It oscillates between low voltage VL and high voltage VH1, while the clock signal SIG... ACLK0 The voltage oscillates between a low voltage VL and a high voltage VH2, which is higher than VH1. In some embodiments, the difference between voltage VH2 and voltage VL may be twice the difference between voltage VH1 and voltage VL. For example, voltage VL may be 0V and voltage VH2 may be 2VH1. In some embodiments, voltage VH1 may be the system operating voltage VDD. However, this disclosure is not limited thereto.

[0014] exist Figure 2 During the time period T1 shown, the clock signal SIG CLK0 With clock signal SIG ACLK0 The voltage is low, VL. In this state, transistor M2 is turned off by the auxiliary control unit 112, and the voltage VAPX at the second terminal of capacitor C2 changes with the clock signal SIG. ACLK0 The voltage VH2 is reduced from high voltage to low voltage VL and coupled to the low voltage. Therefore, voltage VAPX can fully turn on transistor M1. In this disclosure, due to the clock signal SIG ACLK0It is used to turn on transistor M1 to allow the input voltage VIN to pass through, and the clock signal SIG ACLK0 It is also known as the gate clock signal.

[0015] In this way, although at the very beginning of time period T1, the voltage VPX at the second terminal of transistor M1 may also change with the clock signal SIG. CLK0 The voltage is lowered from high voltage VH1 to low voltage VL and coupled to the low voltage, but the voltage VPX at the second terminal of transistor M1 will eventually be pulled high to be the same as the input voltage VIN. In this embodiment, the input voltage VIN can be the system operating voltage VDD. In addition, during time period T1, the output transistor MO1 is turned off, so the voltage VPX will not be output to the output terminal OUT1.

[0016] Next, in time period T2 following time period T1, the clock signal SIG CLK0 The voltage is increased to a high level VH1, and the clock signal SIG... ACLK0 The voltage is increased to a high voltage VH2. In this case, both voltages VAPX and VPX will increase with the clock signal SIG. CLK0 With SIG ACLK0 The voltage is increased and coupled to a higher voltage through capacitors C1 and C2, thus providing the pump voltage VPX. Furthermore, since transistor M2 is turned on by the auxiliary control unit 112 during time period T2, voltages VAPX and VPX can be at the same potential. Additionally, during time period T2, when the clock signal SIG... CLK0 When the voltage is high (VH1) and VPX is boosted to a level higher than the input voltage (VIN), the voltage VPY at the second terminal of transistor M3 is at a low (VL). Therefore, output transistor MO1 is turned on, using the output pump voltage VPX as the output voltage VOUT. Simultaneously, output transistor MO2 is turned off by the pump voltage VPX, so voltage VPY is not output. In this disclosure, due to the clock signal SIG... CLK0 The clock signal SIG is used to boost the voltage VPX to a higher voltage than the input voltage VIN. CLK0 Also known as a boost clock signal.

[0017] It can be noted that in this embodiment, since the output terminal OUT1 can be coupled to the load, the output voltage VOUT (i.e., voltage VPX) may gradually decrease due to the load. With proper design, the clock signal SIG... CLK0 With SIG ACLK0 It will return to a low voltage VL before the output voltage VOUT drops to an unacceptable level, and the clock signal SIG will... CLK1 With SIG ACLK1 The voltages VH1 and VH2 will become high, thus allowing the pump unit 120 to provide the pump voltage VPY as the output voltage VOUT.

[0018] In other words, when the clock signal SIG CLK0 High voltage VH1 and clock signal SIG CLK1 When the voltage is low (VL), pump unit 110 outputs pump voltage VPX as output voltage VOUT; when the clock signal SIG... CLK0 Under low voltage VL and clock signal SIG CLK1 When the voltage is high (VH1), the pump unit 120 outputs a pump voltage (VPY) as the output voltage (VOUT). Therefore, the charge pump circuit 100 can continuously output the pump output voltage (VOUT).

[0019] Specifically, pump unit 120 and pump unit 110 may have the same structure, but operate with different clock signal groups that complement each other. For example... Figure 2 As shown, the clock signal SIG CLK0 With clock signal SIG CLK1 It is inverted, while the clock signal SIG CLK1 With clock signal SIG ACLK1 They are in phase. Additionally, the clock signal SIG... CLK1 It oscillates between low voltage VL and high voltage VH1, while the clock signal SIG... ACLK1 It oscillates between low voltage VL and high voltage VH2. That is, the switching clock signal SIG... ACLK1 The swing is greater than the boost clock signal SIG. CLK1 The swing amplitude. Since the operation of pump unit 120 is essentially similar to that of pump unit 110 described above, it will not be described in detail for the sake of simplicity.

[0020] In some embodiments, transistors M1, M2, M3, and M4 can be P-type transistors, such as PMOSFETs. In this case, since the waveforms of the voltages received by transistors M1 and M2 to provide the pump voltage VPX are out of phase with the waveforms of the voltages received by transistors M3 and M4 to provide the pump voltage VPY, the base terminals of transistors M1 and M2 and the base terminals of transistors M3 and M4 can be biased differently, thereby avoiding leakage current caused by the forward bias of the PN junctions in transistors M1, M2, M3, and M4. In some embodiments, transistors M1 and M2 can be disposed in, for example, a well W1 (represented by a dense point region) of an N-type well, while transistors M3 and M4 can be disposed in, for example, another well W2 (represented by a sparse point region) of an N-type well.

[0021] In some embodiments, the charge pump circuit 100 may further include a well voltage selection unit for providing well voltage to wells W1 and W2. Figure 3The illustration depicts well voltage selection units 130 and 140 according to an embodiment of the present disclosure for providing well voltages to wells W1 and W2. In this embodiment, well voltage selection unit 130 can generate a well voltage VW1 for well W1 where transistors M1 and M2 are located based on the higher of the input voltage VIN and the voltage VAPX at the first terminal of transistor M2 (i.e., the voltage at the second terminal of capacitor C2). Therefore, the base terminals of transistors M1 and M2 can both receive the well voltage VW1 (not shown for simplicity). Figure 1 Similarly, the well voltage selection unit 140 can generate a well voltage VW2 for the well W2 where transistors M3 and M4 are located, based on the higher of the input voltage VIN and the voltage VAPY at the first terminal of transistor M4 (i.e., the voltage at the second terminal of capacitor C4). Therefore, the base terminals of transistors M3 and M4 can both receive the well voltage VW2 (not shown for simplicity). Figure 1 ).

[0022] Specifically, the well voltage selection unit 130 may include well selection transistors MW1 and MW2, which may be disposed in well W1. Well selection transistor MW1 has a first terminal coupled to input terminal IN1, a second terminal for outputting well voltage VW1, and a control terminal. Well selection transistor MW2 has a first terminal coupled to the second terminal of well selection transistor MW1, a second terminal coupled to the second terminal of capacitor C2 to receive voltage VAPX and also coupled to the control terminal of well selection transistor MW1, and a control terminal coupled to the first terminal of well selection transistor MW1.

[0023] In this scenario, when the input voltage VIN is lower than the voltage VAPX, the well selection transistor MW2 is turned on, while the well selection transistor MW1 is turned off; therefore, the well voltage selection unit 130 outputs the voltage VAPX as the well voltage VW1. Conversely, when the input voltage VIN is higher than the voltage VAPX, the well selection transistor MW1 is turned on, while the well selection transistor MW2 is turned off; therefore, the well voltage selection unit 130 outputs the input voltage VIN as the well voltage VW1.

[0024] Similarly, the well voltage selection unit 140 includes well selection transistors MW3 and MW4, which can be disposed in well W2. Well selection transistor MW3 has a first terminal coupled to input terminal IN1, a second terminal for outputting well voltage VW2, and a control terminal. Well selection transistor MW4 has a first terminal coupled to the second terminal of well selection transistor MW3, a second terminal coupled to the second terminal of capacitor C4 to receive voltage VAPY and also coupled to the control terminal of well selection transistor MW3, and a control terminal coupled to the first terminal of well selection transistor MW3.

[0025] In this embodiment, output transistors MO1 and MO2 can both be P-type transistors, such as PMOSFETs, and their base terminals can be biased independently of transistors M1, M2, M3, and M4. Figure 1 As shown, the charge pump circuit 100 may further include well selection transistors MW5 and MW6 to ensure that the base terminals of the output transistors MO1 and MO2 are at a higher voltage, thereby avoiding leakage current.

[0026] like Figure 1 As shown, well selection transistor MW5 has a first terminal coupled to a first terminal of output transistor MO1, a second terminal coupled to a second terminal of capacitor C3 to receive voltage VPY, and a base terminal coupled to the second terminal of well selection transistor MW5 and the base terminal of output transistor MO1. Well selection transistor MW6 has a first terminal coupled to a first terminal of output transistor MO2, a second terminal coupled to a second terminal of well selection transistor MW5, a control terminal coupled to the second terminal of capacitor C1 to receive voltage VPX, and a base terminal coupled to the second terminal of well selection transistor MW6 and the base terminal of output transistor MO2. In this way, the base terminals of well selection transistors MW5 and MW6 and the base terminals of output transistors MO1 and MO2 will be bound to the higher of voltages VPX and VPY, thereby avoiding leakage current. In some embodiments, well selection transistors MW5 and MW6 and output transistors MO1 and MO2 may be disposed in well W3, for example, an N-type well, which is different from well W1 that houses transistors M1 and M2, and also different from well W2 that houses transistors M3 and M4.

[0027] like Figure 1 As shown, the auxiliary control unit 112 includes transistor M5 and transistor M6. Transistor M5 has a first terminal coupled to input terminal IN1, a second terminal coupled to control terminal of transistor M2, and a control terminal coupled to second terminal of capacitor C2. Transistor M6 has a first terminal coupled to control terminal of transistor M2, a second terminal coupled to second terminal of capacitor C3, and a control terminal coupled to second terminal of capacitor C4.

[0028] See Figure 1 and Figure 2 During time period T1, when the clock signal SIG... ACLK0 Low voltage VL, clock signal SIG ACLK1 When the voltage is high (VH2), voltage VAPX is coupled to a low potential (e.g., low voltage VL), while voltage VAPY is coupled to a high potential (e.g., a potential close to the high voltage VH2). In this case, transistor M5 can be turned on by voltage VAPX, while transistor M6 can be turned off by voltage VAPY. Therefore, the control terminal of transistor M2 receives the input voltage VIN and will be cut off during time period T1.

[0029] Furthermore, during time period T2, when the clock signal SIG... ACLK0 High voltage VH2, clock signal SIG ACLK1 When the voltage is low (VL), voltage VAPY is coupled to a low potential (e.g., low voltage VL), while voltage VAPX is coupled to a high potential (e.g., a potential close to high voltage VH2). In this case, transistor M5 is turned off by voltage VAPX, while transistor M6 is turned on by voltage VAPY. Therefore, the control terminal of transistor M2 receives voltage VPY, which is coupled to a low potential, and thus transistor M2 can be turned on during time period T2, thereby making the voltage VAPX at the second terminal of capacitor C2 and the voltage VPX at the second terminal of capacitor C1 at the same potential.

[0030] In this embodiment, the gate-to-source voltage and gate-to-drain voltage of transistors M1, M2, M5 and M6 can be maintained within the operating voltage VDD, thereby allowing transistors M1, M2, M5 and M6 to be implemented by low-voltage transistors with thin oxide layers, while operating in their safe operating area (SOA).

[0031] Auxiliary control unit 122 and auxiliary control unit 112 have the same structure. In this embodiment, auxiliary control unit 122 includes transistor M7 and transistor M8. Transistor M7 has a first terminal coupled to input terminal IN1, a second terminal coupled to control terminal of transistor M4, and a control terminal coupled to second terminal of capacitor C4. Transistor M8 has a first terminal coupled to control terminal of transistor M4, a second terminal coupled to second terminal of capacitor C1, and a control terminal coupled to second terminal of capacitor C2. Since the operation of auxiliary control unit 122 is essentially the same as that of auxiliary control unit 112 described above, it will not be described in detail for the sake of simplicity.

[0032] In some embodiments, transistors M5 and M8 may be disposed in the same well as transistors M1 and M2, while transistors M6 and M7 may be disposed in the same well as transistors M3 and M4. In this case, the charge pump circuit 100 may include three wells. Transistors M1, M2, M5, and M8, as well as well selection transistors MW1 and MW2, may be disposed in well W1, which may be biased by well voltage VW1 provided by well voltage selection unit 130. Transistors M3, M4, M6, and M7, as well as well selection transistors MW3 and MW4, may be disposed in well W2, which may be biased by well voltage VW2 provided by well voltage selection unit 140. Furthermore, output transistors MO1 and MO2, as well as well selection transistors MW5 and MW6, may be disposed in well W3, which may be biased by well selection transistors MW5 and MW6.

[0033] Figure 4A charge pump circuit 200 according to another embodiment of the present disclosure is illustrated. The charge pump circuit 200 differs from the charge pump circuit 100 in that the pump unit 210 of the charge pump circuit 200 further includes a voltage gap unit 214, and the pump unit 220 of the charge pump circuit 200 further includes a voltage gap unit 224.

[0034] Voltage gap unit 214 is coupled between the second terminal of capacitor C2 and the second terminal of transistor M1. Voltage gap unit 214 is used to... (The sentence is incomplete and requires more context to translate accurately.) CLK0 When the voltage is low (VL), the voltage VAPX' at the second terminal of capacitor C2 is lower than the voltage VPX' at the second terminal of transistor M1 by a gap voltage VG. The voltage gap unit 224 is coupled between the second terminal of capacitor C4 and the second terminal of transistor M3. The voltage gap unit 224 is used to... (The sentence is incomplete and requires further context to translate accurately.) CLK1 When the voltage is low (VL), the voltage VAPY' at the second terminal of capacitor C4 is lower than the gap voltage VG than the voltage VPY' at the second terminal of transistor M3.

[0035] Figure 5 The waveforms of the voltage and signals of pump unit 210 and pump unit 220 according to an embodiment of this disclosure are illustrated. During time period T1', the clock signal SIG... CLK0 With SIG ACLK0 Both are at a low voltage VL, transistor M1 is turned on while transistor M2 is turned off, and voltage VPX will become the same as the input voltage VIN. In this case, if there is no voltage gap unit 214, Figure 2 The voltage VAPX in the time period T1 shown may be at a low voltage VL, which is lower than the voltage VH1 compared to the voltage VPX; however, as Figure 5 As shown, the voltage VAPX' in time period T1' is lower than the voltage VPX' by a gap voltage VG provided by the voltage gap unit 214. In this embodiment, the input voltage VIN minus the gap voltage VG will be higher than the low voltage VL, therefore Figure 5 The voltage VAPX' in the time period T1' shown will be at a higher level than Figure 2 The voltage VAPX' in the time period T1 shown is a higher potential. In some embodiments, the gap voltage VG is greater than the threshold voltage of transistor M1, so voltage VAPX' can still fully turn on transistor M1.

[0036] Because in Figure 5 During the time period T1' shown, the voltage VAPX' will be at a higher level than... Figure 2 The voltage VAPX in the time period T1 shown is at a higher potential, therefore when the clock signal SIG... ACLK0When the voltage changes from low to high VH2 during time period T2', voltage VAPX' is expected to rise to a potential higher than voltage VPX'. In this case, once transistor M2 is turned on during time period T2', the pull-up drive provided to voltage VAPX' helps voltage VPX' reach the target pump voltage potential (e.g., voltage VH2) more quickly.

[0037] Similarly, voltage gap unit 224 can cause voltage VAPY' to rise to a higher potential during time period T2'. Therefore, when clock signal SIG ACLK1 When the voltage changes from low voltage VL to high voltage VH2 during time period T3', voltage VAPY' is expected to rise to a higher potential than voltage VPY', thereby helping voltage VPY' reach the target pump voltage potential more quickly.

[0038] In some embodiments, voltage gap units 214 and 224 may each include at least one diode or at least one diode-connected transistor to provide the gap voltage VG. Figure 4 As shown, the voltage gap unit 214 includes diode-connected transistors MD1 and MD2. Diode-connected transistor MD1 has a first terminal coupled to the second terminal of capacitor C2, a second terminal coupled to the second terminal of diode-connected transistor MD1, and a control terminal coupled to the first terminal of diode-connected transistor MD1. Diode-connected transistor MD2 has a first terminal coupled to the second terminal of diode-connected transistor MD1, a second terminal coupled to the second terminal of transistor M1, and a control terminal coupled to the first terminal of diode-connected transistor MD2.

[0039] In this case, the gap voltage VG provided by the gap voltage unit 214 will be equal to the sum of the threshold voltages of the diode-connected transistors MD1 and MD2. In this embodiment, the threshold voltages of the diode-connected transistors MD1 and MD2 can be the same as the threshold voltage of transistor M1; in other words, transistors M1, MD1, and MD2 can be of the same type, which makes the design easier. Therefore, at the end of time period T1', voltage VAPX' will still be twice the threshold voltage of voltage VPX', thereby ensuring that transistor M1 can be fully turned on. Furthermore, in this embodiment, the diode-connected transistors MD1 and MD2 also help ensure that the drain-to-source voltage of transistor M2 remains within its SOA range.

[0040] In this embodiment, the gap voltage unit 224 may have the same structure as the gap voltage unit 214. That is, the gap voltage unit 224 may also use two series-coupled diodes to connect transistors MD3 and MD4. However, in some embodiments, diodes may be used to replace transistors MD1, MD2, MD3, and MD4.

[0041] In some embodiments, diode-connected transistors MD1 and MD2 may be disposed together in well W1 with transistors M1, M2 and M5, while diode-connected transistors MD3 and MD4 may be disposed together in well W2 with transistors M3, M4 and M7.

[0042] Furthermore, unlike transistors M1 and M3, and output transistors MO1 and MO2, which are used to output a higher current output voltage VOUT, other transistors M2, M4, M5, M6, M7, M8, well-select transistors MW1, MW2, MW3, MW4, MW5, MW6, and diode-connected transistors MD1, MD2, MD3, and MD4 are used to adjust a lower current voltage. Therefore, in some embodiments, the dimensions (e.g., effective channel width) of transistors M1 and M3 and output transistors MO1 and MO2 can be larger than the dimensions (e.g., effective channel width) of transistors M2, M4, M5, M6, M7, M8, well-select transistors MW1, MW2, MW3, MW4, MW5, MW6, and diode-connected transistors MD1, MD2, MD3, and MD4. In other words, transistors M2, M4, M5, M6, M7, M8, MW1, MW2, MW3, MW4, MW5, MW6, MD1, MD2, MD3, and MD4 can have smaller dimensions to reduce the total area of ​​the charge pump circuit 100.

[0043] In some embodiments, since all transistors in charge pump circuits 100 and 200 can operate with gate-to-drain voltage, gate-to-source voltage, and drain-to-source voltage less than or equal to the system operating voltage VDD (e.g., but not limited to below 1.2V), all transistors in charge pump circuits 100 and 200 can be implemented by low-voltage transistors with a thin gate oxide layer.

[0044] Furthermore, in some embodiments, to improve the efficiency of the charge pump circuit 100 or 200, the clock signal SIG... ACLK0 The rising edge can lead the clock signal SIG. CLK0 The rising edge of the clock signal SIG. ACLK1 The rising edge can lead the clock signal SIG. CLK1 The rising edge. Figure 6 The diagram illustrates a clock signal SIG according to an embodiment of this disclosure. CLK0 SIG ACLK0 SIG CLK1 With SIG ACLK1 The waveform. For example... Figure 6 As shown, the clock signal SIG ACLK0 Rising edge RE1 leading clock signal SIG CLK0The rising edge RE2. In this case, transistor M1 will be turned off at the rising edge RE1 before the rising edge RE2, thus allowing voltage VPX to couple to the high voltage VH2 faster and more firmly at the rising edge RE2. Similarly, the clock signal SIG ACLK1 The rising edge RE3 will lead the clock signal SIG. CLK1 The rising edge RE4 is used to improve the efficiency of charge pump circuits 100 and 200.

[0045] In some embodiments, charge pump circuits 100 and 200 may be connected in series to generate a pump output voltage with a higher potential. Figure 7 A charge pump device 10 according to an embodiment of the present disclosure is illustrated. The charge pump device 10 includes multi-stage charge pump circuits 1001 to 100N.

[0046] In this embodiment, each stage of the charge pump circuit 1001 to 100N can utilize, for example... Figure 1 The charge pump circuit 100 shown is or Figure 4 The charge pump circuit 200 shown is used for implementation. In this embodiment, the input terminal IN1 of the charge pump circuit 1001 can receive the input voltage VIN, the output terminal OUT1 of the charge pump circuit 1001 is coupled to the input terminal IN2 of the charge pump circuit 1002, the output terminal OUT2 of the charge pump circuit 1002 is coupled to the input terminal IN3 of the charge pump circuit 1003, and so on. Finally, the charge pump circuit 100N can output the output voltage VOUT. In this embodiment, a switching clock signal SIG with a large swing is used. ACLK0 With SIG ACLK1 Each stage of the charge pump device 10 (i.e., each stage of the charge pump circuits 1001 to 100N) is capable of boosting the output voltage by a boost clock signal SIG. CLK0 and SIG CLK1 The full voltage increment provided is VH1. In this case, the output voltage provided by charge pump circuit 1001 can be about 2VH1, the output voltage provided by charge pump circuit 1002 can be about 3VH1, and so on.

[0047] In summary, the charge pump circuit and device disclosed in this embodiment can employ a two-phase boost clock signal and a turn-off clock signal, enabling each stage of the charge pump device to increase the output voltage by a full voltage increment provided by the swing of the boost clock signal. That is, the charge pump circuit and device disclosed in this embodiment can achieve better charge transfer efficiency, making the charge pump circuit particularly suitable for low-power designs. Furthermore, the charge pump circuit and device disclosed in this embodiment can utilize a turn-off clock signal to assist in boosting the output voltage, thereby further improving the efficiency of the charge pump circuit and device.

[0048] Symbol Explanation 10: Charge pump device 100, 200: Charge pump circuit 110, 120, 210, 220: Pump units 112, 122: Auxiliary control unit 130, 140: Well voltage selection unit 214, 224: Voltage gap unit; gap voltage unit 1001, 1002, 1003, 100N: Charge pump circuit C1, C2, C3, C4: Capacitors IN1, IN2, IN3: Input terminals M1, M2, M3, M4, M5, M6, M7, M8: Transistors MD1, MD2, MD3, MD4: Transistors MO1, MO2: Output transistors MW1, MW2, MW3, MW4, MW5, MW6: Well-selected transistors OUT1, OUT2: Output terminals RE1, RE2, RE3, RE4: Ascending Edge SIG CLK0 SIG ACLK0 SIG CLK1 SIG ACLK1 Clock signal T1, T2, T1', T2', T3': Time period VG: Gap voltage VH1, VH2: High voltage VIN: Input voltage VL: Low voltage VOUT: Output voltage VPX, VAPX, VPY, VAPY, VPX', VAPX', VPY', VAPY': Voltage VW1, VW2: Well voltage W1, W2, W3: Well

Claims

1. A charge pump circuit, comprising: The input terminal is used to receive the input voltage. The output terminal is used to output the output voltage; The first pump unit includes: The first capacitor has a first terminal for receiving a first clock signal and a second terminal; The second capacitor has a first terminal and a second terminal for receiving a second clock signal; The first transistor has a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor; The second transistor has a first terminal coupled to the second terminal of the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal; as well as A first auxiliary control unit is coupled to the control terminal of the second transistor and is configured to turn on the second transistor when the first clock signal is at a first high voltage and turn off the second transistor when the first clock signal is at a low voltage. The first output transistor has a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the output terminal, and a control terminal; The second pump unit includes: The third capacitor has a first terminal and a second terminal for receiving a third clock signal; The fourth capacitor has a first terminal and a second terminal for receiving a fourth clock signal; The third transistor has a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the third capacitor and the control terminal of the first output transistor, and a control terminal coupled to the second terminal of the fourth capacitor. The fourth transistor has a first terminal coupled to the second terminal of the fourth capacitor, a second terminal coupled to the second terminal of the third transistor, and a control terminal; as well as The second auxiliary control unit is coupled to the control terminal of the fourth transistor and is used to turn on the fourth transistor when the third clock signal is at the first high voltage and to turn off the fourth transistor when the third clock signal is at the low voltage. as well as The second output transistor has a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the output terminal, and a control terminal coupled to the second terminal of the first transistor; The first clock signal is in phase with the second clock signal, the third clock signal is in phase with the fourth clock signal, the first clock signal is out of phase with the third clock signal, the second clock signal has a larger swing than the first clock signal, and the fourth clock signal has a larger swing than the third clock signal. The first transistor and the second transistor are disposed in the first well, and the third transistor and the fourth transistor are disposed in the second well.

2. The charge pump circuit as described in claim 1, wherein: The first clock signal and the third clock signal oscillate between the low voltage and the first high voltage, and the second clock signal and the fourth clock signal oscillate between the low voltage and a second high voltage higher than the first high voltage; and The difference between the second high voltage and the low voltage is twice the difference between the first high voltage and the low voltage.

3. The charge pump circuit as described in claim 1, wherein: The first output transistor is configured to turn on when the first clock signal is at the first high voltage to generate the output voltage based on the voltage at the second terminal of the first transistor, and to turn off when the first clock signal is at the low voltage; and The second output transistor is turned on when the third clock signal is at the first high voltage to generate the output voltage according to the voltage at the second terminal of the third transistor, and turned off when the third clock signal is at the low voltage.

4. The charge pump circuit of claim 1, wherein the first auxiliary control unit comprises: The fifth transistor has a first terminal coupled to the input terminal, a second terminal coupled to the control terminal of the second transistor, and a control terminal coupled to the second terminal of the second capacitor; and The sixth transistor has a first terminal coupled to the control terminal of the second transistor, a second terminal coupled to the second terminal of the third capacitor, and a control terminal coupled to the second terminal of the fourth capacitor.

5. The charge pump circuit of claim 4, wherein the fifth transistor is disposed in the first well and the sixth transistor is disposed in the second well.

6. The charge pump circuit of claim 4, wherein the second auxiliary control unit comprises: The seventh transistor has a first terminal coupled to the input terminal, a second terminal coupled to the control terminal of the fourth transistor, and a control terminal coupled to the second terminal of the fourth capacitor; and The eighth transistor has a first terminal coupled to the control terminal of the fourth transistor, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor.

7. The charge pump circuit of claim 6, wherein the fifth transistor and the eighth transistor are disposed in the first well, and the sixth transistor and the seventh transistor are disposed in the second well.

8. The charge pump circuit of claim 6, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors.

9. The charge pump circuit of claim 1, wherein the first well is biased by a first well voltage and the second well is biased by a second well voltage, the charge pump circuit further comprising: A first well voltage selection unit is configured to generate a first well voltage for the first well based on the higher of the input voltage and the voltage at the second terminal of the second capacitor; and The second well voltage selection unit is used to generate the second well voltage for the second well based on the higher of the input voltage and the voltage at the second terminal of the fourth capacitor.

10. The charge pump circuit of claim 9, wherein the first well voltage selection unit comprises: The first well selection transistor has a first terminal coupled to the input terminal, a second terminal for outputting the first well voltage, and a control terminal; and The second well select transistor has a first terminal coupled to the second terminal of the first well select transistor, a second terminal coupled to the second terminal of the second capacitor and the control terminal of the first well select transistor, and a control terminal coupled to the first terminal of the first well select transistor.

11. The charge pump circuit of claim 9, wherein the second well voltage selection unit comprises: The third well selection transistor has a first terminal coupled to the input terminal, a second terminal for outputting the second well voltage, and a control terminal; and The fourth well select transistor has a first terminal coupled to the second terminal of the third well select transistor, a second terminal coupled to the second terminal of the fourth capacitor and the control terminal of the third well select transistor, and a control terminal coupled to the first terminal of the third well select transistor.

12. The charge pump circuit of claim 1, further comprising: The fifth well select transistor has a first terminal coupled to the first terminal of the first output transistor, a second terminal coupled to the second terminal of the third capacitor, and a base terminal coupled to the second terminal of the fifth well select transistor and the base terminal of the first output transistor; and The sixth well select transistor has a first terminal coupled to the first terminal of the second output transistor, a second terminal coupled to the second terminal of the fifth well select transistor, a control terminal coupled to the second terminal of the first capacitor, and a base terminal coupled to the second terminal of the fifth well select transistor, the second terminal of the sixth well select transistor, and the base terminal of the sixth well select transistor.

13. The charge pump circuit of claim 1, wherein the first pump unit further includes a voltage gap unit coupled between the second terminal of the second capacitor and the second terminal of the first transistor, and is configured to, when the first clock signal is at the low voltage, make the voltage at the second terminal of the first transistor higher than the voltage at the second terminal of the second capacitor by a gap voltage.

14. The charge pump circuit of claim 13, wherein the voltage gap unit comprises at least one diode or at least one diode-connected transistor.

15. The charge pump circuit of claim 13, wherein the voltage gap unit comprises: The first diode-connected transistor has a first terminal coupled to the second terminal of the second capacitor, a second terminal, and a control terminal coupled to the first terminal of the first diode-connected transistor; and The second diode-connected transistor has a first terminal coupled to the second terminal of the first diode-connected transistor, a second terminal coupled to the second terminal of the first transistor, and a control terminal coupled to the first terminal of the second diode-connected transistor.

16. The charge pump circuit of claim 15, wherein the first diode-connected transistor and the second diode-connected transistor are disposed in the first well.

17. The charge pump circuit of claim 12, wherein the fifth well selection transistor, the sixth well selection transistor, the first output transistor, and the second output transistor are disposed in a third well, which is different from the first well and the second well.

18. The charge pump circuit of claim 1, wherein the size of the first transistor is larger than the size of the second transistor and the size of each transistor in the first auxiliary control unit.

19. A charge pump device, comprising: A multi-stage charge pump circuit, wherein the input terminal of the subsequent charge pump circuit is connected to the output terminal of the preceding charge pump circuit; The first-stage charge pump circuit includes: The input terminal is used to receive the input voltage. The output terminal is used to output the output voltage; The first pump unit includes: The first capacitor has a first terminal for receiving a first clock signal and a second terminal; The second capacitor has a first terminal and a second terminal for receiving a second clock signal; The first transistor has a first terminal coupled to the input terminal of the first-stage charge pump circuit, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor. The second transistor has a first terminal coupled to the second terminal of the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal; as well as A first auxiliary control unit is coupled to the control terminal of the second transistor and is configured to turn on the second transistor when the first clock signal is at a first high voltage and turn off the second transistor when the first clock signal is at a low voltage. The first output transistor has a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the output terminal of the first-stage charge pump circuit, and a control terminal; The second pump unit includes: The third capacitor has a first terminal and a second terminal for receiving a third clock signal; The fourth capacitor has a first terminal and a second terminal for receiving a fourth clock signal; The third transistor has a first terminal coupled to the input terminal of the first-stage charge pump circuit, a second terminal coupled to the second terminal of the third capacitor and the control terminal of the first output transistor, and a control terminal coupled to the second terminal of the fourth capacitor. The fourth transistor has a first terminal coupled to the second terminal of the fourth capacitor, a second terminal coupled to the second terminal of the third transistor, and a control terminal; as well as The second auxiliary control unit is coupled to the control terminal of the fourth transistor and is used to turn on the fourth transistor when the third clock signal is at the first high voltage and to turn off the fourth transistor when the third clock signal is at the low voltage. as well as The second output transistor has a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the output terminal of the first-stage charge pump circuit, and a control terminal coupled to the second terminal of the first transistor. The first clock signal is in phase with the second clock signal, the third clock signal is in phase with the fourth clock signal, the first clock signal is out of phase with the third clock signal, the second clock signal has a larger swing than the first clock signal, and the fourth clock signal has a larger swing than the third clock signal. The first transistor and the second transistor are disposed in the first well, and the third transistor and the fourth transistor are disposed in the second well.

20. The charge pump device of claim 19, wherein the output terminal of the first-stage charge pump circuit is coupled to the input terminal of the second-stage charge pump circuit of the multi-stage charge pump circuit.

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