A switching drive circuit suitable for high speed DACs
By using a two-stage synchronous latch structure and a switching drive circuit with an adjustable-size NMOS pull-down transistor, the problem of asynchronous switching signals in current-controlled DACs is solved, improving the linearity and spurious-free dynamic range of the DAC and meeting the application requirements of high-speed and high-precision DACs.
CN122419461APending Publication Date: 2026-07-17CHONGQING GIGACHIP TECH CO LTD
View PDF 0 Cites 0 Cited by
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHONGQING GIGACHIP TECH CO LTD
- Filing Date
- 2026-04-21
- Publication Date
- 2026-07-17
Smart Images
Figure CN122419461A_ABST
Abstract
本发明属于集成电路技术领域，具体涉及一种适用于高速DAC的开关驱动电路，旨在解决现有电流舵DAC开关信号不同步、差分交叉点不可调导致的失真与杂散恶化问题，包括：锁存电路与采样驱动锁存电路，两级电路采用互为反相的时钟信号控制，锁存电路对差分输入信号进行同步锁存，保证开关指令时序一致；采样驱动锁存电路集成多级反相器链提升驱动能力，并采用交叉耦合与非门结构实现输出锁存，避免输出信号同时为高电平。电路通过设置尺寸可调的NMOS下拉晶体管，利用控制信号调节宽长比，改变下拉电流与电平翻转速度，实现差分输出信号交叉点电压灵活可调。仿真结果表明，本电路可输出边沿陡峭、时序精准的差分驱动信号，能有效消除开关时序偏差，降低时钟馈通与电荷注入噪声，减小输出毛刺与非线性失真，显著提升高速DAC的线性度、无杂散动态范围及信号稳定性，适配高速高精度DAC系统应用。
Need to check novelty before this filing date? Find Prior Art